2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 /* AIC3X register space */
16 #define AIC3X_CACHEREGNUM 103
17 #define AIC3X_COEFF_CACHE_SIZE 52
18 #define COEFF_OFFSET(msbreg) ((msbreg+1)/2)
20 /* Page select register */
21 #define AIC3X_PAGE_SELECT 0
22 /* Software reset register */
24 /* Codec Sample rate select register */
25 #define AIC3X_SAMPLE_RATE_SEL_REG 2
26 /* PLL progrramming register A */
27 #define AIC3X_PLL_PROGA_REG 3
28 /* PLL progrramming register B */
29 #define AIC3X_PLL_PROGB_REG 4
30 /* PLL progrramming register C */
31 #define AIC3X_PLL_PROGC_REG 5
32 /* PLL progrramming register D */
33 #define AIC3X_PLL_PROGD_REG 6
34 /* Codec datapath setup register */
35 #define AIC3X_CODEC_DATAPATH_REG 7
36 /* Audio serial data interface control register A */
37 #define AIC3X_ASD_INTF_CTRLA 8
38 /* Audio serial data interface control register B */
39 #define AIC3X_ASD_INTF_CTRLB 9
40 /* Audio serial data interface control register C */
41 #define AIC3X_ASD_INTF_CTRLC 10
42 /* Audio overflow status and PLL R value programming register */
43 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
44 /* Audio codec digital filter control register */
45 #define AIC3X_CODEC_DFILT_CTRL 12
47 /* ADC PGA Gain control registers */
50 /* MIC3 control registers */
51 #define MIC3LR_2_LADC_CTRL 17
52 #define MIC3LR_2_RADC_CTRL 18
53 /* Line1 Input control registers */
54 #define LINE1L_2_LADC_CTRL 19
55 #define LINE1R_2_RADC_CTRL 22
56 #define LINE1L_2_RADC_CTRL 24
57 /* Line2 Input control registers */
58 #define LINE2L_2_LADC_CTRL 20
59 #define LINE2R_2_RADC_CTRL 23
60 /* MICBIAS Control Register */
61 #define MICBIAS_CTRL 25
63 /* AGC Control Registers A, B, C */
64 #define LAGC_CTRL_A 26
65 #define LAGC_CTRL_B 27
66 #define LAGC_CTRL_C 28
67 #define RAGC_CTRL_A 29
68 #define RAGC_CTRL_B 30
69 #define RAGC_CTRL_C 31
71 /* DAC Power and Left High Power Output control registers */
74 /* Right High Power Output control registers */
76 /* DAC Output Switching control registers */
77 #define DAC_LINE_MUX 41
78 /* High Power Output Driver Pop Reduction registers */
79 #define HPOUT_POP_REDUCTION 42
80 /* DAC Digital control registers */
83 /* High Power Output control registers */
84 #define LINE2L_2_HPLOUT_VOL 45
85 #define LINE2R_2_HPROUT_VOL 62
86 #define PGAL_2_HPLOUT_VOL 46
87 #define PGAR_2_HPROUT_VOL 63
88 #define DACL1_2_HPLOUT_VOL 47
89 #define DACR1_2_HPROUT_VOL 64
90 #define HPLOUT_CTRL 51
91 #define HPROUT_CTRL 65
92 /* High Power COM control registers */
93 #define LINE2L_2_HPLCOM_VOL 52
94 #define LINE2R_2_HPRCOM_VOL 69
95 #define PGAL_2_HPLCOM_VOL 53
96 #define PGAR_2_HPRCOM_VOL 70
97 #define DACL1_2_HPLCOM_VOL 54
98 #define DACR1_2_HPRCOM_VOL 71
99 #define HPLCOM_CTRL 58
100 #define HPRCOM_CTRL 72
101 /* Mono Line Output Plus/Minus control registers */
102 #define LINE2L_2_MONOLOPM_VOL 73
103 #define LINE2R_2_MONOLOPM_VOL 76
104 #define PGAL_2_MONOLOPM_VOL 74
105 #define PGAR_2_MONOLOPM_VOL 77
106 #define DACL1_2_MONOLOPM_VOL 75
107 #define DACR1_2_MONOLOPM_VOL 78
108 #define MONOLOPM_CTRL 79
109 /* Line Output Plus/Minus control registers */
110 #define LINE2L_2_LLOPM_VOL 80
111 #define LINE2R_2_RLOPM_VOL 90
112 #define PGAL_2_LLOPM_VOL 81
113 #define PGAR_2_RLOPM_VOL 91
114 #define DACL1_2_LLOPM_VOL 82
115 #define DACR1_2_RLOPM_VOL 92
116 #define LLOPM_CTRL 86
117 #define RLOPM_CTRL 93
118 /* GPIO/IRQ registers */
119 #define AIC3X_STICKY_IRQ_FLAGS_REG 96
120 #define AIC3X_RT_IRQ_FLAGS_REG 97
121 #define AIC3X_GPIO1_REG 98
122 #define AIC3X_GPIO2_REG 99
123 #define AIC3X_GPIOA_REG 100
124 #define AIC3X_GPIOB_REG 101
125 /* Clock generation control register */
126 #define AIC3X_CLKGEN_CTRL_REG 102
128 /* Page 1 registers for setting coefficients for filters */
129 /* DAC Audio Effects for Left Channel */
130 #define EFFECTS_LEFT_N0 1
131 #define EFFECTS_LEFT_N1 3
132 #define EFFECTS_LEFT_N2 5
133 #define EFFECTS_LEFT_N3 7
134 #define EFFECTS_LEFT_N4 9
135 #define EFFECTS_LEFT_N5 11
137 #define EFFECTS_LEFT_D1 13
138 #define EFFECTS_LEFT_D2 15
139 #define EFFECTS_LEFT_D4 17
140 #define EFFECTS_LEFT_D5 19
142 /* DAC De-Emphasis for Left Channel */
144 #define DEEMPH_LEFT_N0 21
145 #define DEEMPH_LEFT_N1 23
146 #define DEEMPH_LEFT_D1 25
148 /* DAC Audio Effects for Right Channel */
150 #define EFFECTS_RIGHT_N0 27
151 #define EFFECTS_RIGHT_N1 29
152 #define EFFECTS_RIGHT_N2 31
153 #define EFFECTS_RIGHT_N3 33
154 #define EFFECTS_RIGHT_N4 35
155 #define EFFECTS_RIGHT_N5 37
157 #define EFFECTS_RIGHT_D1 39
158 #define EFFECTS_RIGHT_D2 41
159 #define EFFECTS_RIGHT_D4 43
160 #define EFFECTS_RIGHT_D5 45
162 /* DAC De-Emphasis for Right Channel */
164 #define DEEMPH_RIGHT_N0 47
165 #define DEEMPH_RIGHT_N1 49
166 #define DEEMPH_RIGHT_D1 51
168 /* DAC 3D Attenuation */
170 #define EFFECTS_3DATTEN 53
172 /* ADC High-Pass Filter for Left Channel */
174 #define HIGHPASS_LEFT_NO 65
175 #define HIGHPASS_LEFT_N1 67
176 #define HIGHPASS_LEFT_D1 69
178 /* ADC High-Pass Filter for Right Channel */
180 #define HIGHPASS_RIGHT_NO 71
181 #define HIGHPASS_RIGHT_N1 73
182 #define HIGHPASS_RIGHT_D1 75
184 /* Page select register bits */
185 #define PAGE0_SELECT 0
186 #define PAGE1_SELECT 1
188 /* Audio serial data interface control register A bits */
189 #define BIT_CLK_MASTER 0x80
190 #define WORD_CLK_MASTER 0x40
192 /* Codec Datapath setup register 7 */
193 #define FSREF_44100 (1 << 7)
194 #define FSREF_48000 (0 << 7)
195 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
196 #define LDAC2LCH (0x1 << 3)
197 #define RDAC2RCH (0x1 << 1)
199 /* PLL registers bitfields */
204 #define PLLD_MSB_SHIFT 0
205 #define PLLD_LSB_SHIFT 2
207 /* Clock generation register bits */
208 #define CODEC_CLKIN_PLLDIV 0
209 #define CODEC_CLKIN_CLKDIV 1
210 #define PLL_CLKIN_SHIFT 4
211 #define MCLK_SOURCE 0x0
212 #define PLL_CLKDIV_SHIFT 0
214 /* Software reset register bits */
215 #define SOFT_RESET 0x80
217 /* PLL progrramming register A bits */
218 #define PLL_ENABLE 0x80
221 #define ROUTE_ON 0x80
228 #define LADC_PWR_ON 0x04
229 #define RADC_PWR_ON 0x04
230 #define LDAC_PWR_ON 0x80
231 #define RDAC_PWR_ON 0x40
232 #define HPLOUT_PWR_ON 0x01
233 #define HPROUT_PWR_ON 0x01
234 #define HPLCOM_PWR_ON 0x01
235 #define HPRCOM_PWR_ON 0x01
236 #define MONOLOPM_PWR_ON 0x01
237 #define LLOPM_PWR_ON 0x01
238 #define RLOPM_PWR_ON 0x01
240 #define INVERT_VOL(val) (0x7f - val)
242 /* Default output volume (inverted) */
243 #define DEFAULT_VOL INVERT_VOL(0x50)
244 /* Default input volume */
245 #define DEFAULT_GAIN 0x20
249 AIC3X_GPIO1_FUNC_DISABLED = 0,
250 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1,
251 AIC3X_GPIO1_FUNC_CLOCK_MUX = 2,
252 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3,
253 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4,
254 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5,
255 AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6,
256 AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7,
257 AIC3X_GPIO1_FUNC_INPUT = 8,
258 AIC3X_GPIO1_FUNC_OUTPUT = 9,
259 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10,
260 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11,
261 AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12,
262 AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13,
263 AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14,
264 AIC3X_GPIO1_FUNC_ALL_IRQ = 16
268 AIC3X_GPIO2_FUNC_DISABLED = 0,
269 AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2,
270 AIC3X_GPIO2_FUNC_INPUT = 3,
271 AIC3X_GPIO2_FUNC_OUTPUT = 4,
272 AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5,
273 AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8,
274 AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
275 AIC3X_GPIO2_FUNC_ALL_IRQ = 10,
276 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
277 AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
278 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13,
279 AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14,
280 AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15
283 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
284 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
285 int aic3x_headset_detected(struct snd_soc_codec *codec);
287 struct aic3x_setup_data {
289 unsigned short i2c_address;
290 unsigned int gpio_func[2];
293 extern struct snd_soc_dai aic3x_dai;
294 extern struct snd_soc_codec_device soc_codec_dev_aic3x;
296 #endif /* _AIC3X_H */