2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 /* AIC3X register space */
16 #define AIC3X_CACHEREGNUM 103
18 /* Page select register */
19 #define AIC3X_PAGE_SELECT 0
20 /* Software reset register */
22 /* Codec Sample rate select register */
23 #define AIC3X_SAMPLE_RATE_SEL_REG 2
24 /* PLL progrramming register A */
25 #define AIC3X_PLL_PROGA_REG 3
26 /* PLL progrramming register B */
27 #define AIC3X_PLL_PROGB_REG 4
28 /* PLL progrramming register C */
29 #define AIC3X_PLL_PROGC_REG 5
30 /* PLL progrramming register D */
31 #define AIC3X_PLL_PROGD_REG 6
32 /* Codec datapath setup register */
33 #define AIC3X_CODEC_DATAPATH_REG 7
34 /* Audio serial data interface control register A */
35 #define AIC3X_ASD_INTF_CTRLA 8
36 /* Audio serial data interface control register B */
37 #define AIC3X_ASD_INTF_CTRLB 9
38 /* Audio serial data interface control register C */
39 #define AIC3X_ASD_INTF_CTRLC 10
40 /* Audio overflow status and PLL R value programming register */
41 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
42 /* Audio codec digital filter control register */
43 #define AIC3X_CODEC_DFILT_CTRL 12
45 /* ADC PGA Gain control registers */
48 /* MIC3 control registers */
49 #define MIC3LR_2_LADC_CTRL 17
50 #define MIC3LR_2_RADC_CTRL 18
51 /* Line1 Input control registers */
52 #define LINE1L_2_LADC_CTRL 19
53 #define LINE1R_2_RADC_CTRL 22
54 #define LINE1L_2_RADC_CTRL 24
55 /* Line2 Input control registers */
56 #define LINE2L_2_LADC_CTRL 20
57 #define LINE2R_2_RADC_CTRL 23
58 /* MICBIAS Control Register */
59 #define MICBIAS_CTRL 25
61 /* AGC Control Registers A, B, C */
62 #define LAGC_CTRL_A 26
63 #define LAGC_CTRL_B 27
64 #define LAGC_CTRL_C 28
65 #define RAGC_CTRL_A 29
66 #define RAGC_CTRL_B 30
67 #define RAGC_CTRL_C 31
69 /* DAC Power and Left High Power Output control registers */
72 /* Right High Power Output control registers */
74 /* DAC Output Switching control registers */
75 #define DAC_LINE_MUX 41
76 /* High Power Output Driver Pop Reduction registers */
77 #define HPOUT_POP_REDUCTION 42
78 /* DAC Digital control registers */
81 /* High Power Output control registers */
82 #define LINE2L_2_HPLOUT_VOL 45
83 #define LINE2R_2_HPROUT_VOL 62
84 #define PGAL_2_HPLOUT_VOL 46
85 #define PGAR_2_HPROUT_VOL 63
86 #define DACL1_2_HPLOUT_VOL 47
87 #define DACR1_2_HPROUT_VOL 64
88 #define HPLOUT_CTRL 51
89 #define HPROUT_CTRL 65
90 /* High Power COM control registers */
91 #define LINE2L_2_HPLCOM_VOL 52
92 #define LINE2R_2_HPRCOM_VOL 69
93 #define PGAL_2_HPLCOM_VOL 53
94 #define PGAR_2_HPRCOM_VOL 70
95 #define DACL1_2_HPLCOM_VOL 54
96 #define DACR1_2_HPRCOM_VOL 71
97 #define HPLCOM_CTRL 58
98 #define HPRCOM_CTRL 72
99 /* Mono Line Output Plus/Minus control registers */
100 #define LINE2L_2_MONOLOPM_VOL 73
101 #define LINE2R_2_MONOLOPM_VOL 76
102 #define PGAL_2_MONOLOPM_VOL 74
103 #define PGAR_2_MONOLOPM_VOL 77
104 #define DACL1_2_MONOLOPM_VOL 75
105 #define DACR1_2_MONOLOPM_VOL 78
106 #define MONOLOPM_CTRL 79
107 /* Line Output Plus/Minus control registers */
108 #define LINE2L_2_LLOPM_VOL 80
109 #define LINE2R_2_RLOPM_VOL 90
110 #define PGAL_2_LLOPM_VOL 81
111 #define PGAR_2_RLOPM_VOL 91
112 #define DACL1_2_LLOPM_VOL 82
113 #define DACR1_2_RLOPM_VOL 92
114 #define LLOPM_CTRL 86
115 #define RLOPM_CTRL 93
116 /* GPIO/IRQ registers */
117 #define AIC3X_STICKY_IRQ_FLAGS_REG 96
118 #define AIC3X_RT_IRQ_FLAGS_REG 97
119 #define AIC3X_GPIO1_REG 98
120 #define AIC3X_GPIO2_REG 99
121 #define AIC3X_GPIOA_REG 100
122 #define AIC3X_GPIOB_REG 101
123 /* Clock generation control register */
124 #define AIC3X_CLKGEN_CTRL_REG 102
126 /* Page select register bits */
127 #define PAGE0_SELECT 0
128 #define PAGE1_SELECT 1
130 /* Audio serial data interface control register A bits */
131 #define BIT_CLK_MASTER 0x80
132 #define WORD_CLK_MASTER 0x40
134 /* Codec Datapath setup register 7 */
135 #define FSREF_44100 (1 << 7)
136 #define FSREF_48000 (0 << 7)
137 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
138 #define LDAC2LCH (0x1 << 3)
139 #define RDAC2RCH (0x1 << 1)
141 /* PLL registers bitfields */
146 #define PLLD_MSB_SHIFT 0
147 #define PLLD_LSB_SHIFT 2
149 /* Clock generation register bits */
150 #define CODEC_CLKIN_PLLDIV 0
151 #define CODEC_CLKIN_CLKDIV 1
152 #define PLL_CLKIN_SHIFT 4
153 #define MCLK_SOURCE 0x0
154 #define PLL_CLKDIV_SHIFT 0
156 /* Software reset register bits */
157 #define SOFT_RESET 0x80
159 /* PLL progrramming register A bits */
160 #define PLL_ENABLE 0x80
163 #define ROUTE_ON 0x80
170 #define LADC_PWR_ON 0x04
171 #define RADC_PWR_ON 0x04
172 #define LDAC_PWR_ON 0x80
173 #define RDAC_PWR_ON 0x40
174 #define HPLOUT_PWR_ON 0x01
175 #define HPROUT_PWR_ON 0x01
176 #define HPLCOM_PWR_ON 0x01
177 #define HPRCOM_PWR_ON 0x01
178 #define MONOLOPM_PWR_ON 0x01
179 #define LLOPM_PWR_ON 0x01
180 #define RLOPM_PWR_ON 0x01
182 #define INVERT_VOL(val) (0x7f - val)
184 /* Default output volume (inverted) */
185 #define DEFAULT_VOL INVERT_VOL(0x50)
186 /* Default input volume */
187 #define DEFAULT_GAIN 0x20
191 AIC3X_GPIO1_FUNC_DISABLED = 0,
192 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1,
193 AIC3X_GPIO1_FUNC_CLOCK_MUX = 2,
194 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3,
195 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4,
196 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5,
197 AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6,
198 AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7,
199 AIC3X_GPIO1_FUNC_INPUT = 8,
200 AIC3X_GPIO1_FUNC_OUTPUT = 9,
201 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10,
202 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11,
203 AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12,
204 AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13,
205 AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14,
206 AIC3X_GPIO1_FUNC_ALL_IRQ = 16
210 AIC3X_GPIO2_FUNC_DISABLED = 0,
211 AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2,
212 AIC3X_GPIO2_FUNC_INPUT = 3,
213 AIC3X_GPIO2_FUNC_OUTPUT = 4,
214 AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5,
215 AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8,
216 AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
217 AIC3X_GPIO2_FUNC_ALL_IRQ = 10,
218 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
219 AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
220 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13,
221 AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14,
222 AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15
225 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
226 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
227 int aic3x_headset_detected(struct snd_soc_codec *codec);
229 struct aic3x_setup_data {
231 unsigned short i2c_address;
232 unsigned int gpio_func[2];
235 extern struct snd_soc_dai aic3x_dai;
236 extern struct snd_soc_codec_device soc_codec_dev_aic3x;
238 #endif /* _AIC3X_H */