2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
50 #include "tlv320aic3x.h"
52 #define AIC3X_VERSION "0.2"
54 static int hp_dac_lim = 9;
55 module_param(hp_dac_lim, int, 0);
57 /* codec private data */
62 u16 coeff_cache[AIC3X_COEFF_CACHE_SIZE];
66 * AIC3X register cache
67 * We can't read the AIC3X register space when we are
68 * using 2 wire for device control, so we cache them instead.
69 * There is no point in caching the reset register
71 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
72 0x00, 0x00, 0x00, 0x10, /* 0 */
73 0x04, 0x00, 0x00, 0x00, /* 4 */
74 0x00, 0x00, 0x00, 0x01, /* 8 */
75 0x00, 0x00, 0x00, 0x80, /* 12 */
76 0x80, 0xff, 0xff, 0x78, /* 16 */
77 0x78, 0x78, 0x78, 0x78, /* 20 */
78 0x78, 0x00, 0x00, 0xfe, /* 24 */
79 0x00, 0x00, 0xfe, 0x00, /* 28 */
80 0x00, 0x00, 0x00, 0x00, /* 32 */
81 0x00, 0x00, 0x00, 0x00, /* 36 */
82 0x00, 0x00, 0x00, 0x80, /* 40 */
83 0x80, 0x00, 0x00, 0x00, /* 44 */
84 0x00, 0x00, 0x00, 0x04, /* 48 */
85 0x00, 0x00, 0x00, 0x00, /* 52 */
86 0x00, 0x00, 0x04, 0x00, /* 56 */
87 0x00, 0x00, 0x00, 0x00, /* 60 */
88 0x00, 0x04, 0x00, 0x00, /* 64 */
89 0x00, 0x00, 0x00, 0x00, /* 68 */
90 0x04, 0x00, 0x00, 0x00, /* 72 */
91 0x00, 0x00, 0x00, 0x00, /* 76 */
92 0x00, 0x00, 0x00, 0x00, /* 80 */
93 0x00, 0x00, 0x00, 0x00, /* 84 */
94 0x00, 0x00, 0x00, 0x00, /* 88 */
95 0x00, 0x00, 0x00, 0x00, /* 92 */
96 0x00, 0x00, 0x00, 0x00, /* 96 */
97 0x00, 0x00, 0x02, /* 100 */
100 /* Page 1 registers store 2s compliment 16-bit numbers used for
101 * coefficients for effects. Each number is in 2 register, MSB followed
102 * by LSB. Therefore this array contains AIC3X_CACHEREGNUM/2 + 1 items.
104 static const u16 aic3x_coeff[AIC3X_COEFF_CACHE_SIZE] =
107 0x6be3, 0x9666, 0x675d, 0x6be3, /* Reg 1 - 8 */
108 0x9666, 0x675d, 0x7d83, 0x84ee, /* 9 - 16 */
109 0x7d83, 0x84ee, 0x3955, 0xf32d, /* 17 - 24 */
110 0x537e, 0x6be3, 0x9666, 0x675d, /* 25 - 32 */
111 0x6be3, 0x9666, 0x675d, 0x7d83, /* 33 - 40 */
112 0x84ee, 0x7d83, 0x84ee, 0x3955, /* 41 - 48 */
113 0xf32d, 0x537e, 0x7fff, 0x0000, /* 49 - 56 */
114 0x0000, 0x0000, 0x0000, 0x0000, /* 57 - 64 */
115 0x3955, 0xf32d, 0x537e, 0x3955, /* 65 - 72 */
116 0xf32d, 0x537e, 0x0000, 0x0000, /* 73 - 80 */
117 0x0000, 0x0000, 0x0000, 0x0000, /* 81 - 88 */
118 0x0000, 0x0000, 0x0000, 0x0000, /* 89 - 96 */
119 0x0000, 0x0000, 0x0000, /* 97 - 102 */
123 * read aic3x register cache
125 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
128 u8 *cache = codec->reg_cache;
129 if (reg >= AIC3X_CACHEREGNUM)
134 static inline unsigned int aic3x_read_coeff_cache(struct snd_soc_codec *codec,
136 u16 *cache = ((struct aic3x_priv*)codec->private_data)->coeff_cache;
137 return cache[COEFF_OFFSET(reg)];
141 * write aic3x register cache
143 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
146 u8 *cache = codec->reg_cache;
147 if (reg >= AIC3X_CACHEREGNUM)
153 * write to the aic3x register space
155 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
161 * D15..D8 aic3x register offset
162 * D7...D0 register data
164 data[0] = reg & 0xff;
165 data[1] = value & 0xff;
167 if (codec->hw_write(codec->control_data, data, 2) == 2){
168 aic3x_write_reg_cache(codec, data[0], data[1]);
174 /* Write a coefficient to the page 1 registers. Switching the page is
175 * not done here and is left to the caller.
177 static int aic3x_write_coeff(struct snd_soc_codec *codec, unsigned int msbreg,
180 u8 i, values[2], data[2];
182 u16 *cache = ((struct aic3x_priv*)codec->private_data)->coeff_cache;
184 if (msbreg >= AIC3X_CACHEREGNUM)
187 /* Change to 2s compliment and break into MSB and LSB */
189 outp = 65536 + value;
193 values[0] = (outp >> 8) & 0xff;
194 values[1] = outp & 0xff;
196 for(i = 0; i < 2; i++){
197 data[0] = (msbreg + i) & 0xff;
198 data[1] = values[i] & 0xff;
200 if (codec->hw_write(codec->control_data, data, 2) != 2)
204 cache[COEFF_OFFSET(msbreg)] = outp;
209 * read from the aic3x register space
211 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
216 /* No read access is recommended if the chip is reset after use */
217 printk(KERN_ERR "%s(): Values are may be incorrect!\n", __func__);
219 if (codec->hw_read(codec->control_data, value, 1) != 1)
222 aic3x_write_reg_cache(codec, reg, *value);
227 * Reset for getting low power consumption after bypass paths
229 static void aic3x_reset(struct snd_soc_codec *codec)
231 u8 *cache = codec->reg_cache;
235 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
237 /* We do not rewrite page select nor reset again */
238 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) {
241 codec->hw_write(codec->control_data, data, 2);
245 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
246 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
247 .info = snd_soc_info_volsw, \
248 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
249 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
252 * All input lines are connected when !0xf and disconnected with 0xf bit field,
253 * so we have to use specific dapm_put call for input mixer
255 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
256 struct snd_ctl_elem_value *ucontrol)
258 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
259 struct soc_mixer_control *mc =
260 (struct soc_mixer_control *)kcontrol->private_value;
261 unsigned int reg = mc->reg;
262 unsigned int shift = mc->shift;
264 unsigned int mask = (1 << fls(max)) - 1;
265 unsigned int invert = mc->invert;
266 unsigned short val, val_mask;
268 struct snd_soc_dapm_path *path;
271 val = (ucontrol->value.integer.value[0] & mask);
279 val_mask = mask << shift;
282 mutex_lock(&widget->codec->mutex);
284 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
285 /* find dapm widget path assoc with kcontrol */
286 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
287 if (path->kcontrol != kcontrol)
290 /* found, now check type */
294 path->connect = invert ? 0 : 1;
296 /* old connection must be powered down */
297 path->connect = invert ? 1 : 0;
302 snd_soc_dapm_sync(widget->codec);
305 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
307 mutex_unlock(&widget->codec->mutex);
311 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
312 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
313 static const char *aic3x_left_hpcom_mux[] =
314 { "differential of HPLOUT", "constant VCM", "single-ended" };
315 static const char *aic3x_right_hpcom_mux[] =
316 { "differential of HPROUT", "constant VCM", "single-ended",
317 "differential of HPLCOM", "external feedback" };
318 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
319 static const char *aic3x_adc_hpf[] =
320 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
324 #define LHPCOM_ENUM 2
325 #define RHPCOM_ENUM 3
326 #define LINE1L_ENUM 4
327 #define LINE1R_ENUM 5
328 #define LINE2L_ENUM 6
329 #define LINE2R_ENUM 7
330 #define ADC_HPF_ENUM 8
332 static const struct soc_enum aic3x_enum[] = {
333 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
334 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
335 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
336 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
337 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
338 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
339 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
340 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
341 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
345 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
347 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
348 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
349 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
350 /* HP DAC Output gain values. From 0 to 9.0 dB in 1 dB steps */
351 static DECLARE_TLV_DB_SCALE(hpout_tlv, 0, 100, 0);
353 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
354 * Step size is approximately 0.5 dB over most of the scale but increasing
355 * near the very low levels.
356 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
357 * but having increasing dB difference below that (and where it doesn't count
358 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
359 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
361 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
363 #define SOC_DOUBLE_R_TLV_TLV320ALC3X(xname, reg_left, reg_right, xshift, xmax,\
364 xinvert, tlv_array) \
365 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
366 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
367 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
368 .tlv.p = (tlv_array), \
369 .info = tlv320alc3x_info_volsw, \
370 .get = snd_soc_get_volsw_2r,\
371 .put = snd_soc_put_volsw_2r,\
372 .private_value = (unsigned long)&(struct soc_mixer_control) \
373 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
374 .max = xmax, .invert = xinvert} }
376 static int tlv320alc3x_info_volsw(struct snd_kcontrol *kcontrol,
377 struct snd_ctl_elem_info *uinfo)
379 struct soc_mixer_control *mc =
380 (struct soc_mixer_control *)kcontrol->private_value;
383 if (hp_dac_lim != max && hp_dac_lim >= 2 && hp_dac_lim <= 9)
387 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
389 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
392 uinfo->value.integer.min = 0;
393 uinfo->value.integer.max = max;
398 static int snd_soc_get_3d_attenuation_aic3x(struct snd_kcontrol *kcontrol,
399 struct snd_ctl_elem_value *ucontrol)
401 int val = aic3x_read_coeff_cache(snd_kcontrol_chip(kcontrol), EFFECTS_3DATTEN);
404 val = ((val*100)/65530) + 50;
405 ucontrol->value.integer.value[0] = val;
409 static int snd_soc_put_3d_attenuation_aic3x(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
412 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
413 int reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
414 int val = ucontrol->value.integer.value[0];
417 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg | 0x04);
419 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & 0xfb);
422 val = ((val - 50) * 65535) / 100 ;
423 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE1_SELECT);
424 aic3x_write_coeff(codec, EFFECTS_3DATTEN, val);
425 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
430 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
432 SOC_DOUBLE_R_TLV("PCM Playback Volume",
433 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
435 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
436 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
437 0, 118, 1, output_stage_tlv),
438 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
440 SOC_DOUBLE_R_TLV("Line PGA Bypass Playback Volume",
441 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
442 0, 118, 1, output_stage_tlv),
443 SOC_DOUBLE_R_TLV("Line Line2 Bypass Playback Volume",
444 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
445 0, 118, 1, output_stage_tlv),
447 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
448 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
449 0, 118, 1, output_stage_tlv),
450 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
451 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
452 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
453 0, 118, 1, output_stage_tlv),
454 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
455 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
456 0, 118, 1, output_stage_tlv),
458 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
459 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
460 0, 118, 1, output_stage_tlv),
461 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
463 SOC_DOUBLE_R_TLV_TLV320ALC3X("HP DAC Output Volume", HPLOUT_CTRL,
464 HPROUT_CTRL, 4, 9, 0, hpout_tlv),
465 SOC_DOUBLE_R_TLV("HP PGA Bypass Playback Volume",
466 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
467 0, 118, 1, output_stage_tlv),
468 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
469 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
470 0, 118, 1, output_stage_tlv),
472 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
473 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
474 0, 118, 1, output_stage_tlv),
475 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
477 SOC_DOUBLE_R_TLV_TLV320ALC3X("HPCOM DAC Output Volume", HPLCOM_CTRL,
478 HPRCOM_CTRL, 4, 9, 0, hpout_tlv),
479 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Playback Volume",
480 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
481 0, 118, 1, output_stage_tlv),
482 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
483 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
484 0, 118, 1, output_stage_tlv),
487 * Note: enable Automatic input Gain Controller with care. It can
488 * adjust PGA to max value when ADC is on and will never go back.
490 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
493 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
495 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
497 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
499 SOC_SINGLE_EXT("3D Control - Depth", EFFECTS_3DATTEN, 0, 100, 0,
500 snd_soc_get_3d_attenuation_aic3x, snd_soc_put_3d_attenuation_aic3x),
503 /* add non dapm controls */
504 static int aic3x_add_controls(struct snd_soc_codec *codec)
508 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
509 err = snd_ctl_add(codec->card,
510 snd_soc_cnew(&aic3x_snd_controls[i],
519 static int reset_after_bypass(struct snd_soc_dapm_widget *w,
520 struct snd_kcontrol *kcontrol, int event)
522 struct aic3x_priv *aic3x = w->codec->private_data;
523 struct soc_mixer_control *mc = NULL;
524 unsigned int reg = 0;
527 mc = (struct soc_mixer_control *)kcontrol->private_value;
531 if (reg == PGAL_2_LLOPM_VOL || reg == PGAR_2_RLOPM_VOL ||
532 reg == PGAL_2_HPLOUT_VOL || reg == PGAR_2_HPROUT_VOL) {
533 if (w->value & 0x80) {
534 /* Prepare reset on the chip */
535 if (reg == PGAL_2_LLOPM_VOL)
536 aic3x->prepare_reset |= 0x01;
537 else if (reg == PGAR_2_RLOPM_VOL)
538 aic3x->prepare_reset |= 0x02;
539 else if (reg == PGAL_2_HPLOUT_VOL)
540 aic3x->prepare_reset |= 0x04;
541 else if (reg == PGAR_2_HPROUT_VOL)
542 aic3x->prepare_reset |= 0x08;
544 if (aic3x->prepare_reset) {
545 if (reg == PGAL_2_LLOPM_VOL)
546 aic3x->prepare_reset &= ~0x01;
547 else if (reg == PGAR_2_RLOPM_VOL)
548 aic3x->prepare_reset &= ~0x02;
549 else if (reg == PGAL_2_HPLOUT_VOL)
550 aic3x->prepare_reset &= ~0x04;
551 else if (reg == PGAR_2_HPROUT_VOL)
552 aic3x->prepare_reset &= ~0x08;
554 * Controls may have now been turned off,
555 * once they were on, so schedule or
556 * issue a reset on the chip.
558 if (!aic3x->prepare_reset) {
559 if (!((w->codec->bias_level ==
561 (w->codec->bias_level ==
562 SND_SOC_BIAS_PREPARE)))
563 aic3x_reset(w->codec);
573 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
574 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
577 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
578 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
581 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
582 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
584 /* Right HPCOM Mux */
585 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
586 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
588 /* Left DAC_L1 Mixer */
589 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
590 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
591 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
592 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
593 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
596 /* Right DAC_R1 Mixer */
597 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
598 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
599 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
600 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
601 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
605 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
606 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
607 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
608 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
611 /* Right PGA Mixer */
612 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
613 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
614 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
615 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
616 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
620 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
621 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
623 /* Right Line1 Mux */
624 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
625 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
628 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
629 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
631 /* Right Line2 Mux */
632 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
633 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
635 /* Left PGA Bypass Mixer */
636 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
637 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
638 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
639 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
640 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
643 /* Right PGA Bypass Mixer */
644 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
645 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
646 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
647 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
648 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
651 /* Left Line2 Bypass Mixer */
652 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
653 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
654 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
655 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
656 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
659 /* Right Line2 Bypass Mixer */
660 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
661 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
662 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
663 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
664 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
667 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
668 /* Left DAC to Left Outputs */
669 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
670 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
671 &aic3x_left_dac_mux_controls),
672 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
673 &aic3x_left_dac_mixer_controls[0],
674 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
675 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
676 &aic3x_left_hpcom_mux_controls),
677 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
678 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
679 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
681 /* Right DAC to Right Outputs */
682 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
683 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
684 &aic3x_right_dac_mux_controls),
685 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
686 &aic3x_right_dac_mixer_controls[0],
687 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
688 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
689 &aic3x_right_hpcom_mux_controls),
690 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
691 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
692 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
695 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
697 /* Left Inputs to Left ADC */
698 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
699 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
700 &aic3x_left_pga_mixer_controls[0],
701 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
702 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
703 &aic3x_left_line1_mux_controls),
704 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
705 &aic3x_left_line2_mux_controls),
707 /* Right Inputs to Right ADC */
708 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
709 LINE1R_2_RADC_CTRL, 2, 0),
710 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
711 &aic3x_right_pga_mixer_controls[0],
712 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
713 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
714 &aic3x_right_line1_mux_controls),
715 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
716 &aic3x_right_line1_mux_controls),
717 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
718 &aic3x_right_line2_mux_controls),
721 * Not a real mic bias widget but similar function. This is for dynamic
722 * control of GPIO1 digital mic modulator clock output function when
725 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
726 AIC3X_GPIO1_REG, 4, 0xf,
727 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
728 AIC3X_GPIO1_FUNC_DISABLED),
731 * Also similar function like mic bias. Selects digital mic with
732 * configurable oversampling rate instead of ADC converter.
734 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
735 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
736 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
737 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
738 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
739 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
742 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
743 MICBIAS_CTRL, 6, 3, 1, 0),
744 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
745 MICBIAS_CTRL, 6, 3, 2, 0),
746 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
747 MICBIAS_CTRL, 6, 3, 3, 0),
749 /* Left PGA to Left Output bypass */
750 SND_SOC_DAPM_MIXER_E("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
751 &aic3x_left_pga_bp_mixer_controls[0],
752 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls),
753 reset_after_bypass, SND_SOC_DAPM_POST_REG),
755 /* Right PGA to Right Output bypass */
756 SND_SOC_DAPM_MIXER_E("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
757 &aic3x_right_pga_bp_mixer_controls[0],
758 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls),
759 reset_after_bypass, SND_SOC_DAPM_POST_REG),
761 /* Left Line2 to Left Output bypass */
762 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
763 &aic3x_left_line2_bp_mixer_controls[0],
764 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
766 /* Right Line2 to Right Output bypass */
767 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
768 &aic3x_right_line2_bp_mixer_controls[0],
769 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
771 SND_SOC_DAPM_OUTPUT("LLOUT"),
772 SND_SOC_DAPM_OUTPUT("RLOUT"),
773 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
774 SND_SOC_DAPM_OUTPUT("HPLOUT"),
775 SND_SOC_DAPM_OUTPUT("HPROUT"),
776 SND_SOC_DAPM_OUTPUT("HPLCOM"),
777 SND_SOC_DAPM_OUTPUT("HPRCOM"),
779 SND_SOC_DAPM_INPUT("MIC3L"),
780 SND_SOC_DAPM_INPUT("MIC3R"),
781 SND_SOC_DAPM_INPUT("LINE1L"),
782 SND_SOC_DAPM_INPUT("LINE1R"),
783 SND_SOC_DAPM_INPUT("LINE2L"),
784 SND_SOC_DAPM_INPUT("LINE2R"),
787 static const struct snd_soc_dapm_route intercon[] = {
789 {"Left DAC Mux", "DAC_L1", "Left DAC"},
790 {"Left DAC Mux", "DAC_L2", "Left DAC"},
791 {"Left DAC Mux", "DAC_L3", "Left DAC"},
793 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
794 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
795 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
796 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
797 {"Left Line Out", NULL, "Left DAC Mux"},
798 {"Left HP Out", NULL, "Left DAC Mux"},
800 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
801 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
802 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
804 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
805 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
806 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
807 {"Left HP Com", NULL, "Left HPCOM Mux"},
809 {"LLOUT", NULL, "Left Line Out"},
810 {"LLOUT", NULL, "Left Line Out"},
811 {"HPLOUT", NULL, "Left HP Out"},
812 {"HPLCOM", NULL, "Left HP Com"},
815 {"Right DAC Mux", "DAC_R1", "Right DAC"},
816 {"Right DAC Mux", "DAC_R2", "Right DAC"},
817 {"Right DAC Mux", "DAC_R3", "Right DAC"},
819 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
820 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
821 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
822 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
823 {"Right Line Out", NULL, "Right DAC Mux"},
824 {"Right HP Out", NULL, "Right DAC Mux"},
826 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
827 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
828 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
829 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
830 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
832 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
833 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
834 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
835 {"Right HP Com", NULL, "Right HPCOM Mux"},
837 {"RLOUT", NULL, "Right Line Out"},
838 {"RLOUT", NULL, "Right Line Out"},
839 {"HPROUT", NULL, "Right HP Out"},
840 {"HPRCOM", NULL, "Right HP Com"},
843 {"MONO_LOUT", NULL, "Mono Out"},
844 {"MONO_LOUT", NULL, "Mono Out"},
847 {"Left Line1L Mux", "single-ended", "LINE1L"},
848 {"Left Line1L Mux", "differential", "LINE1L"},
850 {"Left Line2L Mux", "single-ended", "LINE2L"},
851 {"Left Line2L Mux", "differential", "LINE2L"},
853 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
854 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
855 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
857 {"Left ADC", NULL, "Left PGA Mixer"},
858 {"Left ADC", NULL, "GPIO1 dmic modclk"},
861 {"Right Line1L Mux", "single-ended", "LINE1L"},
862 {"Right Line1L Mux", "differential", "LINE1L"},
864 {"Right Line1R Mux", "single-ended", "LINE1R"},
865 {"Right Line1R Mux", "differential", "LINE1R"},
867 {"Right Line2R Mux", "single-ended", "LINE2R"},
868 {"Right Line2R Mux", "differential", "LINE2R"},
870 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
871 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
872 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
873 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
875 {"Right ADC", NULL, "Right PGA Mixer"},
876 {"Right ADC", NULL, "GPIO1 dmic modclk"},
878 /* Left PGA Bypass */
879 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
880 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
881 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
882 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
884 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
885 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
886 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
888 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
889 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
890 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
892 /* Right PGA Bypass */
893 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
894 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
895 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
896 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
898 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
899 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
900 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
901 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
902 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
904 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
905 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
906 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
908 /* Left Line2 Bypass */
909 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
910 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
911 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
912 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
914 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
915 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
916 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
918 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
919 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
920 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
922 /* Right Line2 Bypass */
923 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
924 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
925 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
926 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
928 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
929 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
930 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
931 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
932 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
934 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
935 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
936 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
939 * Logical path between digital mic enable and GPIO1 modulator clock
942 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
943 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
944 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
947 static int aic3x_add_widgets(struct snd_soc_codec *codec)
949 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
950 ARRAY_SIZE(aic3x_dapm_widgets));
952 /* set up audio path interconnects */
953 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
955 snd_soc_dapm_new_widgets(codec);
959 static int aic3x_hw_params(struct snd_pcm_substream *substream,
960 struct snd_pcm_hw_params *params)
962 struct snd_soc_pcm_runtime *rtd = substream->private_data;
963 struct snd_soc_device *socdev = rtd->socdev;
964 struct snd_soc_codec *codec = socdev->codec;
965 struct aic3x_priv *aic3x = codec->private_data;
966 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
967 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
970 /* select data word length */
972 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
973 switch (params_format(params)) {
974 case SNDRV_PCM_FORMAT_S16_LE:
976 case SNDRV_PCM_FORMAT_S20_3LE:
979 case SNDRV_PCM_FORMAT_S24_LE:
982 case SNDRV_PCM_FORMAT_S32_LE:
986 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
988 /* Fsref can be 44100 or 48000 */
989 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
991 /* Try to find a value for Q which allows us to bypass the PLL and
992 * generate CODEC_CLK directly. */
993 for (pll_q = 2; pll_q < 18; pll_q++)
994 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1001 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1002 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1004 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1006 /* Route Left DAC to left channel input and
1007 * right DAC to right channel input */
1008 data = (LDAC2LCH | RDAC2RCH);
1009 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1010 if (params_rate(params) >= 64000)
1011 data |= DUAL_RATE_MODE;
1012 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
1014 /* codec sample rate select */
1015 data = (fsref * 20) / params_rate(params);
1016 if (params_rate(params) < 64000)
1020 data |= (data << 4);
1021 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
1027 * find an apropriate setup for j, d, r and p by iterating over
1028 * p and r - j and d are calculated for each fraction.
1029 * Up to 128 values are probed, the closest one wins the game.
1030 * The sysclk is divided by 1000 to prevent integer overflows.
1032 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1034 for (r = 1; r <= 16; r++)
1035 for (p = 1; p <= 8; p++) {
1036 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
1038 u16 d = tmp % 10000;
1043 if (d != 0 && aic3x->sysclk < 10000000)
1046 /* This is actually 1000 * ((j + (d/10000)) * r) / p
1047 * The term had to be converted to get rid of the
1048 * division by 10000 */
1049 clk = ((10000 * j * r) + (d * r)) / (10 * p);
1051 /* check whether this values get closer than the best
1052 * ones we had before */
1053 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1054 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
1058 /* Early exit for exact matches */
1059 if (clk == codec_clk)
1063 if (last_clk == 0) {
1064 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1068 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1069 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
1070 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
1071 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1072 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
1073 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
1074 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1079 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1081 struct snd_soc_codec *codec = dai->codec;
1082 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
1083 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
1086 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1087 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1089 aic3x_write(codec, LDAC_VOL, ldac_reg);
1090 aic3x_write(codec, RDAC_VOL, rdac_reg);
1096 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1097 int clk_id, unsigned int freq, int dir)
1099 struct snd_soc_codec *codec = codec_dai->codec;
1100 struct aic3x_priv *aic3x = codec->private_data;
1102 aic3x->sysclk = freq;
1106 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1109 struct snd_soc_codec *codec = codec_dai->codec;
1110 struct aic3x_priv *aic3x = codec->private_data;
1111 u8 iface_areg, iface_breg;
1114 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1115 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1117 /* set master/slave audio interface */
1118 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1119 case SND_SOC_DAIFMT_CBM_CFM:
1121 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1123 case SND_SOC_DAIFMT_CBS_CFS:
1131 * match both interface format and signal polarities since they
1134 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1135 SND_SOC_DAIFMT_INV_MASK)) {
1136 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1138 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1140 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1141 iface_breg |= (0x01 << 6);
1143 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1144 iface_breg |= (0x02 << 6);
1146 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1147 iface_breg |= (0x03 << 6);
1154 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1155 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1156 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1161 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1162 enum snd_soc_bias_level level)
1164 struct aic3x_priv *aic3x = codec->private_data;
1168 case SND_SOC_BIAS_ON:
1169 /* all power is driven by DAPM system */
1170 if (aic3x->master) {
1172 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1173 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1176 * ensure that bit and word clocks are running also if
1177 * DAC and ADC are shutdown
1179 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1180 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg | 0x10);
1183 case SND_SOC_BIAS_PREPARE:
1185 case SND_SOC_BIAS_STANDBY:
1187 * all power is driven by DAPM system,
1188 * so output power is safe if bypass was set
1190 if (aic3x->master) {
1191 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1192 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1194 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1195 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1198 /* Reset cannot be issued, if bypass paths are in use */
1199 if (!aic3x->prepare_reset)
1202 case SND_SOC_BIAS_OFF:
1203 /* force all power off */
1204 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1205 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1206 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1207 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1209 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1210 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1212 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1213 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1214 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1215 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1217 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1218 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1219 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1220 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1222 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1223 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1225 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1226 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1227 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1228 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1230 if (aic3x->master) {
1231 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1232 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1234 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1235 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1240 codec->bias_level = level;
1245 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1247 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1248 u8 bit = gpio ? 3: 0;
1249 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1250 aic3x_write(codec, reg, val | (!!state << bit));
1252 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1254 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1256 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1257 u8 val, bit = gpio ? 2: 1;
1259 aic3x_read(codec, reg, &val);
1260 return (val >> bit) & 1;
1262 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1264 int aic3x_headset_detected(struct snd_soc_codec *codec)
1267 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
1268 return (val >> 2) & 1;
1270 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1272 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1273 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1274 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1276 struct snd_soc_dai aic3x_dai = {
1277 .name = "tlv320aic3x",
1279 .stream_name = "Playback",
1282 .rates = AIC3X_RATES,
1283 .formats = AIC3X_FORMATS,},
1285 .stream_name = "Capture",
1288 .rates = AIC3X_RATES,
1289 .formats = AIC3X_FORMATS,},
1291 .hw_params = aic3x_hw_params,
1294 .digital_mute = aic3x_mute,
1295 .set_sysclk = aic3x_set_dai_sysclk,
1296 .set_fmt = aic3x_set_dai_fmt,
1299 EXPORT_SYMBOL_GPL(aic3x_dai);
1301 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1303 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1304 struct snd_soc_codec *codec = socdev->codec;
1306 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1311 static int aic3x_resume(struct platform_device *pdev)
1313 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1314 struct snd_soc_codec *codec = socdev->codec;
1317 u8 *reg_cache = codec->reg_cache;
1318 u16 *coeff_cache = ((struct aic3x_priv*)codec->private_data)->coeff_cache;
1320 /* Sync hardware with the coeff_cache first so that filters can be
1323 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE1_SELECT);
1324 for (i = 1; i < ARRAY_SIZE(aic3x_coeff); i++){
1326 data[1] = (coeff_cache[i] >> 8) && 0xff;
1327 codec->hw_write(codec->control_data, data, 2);
1330 data[1] = coeff_cache[i] & 0xff;
1331 codec->hw_write(codec->control_data, data, 2);
1334 /* Sync hardware with the reg_cache */
1335 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1336 for (i = 1; i < ARRAY_SIZE(aic3x_reg); i++) {
1338 data[1] = reg_cache[i];
1339 codec->hw_write(codec->control_data, data, 2);
1342 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1348 * initialise the AIC3X driver
1349 * register the mixer and dsp interfaces with the kernel
1351 static int aic3x_init(struct snd_soc_device *socdev)
1353 struct snd_soc_codec *codec = socdev->codec;
1354 struct aic3x_setup_data *setup = socdev->codec_data;
1357 codec->name = "tlv320aic3x";
1358 codec->owner = THIS_MODULE;
1359 codec->read = aic3x_read_reg_cache;
1360 codec->write = aic3x_write;
1361 codec->set_bias_level = aic3x_set_bias_level;
1362 codec->dai = &aic3x_dai;
1364 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1365 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1366 if (codec->reg_cache == NULL)
1369 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1370 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1373 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1375 printk(KERN_ERR "aic3x: failed to create pcms\n");
1379 /* DAC default volume and mute */
1380 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1381 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1383 /* DAC to HP default volume and route to Output mixer */
1384 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1385 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1386 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1387 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1388 /* DAC to Line Out default volume and route to Output mixer */
1389 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1390 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1391 /* DAC to Mono Line Out default volume and route to Output mixer */
1392 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1393 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1395 /* unmute all outputs */
1396 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1397 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1398 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1399 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1400 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1401 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1402 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1403 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1404 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1405 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1406 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1407 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1408 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1409 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1411 /* ADC default volume and unmute */
1412 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1413 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1414 /* By default route Line1 to ADC PGA mixer */
1415 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1416 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1418 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1419 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1420 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1421 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1422 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1423 /* PGA to Line Out default volume, disconnect from Output Mixer */
1424 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1425 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1426 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1427 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1428 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1430 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1431 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1432 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1433 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1434 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1435 /* Line2 Line Out default volume, disconnect from Output Mixer */
1436 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1437 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1438 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1439 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1440 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1442 /* off, with power on */
1443 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1445 /* setup GPIO functions */
1446 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1447 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1449 aic3x_add_controls(codec);
1450 aic3x_add_widgets(codec);
1451 ret = snd_soc_register_card(socdev);
1453 printk(KERN_ERR "aic3x: failed to register card\n");
1457 /* Set some defaults for coefficients */
1458 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE1_SELECT);
1459 aic3x_write_coeff(codec, EFFECTS_3DATTEN, -32768);
1460 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1465 snd_soc_free_pcms(socdev);
1466 snd_soc_dapm_free(socdev);
1468 kfree(codec->reg_cache);
1472 static struct snd_soc_device *aic3x_socdev;
1474 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1476 * AIC3X 2 wire address can be up to 4 devices with device addresses
1477 * 0x18, 0x19, 0x1A, 0x1B
1481 * If the i2c layer weren't so broken, we could pass this kind of data
1484 static int aic3x_i2c_probe(struct i2c_client *i2c,
1485 const struct i2c_device_id *id)
1487 struct snd_soc_device *socdev = aic3x_socdev;
1488 struct snd_soc_codec *codec = socdev->codec;
1491 i2c_set_clientdata(i2c, codec);
1492 codec->control_data = i2c;
1494 ret = aic3x_init(socdev);
1496 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1500 static int aic3x_i2c_remove(struct i2c_client *client)
1502 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1503 kfree(codec->reg_cache);
1507 static const struct i2c_device_id aic3x_i2c_id[] = {
1508 { "tlv320aic3x", 0 },
1511 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1513 /* machine i2c codec control layer */
1514 static struct i2c_driver aic3x_i2c_driver = {
1516 .name = "aic3x I2C Codec",
1517 .owner = THIS_MODULE,
1519 .probe = aic3x_i2c_probe,
1520 .remove = aic3x_i2c_remove,
1521 .id_table = aic3x_i2c_id,
1524 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1526 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1530 static int aic3x_add_i2c_device(struct platform_device *pdev,
1531 const struct aic3x_setup_data *setup)
1533 struct i2c_board_info info;
1534 struct i2c_adapter *adapter;
1535 struct i2c_client *client;
1538 ret = i2c_add_driver(&aic3x_i2c_driver);
1540 dev_err(&pdev->dev, "can't add i2c driver\n");
1544 memset(&info, 0, sizeof(struct i2c_board_info));
1545 info.addr = setup->i2c_address;
1546 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1548 adapter = i2c_get_adapter(setup->i2c_bus);
1550 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1555 client = i2c_new_device(adapter, &info);
1556 i2c_put_adapter(adapter);
1558 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1559 (unsigned int)info.addr);
1566 i2c_del_driver(&aic3x_i2c_driver);
1571 static int aic3x_probe(struct platform_device *pdev)
1573 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1574 struct aic3x_setup_data *setup;
1575 struct snd_soc_codec *codec;
1576 struct aic3x_priv *aic3x;
1579 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1581 setup = socdev->codec_data;
1582 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1586 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1587 memcpy(aic3x->coeff_cache, aic3x_coeff, sizeof(aic3x_coeff));
1589 if (aic3x == NULL) {
1594 codec->private_data = aic3x;
1595 socdev->codec = codec;
1596 mutex_init(&codec->mutex);
1597 INIT_LIST_HEAD(&codec->dapm_widgets);
1598 INIT_LIST_HEAD(&codec->dapm_paths);
1600 aic3x_socdev = socdev;
1601 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1602 if (setup->i2c_address) {
1603 codec->hw_write = (hw_write_t) i2c_master_send;
1604 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1605 ret = aic3x_add_i2c_device(pdev, setup);
1608 /* Add other interfaces here */
1612 kfree(codec->private_data);
1618 static int aic3x_remove(struct platform_device *pdev)
1620 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1621 struct snd_soc_codec *codec = socdev->codec;
1623 /* power down chip */
1624 if (codec->control_data)
1625 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1627 snd_soc_free_pcms(socdev);
1628 snd_soc_dapm_free(socdev);
1629 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1630 if (codec->control_data)
1631 i2c_unregister_device(codec->control_data);
1632 i2c_del_driver(&aic3x_i2c_driver);
1634 kfree(codec->private_data);
1640 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1641 .probe = aic3x_probe,
1642 .remove = aic3x_remove,
1643 .suspend = aic3x_suspend,
1644 .resume = aic3x_resume,
1646 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1648 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1649 MODULE_AUTHOR("Vladimir Barinov");
1650 MODULE_LICENSE("GPL");