2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
50 #include "tlv320aic3x.h"
52 #define AIC3X_VERSION "0.2"
54 static int hp_dac_lim = 9;
55 module_param(hp_dac_lim, int, 0);
57 /* codec private data */
65 * AIC3X register cache
66 * We can't read the AIC3X register space when we are
67 * using 2 wire for device control, so we cache them instead.
68 * There is no point in caching the reset register
70 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
71 0x00, 0x00, 0x00, 0x10, /* 0 */
72 0x04, 0x00, 0x00, 0x00, /* 4 */
73 0x00, 0x00, 0x00, 0x01, /* 8 */
74 0x00, 0x00, 0x00, 0x80, /* 12 */
75 0x80, 0xff, 0xff, 0x78, /* 16 */
76 0x78, 0x78, 0x78, 0x78, /* 20 */
77 0x78, 0x00, 0x00, 0xfe, /* 24 */
78 0x00, 0x00, 0xfe, 0x00, /* 28 */
79 0x00, 0x00, 0x00, 0x00, /* 32 */
80 0x00, 0x00, 0x00, 0x00, /* 36 */
81 0x00, 0x00, 0x00, 0x80, /* 40 */
82 0x80, 0x00, 0x00, 0x00, /* 44 */
83 0x00, 0x00, 0x00, 0x04, /* 48 */
84 0x00, 0x00, 0x00, 0x00, /* 52 */
85 0x00, 0x00, 0x04, 0x00, /* 56 */
86 0x00, 0x00, 0x00, 0x00, /* 60 */
87 0x00, 0x04, 0x00, 0x00, /* 64 */
88 0x00, 0x00, 0x00, 0x00, /* 68 */
89 0x04, 0x00, 0x00, 0x00, /* 72 */
90 0x00, 0x00, 0x00, 0x00, /* 76 */
91 0x00, 0x00, 0x00, 0x00, /* 80 */
92 0x00, 0x00, 0x00, 0x00, /* 84 */
93 0x00, 0x00, 0x00, 0x00, /* 88 */
94 0x00, 0x00, 0x00, 0x00, /* 92 */
95 0x00, 0x00, 0x00, 0x00, /* 96 */
96 0x00, 0x00, 0x02, /* 100 */
100 * read aic3x register cache
102 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
105 u8 *cache = codec->reg_cache;
106 if (reg >= AIC3X_CACHEREGNUM)
112 * write aic3x register cache
114 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
117 u8 *cache = codec->reg_cache;
118 if (reg >= AIC3X_CACHEREGNUM)
124 * write to the aic3x register space
126 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
132 * D15..D8 aic3x register offset
133 * D7...D0 register data
135 data[0] = reg & 0xff;
136 data[1] = value & 0xff;
138 aic3x_write_reg_cache(codec, data[0], data[1]);
139 if (codec->hw_write(codec->control_data, data, 2) == 2)
146 * read from the aic3x register space
148 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
153 /* No read access is recommended if the chip is reset after use */
154 printk(KERN_ERR "%s(): Values are may be incorrect!\n", __func__);
156 if (codec->hw_read(codec->control_data, value, 1) != 1)
159 aic3x_write_reg_cache(codec, reg, *value);
164 * Reset for getting low power consumption after bypass paths
166 static void aic3x_reset(struct snd_soc_codec *codec)
168 u8 *cache = codec->reg_cache;
172 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
174 /* We do not rewrite page select nor reset again */
175 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) {
178 codec->hw_write(codec->control_data, data, 2);
182 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
183 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
184 .info = snd_soc_info_volsw, \
185 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
186 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
189 * All input lines are connected when !0xf and disconnected with 0xf bit field,
190 * so we have to use specific dapm_put call for input mixer
192 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
193 struct snd_ctl_elem_value *ucontrol)
195 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
196 struct soc_mixer_control *mc =
197 (struct soc_mixer_control *)kcontrol->private_value;
198 unsigned int reg = mc->reg;
199 unsigned int shift = mc->shift;
201 unsigned int mask = (1 << fls(max)) - 1;
202 unsigned int invert = mc->invert;
203 unsigned short val, val_mask;
205 struct snd_soc_dapm_path *path;
208 val = (ucontrol->value.integer.value[0] & mask);
216 val_mask = mask << shift;
219 mutex_lock(&widget->codec->mutex);
221 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
222 /* find dapm widget path assoc with kcontrol */
223 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
224 if (path->kcontrol != kcontrol)
227 /* found, now check type */
231 path->connect = invert ? 0 : 1;
233 /* old connection must be powered down */
234 path->connect = invert ? 1 : 0;
239 snd_soc_dapm_sync(widget->codec);
242 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
244 mutex_unlock(&widget->codec->mutex);
248 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
249 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
250 static const char *aic3x_left_hpcom_mux[] =
251 { "differential of HPLOUT", "constant VCM", "single-ended" };
252 static const char *aic3x_right_hpcom_mux[] =
253 { "differential of HPROUT", "constant VCM", "single-ended",
254 "differential of HPLCOM", "external feedback" };
255 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
256 static const char *aic3x_adc_hpf[] =
257 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
261 #define LHPCOM_ENUM 2
262 #define RHPCOM_ENUM 3
263 #define LINE1L_ENUM 4
264 #define LINE1R_ENUM 5
265 #define LINE2L_ENUM 6
266 #define LINE2R_ENUM 7
267 #define ADC_HPF_ENUM 8
269 static const struct soc_enum aic3x_enum[] = {
270 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
271 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
272 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
273 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
274 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
275 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
276 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
277 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
278 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
282 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
284 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
285 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
286 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
287 /* HP DAC Output gain values. From 0 to 9.0 dB in 1 dB steps */
288 static DECLARE_TLV_DB_SCALE(hpout_tlv, 0, 100, 0);
290 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
291 * Step size is approximately 0.5 dB over most of the scale but increasing
292 * near the very low levels.
293 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
294 * but having increasing dB difference below that (and where it doesn't count
295 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
296 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
298 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
300 #define SOC_DOUBLE_R_TLV_TLV320ALC3X(xname, reg_left, reg_right, xshift, xmax,\
301 xinvert, tlv_array) \
302 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
303 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
304 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
305 .tlv.p = (tlv_array), \
306 .info = tlv320alc3x_info_volsw, \
307 .get = snd_soc_get_volsw_2r,\
308 .put = snd_soc_put_volsw_2r,\
309 .private_value = (unsigned long)&(struct soc_mixer_control) \
310 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
311 .max = xmax, .invert = xinvert} }
313 static int tlv320alc3x_info_volsw(struct snd_kcontrol *kcontrol,
314 struct snd_ctl_elem_info *uinfo)
316 struct soc_mixer_control *mc =
317 (struct soc_mixer_control *)kcontrol->private_value;
320 if (hp_dac_lim != max && hp_dac_lim >= 2 && hp_dac_lim <= 9)
324 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
326 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
329 uinfo->value.integer.min = 0;
330 uinfo->value.integer.max = max;
334 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
336 SOC_DOUBLE_R_TLV("PCM Playback Volume",
337 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
339 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
340 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
341 0, 118, 1, output_stage_tlv),
342 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
344 SOC_DOUBLE_R_TLV("Line PGA Bypass Playback Volume",
345 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
346 0, 118, 1, output_stage_tlv),
347 SOC_DOUBLE_R_TLV("Line Line2 Bypass Playback Volume",
348 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
349 0, 118, 1, output_stage_tlv),
351 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
352 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
353 0, 118, 1, output_stage_tlv),
354 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
355 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
356 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
357 0, 118, 1, output_stage_tlv),
358 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
359 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
360 0, 118, 1, output_stage_tlv),
362 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
363 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
364 0, 118, 1, output_stage_tlv),
365 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
367 SOC_DOUBLE_R_TLV_TLV320ALC3X("HP DAC Output Volume", HPLOUT_CTRL,
368 HPROUT_CTRL, 4, 9, 0, hpout_tlv),
369 SOC_DOUBLE_R_TLV("HP PGA Bypass Playback Volume",
370 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
371 0, 118, 1, output_stage_tlv),
372 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
373 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
374 0, 118, 1, output_stage_tlv),
376 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
377 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
378 0, 118, 1, output_stage_tlv),
379 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
381 SOC_DOUBLE_R_TLV_TLV320ALC3X("HPCOM DAC Output Volume", HPLCOM_CTRL,
382 HPRCOM_CTRL, 4, 9, 0, hpout_tlv),
383 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Playback Volume",
384 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
385 0, 118, 1, output_stage_tlv),
386 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
387 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
388 0, 118, 1, output_stage_tlv),
391 * Note: enable Automatic input Gain Controller with care. It can
392 * adjust PGA to max value when ADC is on and will never go back.
394 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
397 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
399 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
401 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
404 /* add non dapm controls */
405 static int aic3x_add_controls(struct snd_soc_codec *codec)
409 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
410 err = snd_ctl_add(codec->card,
411 snd_soc_cnew(&aic3x_snd_controls[i],
420 static int reset_after_bypass(struct snd_soc_dapm_widget *w,
421 struct snd_kcontrol *kcontrol, int event)
423 struct aic3x_priv *aic3x = w->codec->private_data;
424 struct soc_mixer_control *mc = NULL;
425 unsigned int reg = 0;
428 mc = (struct soc_mixer_control *)kcontrol->private_value;
432 if (reg == PGAL_2_LLOPM_VOL || reg == PGAR_2_RLOPM_VOL ||
433 reg == PGAL_2_HPLOUT_VOL || reg == PGAR_2_HPROUT_VOL) {
434 if (w->value & 0x80) {
435 /* Prepare reset on the chip */
436 if (reg == PGAL_2_LLOPM_VOL)
437 aic3x->prepare_reset |= 0x01;
438 else if (reg == PGAR_2_RLOPM_VOL)
439 aic3x->prepare_reset |= 0x02;
440 else if (reg == PGAL_2_HPLOUT_VOL)
441 aic3x->prepare_reset |= 0x04;
442 else if (reg == PGAR_2_HPROUT_VOL)
443 aic3x->prepare_reset |= 0x08;
445 if (aic3x->prepare_reset) {
446 if (reg == PGAL_2_LLOPM_VOL)
447 aic3x->prepare_reset &= ~0x01;
448 else if (reg == PGAR_2_RLOPM_VOL)
449 aic3x->prepare_reset &= ~0x02;
450 else if (reg == PGAL_2_HPLOUT_VOL)
451 aic3x->prepare_reset &= ~0x04;
452 else if (reg == PGAR_2_HPROUT_VOL)
453 aic3x->prepare_reset &= ~0x08;
455 * Controls may have now been turned off,
456 * once they were on, so schedule or
457 * issue a reset on the chip.
459 if (!aic3x->prepare_reset) {
460 if (!((w->codec->bias_level ==
462 (w->codec->bias_level ==
463 SND_SOC_BIAS_PREPARE)))
464 aic3x_reset(w->codec);
474 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
475 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
478 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
479 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
482 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
483 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
485 /* Right HPCOM Mux */
486 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
487 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
489 /* Left DAC_L1 Mixer */
490 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
491 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
492 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
493 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
494 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
497 /* Right DAC_R1 Mixer */
498 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
499 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
500 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
501 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
502 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
506 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
507 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
508 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
509 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
512 /* Right PGA Mixer */
513 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
514 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
515 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
516 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
517 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
521 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
522 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
524 /* Right Line1 Mux */
525 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
526 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
529 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
530 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
532 /* Right Line2 Mux */
533 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
534 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
536 /* Left PGA Bypass Mixer */
537 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
538 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
539 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
540 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
541 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
544 /* Right PGA Bypass Mixer */
545 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
546 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
547 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
548 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
549 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
552 /* Left Line2 Bypass Mixer */
553 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
554 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
555 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
556 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
557 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
560 /* Right Line2 Bypass Mixer */
561 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
562 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
563 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
564 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
565 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
568 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
569 /* Left DAC to Left Outputs */
570 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
571 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
572 &aic3x_left_dac_mux_controls),
573 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
574 &aic3x_left_dac_mixer_controls[0],
575 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
576 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
577 &aic3x_left_hpcom_mux_controls),
578 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
579 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
580 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
582 /* Right DAC to Right Outputs */
583 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
584 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
585 &aic3x_right_dac_mux_controls),
586 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
587 &aic3x_right_dac_mixer_controls[0],
588 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
589 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
590 &aic3x_right_hpcom_mux_controls),
591 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
592 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
593 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
596 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
598 /* Left Inputs to Left ADC */
599 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
600 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
601 &aic3x_left_pga_mixer_controls[0],
602 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
603 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
604 &aic3x_left_line1_mux_controls),
605 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
606 &aic3x_left_line2_mux_controls),
608 /* Right Inputs to Right ADC */
609 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
610 LINE1R_2_RADC_CTRL, 2, 0),
611 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
612 &aic3x_right_pga_mixer_controls[0],
613 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
614 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
615 &aic3x_right_line1_mux_controls),
616 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
617 &aic3x_right_line1_mux_controls),
618 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
619 &aic3x_right_line2_mux_controls),
622 * Not a real mic bias widget but similar function. This is for dynamic
623 * control of GPIO1 digital mic modulator clock output function when
626 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
627 AIC3X_GPIO1_REG, 4, 0xf,
628 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
629 AIC3X_GPIO1_FUNC_DISABLED),
632 * Also similar function like mic bias. Selects digital mic with
633 * configurable oversampling rate instead of ADC converter.
635 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
636 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
637 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
638 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
639 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
640 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
643 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
644 MICBIAS_CTRL, 6, 3, 1, 0),
645 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
646 MICBIAS_CTRL, 6, 3, 2, 0),
647 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
648 MICBIAS_CTRL, 6, 3, 3, 0),
650 /* Left PGA to Left Output bypass */
651 SND_SOC_DAPM_MIXER_E("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
652 &aic3x_left_pga_bp_mixer_controls[0],
653 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls),
654 reset_after_bypass, SND_SOC_DAPM_POST_REG),
656 /* Right PGA to Right Output bypass */
657 SND_SOC_DAPM_MIXER_E("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
658 &aic3x_right_pga_bp_mixer_controls[0],
659 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls),
660 reset_after_bypass, SND_SOC_DAPM_POST_REG),
662 /* Left Line2 to Left Output bypass */
663 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
664 &aic3x_left_line2_bp_mixer_controls[0],
665 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
667 /* Right Line2 to Right Output bypass */
668 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
669 &aic3x_right_line2_bp_mixer_controls[0],
670 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
672 SND_SOC_DAPM_OUTPUT("LLOUT"),
673 SND_SOC_DAPM_OUTPUT("RLOUT"),
674 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
675 SND_SOC_DAPM_OUTPUT("HPLOUT"),
676 SND_SOC_DAPM_OUTPUT("HPROUT"),
677 SND_SOC_DAPM_OUTPUT("HPLCOM"),
678 SND_SOC_DAPM_OUTPUT("HPRCOM"),
680 SND_SOC_DAPM_INPUT("MIC3L"),
681 SND_SOC_DAPM_INPUT("MIC3R"),
682 SND_SOC_DAPM_INPUT("LINE1L"),
683 SND_SOC_DAPM_INPUT("LINE1R"),
684 SND_SOC_DAPM_INPUT("LINE2L"),
685 SND_SOC_DAPM_INPUT("LINE2R"),
688 static const struct snd_soc_dapm_route intercon[] = {
690 {"Left DAC Mux", "DAC_L1", "Left DAC"},
691 {"Left DAC Mux", "DAC_L2", "Left DAC"},
692 {"Left DAC Mux", "DAC_L3", "Left DAC"},
694 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
695 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
696 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
697 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
698 {"Left Line Out", NULL, "Left DAC Mux"},
699 {"Left HP Out", NULL, "Left DAC Mux"},
701 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
702 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
703 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
705 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
706 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
707 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
708 {"Left HP Com", NULL, "Left HPCOM Mux"},
710 {"LLOUT", NULL, "Left Line Out"},
711 {"LLOUT", NULL, "Left Line Out"},
712 {"HPLOUT", NULL, "Left HP Out"},
713 {"HPLCOM", NULL, "Left HP Com"},
716 {"Right DAC Mux", "DAC_R1", "Right DAC"},
717 {"Right DAC Mux", "DAC_R2", "Right DAC"},
718 {"Right DAC Mux", "DAC_R3", "Right DAC"},
720 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
721 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
722 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
723 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
724 {"Right Line Out", NULL, "Right DAC Mux"},
725 {"Right HP Out", NULL, "Right DAC Mux"},
727 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
728 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
729 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
730 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
731 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
733 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
734 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
735 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
736 {"Right HP Com", NULL, "Right HPCOM Mux"},
738 {"RLOUT", NULL, "Right Line Out"},
739 {"RLOUT", NULL, "Right Line Out"},
740 {"HPROUT", NULL, "Right HP Out"},
741 {"HPRCOM", NULL, "Right HP Com"},
744 {"MONO_LOUT", NULL, "Mono Out"},
745 {"MONO_LOUT", NULL, "Mono Out"},
748 {"Left Line1L Mux", "single-ended", "LINE1L"},
749 {"Left Line1L Mux", "differential", "LINE1L"},
751 {"Left Line2L Mux", "single-ended", "LINE2L"},
752 {"Left Line2L Mux", "differential", "LINE2L"},
754 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
755 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
756 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
758 {"Left ADC", NULL, "Left PGA Mixer"},
759 {"Left ADC", NULL, "GPIO1 dmic modclk"},
762 {"Right Line1L Mux", "single-ended", "LINE1L"},
763 {"Right Line1L Mux", "differential", "LINE1L"},
765 {"Right Line1R Mux", "single-ended", "LINE1R"},
766 {"Right Line1R Mux", "differential", "LINE1R"},
768 {"Right Line2R Mux", "single-ended", "LINE2R"},
769 {"Right Line2R Mux", "differential", "LINE2R"},
771 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
772 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
773 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
774 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
776 {"Right ADC", NULL, "Right PGA Mixer"},
777 {"Right ADC", NULL, "GPIO1 dmic modclk"},
779 /* Left PGA Bypass */
780 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
781 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
782 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
783 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
785 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
786 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
787 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
789 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
790 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
791 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
793 /* Right PGA Bypass */
794 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
795 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
796 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
797 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
799 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
800 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
801 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
802 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
803 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
805 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
806 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
807 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
809 /* Left Line2 Bypass */
810 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
811 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
812 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
813 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
815 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
816 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
817 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
819 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
820 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
821 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
823 /* Right Line2 Bypass */
824 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
825 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
826 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
827 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
829 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
830 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
831 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
832 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
833 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
835 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
836 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
837 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
840 * Logical path between digital mic enable and GPIO1 modulator clock
843 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
844 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
845 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
848 static int aic3x_add_widgets(struct snd_soc_codec *codec)
850 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
851 ARRAY_SIZE(aic3x_dapm_widgets));
853 /* set up audio path interconnects */
854 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
856 snd_soc_dapm_new_widgets(codec);
860 static int aic3x_hw_params(struct snd_pcm_substream *substream,
861 struct snd_pcm_hw_params *params)
863 struct snd_soc_pcm_runtime *rtd = substream->private_data;
864 struct snd_soc_device *socdev = rtd->socdev;
865 struct snd_soc_codec *codec = socdev->codec;
866 struct aic3x_priv *aic3x = codec->private_data;
867 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
868 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
871 /* select data word length */
873 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
874 switch (params_format(params)) {
875 case SNDRV_PCM_FORMAT_S16_LE:
877 case SNDRV_PCM_FORMAT_S20_3LE:
880 case SNDRV_PCM_FORMAT_S24_LE:
883 case SNDRV_PCM_FORMAT_S32_LE:
887 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
889 /* Fsref can be 44100 or 48000 */
890 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
892 /* Try to find a value for Q which allows us to bypass the PLL and
893 * generate CODEC_CLK directly. */
894 for (pll_q = 2; pll_q < 18; pll_q++)
895 if (aic3x->sysclk / (128 * pll_q) == fsref) {
902 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
903 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
905 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
907 /* Route Left DAC to left channel input and
908 * right DAC to right channel input */
909 data = (LDAC2LCH | RDAC2RCH);
910 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
911 if (params_rate(params) >= 64000)
912 data |= DUAL_RATE_MODE;
913 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
915 /* codec sample rate select */
916 data = (fsref * 20) / params_rate(params);
917 if (params_rate(params) < 64000)
922 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
928 * find an apropriate setup for j, d, r and p by iterating over
929 * p and r - j and d are calculated for each fraction.
930 * Up to 128 values are probed, the closest one wins the game.
931 * The sysclk is divided by 1000 to prevent integer overflows.
933 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
935 for (r = 1; r <= 16; r++)
936 for (p = 1; p <= 8; p++) {
937 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
944 if (d != 0 && aic3x->sysclk < 10000000)
947 /* This is actually 1000 * ((j + (d/10000)) * r) / p
948 * The term had to be converted to get rid of the
949 * division by 10000 */
950 clk = ((10000 * j * r) + (d * r)) / (10 * p);
952 /* check whether this values get closer than the best
953 * ones we had before */
954 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
955 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
959 /* Early exit for exact matches */
960 if (clk == codec_clk)
965 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
969 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
970 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
971 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
972 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
973 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
974 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
975 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
980 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
982 struct snd_soc_codec *codec = dai->codec;
983 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
984 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
987 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
988 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
990 aic3x_write(codec, LDAC_VOL, ldac_reg);
991 aic3x_write(codec, RDAC_VOL, rdac_reg);
997 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
998 int clk_id, unsigned int freq, int dir)
1000 struct snd_soc_codec *codec = codec_dai->codec;
1001 struct aic3x_priv *aic3x = codec->private_data;
1003 aic3x->sysclk = freq;
1007 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1010 struct snd_soc_codec *codec = codec_dai->codec;
1011 struct aic3x_priv *aic3x = codec->private_data;
1012 u8 iface_areg, iface_breg;
1015 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1016 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1018 /* set master/slave audio interface */
1019 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1020 case SND_SOC_DAIFMT_CBM_CFM:
1022 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1024 case SND_SOC_DAIFMT_CBS_CFS:
1032 * match both interface format and signal polarities since they
1035 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1036 SND_SOC_DAIFMT_INV_MASK)) {
1037 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1039 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1041 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1042 iface_breg |= (0x01 << 6);
1044 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1045 iface_breg |= (0x02 << 6);
1047 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1048 iface_breg |= (0x03 << 6);
1055 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1056 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1057 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1062 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1063 enum snd_soc_bias_level level)
1065 struct aic3x_priv *aic3x = codec->private_data;
1069 case SND_SOC_BIAS_ON:
1070 /* all power is driven by DAPM system */
1071 if (aic3x->master) {
1073 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1074 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1077 * ensure that bit and word clocks are running also if
1078 * DAC and ADC are shutdown
1080 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1081 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg | 0x10);
1084 case SND_SOC_BIAS_PREPARE:
1086 case SND_SOC_BIAS_STANDBY:
1088 * all power is driven by DAPM system,
1089 * so output power is safe if bypass was set
1091 if (aic3x->master) {
1092 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1093 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1095 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1096 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1099 /* Reset cannot be issued, if bypass paths are in use */
1100 if (!aic3x->prepare_reset)
1103 case SND_SOC_BIAS_OFF:
1104 /* force all power off */
1105 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1106 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1107 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1108 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1110 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1111 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1113 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1114 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1115 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1116 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1118 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1119 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1120 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1121 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1123 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1124 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1126 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1127 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1128 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1129 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1131 if (aic3x->master) {
1132 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1133 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1135 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1136 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1141 codec->bias_level = level;
1146 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1148 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1149 u8 bit = gpio ? 3: 0;
1150 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1151 aic3x_write(codec, reg, val | (!!state << bit));
1153 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1155 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1157 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1158 u8 val, bit = gpio ? 2: 1;
1160 aic3x_read(codec, reg, &val);
1161 return (val >> bit) & 1;
1163 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1165 int aic3x_headset_detected(struct snd_soc_codec *codec)
1168 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
1169 return (val >> 2) & 1;
1171 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1173 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1174 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1175 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1177 struct snd_soc_dai aic3x_dai = {
1178 .name = "tlv320aic3x",
1180 .stream_name = "Playback",
1183 .rates = AIC3X_RATES,
1184 .formats = AIC3X_FORMATS,},
1186 .stream_name = "Capture",
1189 .rates = AIC3X_RATES,
1190 .formats = AIC3X_FORMATS,},
1192 .hw_params = aic3x_hw_params,
1195 .digital_mute = aic3x_mute,
1196 .set_sysclk = aic3x_set_dai_sysclk,
1197 .set_fmt = aic3x_set_dai_fmt,
1200 EXPORT_SYMBOL_GPL(aic3x_dai);
1202 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1204 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1205 struct snd_soc_codec *codec = socdev->codec;
1207 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1212 static int aic3x_resume(struct platform_device *pdev)
1214 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1215 struct snd_soc_codec *codec = socdev->codec;
1218 u8 *cache = codec->reg_cache;
1220 /* Sync reg_cache with the hardware */
1221 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1224 codec->hw_write(codec->control_data, data, 2);
1227 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1233 * initialise the AIC3X driver
1234 * register the mixer and dsp interfaces with the kernel
1236 static int aic3x_init(struct snd_soc_device *socdev)
1238 struct snd_soc_codec *codec = socdev->codec;
1239 struct aic3x_setup_data *setup = socdev->codec_data;
1242 codec->name = "tlv320aic3x";
1243 codec->owner = THIS_MODULE;
1244 codec->read = aic3x_read_reg_cache;
1245 codec->write = aic3x_write;
1246 codec->set_bias_level = aic3x_set_bias_level;
1247 codec->dai = &aic3x_dai;
1249 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1250 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1251 if (codec->reg_cache == NULL)
1254 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1255 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1258 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1260 printk(KERN_ERR "aic3x: failed to create pcms\n");
1264 /* DAC default volume and mute */
1265 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1266 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1268 /* DAC to HP default volume and route to Output mixer */
1269 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1270 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1271 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1272 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1273 /* DAC to Line Out default volume and route to Output mixer */
1274 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1275 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1276 /* DAC to Mono Line Out default volume and route to Output mixer */
1277 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1278 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1280 /* unmute all outputs */
1281 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1282 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1283 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1284 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1285 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1286 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1287 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1288 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1289 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1290 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1291 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1292 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1293 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1294 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1296 /* ADC default volume and unmute */
1297 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1298 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1299 /* By default route Line1 to ADC PGA mixer */
1300 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1301 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1303 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1304 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1305 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1306 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1307 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1308 /* PGA to Line Out default volume, disconnect from Output Mixer */
1309 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1310 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1311 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1312 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1313 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1315 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1316 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1317 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1318 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1319 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1320 /* Line2 Line Out default volume, disconnect from Output Mixer */
1321 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1322 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1323 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1324 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1325 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1327 /* off, with power on */
1328 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1330 /* setup GPIO functions */
1331 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1332 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1334 aic3x_add_controls(codec);
1335 aic3x_add_widgets(codec);
1336 ret = snd_soc_register_card(socdev);
1338 printk(KERN_ERR "aic3x: failed to register card\n");
1345 snd_soc_free_pcms(socdev);
1346 snd_soc_dapm_free(socdev);
1348 kfree(codec->reg_cache);
1352 static struct snd_soc_device *aic3x_socdev;
1354 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1356 * AIC3X 2 wire address can be up to 4 devices with device addresses
1357 * 0x18, 0x19, 0x1A, 0x1B
1361 * If the i2c layer weren't so broken, we could pass this kind of data
1364 static int aic3x_i2c_probe(struct i2c_client *i2c,
1365 const struct i2c_device_id *id)
1367 struct snd_soc_device *socdev = aic3x_socdev;
1368 struct snd_soc_codec *codec = socdev->codec;
1371 i2c_set_clientdata(i2c, codec);
1372 codec->control_data = i2c;
1374 ret = aic3x_init(socdev);
1376 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1380 static int aic3x_i2c_remove(struct i2c_client *client)
1382 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1383 kfree(codec->reg_cache);
1387 static const struct i2c_device_id aic3x_i2c_id[] = {
1388 { "tlv320aic3x", 0 },
1391 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1393 /* machine i2c codec control layer */
1394 static struct i2c_driver aic3x_i2c_driver = {
1396 .name = "aic3x I2C Codec",
1397 .owner = THIS_MODULE,
1399 .probe = aic3x_i2c_probe,
1400 .remove = aic3x_i2c_remove,
1401 .id_table = aic3x_i2c_id,
1404 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1406 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1410 static int aic3x_add_i2c_device(struct platform_device *pdev,
1411 const struct aic3x_setup_data *setup)
1413 struct i2c_board_info info;
1414 struct i2c_adapter *adapter;
1415 struct i2c_client *client;
1418 ret = i2c_add_driver(&aic3x_i2c_driver);
1420 dev_err(&pdev->dev, "can't add i2c driver\n");
1424 memset(&info, 0, sizeof(struct i2c_board_info));
1425 info.addr = setup->i2c_address;
1426 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1428 adapter = i2c_get_adapter(setup->i2c_bus);
1430 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1435 client = i2c_new_device(adapter, &info);
1436 i2c_put_adapter(adapter);
1438 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1439 (unsigned int)info.addr);
1446 i2c_del_driver(&aic3x_i2c_driver);
1451 static int aic3x_probe(struct platform_device *pdev)
1453 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1454 struct aic3x_setup_data *setup;
1455 struct snd_soc_codec *codec;
1456 struct aic3x_priv *aic3x;
1459 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1461 setup = socdev->codec_data;
1462 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1466 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1467 if (aic3x == NULL) {
1472 codec->private_data = aic3x;
1473 socdev->codec = codec;
1474 mutex_init(&codec->mutex);
1475 INIT_LIST_HEAD(&codec->dapm_widgets);
1476 INIT_LIST_HEAD(&codec->dapm_paths);
1478 aic3x_socdev = socdev;
1479 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1480 if (setup->i2c_address) {
1481 codec->hw_write = (hw_write_t) i2c_master_send;
1482 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1483 ret = aic3x_add_i2c_device(pdev, setup);
1486 /* Add other interfaces here */
1490 kfree(codec->private_data);
1496 static int aic3x_remove(struct platform_device *pdev)
1498 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1499 struct snd_soc_codec *codec = socdev->codec;
1501 /* power down chip */
1502 if (codec->control_data)
1503 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1505 snd_soc_free_pcms(socdev);
1506 snd_soc_dapm_free(socdev);
1507 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1508 if (codec->control_data)
1509 i2c_unregister_device(codec->control_data);
1510 i2c_del_driver(&aic3x_i2c_driver);
1512 kfree(codec->private_data);
1518 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1519 .probe = aic3x_probe,
1520 .remove = aic3x_remove,
1521 .suspend = aic3x_suspend,
1522 .resume = aic3x_resume,
1524 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1526 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1527 MODULE_AUTHOR("Vladimir Barinov");
1528 MODULE_LICENSE("GPL");