git.maemo.org Git - drnoksnes/blob - getset.h

   1 /*
   2  * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
   3  *
   4  * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and
   5  *                           Jerremy Koot (jkoot@snes9x.com)
   6  *
   7  * Super FX C emulator code
   8  * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and
   9  *                           Gary Henderson.
  10  * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
  11  *
  12  * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson.
  13  * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_.
  14  * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com).
  15  *
  16  * DOS port code contains the works of other authors. See headers in
  17  * individual files.
  18  *
  19  * Snes9x homepage: http://www.snes9x.com
  20  *
  21  * Permission to use, copy, modify and distribute Snes9x in both binary and
  22  * source form, for non-commercial purposes, is hereby granted without fee,
  23  * providing that this license information and copyright notice appear with
  24  * all copies and any derived work.
  25  *
  26  * This software is provided 'as-is', without any express or implied
  27  * warranty. In no event shall the authors be held liable for any damages
  28  * arising from the use of this software.
  29  *
  30  * Snes9x is freeware for PERSONAL USE only. Commercial users should
  31  * seek permission of the copyright holders first. Commercial use includes
  32  * charging money for Snes9x or software derived from Snes9x.
  33  *
  34  * The copyright holders request that bug fixes and improvements to the code
  35  * should be forwarded to them so everyone can benefit from the modifications
  36  * in future versions.
  37  *
  38  * Super NES and Super Nintendo Entertainment System are trademarks of
  39  * Nintendo Co., Limited and its subsidiary companies.
  40  */
  41 #ifndef _GETSET_H_
  42 #define _GETSET_H_
  43
  44 #include "ppu.h"
  45 #include "dsp1.h"
  46 #include "cpuexec.h"
  47 #include "sa1.h"
  48
  49 //#define __memcheck__
  50 //#define __show_io__
  51 extern int oppause;
  52 extern uint16 mem_check;
  53
  54 INLINE uint8 S9xGetByte (uint32 Address)
  55 {
  56 #ifdef __show_io__
  57         char str[64];
  58         sprintf(str,"rd @ %04X",Address);
  59         S9xMessage(0,0,str);
  60 #endif
  61 #ifdef __memcheck__
  62         mem_check+=(Address>>16)+Address;
  63 #endif
  64 #if defined(VAR_CYCLES) || defined(CPU_SHUTDOWN)
  65     int block;
  66     uint8 *GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
  67 #else
  68     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
  69 #endif
  70     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
  71     {
  72 #ifdef VAR_CYCLES
  73         CPU.Cycles += Memory.MemorySpeed [block];
  74 #endif
  75 #ifdef CPU_SHUTDOWN
  76         if (Memory.BlockIsRAM [block])
  77             CPU.WaitAddress = CPU.PCAtOpcodeStart;
  78 #endif
  79         return (*(GetAddress + (Address & 0xffff)));
  80     }
  81
  82     switch ((int) GetAddress)
  83     {
  84     case CMemory::MAP_PPU:
  85 #ifdef VAR_CYCLES
  86         if (!CPU.InDMA)
  87             CPU.Cycles += ONE_CYCLE;
  88 #endif
  89         return (S9xGetPPU (Address & 0xffff));
  90     case CMemory::MAP_CPU:
  91 #ifdef VAR_CYCLES
  92         CPU.Cycles += ONE_CYCLE;
  93 #endif
  94         return (S9xGetCPU (Address & 0xffff));
  95     case CMemory::MAP_DSP:
  96 #ifdef VAR_CYCLES
  97         CPU.Cycles += SLOW_ONE_CYCLE;
  98 #endif
  99         return (S9xGetDSP (Address & 0xffff));
 100     case CMemory::MAP_SA1RAM:
 101     case CMemory::MAP_LOROM_SRAM:
 102 #ifdef VAR_CYCLES
 103         CPU.Cycles += SLOW_ONE_CYCLE;
 104 #endif
 105         return (*(Memory.SRAM + ((Address & CPU.Memory_SRAMMask))));
 106
 107     case CMemory::MAP_HIROM_SRAM:
 108 #ifdef VAR_CYCLES
 109         CPU.Cycles += SLOW_ONE_CYCLE;
 110 #endif
 111         return (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
 112                                   ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)));
 113
 114     case CMemory::MAP_DEBUG:
 115 #ifdef DEBUGGER
 116         printf ("R(B) %06x\n", Address);
 117 #endif
 118
 119     case CMemory::MAP_BWRAM:
 120 #ifdef VAR_CYCLES
 121         CPU.Cycles += SLOW_ONE_CYCLE;
 122 #endif
 123         return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)));
 124
 125     case CMemory::MAP_C4:
 126         return (S9xGetC4 (Address & 0xffff));
 127
 128     default:
 129     case CMemory::MAP_NONE:
 130 #ifdef VAR_CYCLES
 131         CPU.Cycles += SLOW_ONE_CYCLE;
 132 #endif
 133 #ifdef DEBUGGER
 134         printf ("R(B) %06x\n", Address);
 135 #endif
 136         return ((Address >> 8) & 0xff);
 137     }
 138 }
 139
 140 INLINE uint16 S9xGetWord (uint32 Address)
 141 {
 142 #ifdef __show_io__
 143         char str[64];
 144         sprintf(str,"rd @ %04X",Address);
 145         S9xMessage(0,0,str);
 146 #endif
 147 #ifdef __memcheck__
 148         mem_check+=(Address>>16)+Address;
 149 #endif
 150     if ((Address & 0x1fff) == 0x1fff)
 151     {
 152         return (S9xGetByte (Address) | (S9xGetByte (Address + 1) << 8));
 153     }
 154 #if defined(VAR_CYCLES) || defined(CPU_SHUTDOWN)
 155     int block;
 156     uint8 *GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 157 #else
 158     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 159 #endif
 160     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 161     {
 162 #ifdef VAR_CYCLES
 163         CPU.Cycles += Memory.MemorySpeed [block] << 1;
 164 #endif
 165 #ifdef CPU_SHUTDOWN
 166         if (Memory.BlockIsRAM [block])
 167             CPU.WaitAddress = CPU.PCAtOpcodeStart;
 168 #endif
 169 #ifdef FAST_LSB_WORD_ACCESS
 170         return (*(uint16 *) (GetAddress + (Address & 0xffff)));
 171 #else
 172         return (*(GetAddress + (Address & 0xffff)) |
 173                 (*(GetAddress + (Address & 0xffff) + 1) << 8));
 174 #endif
 175     }
 176
 177     switch ((int) GetAddress)
 178     {
 179     case CMemory::MAP_PPU:
 180 #ifdef VAR_CYCLES
 181         if (!CPU.InDMA)
 182             CPU.Cycles += TWO_CYCLES;
 183 #endif
 184         return (S9xGetPPU (Address & 0xffff) |
 185                 (S9xGetPPU ((Address + 1) & 0xffff) << 8));
 186     case CMemory::MAP_CPU:
 187 #ifdef VAR_CYCLES
 188         CPU.Cycles += TWO_CYCLES;
 189 #endif
 190         return (S9xGetCPU (Address & 0xffff) |
 191                 (S9xGetCPU ((Address + 1) & 0xffff) << 8));
 192     case CMemory::MAP_DSP:
 193 #ifdef VAR_CYCLES
 194         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 195 #endif
 196         return (S9xGetDSP (Address & 0xffff) |
 197                 (S9xGetDSP ((Address + 1) & 0xffff) << 8));
 198     case CMemory::MAP_SA1RAM:
 199     case CMemory::MAP_LOROM_SRAM:
 200 #ifdef VAR_CYCLES
 201         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 202 #endif
 203         return (*(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) |
 204                 (*(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) << 8));
 205
 206     case CMemory::MAP_HIROM_SRAM:
 207 #ifdef VAR_CYCLES
 208         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 209 #endif
 210         return (*(Memory.SRAM +
 211                   (((Address & 0x7fff) - 0x6000 +
 212                     ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) |
 213                 (*(Memory.SRAM +
 214                    ((((Address + 1) & 0x7fff) - 0x6000 +
 215                      (((Address + 1) & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) << 8));
 216
 217     case CMemory::MAP_BWRAM:
 218 #ifdef VAR_CYCLES
 219         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 220 #endif
 221         return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) |
 222                 (*(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) << 8));
 223
 224     case CMemory::MAP_DEBUG:
 225 #ifdef DEBUGGER
 226         printf ("R(W) %06x\n", Address);
 227 #endif
 228
 229     case CMemory::MAP_C4:
 230         return (S9xGetC4 (Address & 0xffff) |
 231                 (S9xGetC4 ((Address + 1) & 0xffff) << 8));
 232
 233     default:
 234     case CMemory::MAP_NONE:
 235 #ifdef VAR_CYCLES
 236         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 237 #endif
 238 #ifdef DEBUGGER
 239         printf ("R(W) %06x\n", Address);
 240 #endif
 241         return (((Address >> 8) | (Address & 0xff00)) & 0xffff);
 242     }
 243 }
 244
 245 INLINE void S9xSetByte (uint8 Byte, uint32 Address)
 246 {
 247 #ifdef __show_io__
 248         char str[64];
 249         sprintf(str,"wr @ %04X %02X",Address,Byte);
 250         S9xMessage(0,0,str);
 251 #endif
 252 #ifdef __memcheck__
 253         mem_check+=Byte;
 254 #endif
 255
 256 #if defined(CPU_SHUTDOWN)
 257     CPU.WaitAddress = NULL;
 258 #endif
 259 #if defined(VAR_CYCLES)
 260     int block;
 261     uint8 *SetAddress = Memory.WriteMap [block = ((Address >> MEMMAP_SHIFT) & MEMMAP_MASK)];
 262 #else
 263     uint8 *SetAddress = Memory.WriteMap [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 264 #endif
 265
 266     if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
 267     {
 268 #ifdef VAR_CYCLES
 269         CPU.Cycles += Memory.MemorySpeed [block];
 270 #endif
 271 #ifdef CPU_SHUTDOWN
 272         SetAddress += Address & 0xffff;
 273 #ifdef USE_SA1
 274         if (SetAddress == SA1.WaitByteAddress1 ||
 275             SetAddress == SA1.WaitByteAddress2)
 276         {
 277             SA1.Executing = SA1.S9xOpcodes != NULL;
 278             SA1.WaitCounter = 0;
 279         }
 280 #endif
 281         *SetAddress = Byte;
 282 #else
 283         *(SetAddress + (Address & 0xffff)) = Byte;
 284 #endif
 285         return;
 286     }
 287
 288     switch ((int) SetAddress)
 289     {
 290     case CMemory::MAP_PPU:
 291 #ifdef VAR_CYCLES
 292         if (!CPU.InDMA)
 293             CPU.Cycles += ONE_CYCLE;
 294 #endif
 295         S9xSetPPU (Byte, Address & 0xffff);
 296         return;
 297
 298     case CMemory::MAP_CPU:
 299 #ifdef VAR_CYCLES
 300         CPU.Cycles += ONE_CYCLE;
 301 #endif
 302         S9xSetCPU (Byte, Address & 0xffff);
 303         return;
 304
 305     case CMemory::MAP_DSP:
 306 #ifdef VAR_CYCLES
 307         CPU.Cycles += SLOW_ONE_CYCLE;
 308 #endif
 309         S9xSetDSP (Byte, Address & 0xffff);
 310         return;
 311
 312     case CMemory::MAP_LOROM_SRAM:
 313 #ifdef VAR_CYCLES
 314         CPU.Cycles += SLOW_ONE_CYCLE;
 315 #endif
 316         if (CPU.Memory_SRAMMask)
 317         {
 318             *(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = Byte;
 319             CPU.SRAMModified = TRUE;
 320         }
 321         return;
 322
 323     case CMemory::MAP_HIROM_SRAM:
 324 #ifdef VAR_CYCLES
 325         CPU.Cycles += SLOW_ONE_CYCLE;
 326 #endif
 327         if (CPU.Memory_SRAMMask)
 328         {
 329             *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
 330                               ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) = Byte;
 331             CPU.SRAMModified = TRUE;
 332         }
 333         return;
 334
 335     case CMemory::MAP_BWRAM:
 336 #ifdef VAR_CYCLES
 337         CPU.Cycles += SLOW_ONE_CYCLE;
 338 #endif
 339         *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte;
 340         CPU.SRAMModified = TRUE;
 341         return;
 342
 343     case CMemory::MAP_DEBUG:
 344 #ifdef DEBUGGER
 345         printf ("W(B) %06x\n", Address);
 346 #endif
 347
 348     case CMemory::MAP_SA1RAM:
 349 #ifdef VAR_CYCLES
 350         CPU.Cycles += SLOW_ONE_CYCLE;
 351 #endif
 352         *(Memory.SRAM + (Address & 0xffff)) = Byte;
 353         SA1.Executing = !SA1.Waiting;
 354         break;
 355
 356     case CMemory::MAP_C4:
 357         S9xSetC4 (Byte, Address & 0xffff);
 358         return;
 359
 360     default:
 361     case CMemory::MAP_NONE:
 362 #ifdef VAR_CYCLES
 363         CPU.Cycles += SLOW_ONE_CYCLE;
 364 #endif
 365 #ifdef DEBUGGER
 366         printf ("W(B) %06x\n", Address);
 367 #endif
 368         return;
 369     }
 370 }
 371
 372 INLINE void S9xSetWord (uint16 Word, uint32 Address)
 373 {
 374 #ifdef __show_io__
 375         char str[64];
 376         sprintf(str,"wr @ %04X %04X",Address,Word);
 377         S9xMessage(0,0,str);
 378 #endif
 379 #ifdef __memcheck__
 380         mem_check+=Word;
 381 #endif
 382 #if defined(CPU_SHUTDOWN)
 383     CPU.WaitAddress = NULL;
 384 #endif
 385 #if defined (VAR_CYCLES)
 386     int block;
 387     uint8 *SetAddress = Memory.WriteMap [block = ((Address >> MEMMAP_SHIFT) & MEMMAP_MASK)];
 388 #else
 389     uint8 *SetAddress = Memory.WriteMap [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 390 #endif
 391
 392     if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
 393     {
 394 #ifdef VAR_CYCLES
 395         CPU.Cycles += Memory.MemorySpeed [block] << 1;
 396 #endif
 397 #if defined(CPU_SHUTDOWN) && defined(USE_SA1)
 398         uint8 *SetAddressSA1 = SetAddress + (Address & 0xffff);
 399         if (SetAddressSA1 == SA1.WaitByteAddress1 ||
 400             SetAddressSA1 == SA1.WaitByteAddress2)
 401         {
 402             SA1.Executing = SA1.S9xOpcodes != NULL;
 403             SA1.WaitCounter = 0;
 404         }
 405 #endif
 406 #ifdef FAST_LSB_WORD_ACCESS
 407         *(uint16 *) (SetAddress + (Address & 0xffff)) = Word;
 408 #else
 409         *(SetAddress + (Address & 0xffff)) = (uint8) Word;
 410         *(SetAddress + ((Address + 1) & 0xffff)) = Word >> 8;
 411 #endif
 412         return;
 413     }
 414
 415     switch ((int) SetAddress)
 416     {
 417     case CMemory::MAP_PPU:
 418 #ifdef VAR_CYCLES
 419         if (!CPU.InDMA)
 420             CPU.Cycles += TWO_CYCLES;
 421 #endif
 422         S9xSetPPU ((uint8) Word, Address & 0xffff);
 423         S9xSetPPU (Word >> 8, (Address & 0xffff) + 1);
 424         return;
 425
 426     case CMemory::MAP_CPU:
 427 #ifdef VAR_CYCLES
 428         CPU.Cycles += TWO_CYCLES;
 429 #endif
 430         S9xSetCPU ((uint8) Word, (Address & 0xffff));
 431         S9xSetCPU (Word >> 8, (Address & 0xffff) + 1);
 432         return;
 433
 434     case CMemory::MAP_DSP:
 435 #ifdef VAR_CYCLES
 436         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 437 #endif
 438         S9xSetDSP ((uint8) Word, (Address & 0xffff));
 439         S9xSetDSP (Word >> 8, (Address & 0xffff) + 1);
 440         return;
 441
 442     case CMemory::MAP_LOROM_SRAM:
 443 #ifdef VAR_CYCLES
 444         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 445 #endif
 446         if (CPU.Memory_SRAMMask)
 447         {
 448             *(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = (uint8) Word;
 449             *(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) = Word >> 8;
 450             CPU.SRAMModified = TRUE;
 451         }
 452         return;
 453
 454     case CMemory::MAP_HIROM_SRAM:
 455 #ifdef VAR_CYCLES
 456         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 457 #endif
 458         if (CPU.Memory_SRAMMask)
 459         {
 460             *(Memory.SRAM +
 461               (((Address & 0x7fff) - 0x6000 +
 462                 ((Address & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask))) = (uint8) Word;
 463             *(Memory.SRAM +
 464               ((((Address + 1) & 0x7fff) - 0x6000 +
 465                 (((Address + 1) & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask))) = (uint8) (Word >> 8);
 466             CPU.SRAMModified = TRUE;
 467         }
 468         return;
 469
 470     case CMemory::MAP_BWRAM:
 471 #ifdef VAR_CYCLES
 472         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 473 #endif
 474         *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = (uint8) Word;
 475         *(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) = (uint8) (Word >> 8);
 476         CPU.SRAMModified = TRUE;
 477         return;
 478
 479     case CMemory::MAP_DEBUG:
 480 #ifdef DEBUGGER
 481         printf ("W(W) %06x\n", Address);
 482 #endif
 483
 484     case CMemory::MAP_SA1RAM:
 485 #ifdef VAR_CYCLES
 486         CPU.Cycles += SLOW_ONE_CYCLE;
 487 #endif
 488         *(Memory.SRAM + (Address & 0xffff)) = (uint8) Word;
 489         *(Memory.SRAM + ((Address + 1) & 0xffff)) = (uint8) (Word >> 8);
 490         SA1.Executing = !SA1.Waiting;
 491         break;
 492
 493     case CMemory::MAP_C4:
 494         S9xSetC4 (Word & 0xff, Address & 0xffff);
 495         S9xSetC4 ((uint8) (Word >> 8), (Address + 1) & 0xffff);
 496         return;
 497
 498     default:
 499     case CMemory::MAP_NONE:
 500 #ifdef VAR_CYCLES
 501         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 502 #endif
 503 #ifdef DEBUGGER
 504         printf ("W(W) %06x\n", Address);
 505 #endif
 506         return;
 507     }
 508 }
 509
 510 INLINE uint8 *GetBasePointer (uint32 Address)
 511 {
 512     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 513     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 514         return (GetAddress);
 515
 516     switch ((int) GetAddress)
 517     {
 518     case CMemory::MAP_PPU:
 519         return (Memory.FillRAM - 0x2000);
 520     case CMemory::MAP_CPU:
 521         return (Memory.FillRAM - 0x4000);
 522     case CMemory::MAP_DSP:
 523         return (Memory.FillRAM - 0x6000);
 524     case CMemory::MAP_SA1RAM:
 525     case CMemory::MAP_LOROM_SRAM:
 526         return (Memory.SRAM);
 527     case CMemory::MAP_BWRAM:
 528         return (Memory.BWRAM - 0x6000);
 529     case CMemory::MAP_HIROM_SRAM:
 530         return (Memory.SRAM - 0x6000);
 531     case CMemory::MAP_C4:
 532         return (Memory.C4RAM - 0x6000);
 533     case CMemory::MAP_DEBUG:
 534 #ifdef DEBUGGER
 535         printf ("GBP %06x\n", Address);
 536 #endif
 537     default:
 538     case CMemory::MAP_NONE:
 539 #ifdef DEBUGGER
 540         printf ("GBP %06x\n", Address);
 541 #endif
 542         return (0);
 543     }
 544 }
 545
 546 INLINE uint8 *S9xGetMemPointer (uint32 Address)
 547 {
 548     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 549     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 550         return (GetAddress + (Address & 0xffff));
 551
 552     switch ((int) GetAddress)
 553     {
 554     case CMemory::MAP_PPU:
 555         return (Memory.FillRAM - 0x2000 + (Address & 0xffff));
 556     case CMemory::MAP_CPU:
 557         return (Memory.FillRAM - 0x4000 + (Address & 0xffff));
 558     case CMemory::MAP_DSP:
 559         return (Memory.FillRAM - 0x6000 + (Address & 0xffff));
 560     case CMemory::MAP_SA1RAM:
 561     case CMemory::MAP_LOROM_SRAM:
 562         return (Memory.SRAM + (Address & 0xffff));
 563     case CMemory::MAP_BWRAM:
 564         return (Memory.BWRAM - 0x6000 + (Address & 0xffff));
 565     case CMemory::MAP_HIROM_SRAM:
 566         return (Memory.SRAM - 0x6000 + (Address & 0xffff));
 567
 568     case CMemory::MAP_C4:
 569         return (Memory.C4RAM - 0x6000 + (Address & 0xffff));
 570
 571     case CMemory::MAP_DEBUG:
 572 #ifdef DEBUGGER
 573         printf ("GMP %06x\n", Address);
 574 #endif
 575     default:
 576     case CMemory::MAP_NONE:
 577 #ifdef DEBUGGER
 578         printf ("GMP %06x\n", Address);
 579 #endif
 580         return (0);
 581     }
 582 }
 583
 584 INLINE void S9xSetPCBase (uint32 Address)
 585 {
 586 #ifdef VAR_CYCLES
 587     int block;
 588     uint8 *GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 589 #else
 590     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 591 #endif
 592     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 593     {
 594 #ifdef VAR_CYCLES
 595         CPU.MemSpeed = Memory.MemorySpeed [block];
 596         CPU.MemSpeedx2 = CPU.MemSpeed << 1;
 597 #endif
 598         CPU.PCBase = GetAddress;
 599         CPU.PC = GetAddress + (Address & 0xffff);
 600         return;
 601     }
 602
 603     switch ((int) GetAddress)
 604     {
 605     case CMemory::MAP_PPU:
 606 #ifdef VAR_CYCLES
 607         CPU.MemSpeed = ONE_CYCLE;
 608         CPU.MemSpeedx2 = TWO_CYCLES;
 609 #endif
 610         CPU.PCBase = Memory.FillRAM - 0x2000;
 611         CPU.PC = CPU.PCBase + (Address & 0xffff);
 612         return;
 613
 614     case CMemory::MAP_CPU:
 615 #ifdef VAR_CYCLES
 616         CPU.MemSpeed = ONE_CYCLE;
 617         CPU.MemSpeedx2 = TWO_CYCLES;
 618 #endif
 619         CPU.PCBase = Memory.FillRAM - 0x4000;
 620         CPU.PC = CPU.PCBase + (Address & 0xffff);
 621         return;
 622
 623     case CMemory::MAP_DSP:
 624 #ifdef VAR_CYCLES
 625         CPU.MemSpeed = SLOW_ONE_CYCLE;
 626         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 627 #endif
 628         CPU.PCBase = Memory.FillRAM - 0x6000;
 629         CPU.PC = CPU.PCBase + (Address & 0xffff);
 630         return;
 631
 632     case CMemory::MAP_SA1RAM:
 633     case CMemory::MAP_LOROM_SRAM:
 634 #ifdef VAR_CYCLES
 635         CPU.MemSpeed = SLOW_ONE_CYCLE;
 636         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 637 #endif
 638         CPU.PCBase = Memory.SRAM;
 639         CPU.PC = CPU.PCBase + (Address & 0xffff);
 640         return;
 641
 642     case CMemory::MAP_BWRAM:
 643 #ifdef VAR_CYCLES
 644         CPU.MemSpeed = SLOW_ONE_CYCLE;
 645         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 646 #endif
 647         CPU.PCBase = Memory.BWRAM - 0x6000;
 648         CPU.PC = CPU.PCBase + (Address & 0xffff);
 649         return;
 650     case CMemory::MAP_HIROM_SRAM:
 651 #ifdef VAR_CYCLES
 652         CPU.MemSpeed = SLOW_ONE_CYCLE;
 653         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 654 #endif
 655         CPU.PCBase = Memory.SRAM - 0x6000;
 656         CPU.PC = CPU.PCBase + (Address & 0xffff);
 657         return;
 658
 659     case CMemory::MAP_C4:
 660 #ifdef VAR_CYCLES
 661         CPU.MemSpeed = SLOW_ONE_CYCLE;
 662         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 663 #endif
 664         CPU.PCBase = Memory.C4RAM - 0x6000;
 665         CPU.PC = CPU.PCBase + (Address & 0xffff);
 666         return;
 667
 668     case CMemory::MAP_DEBUG:
 669 #ifdef DEBUGGER
 670         printf ("SBP %06x\n", Address);
 671 #endif
 672
 673     default:
 674     case CMemory::MAP_NONE:
 675 #ifdef VAR_CYCLES
 676         CPU.MemSpeed = SLOW_ONE_CYCLE;
 677         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 678 #endif
 679 #ifdef DEBUGGER
 680         printf ("SBP %06x\n", Address);
 681 #endif
 682         CPU.PCBase = Memory.SRAM;
 683         CPU.PC = Memory.SRAM + (Address & 0xffff);
 684         return;
 685     }
 686 }
 687 #endif