git.maemo.org Git - drnoksnes/blob - os9x_65c816_mac_gen.h

   1
   2 /*****************************************************************/
   3 /*     Offset in SCPUState structure                             */
   4 /*****************************************************************/
   5 #define Flags_ofs               0
   6 #define BranchSkip_ofs          4
   7 #define NMIActive_ofs           5
   8 #define IRQActive_ofs           6
   9 #define WaitingForInterrupt_ofs 7
  10 #define InDMA_ofs               8
  11 #define WhichEvent              9
  12 #define SRAMModified_ofs        10
  13 #define BRKTriggered_ofs        11
  14 #define PC_ofs                  12
  15 #define PCBase_ofs              16
  16
  17 #define PCAtOpcodeStart_ofs     20
  18
  19 #define WaitAddress_ofs         24
  20
  21 #define WaitCounter_ofs         28
  22 #define Cycles_ofs              32
  23 #define NextEvent_ofs           36
  24 #define V_Counter_ofs           40
  25 #define MemSpeed_ofs            44
  26 #define MemSpeedx2_ofs          48
  27 #define FastROMSpeed_ofs        52
  28 #define AutoSaveTimer_ofs       56
  29 #define NMITriggerPoint_ofs     60
  30 #define NMICycleCount_ofs       64
  31 #define IRQCycleCount_ofs       68
  32
  33 #define RPB_ofs         72
  34 #define RDB_ofs         73
  35 #define RP_ofs          74
  36 #define RA_ofs          76
  37 #define RAH_ofs         RA_ofs+1
  38 #define RD_ofs          78
  39 #define RS_ofs          80
  40 #define RX_ofs          82
  41 #define RY_ofs          84
  42 #define RPC_ofs         86
  43
  44
  45 #define asm_OPTABLE_ofs         88
  46 #define TriedInterleavedMode2_ofs       92
  47
  48
  49
  50 #define Map_ofs         96
  51 #define WriteMap_ofs    100
  52 #define MemorySpeed_ofs 104
  53 #define BlockIsRAM_ofs  108
  54 #define SRAM            112
  55 #define BWRAM           116
  56 #define SRAMMask        120
  57
  58 #define APUExecuting_ofs 122
  59
  60 #define PALMOS_R9_ofs   124
  61 #define PALMOS_R10_ofs  128
  62 /*****************************************************************/
  63
  64
  65 #ifdef __PALMOS__
  66 /* prepare */
  67 .macro          PREPARE_C_CALL
  68         STMFD   R13!,{R9,R10,R12,R14}
  69         LDR     R9,[regCPUvar,#PALMOS_R9_ofs]
  70         LDR     R10,[regCPUvar,#PALMOS_R10_ofs]
  71 .endm
  72 .macro          PREPARE_C_CALL_R0
  73         STMFD   R13!,{R0,R9,R10,R12,R14}
  74         LDR     R9,[regCPUvar,#PALMOS_R9_ofs]
  75         LDR     R10,[regCPUvar,#PALMOS_R10_ofs]
  76 .endm
  77 .macro          PREPARE_C_CALL_R0R1
  78         STMFD   R13!,{R0,R1,R9,R10,R12,R14}
  79         LDR     R9,[regCPUvar,#PALMOS_R9_ofs]
  80         LDR     R10,[regCPUvar,#PALMOS_R10_ofs]
  81 .endm
  82 .macro          PREPARE_C_CALL_LIGHT
  83         STMFD   R13!,{R14}
  84         LDR     R9,[regCPUvar,#PALMOS_R9_ofs]
  85         LDR     R10,[regCPUvar,#PALMOS_R10_ofs]
  86 .endm
  87 .macro          PREPARE_C_CALL_LIGHTR12
  88         STMFD   R13!,{R9,R10,R12,R14}
  89         LDR     R9,[regCPUvar,#PALMOS_R9_ofs]
  90         LDR     R10,[regCPUvar,#PALMOS_R10_ofs]
  91 .endm
  92 /* restore */
  93 .macro          RESTORE_C_CALL
  94         LDMFD   R13!,{R9,R10,R12,R14}
  95
  96 .endm
  97 .macro          RESTORE_C_CALL_R0
  98         LDMFD   R13!,{R0,R9,R10,R12,R14}
  99 .endm
 100 .macro          RESTORE_C_CALL_R1
 101         LDMFD   R13!,{R1,R9,R10,R12,R14}
 102 .endm
 103 .macro          RESTORE_C_CALL_LIGHT
 104         LDMFD   R13!,{R14}
 105 .endm
 106 .macro          RESTORE_C_CALL_LIGHTR12
 107         LDMFD   R13!,{R9,R10,R12,R14}
 108 .endm
 109 #else
 110 /* prepare */
 111 .macro          PREPARE_C_CALL
 112         STMFD   R13!,{R12,R14}
 113 .endm
 114 .macro          PREPARE_C_CALL_R0
 115         STMFD   R13!,{R0,R12,R14}
 116 .endm
 117 .macro          PREPARE_C_CALL_R0R1
 118         STMFD   R13!,{R0,R1,R12,R14}
 119 .endm
 120 .macro          PREPARE_C_CALL_LIGHT
 121         STMFD   R13!,{R14}
 122 .endm
 123 .macro          PREPARE_C_CALL_LIGHTR12
 124         STMFD   R13!,{R12,R14}
 125 .endm
 126 /* restore */
 127 .macro          RESTORE_C_CALL
 128         LDMFD   R13!,{R12,R14}
 129 .endm
 130 .macro          RESTORE_C_CALL_R0
 131         LDMFD   R13!,{R0,R12,R14}
 132 .endm
 133 .macro          RESTORE_C_CALL_R1
 134         LDMFD   R13!,{R1,R12,R14}
 135 .endm
 136 .macro          RESTORE_C_CALL_LIGHT
 137         LDMFD   R13!,{R14}
 138 .endm
 139 .macro          RESTORE_C_CALL_LIGHTR12
 140         LDMFD   R13!,{R12,R14}
 141 .endm
 142 #endif
 143
 144 //--------------
 145 .macro          LOAD_REGS
 146         //regD & regPBank share the same register
 147         LDRB            regPBank,[regCPUvar,#RPB_ofs]
 148         LDRH            rscratch,[regCPUvar,#RD_ofs]
 149         ORR             regD,regD,rscratch, LSL #16
 150         //rstatus & regDBank share the same register
 151         LDRB            regDBank,[regCPUvar,#RDB_ofs]
 152         LDRH            rscratch,[regCPUvar,#RP_ofs]
 153         ORRS            rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER
 154         //if Carry set, then EMULATION bit was set
 155         ORRCS           rstatus,rstatus,#MASK_EMUL
 156         //
 157         LDRH            regA,[regCPUvar,#RA_ofs]
 158         LDRH            regX,[regCPUvar,#RX_ofs]
 159         LDRH            regY,[regCPUvar,#RY_ofs]
 160         LDRH            regS,[regCPUvar,#RS_ofs]
 161         //Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 162         TST             rstatus,#MASK_INDEX
 163         MOVNE           regX,regX,LSL #24
 164         MOVNE           regY,regY,LSL #24
 165         MOVEQ           regX,regX,LSL #16
 166         MOVEQ           regY,regY,LSL #16
 167         TST             rstatus,#MASK_MEM
 168         MOVNE           regA,regA,LSL #24
 169         MOVEQ           regA,regA,LSL #16
 170
 171         LDR             regpcbase,[regCPUvar,#PCBase_ofs]
 172         LDR             rpc,[regCPUvar,#PC_ofs]
 173         LDR             regCycles,[regCPUvar,#Cycles_ofs]
 174 .endm
 175
 176
 177 .macro          SAVE_REGS
 178         //regD & regPBank is same register
 179         STRB            regPBank,[regCPUvar,#RPB_ofs]
 180         MOV             rscratch,regD, LSR #16
 181         STRH            rscratch,[regCPUvar,#RD_ofs]
 182         //rstatus & regDBank is same register
 183         STRB            regDBank,[regCPUvar,#RDB_ofs]
 184         MOVS            rscratch, rstatus, LSR #STATUS_SHIFTER
 185         ORRCS           rscratch,rscratch,#0x100 //EMULATION bit
 186         STRH            rscratch,[regCPUvar,#RP_ofs]
 187         //
 188         //Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 189         TST             rstatus,#MASK_INDEX
 190         MOVNE           rscratch,regX,LSR #24
 191         MOVNE           rscratch2,regY,LSR #24
 192         MOVEQ           rscratch,regX,LSR #16
 193         MOVEQ           rscratch2,regY,LSR #16
 194         STRH            rscratch,[regCPUvar,#RX_ofs]
 195         STRH            rscratch2,[regCPUvar,#RY_ofs]
 196         TST             rstatus,#MASK_MEM
 197         LDRNEH          rscratch,[regCPUvar,#RA_ofs]
 198         BICNE           rscratch,rscratch,#0xFF
 199         ORRNE           rscratch,rscratch,regA,LSR #24
 200         MOVEQ           rscratch,regA,LSR #16
 201         STRH            rscratch,[regCPUvar,#RA_ofs]
 202
 203         STRH            regS,[regCPUvar,#RS_ofs]
 204         STR             regpcbase,[regCPUvar,#PCBase_ofs]
 205         STR             rpc,[regCPUvar,#PC_ofs]
 206
 207         STR             regCycles,[regCPUvar,#Cycles_ofs]
 208 .endm
 209
 210 /*****************************************************************/
 211 .macro          ADD1CYCLE
 212                 add     regCycles,regCycles, #ONE_CYCLE
 213 .endm
 214 .macro          ADD1CYCLENE
 215                 addne   regCycles,regCycles, #ONE_CYCLE
 216 .endm
 217 .macro          ADD1CYCLEEQ
 218                 addeq   regCycles,regCycles, #ONE_CYCLE
 219 .endm
 220
 221 .macro          ADD2CYCLE
 222                 add     regCycles,regCycles, #(ONE_CYCLE*2)
 223 .endm
 224 .macro          ADD2CYCLENE
 225                 addne   regCycles,regCycles, #(ONE_CYCLE*2)
 226 .endm
 227 .macro          ADD2CYCLE2MEM
 228                 ldr     rscratch,[regCPUvar,#MemSpeed_ofs]
 229                 add     regCycles,regCycles, #(ONE_CYCLE*2)
 230                 add     regCycles, regCycles, rscratch, LSL #1
 231 .endm
 232 .macro          ADD2CYCLE1MEM
 233                 ldr     rscratch,[regCPUvar,#MemSpeed_ofs]
 234                 add     regCycles,regCycles, #(ONE_CYCLE*2)
 235                 add     regCycles, regCycles, rscratch
 236 .endm
 237
 238 .macro          ADD3CYCLE
 239                 add     regCycles,regCycles, #(ONE_CYCLE*3)
 240 .endm
 241
 242 .macro          ADD1CYCLE1MEM
 243                 ldr     rscratch,[regCPUvar,#MemSpeed_ofs]
 244                 add     regCycles,regCycles, #ONE_CYCLE
 245                 add     regCycles, regCycles, rscratch
 246 .endm
 247
 248 .macro          ADD1CYCLE2MEM
 249                 ldr     rscratch,[regCPUvar,#MemSpeed_ofs]
 250                 add     regCycles,regCycles, #ONE_CYCLE
 251                 add     regCycles, regCycles, rscratch, lsl #1
 252 .endm
 253
 254 .macro          ADD1MEM
 255                 ldr     rscratch,[regCPUvar,#MemSpeed_ofs]
 256                 add     regCycles, regCycles, rscratch
 257 .endm
 258
 259 .macro          ADD2MEM
 260                 ldr     rscratch,[regCPUvar,#MemSpeed_ofs]
 261                 add     regCycles, regCycles, rscratch, lsl #1
 262 .endm
 263
 264 .macro          ADD3MEM
 265                 ldr     rscratch,[regCPUvar,#MemSpeed_ofs]
 266                 add     regCycles, rscratch, regCycles
 267                 add     regCycles, regCycles, rscratch, lsl #1
 268 .endm
 269
 270 /**************/
 271 .macro          ClearDecimal
 272                 BIC     rstatus,rstatus,#MASK_DECIMAL
 273 .endm
 274 .macro          SetDecimal
 275                 ORR     rstatus,rstatus,#MASK_DECIMAL
 276 .endm
 277 .macro          SetIRQ
 278                 ORR     rstatus,rstatus,#MASK_IRQ
 279 .endm
 280 .macro          ClearIRQ
 281                 BIC     rstatus,rstatus,#MASK_IRQ
 282 .endm
 283
 284 .macro          CPUShutdown
 285 //if (Settings.Shutdown && CPU.PC == CPU.WaitAddress)
 286                 LDR             rscratch,[regCPUvar,#WaitAddress_ofs]
 287                 CMP             rpc,rscratch
 288                 BNE             5431f
 289 //if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG)))
 290                 LDR             rscratch,[regCPUvar,#Flags_ofs]
 291                 LDR             rscratch2,[regCPUvar,#WaitCounter_ofs]
 292                 TST             rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG)
 293                 BNE             5432f
 294                 MOVS            rscratch2,rscratch2
 295                 BNE             5432f
 296 //CPU.WaitAddress = NULL;
 297                 MOV             rscratch,#0
 298                 STR             rscratch,[regCPUvar,#WaitAddress_ofs]
 299 //if (Settings.SA1)
 300 //              S9xSA1ExecuteDuringSleep ();            : TODO
 301
 302 //          CPU.Cycles = CPU.NextEvent;
 303                 LDR             regCycles,[regCPUvar,#NextEvent_ofs]
 304                 LDRB            r0,[regCPUvar,#APUExecuting_ofs]
 305                 MOVS            r0,r0
 306                 BEQ             5431f
 307 //          if (IAPU.APUExecuting)
 308 /*          {
 309                 ICPU.CPUExecuting = FALSE;
 310                 do
 311                 {
 312                     APU_EXECUTE1();
 313                 } while (APU.Cycles < CPU.NextEvent);
 314                 ICPU.CPUExecuting = TRUE;
 315             }
 316         */
 317                 asmAPU_EXECUTE2
 318                 B               5431f
 319 .pool
 320 5432:
 321 /*      else
 322         if (CPU.WaitCounter >= 2)
 323             CPU.WaitCounter = 1;
 324         else
 325             CPU.WaitCounter--;
 326 */
 327                 CMP             rscratch2,#1
 328                 MOVHI           rscratch2,#1
 329                 //SUBLS         rscratch2,rscratch2,#1
 330                 MOVLS           rscratch2,#0
 331                 STR             rscratch2,[regCPUvar,#WaitCounter_ofs]
 332 5431:
 333
 334 .endm
 335 .macro          BranchCheck0
 336                 /*in rsctach : OpAddress
 337                 /*destroy rscratch2*/
 338                 LDRB    rscratch2,[regCPUvar,#BranchSkip_ofs]
 339                 MOVS    rscratch2,rscratch2
 340                 BEQ     1110f
 341                 MOV     rscratch2,#0
 342                 STRB    rscratch2,[regCPUvar,#BranchSkip_ofs]
 343                 SUB     rscratch2,rpc,regpcbase
 344                 //if( CPU.PC - CPU.PCBase > OpAddress) return;
 345                 CMP     rscratch2,rscratch
 346                 BHI     1111f
 347 1110:
 348 .endm
 349 .macro          BranchCheck1
 350                 /*in rsctach : OpAddress
 351                 /*destroy rscratch2*/
 352                 LDRB    rscratch2,[regCPUvar,#BranchSkip_ofs]
 353                 MOVS    rscratch2,rscratch2
 354                 BEQ     1110f
 355                 MOV     rscratch2,#0
 356                 STRB    rscratch2,[regCPUvar,#BranchSkip_ofs]
 357                 SUB     rscratch2,rpc,regpcbase
 358                 //if( CPU.PC - CPU.PCBase > OpAddress) return;
 359                 CMP     rscratch2,rscratch
 360                 BHI     1111f
 361 1110:
 362 .endm
 363 .macro          BranchCheck2
 364                 /*in rsctach : OpAddress
 365                 /*destroy rscratch2*/
 366                 LDRB    rscratch2,[regCPUvar,#BranchSkip_ofs]
 367                 MOVS    rscratch2,rscratch2
 368                 BEQ     1110f
 369                 MOV     rscratch2,#0
 370                 STRB    rscratch2,[regCPUvar,#BranchSkip_ofs]
 371                 SUB     rscratch2,rpc,regpcbase
 372                 //if( CPU.PC - CPU.PCBase > OpAddress) return;
 373                 CMP     rscratch2,rscratch
 374                 BHI     1111f
 375 1110:
 376 .endm
 377
 378 .macro          S9xSetPCBase
 379                 // in  : rscratch (0x00hhmmll)
 380                 PREPARE_C_CALL
 381                 BL      asm_S9xSetPCBase
 382                 RESTORE_C_CALL
 383                 LDR     rpc,[regCPUvar,#PC_ofs]
 384                 LDR     regpcbase,[regCPUvar,#PCBase_ofs]
 385 .endm
 386
 387 .macro          S9xFixCycles
 388 #ifdef  __PALMOS__
 389                 LDR             rscratch2,[regCPUvar,#PALMOS_R10_ofs]
 390 #endif
 391                 TST             rstatus,#MASK_EMUL
 392                 LDRNE           rscratch, = jumptable1     //Mode 0 : M=1,X=1
 393                 BNE             991111f
 394                 //EMULATION=0
 395                 TST             rstatus,#MASK_MEM
 396                 BEQ             991112f
 397                 //MEMORY=1
 398                 TST             rstatus,#MASK_INDEX
 399                 //INDEX=1  //Mode 0 : M=1,X=1
 400                 LDRNE           rscratch, = jumptable1
 401                 //INDEX=0  //Mode 1 : M=1,X=0
 402                 LDREQ           rscratch, = jumptable2
 403                 B               991111f
 404 991112:         //MEMORY=0
 405                 TST             rstatus,#MASK_INDEX
 406                 //INDEX=1   //Mode 3 : M=0,X=1
 407                 LDRNE           rscratch, = jumptable4
 408                 //INDEX=0   //Mode 2 : M=0,X=0
 409                 LDREQ           rscratch, = jumptable3
 410 991111:
 411 #ifdef  __PALMOS__
 412                 ADD             rscratch,rscratch,rscratch2
 413 #endif
 414                 STR             rscratch,[regCPUvar,#asm_OPTABLE_ofs]
 415 .endm
 416 .macro          S9xOpcode_NMI
 417                 SAVE_REGS
 418                 PREPARE_C_CALL_LIGHT
 419                 BL      asm_S9xOpcode_NMI
 420                 RESTORE_C_CALL_LIGHT
 421                 LOAD_REGS
 422 .endm
 423 .macro          S9xOpcode_IRQ
 424                 SAVE_REGS
 425                 PREPARE_C_CALL_LIGHT
 426                 BL      asm_S9xOpcode_IRQ
 427                 RESTORE_C_CALL_LIGHT
 428                 LOAD_REGS
 429 .endm
 430 .macro          S9xDoHBlankProcessing
 431                 SAVE_REGS
 432                 PREPARE_C_CALL_LIGHT
 433                 BL      asm_S9xDoHBlankProcessing
 434                 RESTORE_C_CALL_LIGHT
 435                 LOAD_REGS
 436 .endm
 437
 438 /********************************/
 439 .macro          EXEC_OP
 440                 LDR             R1,[regCPUvar,#asm_OPTABLE_ofs]
 441                 STR             rpc,[regCPUvar,#PCAtOpcodeStart_ofs]
 442                 ADD1MEM
 443                 LDRB            R0, [rpc], #1
 444
 445 #ifdef  __PALMOS__
 446                 LDR             R2,[regCPUvar,#PALMOS_R10_ofs]
 447                 LDR             R3,[R1,R0,LSL #2]
 448                 ADD             PC,R2,R3
 449 #else
 450                 LDR             PC, [R1,R0, LSL #2]
 451 #endif
 452 .endm
 453 .macro          NEXTOPCODE
 454 #ifdef  __TESTING__
 455                 B       endmainLoop
 456 #endif
 457                 LDR                     rscratch,[regCPUvar,#NextEvent_ofs]
 458                 CMP                     regCycles,rscratch
 459                 BLT                     mainLoop
 460                 S9xDoHBlankProcessing
 461                 B                       mainLoop
 462 .endm
 463
 464 .macro          asmAPU_EXECUTE
 465                 LDRB            R0,[regCPUvar,#APUExecuting_ofs]
 466                 MOVS            R0,R0
 467                 BEQ             43210f
 468                 //SAVE_REGS
 469                 STR             regCycles,[regCPUvar,#Cycles_ofs]
 470                 PREPARE_C_CALL_LIGHTR12
 471                 BL              asm_APU_EXECUTE
 472                 RESTORE_C_CALL_LIGHTR12
 473                 LDR             regCycles,[regCPUvar,#Cycles_ofs]
 474                 //LOAD_REGS
 475                 //S9xFixCycles
 476 43210:
 477 .endm
 478
 479 .macro          asmAPU_EXECUTE2
 480                 //SAVE_REGS
 481                 STR             regCycles,[regCPUvar,#Cycles_ofs]
 482                 PREPARE_C_CALL_LIGHTR12
 483                 BL              asm_APU_EXECUTE2
 484                 RESTORE_C_CALL_LIGHTR12
 485                 LDR             regCycles,[regCPUvar,#Cycles_ofs]
 486                 //LOAD_REGS
 487 .endm
 488
 489
 490 //void asmMainLoop(asm_cpu_var_t *asmcpuPtr);
 491 asmMainLoop:
 492         //save registers
 493         STMFD           R13!,{R4-R11,LR}
 494         //init pointer to CPUvar structure
 495         MOV             regCPUvar,R0
 496         //init registers
 497         LOAD_REGS
 498         //get cpu mode from flag and init jump table
 499         S9xFixCycles
 500 mainLoop:
 501         //APU Execute
 502         asmAPU_EXECUTE
 503
 504         //Test Flags
 505         LDR             rscratch,[regCPUvar,#Flags_ofs]
 506         MOVS            rscratch,rscratch
 507         BNE             CPUFlags_set    //If flags => check for irq/nmi/scan_keys...
 508
 509         EXEC_OP                                         //Execute next opcode
 510
 511 CPUFlags_set:   //Check flags (!=0)
 512                 TST     rscratch,#NMI_FLAG              //Check NMI
 513                 BEQ     CPUFlagsNMI_FLAG_cleared
 514                 LDR     rscratch2,[regCPUvar,#NMICycleCount_ofs]
 515                 SUBS    rscratch2,rscratch2,#1
 516                 STR     rscratch2,[regCPUvar,#NMICycleCount_ofs]
 517                 BNE     CPUFlagsNMI_FLAG_cleared
 518                 BIC     rscratch,rscratch,#NMI_FLAG
 519                 STR     rscratch,[regCPUvar,#Flags_ofs]
 520                 LDRB    rscratch2,[regCPUvar,#WaitingForInterrupt_ofs]
 521                 MOVS    rscratch2,rscratch2
 522                 BEQ     NotCPUaitingForInterruptNMI
 523                 MOV     rscratch2,#0
 524                 ADD     rpc,rpc,#1
 525                 STRB    rscratch2,[regCPUvar,#WaitingForInterrupt_ofs]
 526 NotCPUaitingForInterruptNMI:
 527                 S9xOpcode_NMI
 528                 LDR     rscratch,[regCPUvar,#Flags_ofs]
 529 CPUFlagsNMI_FLAG_cleared:
 530                 TST     rscratch,#IRQ_PENDING_FLAG   //Check IRQ_PENDING_FLAG
 531                 BEQ     CPUFlagsIRQ_PENDING_FLAG_cleared
 532                 LDR     rscratch2,[regCPUvar,#IRQCycleCount_ofs]
 533                 MOVS    rscratch2,rscratch2
 534                 BNE     CPUIRQCycleCount_NotZero
 535                 LDRB    rscratch2,[regCPUvar,#WaitingForInterrupt_ofs]
 536                 MOVS    rscratch2,rscratch2
 537                 BEQ     NotCPUaitingForInterruptIRQ
 538                 MOV     rscratch2,#0
 539                 ADD     rpc,rpc,#1
 540                 STRB    rscratch2,[regCPUvar,#WaitingForInterrupt_ofs]
 541 NotCPUaitingForInterruptIRQ:
 542                 LDRB    rscratch2,[regCPUvar,#IRQActive_ofs]
 543                 MOVS    rscratch2,rscratch2
 544                 BEQ     CPUIRQActive_cleared
 545                 TST     rstatus,#MASK_IRQ
 546                 BNE     CPUFlagsIRQ_PENDING_FLAG_cleared
 547                 S9xOpcode_IRQ
 548                 LDR     rscratch,[regCPUvar,#Flags_ofs]
 549                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
 550 CPUIRQActive_cleared:
 551                 BIC     rscratch,rscratch,#IRQ_PENDING_FLAG
 552                 STR     rscratch,[regCPUvar,#Flags_ofs]
 553                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
 554 CPUIRQCycleCount_NotZero:
 555                 SUB     rscratch2,rscratch2,#1
 556                 STR     rscratch2,[regCPUvar,#IRQCycleCount_ofs]
 557 CPUFlagsIRQ_PENDING_FLAG_cleared:
 558
 559                 TST     rscratch,#SCAN_KEYS_FLAG   //Check SCAN_KEYS_FLAG
 560                 BNE     endmainLoop
 561
 562         EXEC_OP //Execute next opcode
 563
 564 endmainLoop:
 565     /*Registers.PC = CPU.PC - CPU.PCBase;
 566     S9xPackStatus ();
 567     APURegisters.PC = IAPU.PC - IAPU.RAM;
 568     S9xAPUPackStatus ();
 569
 570     if (CPU.Flags & SCAN_KEYS_FLAG)
 571     {
 572             S9xSyncSpeed ();
 573         CPU.Flags &= ~SCAN_KEYS_FLAG;
 574     }   */
 575 /********end*/
 576         SAVE_REGS
 577         LDMFD           R13!,{R4-R11,LR}
 578         MOV             PC,LR
 579
 580
 581 .pool
 582
 583 //void test_opcode(struct asm_cpu_var *asm_var);
 584 test_opcode:
 585         //save registers
 586         STMFD           R13!,{R4-R11,LR}
 587         //init pointer to CPUvar structure
 588         MOV             regCPUvar,R0
 589         //init registers
 590         LOAD_REGS
 591         //get cpu mode from flag and init jump table
 592         S9xFixCycles
 593
 594         EXEC_OP
 595 .pool