git.maemo.org Git - drnoksnes/blob - os9x_65c816_mac_mem.h

   1 /*****************************************************************
   2
   3 *****************************************************************/
   4
   5 //#define _C_GB_
   6 //#define _C_GW_
   7 //#define _C_SB_
   8 //#define _C_SW_
   9
  10 .macro          S9xGetWord
  11                 // in  : rscratch (0x00hhmmll)
  12                 // out : rscratch (0xhhll0000)
  13 #ifdef  _C_GW_
  14                 STR     regCycles,[regCPUvar,#Cycles_ofs]
  15                 PREPARE_C_CALL
  16                 BL      asm_S9xGetWord
  17                 RESTORE_C_CALL
  18                 MOV     R0, R0, LSL #16
  19                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
  20 #else
  21                 STMFD   R13!,{PC} //Push return address
  22                 B       asmS9xGetWord
  23                 MOV     R0, R0, LSL #16
  24 #endif
  25 .endm
  26 .macro          S9xGetWordLow
  27                 // in  : rscratch (0x00hhmmll)
  28                 // out : rscratch (0x0000hhll)
  29 #ifdef  _C_GW_
  30                 STR     regCycles,[regCPUvar,#Cycles_ofs]
  31                 PREPARE_C_CALL
  32                 BL      asm_S9xGetWord
  33                 RESTORE_C_CALL
  34                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
  35 #else
  36                 STMFD   R13!,{PC} //Push return address
  37                 B       asmS9xGetWord
  38                 MOV     R0,R0
  39 #endif
  40 .endm
  41 .macro          S9xGetWordRegStatus     reg
  42                 // in  : rscratch (0x00hhmmll)
  43                 // out : reg      (0xhhll0000)
  44                 // flags have to be updated with read value
  45 #ifdef  _C_GW_
  46                 STR     regCycles,[regCPUvar,#Cycles_ofs]
  47                 PREPARE_C_CALL
  48                 BL      asm_S9xGetWord
  49                 RESTORE_C_CALL
  50                 MOVS    \reg, R0, LSL #16
  51                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
  52 #else
  53                 STMFD   R13!,{PC} //Push return address
  54                 B       asmS9xGetWord
  55                 MOV     R0,R0
  56                 MOVS    \reg, R0, LSL #16
  57 #endif
  58 .endm
  59 .macro          S9xGetWordRegNS reg
  60                 // in  : rscratch (0x00hhmmll)
  61                 // out : reg (0xhhll0000)
  62                 // DOES NOT DESTROY rscratch (R0)
  63 #ifdef  _C_GW_
  64                 STR     regCycles,[regCPUvar,#Cycles_ofs]
  65                 PREPARE_C_CALL_R0
  66                 BL      asm_S9xGetWord
  67                 MOV     \reg, R0, LSL #16
  68                 RESTORE_C_CALL_R0
  69                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
  70 #else
  71                 STMFD   R13!,{R0}
  72                 STMFD   R13!,{PC} //Push return address
  73                 B       asmS9xGetWord
  74                 MOV     R0,R0
  75                 MOV     \reg, R0, LSL #16
  76                 LDMFD   R13!,{R0}
  77 #endif
  78 .endm
  79 .macro          S9xGetWordLowRegNS      reg
  80                 // in  : rscratch (0x00hhmmll)
  81                 // out : reg (0xhhll0000)
  82                 // DOES NOT DESTROY rscratch (R0)
  83 #ifdef  _C_GW_
  84                 STR     regCycles,[regCPUvar,#Cycles_ofs]
  85                 PREPARE_C_CALL_R0
  86                 BL      asm_S9xGetWord
  87                 MOV     \reg, R0
  88                 RESTORE_C_CALL_R0
  89                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
  90 #else
  91                 STMFD   R13!,{R0}
  92                 STMFD   R13!,{PC} //Push return address
  93                 B       asmS9xGetWord
  94                 MOV     R0,R0
  95                 MOV     \reg, R0
  96                 LDMFD   R13!,{R0}
  97 #endif
  98 .endm
  99
 100 .macro          S9xGetByte
 101                 // in  : rscratch (0x00hhmmll)
 102                 // out : rscratch (0xll000000)
 103 #ifdef  _C_GB_
 104                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 105                 PREPARE_C_CALL
 106                 BL      asm_S9xGetByte
 107                 RESTORE_C_CALL
 108                 MOV     R0, R0, LSL #24
 109                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 110 #else
 111                 STMFD   R13!,{PC} //Push return address
 112                 B       asmS9xGetByte
 113                 MOV     R0,R0
 114                 MOV     R0, R0, LSL #24
 115 #endif
 116 .endm
 117 .macro          S9xGetByteLow
 118                 // in  : rscratch (0x00hhmmll)
 119                 // out : rscratch (0x000000ll)
 120 #ifdef  _C_GB_
 121                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 122                 PREPARE_C_CALL
 123                 BL      asm_S9xGetByte
 124                 RESTORE_C_CALL
 125                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 126 #else
 127                 STMFD   R13!,{PC}
 128                 B       asmS9xGetByte
 129                 MOV     R0,R0
 130 #endif
 131 .endm
 132 .macro          S9xGetByteRegStatus     reg
 133                 // in  : rscratch (0x00hhmmll)
 134                 // out : reg      (0xll000000)
 135                 // flags have to be updated with read value
 136 #ifdef  _C_GB_
 137                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 138                 PREPARE_C_CALL
 139                 BL      asm_S9xGetByte
 140                 RESTORE_C_CALL
 141                 MOVS    \reg, R0, LSL #24
 142                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 143 #else
 144                 STMFD   R13!,{PC} //Push return address
 145                 B       asmS9xGetByte
 146                 MOV     R0,R0
 147                 MOVS    \reg, R0, LSL #24
 148 #endif
 149 .endm
 150 .macro          S9xGetByteRegNS reg
 151                 // in  : rscratch (0x00hhmmll)
 152                 // out : reg      (0xll000000)
 153                 // DOES NOT DESTROY rscratch (R0)
 154 #ifdef  _C_GB_
 155                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 156                 PREPARE_C_CALL_R0
 157                 BL      asm_S9xGetByte
 158                 MOV     \reg, R0, LSL #24
 159                 RESTORE_C_CALL_R0
 160                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 161 #else
 162                 STMFD   R13!,{R0}
 163                 STMFD   R13!,{PC} //Push return address
 164                 B       asmS9xGetByte
 165                 MOV     R0,R0
 166                 MOVS    \reg, R0, LSL #24
 167                 LDMFD   R13!,{R0}
 168 #endif
 169 .endm
 170 .macro          S9xGetByteLowRegNS      reg
 171                 // in  : rscratch (0x00hhmmll)
 172                 // out : reg      (0x000000ll)
 173                 // DOES NOT DESTROY rscratch (R0)
 174 #ifdef  _C_GB_
 175                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 176                 PREPARE_C_CALL_R0
 177                 BL      asm_S9xGetByte
 178                 MOV     \reg, R0, LSL #24
 179                 RESTORE_C_CALL_R0
 180                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 181 #else
 182                 STMFD   R13!,{R0}
 183                 STMFD   R13!,{PC} //Push return address
 184                 B       asmS9xGetByte
 185                 MOV     R0,R0
 186                 MOVS    \reg, R0
 187                 LDMFD   R13!,{R0}
 188 #endif
 189 .endm
 190
 191 .macro          S9xSetWord      regValue
 192                 // in  : regValue  (0xhhll0000)
 193                 // in  : rscratch=address   (0x00hhmmll)
 194 #ifdef  _C_SW_
 195                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 196                 MOV     R1,\regValue, LSR #16
 197                 PREPARE_C_CALL
 198                 BL      asm_S9xSetWord
 199                 RESTORE_C_CALL
 200                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 201 #else
 202                 STMFD   R13!,{PC} //Push return address
 203                 MOV     R1,\regValue, LSR #16
 204                 B       asmS9xSetWord
 205                 MOV     R0,R0
 206 #endif
 207 .endm
 208 .macro          S9xSetWordZero
 209                 // in  : rscratch=address   (0x00hhmmll)
 210 #ifdef  _C_SW_
 211                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 212                 MOV     R1,#0
 213                 PREPARE_C_CALL
 214                 BL      asm_S9xSetWord
 215                 RESTORE_C_CALL
 216                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 217 #else
 218                 STMFD   R13!,{PC} //Push return address
 219                 MOV     R1,#0
 220                 B       asmS9xSetWord
 221                 MOV     R0,R0
 222 #endif
 223 .endm
 224 .macro          S9xSetWordLow   regValue
 225                 // in  : regValue  (0x0000hhll)
 226                 // in  : rscratch=address   (0x00hhmmll)
 227 #ifdef  _C_SW_
 228                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 229                 MOV     R1,\regValue
 230                 PREPARE_C_CALL
 231                 BL      asm_S9xSetWord
 232                 RESTORE_C_CALL
 233                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 234 #else
 235                 STMFD   R13!,{PC} //Push return address
 236                 MOV     R1,\regValue
 237                 B       asmS9xSetWord
 238                 MOV     R0,R0
 239 #endif
 240 .endm
 241 .macro          S9xSetByte      regValue
 242                 // in  : regValue  (0xll000000)
 243                 // in  : rscratch=address   (0x00hhmmll)
 244 #ifdef  _C_SB_
 245                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 246                 MOV     R1,\regValue, LSR #24
 247                 PREPARE_C_CALL
 248                 BL      asm_S9xSetByte
 249                 RESTORE_C_CALL
 250                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 251 #else
 252                 STMFD   R13!,{PC} //Push return address
 253                 MOV     R1,\regValue, LSR #24
 254                 B       asmS9xSetByte
 255                 MOV     R0,R0
 256 #endif
 257 .endm
 258 .macro          S9xSetByteZero
 259                 // in  : rscratch=address   (0x00hhmmll)
 260 #ifdef  _C_SB_
 261                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 262                 MOV     R1,#0
 263                 PREPARE_C_CALL
 264                 BL      asm_S9xSetByte
 265                 RESTORE_C_CALL
 266                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 267 #else
 268                 STMFD   R13!,{PC} //Push return address
 269                 MOV     R1,#0
 270                 B       asmS9xSetByte
 271                 MOV     R0,R0
 272 #endif
 273 .endm
 274 .macro          S9xSetByteLow   regValue
 275                 // in  : regValue  (0x000000ll)
 276                 // in  : rscratch=address   (0x00hhmmll)
 277 #ifdef  _C_SB_
 278                 STR     regCycles,[regCPUvar,#Cycles_ofs]
 279                 MOV     R1,\regValue
 280                 PREPARE_C_CALL
 281                 BL      asm_S9xSetByte
 282                 RESTORE_C_CALL
 283                 LDR     regCycles,[regCPUvar,#Cycles_ofs]
 284 #else
 285                 STMFD   R13!,{PC} //Push return address
 286                 MOV     R1,\regValue
 287                 B       asmS9xSetByte
 288                 MOV     R0,R0
 289 #endif
 290 .endm
 291
 292
 293 // ===========================================
 294 // ===========================================
 295 // Adressing mode
 296 // ===========================================
 297 // ===========================================
 298
 299
 300 .macro          Absolute
 301                 ADD2MEM
 302                 LDRB    rscratch2    , [rpc, #1]
 303                 LDRB    rscratch   , [rpc],#2
 304                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 305                 ORR     rscratch    , rscratch, regDBank, LSL #16
 306 .endm
 307 .macro          AbsoluteIndexedIndirectX0
 308                 ADD2MEM
 309                 LDRB    rscratch2    , [rpc, #1]
 310                 LDRB    rscratch   , [rpc], #2
 311                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 312                 ADD     rscratch    , regX, rscratch, LSL #16
 313                 MOV     rscratch , rscratch, LSR #16
 314                 ORR     rscratch    , rscratch, regPBank, LSL #16
 315                 S9xGetWordLow
 316
 317 .endm
 318 .macro          AbsoluteIndexedIndirectX1
 319                 ADD2MEM
 320                 LDRB    rscratch2    , [rpc, #1]
 321                 LDRB    rscratch   , [rpc], #2
 322                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 323                 ADD     rscratch    , rscratch, regX, LSR #24
 324                 BIC     rscratch , rscratch, #0x00FF0000
 325                 ORR     rscratch    , rscratch, regPBank, LSL #16
 326                 S9xGetWordLow
 327
 328 .endm
 329 .macro          AbsoluteIndirectLong
 330                 ADD2MEM
 331                 LDRB                    rscratch2    , [rpc, #1]
 332                 LDRB                    rscratch   , [rpc], #2
 333                 ORR                     rscratch    , rscratch, rscratch2, LSL #8
 334                 S9xGetWordLowRegNS      rscratch2
 335                 ADD                     rscratch   , rscratch,  #2
 336                 STMFD                   r13!,{rscratch2}
 337                 S9xGetByteLow
 338                 LDMFD                   r13!,{rscratch2}
 339                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 340 .endm
 341 .macro          AbsoluteIndirect
 342                 ADD2MEM
 343                 LDRB    rscratch2    , [rpc,#1]
 344                 LDRB    rscratch   , [rpc], #2
 345                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 346                 S9xGetWordLow
 347                 ORR     rscratch    , rscratch, regPBank, LSL #16
 348 .endm
 349 .macro          AbsoluteIndexedX0
 350                 ADD2MEM
 351                 LDRB    rscratch2    , [rpc, #1]
 352                 LDRB    rscratch   , [rpc], #2
 353                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 354                 ORR     rscratch    , rscratch, regDBank, LSL #16
 355                 ADD     rscratch    , rscratch, regX, LSR #16
 356 .endm
 357 .macro          AbsoluteIndexedX1
 358                 ADD2MEM
 359                 LDRB    rscratch2    , [rpc, #1]
 360                 LDRB    rscratch   , [rpc], #2
 361                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 362                 ORR     rscratch    , rscratch, regDBank, LSL #16
 363                 ADD     rscratch    , rscratch, regX, LSR #24
 364 .endm
 365
 366
 367 .macro          AbsoluteIndexedY0
 368                 ADD2MEM
 369                 LDRB    rscratch2    , [rpc, #1]
 370                 LDRB    rscratch   , [rpc], #2
 371                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 372                 ORR     rscratch    , rscratch, regDBank, LSL #16
 373                 ADD     rscratch    , rscratch, regY, LSR #16
 374 .endm
 375 .macro          AbsoluteIndexedY1
 376                 ADD2MEM
 377                 LDRB    rscratch2    , [rpc, #1]
 378                 LDRB    rscratch   , [rpc], #2
 379                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 380                 ORR     rscratch    , rscratch, regDBank, LSL #16
 381                 ADD     rscratch    , rscratch, regY, LSR #24
 382 .endm
 383 .macro          AbsoluteLong
 384                 ADD3MEM
 385                 LDRB    rscratch2    , [rpc, #1]
 386                 LDRB    rscratch   , [rpc], #2
 387                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 388                 LDRB    rscratch2   , [rpc], #1
 389                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 390 .endm
 391
 392
 393 .macro          AbsoluteLongIndexedX0
 394                 ADD3MEM
 395                 LDRB    rscratch2    , [rpc, #1]
 396                 LDRB    rscratch   , [rpc], #2
 397                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 398                 LDRB    rscratch2   , [rpc], #1
 399                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 400                 ADD     rscratch    , rscratch, regX, LSR #16
 401                 BIC     rscratch, rscratch, #0xFF000000
 402 .endm
 403 .macro          AbsoluteLongIndexedX1
 404                 ADD3MEM
 405                 LDRB    rscratch2    , [rpc, #1]
 406                 LDRB    rscratch   , [rpc], #2
 407                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 408                 LDRB    rscratch2   , [rpc], #1
 409                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 410                 ADD     rscratch    , rscratch, regX, LSR #24
 411                 BIC     rscratch, rscratch, #0xFF000000
 412 .endm
 413 .macro          Direct
 414                 ADD1MEM
 415                 LDRB    rscratch    , [rpc], #1
 416                 ADD     rscratch    , regD, rscratch, LSL #16
 417                 MOV     rscratch, rscratch, LSR #16
 418 .endm
 419 .macro          DirectIndirect
 420                 ADD1MEM
 421                 LDRB    rscratch    , [rpc], #1
 422                 ADD     rscratch    , regD, rscratch,    LSL #16
 423                 MOV     rscratch, rscratch, LSR #16
 424                 S9xGetWordLow
 425                 ORR     rscratch    , rscratch, regDBank, LSL #16
 426 .endm
 427 .macro          DirectIndirectLong
 428                 ADD1MEM
 429                 LDRB                    rscratch    , [rpc], #1
 430                 ADD                     rscratch    , regD, rscratch,    LSL #16
 431                 MOV                     rscratch, rscratch, LSR #16
 432                 S9xGetWordLowRegNS      rscratch2
 433                 ADD                     rscratch    , rscratch,#2
 434                 STMFD                   r13!,{rscratch2}
 435                 S9xGetByteLow
 436                 LDMFD                   r13!,{rscratch2}
 437                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 438 .endm
 439 .macro          DirectIndirectIndexed0
 440                 ADD1MEM
 441                 LDRB    rscratch    , [rpc], #1
 442                 ADD     rscratch    , regD, rscratch,    LSL #16
 443                 MOV     rscratch, rscratch, LSR #16
 444                 S9xGetWordLow
 445                 ORR     rscratch, rscratch,regDBank, LSL #16
 446                 ADD     rscratch, rscratch,regY, LSR #16
 447 .endm
 448 .macro          DirectIndirectIndexed1
 449                 ADD1MEM
 450                 LDRB    rscratch    , [rpc], #1
 451                 ADD     rscratch    , regD, rscratch,    LSL #16
 452                 MOV     rscratch, rscratch, LSR #16
 453                 S9xGetWordLow
 454                 ORR     rscratch, rscratch,regDBank, LSL #16
 455                 ADD     rscratch, rscratch,regY, LSR #24
 456 .endm
 457 .macro          DirectIndirectIndexedLong0
 458                 ADD1MEM
 459                 LDRB                    rscratch    , [rpc], #1
 460                 ADD                     rscratch    , regD, rscratch,    LSL #16
 461                 MOV                     rscratch, rscratch, LSR #16
 462                 S9xGetWordLowRegNS      rscratch2
 463                 ADD                     rscratch    , rscratch,#2
 464                 STMFD                   r13!,{rscratch2}
 465                 S9xGetByteLow
 466                 LDMFD                   r13!,{rscratch2}
 467                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 468                 ADD                     rscratch, rscratch,regY, LSR #16
 469 .endm
 470 .macro          DirectIndirectIndexedLong1
 471                 ADD1MEM
 472                 LDRB                    rscratch    , [rpc], #1
 473                 ADD                     rscratch    , regD, rscratch,    LSL #16
 474                 MOV                     rscratch, rscratch, LSR #16
 475                 S9xGetWordLowRegNS      rscratch2
 476                 ADD                     rscratch    , rscratch,#2
 477                 STMFD                   r13!,{rscratch2}
 478                 S9xGetByteLow
 479                 LDMFD                   r13!,{rscratch2}
 480                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 481                 ADD                     rscratch, rscratch,regY, LSR #24
 482 .endm
 483 .macro          DirectIndexedIndirect0
 484                 ADD1CYCLE1MEM
 485                 LDRB    rscratch    , [rpc], #1
 486                 ADD     rscratch2   , regD , regX
 487                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 488                 MOV     rscratch, rscratch, LSR #16
 489                 S9xGetWordLow
 490                 ORR     rscratch    , rscratch , regDBank, LSL #16
 491 .endm
 492 .macro          DirectIndexedIndirect1
 493                 ADD1CYCLE1MEM
 494                 LDRB    rscratch    , [rpc], #1
 495                 ADD     rscratch2   , regD , regX, LSR #8
 496                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 497                 MOV     rscratch, rscratch, LSR #16
 498                 S9xGetWordLow
 499                 ORR     rscratch    , rscratch , regDBank, LSL #16
 500 .endm
 501 .macro          DirectIndexedX0
 502                 ADD1CYCLE1MEM
 503                 LDRB    rscratch    , [rpc], #1
 504                 ADD     rscratch2   , regD , regX
 505                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 506                 MOV     rscratch, rscratch, LSR #16
 507 .endm
 508 .macro          DirectIndexedX1
 509                 ADD1CYCLE1MEM
 510                 LDRB    rscratch    , [rpc], #1
 511                 ADD     rscratch2   , regD , regX, LSR #8
 512                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 513                 MOV     rscratch, rscratch, LSR #16
 514 .endm
 515 .macro          DirectIndexedY0
 516                 ADD1CYCLE1MEM
 517                 LDRB    rscratch    , [rpc], #1
 518                 ADD     rscratch2   , regD , regY
 519                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 520                 MOV     rscratch, rscratch, LSR #16
 521 .endm
 522 .macro          DirectIndexedY1
 523                 ADD1CYCLE1MEM
 524                 LDRB    rscratch    , [rpc], #1
 525                 ADD     rscratch2   , regD , regY, LSR #8
 526                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 527                 MOV     rscratch, rscratch, LSR #16
 528 .endm
 529 .macro          Immediate8
 530                 ADD     rscratch, rpc, regPBank, LSL #16
 531                 SUB     rscratch, rscratch, regpcbase
 532                 ADD     rpc, rpc, #1
 533 .endm
 534 .macro          Immediate16
 535                 ADD     rscratch, rpc, regPBank, LSL #16
 536                 SUB     rscratch, rscratch, regpcbase
 537                 ADD     rpc, rpc, #2
 538 .endm
 539 .macro          asmRelative
 540                 ADD1MEM
 541                 LDRSB   rscratch    , [rpc],#1
 542                 ADD     rscratch , rscratch , rpc
 543                 SUB     rscratch , rscratch, regpcbase
 544                 BIC     rscratch,rscratch,#0x00FF0000
 545                 BIC     rscratch,rscratch,#0xFF000000
 546 .endm
 547 .macro          asmRelativeLong
 548                 ADD1CYCLE2MEM
 549                 LDRB    rscratch2    , [rpc, #1]
 550                 LDRB    rscratch   , [rpc], #2
 551                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 552                 SUB     rscratch2    , rpc, regpcbase
 553                 ADD     rscratch    , rscratch2, rscratch
 554                 BIC     rscratch,rscratch,#0x00FF0000
 555 .endm
 556
 557
 558 .macro          StackasmRelative
 559                 ADD1CYCLE1MEM
 560                 LDRB    rscratch    , [rpc], #1
 561                 ADD     rscratch    , rscratch, regS
 562                 BIC     rscratch,rscratch,#0x00FF0000
 563 .endm
 564 .macro          StackasmRelativeIndirectIndexed0
 565                 ADD2CYCLE1MEM
 566                 LDRB    rscratch    , [rpc], #1
 567                 ADD     rscratch    , rscratch, regS
 568                 BIC     rscratch,rscratch,#0x00FF0000
 569                 S9xGetWordLow
 570                 ORR     rscratch    , rscratch, regDBank, LSL #16
 571                 ADD     rscratch    , rscratch, regY, LSR #16
 572                 BIC     rscratch, rscratch, #0xFF000000
 573 .endm
 574 .macro          StackasmRelativeIndirectIndexed1
 575                 ADD2CYCLE1MEM
 576                 LDRB    rscratch    , [rpc], #1
 577                 ADD     rscratch    , rscratch, regS
 578                 BIC     rscratch,rscratch,#0x00FF0000
 579                 S9xGetWordLow
 580                 ORR     rscratch    , rscratch, regDBank, LSL #16
 581                 ADD     rscratch    , rscratch, regY, LSR #24
 582                 BIC     rscratch, rscratch, #0xFF000000
 583 .endm
 584
 585
 586 /****************************************/
 587 .macro          PushB           reg
 588                 MOV             rscratch,regS
 589                 S9xSetByte      \reg
 590                 SUB             regS,regS,#1
 591 .endm
 592 .macro          PushBLow        reg
 593                 MOV             rscratch,regS
 594                 S9xSetByteLow   \reg
 595                 SUB             regS,regS,#1
 596 .endm
 597 .macro          PushWLow        reg
 598                 SUB             rscratch,regS,#1
 599                 S9xSetWordLow   \reg
 600                 SUB             regS,regS,#2
 601 .endm
 602 .macro          PushWrLow
 603                 MOV             rscratch2,rscratch
 604                 SUB             rscratch,regS,#1
 605                 S9xSetWordLow   rscratch2
 606                 SUB             regS,regS,#2
 607 .endm
 608 .macro          PushW           reg
 609                 SUB             rscratch,regS,#1
 610                 S9xSetWord      \reg
 611                 SUB             regS,regS,#2
 612 .endm
 613
 614 /********/
 615
 616 .macro          PullB           reg
 617                 ADD             rscratch,regS,#1
 618                 S9xGetByteLow
 619                 ADD             regS,regS,#1
 620                 MOV             \reg,rscratch,LSL #24
 621 .endm
 622 .macro          PullBr
 623                 ADD             rscratch,regS,#1
 624                 S9xGetByte
 625                 ADD             regS,regS,#1
 626 .endm
 627 .macro          PullBLow        reg
 628                 ADD             rscratch,regS,#1
 629                 S9xGetByteLow
 630                 ADD             regS,regS,#1
 631                 MOV             \reg,rscratch
 632 .endm
 633 .macro          PullBrLow
 634                 ADD             rscratch,regS,#1
 635                 S9xGetByteLow
 636                 ADD             regS,regS,#1
 637 .endm
 638 .macro          PullW           reg
 639                 ADD             rscratch,regS,#1
 640                 S9xGetWordLow
 641                 ADD             regS,regS,#2
 642                 MOV             \reg,rscratch,LSL #16
 643 .endm
 644
 645 .macro          PullWLow        reg
 646                 ADD             rscratch,regS,#1
 647                 S9xGetWordLow
 648                 ADD             regS,regS,#2
 649                 MOV             \reg,rscratch
 650 .endm
 651
 652
 653 /*****************/
 654 .macro          PullBS          reg
 655                 ADD             rscratch,regS,#1
 656                 S9xGetByteLow
 657                 ADD             regS,regS,#1
 658                 MOVS            \reg,rscratch,LSL #24
 659 .endm
 660 .macro          PullBrS
 661                 ADD             rscratch,regS,#1
 662                 S9xGetByteLow
 663                 ADD             regS,regS,#1
 664                 MOVS            rscratch,rscratch,LSL #24
 665 .endm
 666 .macro          PullBLowS       reg
 667                 ADD             rscratch,regS,#1
 668                 S9xGetByteLow
 669                 ADD             regS,regS,#1
 670                 MOVS            \reg,rscratch
 671 .endm
 672 .macro          PullBrLowS
 673                 ADD             rscratch,regS,#1
 674                 S9xGetByteLow
 675                 ADD             regS,regS,#1
 676                 MOVS            rscratch,rscratch
 677 .endm
 678 .macro          PullWS          reg
 679                 ADD             rscratch,regS,#1
 680                 S9xGetWordLow
 681                 ADD             regS,regS,#2
 682                 MOVS            \reg,rscratch, LSL #16
 683 .endm
 684 .macro          PullWrS
 685                 ADD             rscratch,regS,#1
 686                 S9xGetWordLow
 687                 ADD             regS,regS,#2
 688                 MOVS            rscratch,rscratch, LSL #16
 689 .endm
 690 .macro          PullWLowS       reg
 691                 ADD             rscratch,regS,#1
 692                 S9xGetWordLow
 693                 ADD             regS,regS,#2
 694                 MOVS            \reg,rscratch
 695 .endm
 696 .macro          PullWrLowS
 697                 ADD             rscratch,regS,#1
 698                 S9xGetWordLow
 699                 ADD             regS,regS,#2
 700                 MOVS            rscratch,rscratch
 701 .endm
 702
 703
 704 .globl asmS9xGetByte
 705 .globl asmS9xGetWord
 706 .globl asmS9xSetByte
 707 .globl asmS9xSetWord
 708
 709 //uint8 aaS9xGetByte(uint32 address);
 710 asmS9xGetByte:
 711         // in : R0  = 0x00hhmmll
 712         // out : R0 = 0x000000ll
 713         // DESTROYED : R1,R2,R3
 714         // UPDATE : regCycles
 715         //R1 <= block
 716         MOV             R1,R0,LSR #MEMMAP_SHIFT
 717         //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
 718         //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
 719         //so AND MEMMAP_MASK is BIC 0xFF000
 720         BIC             R1,R1,#0xFF000
 721         //R2 <= Map[block] (GetAddress)
 722         LDR             R2,[regCPUvar,#Map_ofs]
 723         LDR             R2,[R2,R1,LSL #2]
 724         CMP             R2,#MAP_LAST
 725         BLO             GBSpecial  //special
 726         // Direct ROM/RAM acess
 727         //R2 <= GetAddress + Address & 0xFFFF
 728         //R3 <= MemorySpeed[block]
 729         LDR             R3,[regCPUvar,#MemorySpeed_ofs]
 730         MOV             R0,R0,LSL #16
 731         LDRB            R3,[R3,R1]
 732         ADD             R2,R2,R0,LSR #16
 733         //Update CPU.Cycles
 734         ADD             regCycles,regCycles,R3
 735         //R3 = BlockIsRAM[block]
 736         LDR             R3,[regCPUvar,#BlockIsRAM_ofs]
 737         //Get value to return
 738         LDRB            R0,[R2]
 739         LDRB            R3,[R3,R1]
 740         MOVS            R3,R3
 741         // if BlockIsRAM => update for CPUShutdown
 742         LDRNE           R1,[regCPUvar,#PCAtOpcodeStart_ofs]
 743         STRNE           R1,[regCPUvar,#WaitAddress_ofs]
 744
 745         LDMFD           R13!,{PC} //Return
 746 GBSpecial:
 747
 748 #ifdef __PALMOS__
 749         LDR             R3,[regCPUvar,#PALMOS_R10_ofs]
 750         LDR             R2,[PC,R2,LSL #2]
 751         ADD             PC,R2,R3
 752 #else
 753         LDR             PC,[PC,R2,LSL #2]
 754         MOV             R0,R0           //nop, for align
 755 #endif
 756         .long GBPPU
 757         .long GBCPU
 758         .long GBDSP
 759         .long GBLSRAM
 760         .long GBHSRAM
 761         .long GBNONE
 762         .long GBDEBUG
 763         .long GBC4
 764         .long GBBWRAM
 765         .long GBNONE
 766         .long GBNONE
 767         .long GBNONE
 768         /*.long GB7ROM
 769         .long GB7RAM
 770         .long GB7SRM*/
 771 GBPPU:
 772         //InDMA ?
 773         LDRB            R1,[regCPUvar,#InDMA_ofs]
 774         MOVS            R1,R1
 775         ADDEQ           regCycles,regCycles,#ONE_CYCLE          //No -> update Cycles
 776         MOV             R0,R0,LSL #16   //S9xGetPPU(Address&0xFFFF);
 777         STR             regCycles,[regCPUvar,#Cycles_ofs]       //Save Cycles
 778         MOV             R0,R0,LSR #16
 779                 PREPARE_C_CALL
 780         BL              S9xGetPPU
 781                 RESTORE_C_CALL
 782         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
 783         LDMFD           R13!,{PC} //Return
 784 GBCPU:
 785         ADD             regCycles,regCycles,#ONE_CYCLE  //update Cycles
 786         MOV             R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
 787         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
 788         MOV             R0,R0,LSR #16
 789                 PREPARE_C_CALL
 790         BL              S9xGetCPU
 791                 RESTORE_C_CALL
 792         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
 793         LDMFD           R13!,{PC} //Return
 794 GBDSP:
 795         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
 796         MOV             R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
 797         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
 798         MOV             R0,R0,LSR #16
 799                 PREPARE_C_CALL
 800         BL              S9xGetDSP
 801                 RESTORE_C_CALL
 802         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
 803         LDMFD           R13!,{PC} //Return
 804 GBLSRAM:
 805         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
 806         LDRH            R2,[regCPUvar,#SRAMMask]
 807         LDR             R1,[regCPUvar,#SRAM]
 808         AND             R0,R2,R0                //Address&SRAMMask
 809         LDRB            R0,[R1,R0]              //*Memory.SRAM + Address&SRAMMask
 810         LDMFD           R13!,{PC}
 811 GB7SRM:
 812 GBHSRAM:
 813         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
 814
 815         MOV             R1,R0,LSL #17
 816         AND             R2,R0,#0xF0000
 817         MOV             R1,R1,LSR #17   //Address&0x7FFF
 818         MOV             R2,R2,LSR #3 //(Address&0xF0000 >> 3)
 819         ADD             R0,R2,R1
 820         LDRH            R2,[regCPUvar,#SRAMMask]
 821         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
 822         LDR             R1,[regCPUvar,#SRAM]
 823         AND             R0,R2,R0                //Address&SRAMMask
 824         LDRB            R0,[R1,R0]              //*Memory.SRAM + Address&SRAMMask
 825         LDMFD           R13!,{PC}               //return
 826 GB7ROM:
 827 GB7RAM:
 828 GBNONE:
 829         MOV             R0,R0,LSR #8
 830         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
 831         AND             R0,R0,#0xFF
 832         LDMFD           R13!,{PC}
 833 //GBDEBUG:
 834         /*ADD           regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
 835         MOV             R0,#0
 836         LDMFD           R13!,{PC}*/
 837 GBC4:
 838         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
 839         MOV             R0,R0,LSL #16 //S9xGetC4(Address&0xFFFF);
 840         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
 841         MOV             R0,R0,LSR #16
 842                 PREPARE_C_CALL
 843         BL              S9xGetC4
 844                 RESTORE_C_CALL
 845         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
 846         LDMFD           R13!,{PC} //Return
 847 GBDEBUG:
 848 GBBWRAM:
 849         MOV             R0,R0,LSL #17
 850         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
 851         MOV             R0,R0,LSR #17   //Address&0x7FFF
 852         LDR             R1,[regCPUvar,#BWRAM]
 853         SUB             R0,R0,#0x6000   //((Address & 0x7fff) - 0x6000)
 854         LDRB            R0,[R0,R1]              //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
 855         LDMFD           R13!,{PC}
 856
 857
 858 //uint16 aaS9xGetWord(uint32 address);
 859 asmS9xGetWord:
 860         // in : R0  = 0x00hhmmll
 861         // out : R0 = 0x000000ll
 862         // DESTROYED : R1,R2,R3
 863         // UPDATE : regCycles
 864
 865
 866         MOV             R1,R0,LSL #19
 867         ADDS            R1,R1,#0x80000
 868         //if = 0x1FFF => 0
 869         BNE             GW_NotBoundary
 870
 871         STMFD           R13!,{R0}
 872                 STMFD           R13!,{PC}
 873         B               asmS9xGetByte
 874                 MOV             R0,R0
 875         LDMFD           R13!,{R1}
 876         STMFD           R13!,{R0}
 877         ADD             R0,R1,#1
 878                 STMFD           R13!,{PC}
 879         B               asmS9xGetByte
 880                 MOV             R0,R0
 881         LDMFD           R13!,{R1}
 882         ORR             R0,R1,R0,LSL #8
 883         LDMFD           R13!,{PC}
 884
 885 GW_NotBoundary:
 886
 887         //R1 <= block
 888         MOV             R1,R0,LSR #MEMMAP_SHIFT
 889         //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
 890         //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
 891         //so AND MEMMAP_MASK is BIC 0xFF000
 892         BIC             R1,R1,#0xFF000
 893         //R2 <= Map[block] (GetAddress)
 894         LDR             R2,[regCPUvar,#Map_ofs]
 895         LDR             R2,[R2,R1,LSL #2]
 896         CMP             R2,#MAP_LAST
 897         BLO             GWSpecial  //special
 898         // Direct ROM/RAM acess
 899
 900         TST             R0,#1
 901         BNE             GW_Not_Aligned1
 902         //R2 <= GetAddress + Address & 0xFFFF
 903         //R3 <= MemorySpeed[block]
 904         LDR             R3,[regCPUvar,#MemorySpeed_ofs]
 905         MOV             R0,R0,LSL #16
 906         LDRB            R3,[R3,R1]
 907         MOV             R0,R0,LSR #16
 908         //Update CPU.Cycles
 909         ADD             regCycles,regCycles,R3, LSL #1
 910         //R3 = BlockIsRAM[block]
 911         LDR             R3,[regCPUvar,#BlockIsRAM_ofs]
 912         //Get value to return
 913         LDRH            R0,[R2,R0]
 914         LDRB            R3,[R3,R1]
 915         MOVS            R3,R3
 916         // if BlockIsRAM => update for CPUShutdown
 917         LDRNE           R1,[regCPUvar,#PCAtOpcodeStart_ofs]
 918         STRNE           R1,[regCPUvar,#WaitAddress_ofs]
 919
 920         LDMFD           R13!,{PC} //Return
 921 GW_Not_Aligned1:
 922
 923         MOV             R0,R0,LSL #16
 924         ADD             R3,R0,#0x10000
 925         LDRB            R3,[R2,R3,LSR #16]      //GetAddress+ (Address+1)&0xFFFF
 926         LDRB            R0,[R2,R0,LSR #16]      //GetAddress+ Address&0xFFFF
 927         ORR             R0,R0,R3,LSL #8
 928
 929         // if BlockIsRAM => update for CPUShutdown
 930         LDR             R3,[regCPUvar,#BlockIsRAM_ofs]
 931         LDR             R2,[regCPUvar,#MemorySpeed_ofs]
 932         LDRB            R3,[R3,R1]   //R3 = BlockIsRAM[block]
 933         LDRB            R2,[R2,R1]   //R2 <= MemorySpeed[block]
 934         MOVS            R3,R3       //IsRAM ? CPUShutdown stuff
 935         LDRNE           R1,[regCPUvar,#PCAtOpcodeStart_ofs]
 936         STRNE           R1,[regCPUvar,#WaitAddress_ofs]
 937         ADD             regCycles,regCycles,R2, LSL #1 //Update CPU.Cycles
 938         LDMFD           R13!,{PC}  //Return
 939 GWSpecial:
 940 #ifdef __PALMOS__
 941         LDR             R3,[regCPUvar,#PALMOS_R10_ofs]
 942         LDR             R2,[PC,R2,LSL #2]
 943         ADD             PC,R2,R3
 944 #else
 945         LDR             PC,[PC,R2,LSL #2]
 946         MOV             R0,R0           //nop, for align
 947 #endif
 948         .long GWPPU
 949         .long GWCPU
 950         .long GWDSP
 951         .long GWLSRAM
 952         .long GWHSRAM
 953         .long GWNONE
 954         .long GWDEBUG
 955         .long GWC4
 956         .long GWBWRAM
 957         .long GWNONE
 958         .long GWNONE
 959         .long GWNONE
 960         /*.long GW7ROM
 961         .long GW7RAM
 962         .long GW7SRM*/
 963 /*      MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
 964         MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
 965         MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
 966
 967 GWPPU:
 968         //InDMA ?
 969         LDRB            R1,[regCPUvar,#InDMA_ofs]
 970         MOVS            R1,R1
 971         ADDEQ           regCycles,regCycles,#(ONE_CYCLE*2)              //No -> update Cycles
 972         MOV             R0,R0,LSL #16   //S9xGetPPU(Address&0xFFFF);
 973         STR             regCycles,[regCPUvar,#Cycles_ofs]       //Save Cycles
 974         MOV             R0,R0,LSR #16
 975                 PREPARE_C_CALL_R0
 976         BL              S9xGetPPU
 977         LDMFD           R13!,{R1}
 978         STMFD           R13!,{R0}
 979         ADD             R0,R1,#1
 980         //BIC           R0,R0,#0x10000
 981         BL              S9xGetPPU
 982                 RESTORE_C_CALL_R1
 983         ORR             R0,R1,R0,LSL #8
 984         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
 985         LDMFD           R13!,{PC} //Return
 986 GWCPU:
 987         ADD             regCycles,regCycles,#(ONE_CYCLE*2)      //update Cycles
 988         MOV             R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
 989         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
 990         MOV             R0,R0,LSR #16
 991                 PREPARE_C_CALL_R0
 992         BL              S9xGetCPU
 993         LDMFD           R13!,{R1}
 994         STMFD           R13!,{R0}
 995         ADD             R0,R1,#1
 996         //BIC           R0,R0,#0x10000
 997         BL              S9xGetCPU
 998                 RESTORE_C_CALL_R1
 999         ORR             R0,R1,R0,LSL #8
1000         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1001         LDMFD           R13!,{PC} //Return
1002 GWDSP:
1003         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1004         MOV             R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
1005         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1006         MOV             R0,R0,LSR #16
1007                 PREPARE_C_CALL_R0
1008         BL              S9xGetDSP
1009         LDMFD           R13!,{R1}
1010         STMFD           R13!,{R0}
1011         ADD             R0,R1,#1
1012         //BIC           R0,R0,#0x10000
1013         BL              S9xGetDSP
1014                 RESTORE_C_CALL_R1
1015         ORR             R0,R1,R0,LSL #8
1016         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1017         LDMFD           R13!,{PC} //Return
1018 GWLSRAM:
1019         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1020
1021         TST             R0,#1
1022         BNE             GW_Not_Aligned2
1023         LDRH            R2,[regCPUvar,#SRAMMask]
1024         LDR             R1,[regCPUvar,#SRAM]
1025         AND             R3,R2,R0                //Address&SRAMMask
1026         LDRH            R0,[R3,R1]              //*Memory.SRAM + Address&SRAMMask
1027         LDMFD           R13!,{PC}       //return
1028 GW_Not_Aligned2:
1029         LDRH            R2,[regCPUvar,#SRAMMask]
1030         LDR             R1,[regCPUvar,#SRAM]
1031         AND             R3,R2,R0                //Address&SRAMMask
1032         ADD             R0,R0,#1
1033         AND             R2,R0,R2                //Address&SRAMMask
1034         LDRB            R3,[R1,R3]              //*Memory.SRAM + Address&SRAMMask
1035         LDRB            R2,[R1,R2]              //*Memory.SRAM + Address&SRAMMask
1036         ORR             R0,R3,R2,LSL #8
1037         LDMFD           R13!,{PC}       //return
1038 GW7SRM:
1039 GWHSRAM:
1040         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1041
1042         TST             R0,#1
1043         BNE             GW_Not_Aligned3
1044
1045         MOV             R1,R0,LSL #17
1046         AND             R2,R0,#0xF0000
1047         MOV             R1,R1,LSR #17   //Address&0x7FFF
1048         MOV             R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1049         ADD             R0,R2,R1
1050         LDRH            R2,[regCPUvar,#SRAMMask]
1051         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1052         LDR             R1,[regCPUvar,#SRAM]
1053         AND             R0,R2,R0                //Address&SRAMMask
1054         LDRH            R0,[R1,R0]              //*Memory.SRAM + Address&SRAMMask
1055         LDMFD           R13!,{PC}               //return
1056
1057 GW_Not_Aligned3:
1058         MOV             R3,R0,LSL #17
1059         AND             R2,R0,#0xF0000
1060         MOV             R3,R3,LSR #17   //Address&0x7FFF
1061         MOV             R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1062         ADD             R2,R2,R3
1063         ADD             R0,R0,#1
1064         SUB             R2,R2,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1065         MOV             R3,R0,LSL #17
1066         AND             R0,R0,#0xF0000
1067         MOV             R3,R3,LSR #17   //(Address+1)&0x7FFF
1068         MOV             R0,R0,LSR #3 //((Address+1)&0xF0000 >> 3)
1069         ADD             R0,R0,R3
1070         LDRH            R3,[regCPUvar,#SRAMMask]        //reload mask
1071         SUB             R0,R0,#0x6000 //(((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1072         AND             R2,R3,R2                //Address...&SRAMMask
1073         AND             R0,R3,R0                //(Address+1...)&SRAMMask
1074
1075         LDR             R3,[regCPUvar,#SRAM]
1076         LDRB            R0,[R0,R3]              //*Memory.SRAM + (Address...)&SRAMMask
1077         LDRB            R2,[R2,R3]              //*Memory.SRAM + (Address+1...)&SRAMMask
1078         ORR             R0,R2,R0,LSL #8
1079
1080         LDMFD           R13!,{PC}               //return
1081 GW7ROM:
1082 GW7RAM:
1083 GWNONE:
1084         MOV             R0,R0,LSL #16
1085         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1086         MOV             R0,R0,LSR #24
1087         ORR             R0,R0,R0,LSL #8
1088         LDMFD           R13!,{PC}
1089 GWDEBUG:
1090         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1091         MOV             R0,#0
1092         LDMFD           R13!,{PC}
1093 GWC4:
1094         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1095         MOV             R0,R0,LSL #16 //S9xGetC4(Address&0xFFFF);
1096         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1097         MOV             R0,R0,LSR #16
1098                 PREPARE_C_CALL_R0
1099         BL              S9xGetC4
1100         LDMFD           R13!,{R1}
1101         STMFD           R13!,{R0}
1102         ADD             R0,R1,#1
1103         //BIC           R0,R0,#0x10000
1104         BL              S9xGetC4
1105                 RESTORE_C_CALL_R1
1106         ORR             R0,R1,R0,LSL #8
1107         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1108         LDMFD           R13!,{PC} //Return
1109 GWBWRAM:
1110         TST             R0,#1
1111         BNE             GW_Not_Aligned4
1112         MOV             R0,R0,LSL #17
1113         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1114         MOV             R0,R0,LSR #17   //Address&0x7FFF
1115         LDR             R1,[regCPUvar,#BWRAM]
1116         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1117         LDRH            R0,[R1,R0]              //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1118         LDMFD           R13!,{PC}               //return
1119 GW_Not_Aligned4:
1120         MOV             R0,R0,LSL #17
1121         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1122         ADD             R3,R0,#0x20000
1123         MOV             R0,R0,LSR #17   //Address&0x7FFF
1124         MOV             R3,R3,LSR #17   //(Address+1)&0x7FFF
1125         LDR             R1,[regCPUvar,#BWRAM]
1126         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1127         SUB             R3,R3,#0x6000 //(((Address+1) & 0x7fff) - 0x6000)
1128         LDRB            R0,[R1,R0]              //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1129         LDRB            R3,[R1,R3]              //*Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1130         ORR             R0,R0,R3,LSL #8
1131         LDMFD           R13!,{PC}               //return
1132
1133 .pool
1134
1135
1136 //void aaS9xSetByte(uint32 address,uint8 val);
1137 asmS9xSetByte:
1138         // in : R0=0x00hhmmll  R1=0x000000ll
1139         // DESTROYED : R0,R1,R2,R3
1140         // UPDATE : regCycles
1141         //cpu shutdown
1142         MOV             R2,#0
1143         STR             R2,[regCPUvar,#WaitAddress_ofs]
1144         //
1145
1146         //R3 <= block
1147         MOV             R3,R0,LSR #MEMMAP_SHIFT
1148         //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1149         //R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1150         //so AND MEMMAP_MASK is BIC 0xFF000
1151         BIC             R3,R3,#0xFF000
1152         //R2 <= Map[block] (SetAddress)
1153         LDR             R2,[regCPUvar,#WriteMap_ofs]
1154         LDR             R2,[R2,R3,LSL #2]
1155         CMP             R2,#MAP_LAST
1156         BLO             SBSpecial  //special
1157         // Direct ROM/RAM acess
1158
1159         //R2 <= SetAddress + Address & 0xFFFF
1160         MOV             R0,R0,LSL #16
1161         ADD             R2,R2,R0,LSR #16
1162         LDR             R0,[regCPUvar,#MemorySpeed_ofs]
1163         //Set byte
1164         STRB            R1,[R2]
1165         //R0 <= MemorySpeed[block]
1166         LDRB            R0,[R0,R3]
1167         //Update CPU.Cycles
1168         ADD             regCycles,regCycles,R0
1169         //CPUShutdown
1170         //only SA1 here : TODO
1171         //Return
1172         LDMFD           R13!,{PC}
1173 SBSpecial:
1174 #ifdef __PALMOS__
1175         LDR             R3,[regCPUvar,#PALMOS_R10_ofs]
1176         LDR             R2,[PC,R2,LSL #2]
1177         ADD             PC,R2,R3
1178 #else
1179         LDR             PC,[PC,R2,LSL #2]
1180         MOV             R0,R0           //nop, for align
1181 #endif
1182         .long SBPPU
1183         .long SBCPU
1184         .long SBDSP
1185         .long SBLSRAM
1186         .long SBHSRAM
1187         .long SBNONE
1188         .long SBDEBUG
1189         .long SBC4
1190         .long SBBWRAM
1191         .long SBNONE
1192         .long SBNONE
1193         .long SBNONE
1194         /*.long SB7ROM
1195         .long SB7RAM
1196         .long SB7SRM*/
1197 SBPPU:
1198         //InDMA ?
1199         LDRB            R2,[regCPUvar,#InDMA_ofs]
1200         MOVS            R2,R2
1201         ADDEQ           regCycles,regCycles,#ONE_CYCLE          //No -> update Cycles
1202         MOV             R0,R0,LSL #16
1203         STR             regCycles,[regCPUvar,#Cycles_ofs]       //Save Cycles
1204         MOV             R0,R0,LSR #16
1205                 PREPARE_C_CALL
1206         MOV             R12,R0
1207         MOV             R0,R1
1208         MOV             R1,R12
1209         BL              S9xSetPPU
1210                 RESTORE_C_CALL
1211         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1212         LDMFD           R13!,{PC} //Return
1213 SBCPU:
1214         ADD             regCycles,regCycles,#ONE_CYCLE  //update Cycles
1215         MOV             R0,R0,LSL #16
1216         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1217         MOV             R0,R0,LSR #16   //Address&0xFFFF
1218                 PREPARE_C_CALL
1219         MOV             R12,R0
1220         MOV             R0,R1
1221         MOV             R1,R12
1222         BL              S9xSetCPU
1223                 RESTORE_C_CALL
1224         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1225         LDMFD           R13!,{PC} //Return
1226 SBDSP:
1227         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
1228         MOV             R0,R0,LSL #16
1229         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1230         MOV             R0,R0,LSR #16   //Address&0xFFFF
1231                 PREPARE_C_CALL
1232         MOV             R12,R0
1233         MOV             R0,R1
1234         MOV             R1,R12
1235         BL              S9xSetDSP
1236                 RESTORE_C_CALL
1237         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1238         LDMFD           R13!,{PC} //Return
1239 SBLSRAM:
1240         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
1241         LDRH            R2,[regCPUvar,#SRAMMask]
1242         MOVS            R2,R2
1243         LDMEQFD         R13!,{PC} //return if SRAMMask=0
1244         LDR             R3,[regCPUvar,#SRAM]
1245         AND             R0,R2,R0                //Address&SRAMMask
1246         STRB            R1,[R0,R3]              //*Memory.SRAM + Address&SRAMMask
1247
1248         MOV             R0,#1
1249         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1250         LDMFD           R13!,{PC}  //return
1251 SB7SRM:
1252 SBHSRAM:
1253         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
1254
1255         MOV             R3,R0,LSL #17
1256         AND             R2,R0,#0xF0000
1257         MOV             R3,R3,LSR #17   //Address&0x7FFF
1258         MOV             R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1259         ADD             R0,R2,R3
1260
1261         LDRH            R2,[regCPUvar,#SRAMMask]
1262         MOVS            R2,R2
1263         LDMEQFD         R13!,{PC} //return if SRAMMask=0
1264
1265         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1266         LDR             R3,[regCPUvar,#SRAM]
1267         AND             R0,R2,R0                //Address&SRAMMask
1268         STRB            R1,[R0,R3]              //*Memory.SRAM + Address&SRAMMask
1269
1270         MOV             R0,#1
1271         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1272         LDMFD           R13!,{PC}       //return
1273 SB7ROM:
1274 SB7RAM:
1275 SBNONE:
1276 SBDEBUG:
1277         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
1278         LDMFD           R13!,{PC}
1279 SBC4:
1280         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
1281         MOV             R0,R0,LSL #16
1282         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1283         MOV             R0,R0,LSR #16   //Address&0xFFFF
1284                 PREPARE_C_CALL
1285         MOV             R12,R0
1286         MOV             R0,R1
1287         MOV             R1,R12
1288         BL              S9xSetC4
1289                 RESTORE_C_CALL
1290         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1291         LDMFD           R13!,{PC} //Return
1292 SBBWRAM:
1293         MOV             R0,R0,LSL #17
1294         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
1295         MOV             R0,R0,LSR #17   //Address&0x7FFF
1296         LDR             R2,[regCPUvar,#BWRAM]
1297         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1298         STRB            R1,[R0,R2]              //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1299
1300         MOV             R0,#1
1301         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1302
1303         LDMFD           R13!,{PC}
1304
1305
1306
1307 //void aaS9xSetWord(uint32 address,uint16 val);
1308 asmS9xSetWord:
1309         // in : R0  = 0x00hhmmll R1=0x0000hhll
1310         // DESTROYED : R0,R1,R2,R3
1311         // UPDATE : regCycles
1312         //R1 <= block
1313
1314         MOV             R2,R0,LSL #19
1315         ADDS            R2,R2,#0x80000
1316         //if = 0x1FFF => 0
1317         BNE             SW_NotBoundary
1318
1319         STMFD           R13!,{R0,R1}
1320                 STMFD           R13!,{PC}
1321         B               asmS9xSetByte
1322                 MOV             R0,R0
1323         LDMFD           R13!,{R0,R1}
1324         ADD             R0,R0,#1
1325         MOV             R1,R1,LSR #8
1326                 STMFD           R13!,{PC}
1327         B               asmS9xSetByte
1328                 MOV             R0,R0
1329
1330         LDMFD           R13!,{PC}
1331
1332 SW_NotBoundary:
1333
1334         MOV             R2,#0
1335         STR             R2,[regCPUvar,#WaitAddress_ofs]
1336         //
1337         //R3 <= block
1338         MOV             R3,R0,LSR #MEMMAP_SHIFT
1339         //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1340         //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1341         //so AND MEMMAP_MASK is BIC 0xFF000
1342         BIC             R3,R3,#0xFF000
1343         //R2 <= Map[block] (SetAddress)
1344         LDR             R2,[regCPUvar,#WriteMap_ofs]
1345         LDR             R2,[R2,R3,LSL #2]
1346         CMP             R2,#MAP_LAST
1347         BLO             SWSpecial  //special
1348         // Direct ROM/RAM acess
1349
1350
1351         //check if address is 16bits aligned or not
1352         TST             R0,#1
1353         BNE             SW_not_aligned1
1354         //aligned
1355         MOV             R0,R0,LSL #16
1356         ADD             R2,R2,R0,LSR #16        //address & 0xFFFF + SetAddress
1357         LDR             R0,[regCPUvar,#MemorySpeed_ofs]
1358         //Set word
1359         STRH            R1,[R2]
1360         //R1 <= MemorySpeed[block]
1361         LDRB            R0,[R0,R3]
1362         //Update CPU.Cycles
1363         ADD             regCycles,regCycles,R0, LSL #1
1364         //CPUShutdown
1365         //only SA1 here : TODO
1366         //Return
1367         LDMFD           R13!,{PC}
1368
1369 SW_not_aligned1:
1370         //R1 = (Address&0xFFFF)<<16
1371         MOV             R0,R0,LSL #16
1372         //First write @address
1373         STRB            R1,[R2,R0,LSR #16]
1374         ADD             R0,R0,#0x10000
1375         MOV             R1,R1,LSR #8
1376         //Second write @address+1
1377         STRB            R1,[R2,R0,LSR #16]
1378         //R1 <= MemorySpeed[block]
1379         LDR             R0,[regCPUvar,#MemorySpeed_ofs]
1380         LDRB            R0,[R0,R3]
1381         //Update CPU.Cycles
1382         ADD             regCycles,regCycles,R0,LSL #1
1383         //CPUShutdown
1384         //only SA1 here : TODO
1385         //Return
1386         LDMFD           R13!,{PC}
1387 SWSpecial:
1388 #ifdef __PALMOS__
1389         LDR             R3,[regCPUvar,#PALMOS_R10_ofs]
1390         LDR             R2,[PC,R2,LSL #2]
1391         ADD             PC,R2,R3
1392 #else
1393         LDR             PC,[PC,R2,LSL #2]
1394         MOV             R0,R0           //nop, for align
1395 #endif
1396         .long SWPPU
1397         .long SWCPU
1398         .long SWDSP
1399         .long SWLSRAM
1400         .long SWHSRAM
1401         .long SWNONE
1402         .long SWDEBUG
1403         .long SWC4
1404         .long SWBWRAM
1405         .long SWNONE
1406         .long SWNONE
1407         .long SWNONE
1408         /*.long SW7ROM
1409         .long SW7RAM
1410         .long SW7SRM*/
1411 SWPPU:
1412         //InDMA ?
1413         LDRB            R2,[regCPUvar,#InDMA_ofs]
1414         MOVS            R2,R2
1415         ADDEQ           regCycles,regCycles,#(ONE_CYCLE*2)              //No -> update Cycles
1416         MOV             R0,R0,LSL #16
1417         STR             regCycles,[regCPUvar,#Cycles_ofs]       //Save Cycles
1418         MOV             R0,R0,LSR #16
1419         MOV             R2,R1
1420         MOV             R1,R0
1421         MOV             R0,R2
1422                 PREPARE_C_CALL_R0R1
1423         BL              S9xSetPPU
1424         LDMFD           R13!,{R0,R1}
1425         ADD             R1,R1,#1
1426         MOV             R0,R0,LSR #8
1427         BIC             R1,R1,#0x10000
1428         BL              S9xSetPPU
1429                 RESTORE_C_CALL
1430         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1431         LDMFD           R13!,{PC} //Return
1432 SWCPU:
1433         ADD             regCycles,regCycles,#(ONE_CYCLE*2)      //update Cycles
1434         MOV             R0,R0,LSL #16
1435         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1436         MOV             R0,R0,LSR #16   //Address&0xFFFF
1437         MOV             R2,R1
1438         MOV             R1,R0
1439         MOV             R0,R2
1440                 PREPARE_C_CALL_R0R1
1441         BL              S9xSetCPU
1442         LDMFD           R13!,{R0,R1}
1443         ADD             R1,R1,#1
1444         MOV             R0,R0,LSR #8
1445         BIC             R1,R1,#0x10000
1446         BL              S9xSetCPU
1447                 RESTORE_C_CALL
1448         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1449         LDMFD           R13!,{PC} //Return
1450 SWDSP:
1451         ADD             regCycles,regCycles,#SLOW_ONE_CYCLE     //update Cycles
1452         MOV             R0,R0,LSL #16
1453         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1454         MOV             R0,R0,LSR #16   //Address&0xFFFF
1455         MOV             R2,R1
1456         MOV             R1,R0
1457         MOV             R0,R2
1458                 PREPARE_C_CALL_R0R1
1459         BL              S9xSetDSP
1460         LDMFD           R13!,{R0,R1}
1461         ADD             R1,R1,#1
1462         MOV             R0,R0,LSR #8
1463         BIC             R1,R1,#0x10000
1464         BL              S9xSetDSP
1465                 RESTORE_C_CALL
1466         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1467         LDMFD           R13!,{PC} //Return
1468 SWLSRAM:
1469         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1470         LDRH            R2,[regCPUvar,#SRAMMask]
1471         MOVS            R2,R2
1472         LDMEQFD         R13!,{PC} //return if SRAMMask=0
1473
1474         AND             R3,R2,R0                //Address&SRAMMask
1475         TST             R0,#1
1476         BNE             SW_not_aligned2
1477         //aligned
1478         LDR             R0,[regCPUvar,#SRAM]
1479         STRH            R1,[R0,R3]              //*Memory.SRAM + Address&SRAMMask
1480         MOV             R0,#1
1481         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1482         LDMFD           R13!,{PC}  //return
1483 SW_not_aligned2:
1484
1485         ADD             R0,R0,#1
1486         AND             R2,R2,R0                //(Address+1)&SRAMMask
1487         LDR             R0,[regCPUvar,#SRAM]
1488         STRB            R1,[R0,R3]              //*Memory.SRAM + Address&SRAMMask
1489         MOV             R1,R1,LSR #8
1490         STRB            R1,[R0,R2]              //*Memory.SRAM + (Address+1)&SRAMMask
1491         MOV             R0,#1
1492         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1493         LDMFD           R13!,{PC}  //return
1494 SW7SRM:
1495 SWHSRAM:
1496         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1497
1498         LDRH            R2,[regCPUvar,#SRAMMask]
1499         MOVS            R2,R2
1500         LDMEQFD         R13!,{PC} //return if SRAMMask=0
1501
1502         TST             R0,#1
1503         BNE             SW_not_aligned3
1504         //aligned
1505         MOV             R3,R0,LSL #17
1506         AND             R2,R0,#0xF0000
1507         MOV             R3,R3,LSR #17   //Address&0x7FFF
1508         MOV             R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1509         ADD             R0,R2,R3
1510         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1511         LDRH            R2,[regCPUvar,#SRAMMask]
1512         LDR             R3,[regCPUvar,#SRAM]
1513         AND             R0,R2,R0                //Address&SRAMMask
1514         STRH            R1,[R0,R3]              //*Memory.SRAM + Address&SRAMMask
1515         MOV             R0,#1
1516         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1517         LDMFD           R13!,{PC}       //return
1518 SW_not_aligned3:
1519         MOV             R3,R0,LSL #17
1520         AND             R2,R0,#0xF0000
1521         MOV             R3,R3,LSR #17   //Address&0x7FFF
1522         MOV             R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1523         ADD             R2,R2,R3
1524         SUB             R2,R2,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1525
1526         ADD             R0,R0,#1
1527         MOV             R3,R0,LSL #17
1528         AND             R0,R0,#0xF0000
1529         MOV             R3,R3,LSR #17   //(Address+1)&0x7FFF
1530         MOV             R0,R0,LSR #3 //((Address+1)&0xF0000 >> 3)
1531         ADD             R0,R0,R3
1532         LDRH            R3,[regCPUvar,#SRAMMask]        //reload mask
1533         SUB             R0,R0,#0x6000 //(((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1534         AND             R2,R3,R2                //Address...&SRAMMask
1535         AND             R0,R3,R0                //(Address+1...)&SRAMMask
1536
1537         LDR             R3,[regCPUvar,#SRAM]
1538         STRB            R1,[R2,R3]              //*Memory.SRAM + (Address...)&SRAMMask
1539         MOV             R1,R1,LSR #8
1540         STRB            R1,[R0,R3]              //*Memory.SRAM + (Address+1...)&SRAMMask
1541
1542         MOV             R0,#1
1543         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1544         LDMFD           R13!,{PC}       //return
1545 SW7ROM:
1546 SW7RAM:
1547 SWNONE:
1548 SWDEBUG:
1549         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1550         LDMFD           R13!,{PC}       //return
1551 SWC4:
1552         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1553         MOV             R0,R0,LSL #16
1554         STR             regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1555         MOV             R0,R0,LSR #16   //Address&0xFFFF
1556         MOV             R2,R1
1557         MOV             R1,R0
1558         MOV             R0,R2
1559                 PREPARE_C_CALL_R0R1
1560         BL              S9xSetC4
1561         LDMFD           R13!,{R0,R1}
1562         ADD             R1,R1,#1
1563         MOV             R0,R0,LSR #8
1564         BIC             R1,R1,#0x10000
1565         BL              S9xSetC4
1566                 RESTORE_C_CALL
1567         LDR             regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1568         LDMFD           R13!,{PC} //Return
1569 SWBWRAM:
1570         ADD             regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1571         TST             R0,#1
1572         BNE             SW_not_aligned4
1573         //aligned
1574         MOV             R0,R0,LSL #17
1575         LDR             R2,[regCPUvar,#BWRAM]
1576         MOV             R0,R0,LSR #17   //Address&0x7FFF
1577         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1578         MOV             R3,#1
1579         STRH            R1,[R0,R2]              //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1580         STRB            R3,[regCPUvar,#SRAMModified_ofs]
1581         LDMFD           R13!,{PC}       //return
1582 SW_not_aligned4:
1583         MOV             R0,R0,LSL #17
1584         ADD             R3,R0,#0x20000
1585         MOV             R0,R0,LSR #17   //Address&0x7FFF
1586         MOV             R3,R3,LSR #17   //(Address+1)&0x7FFF
1587         LDR             R2,[regCPUvar,#BWRAM]
1588         SUB             R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1589         SUB             R3,R3,#0x6000 //(((Address+1) & 0x7fff) - 0x6000)
1590         STRB            R1,[R2,R0]              //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1591         MOV             R1,R1,LSR #8
1592         STRB            R1,[R2,R3]              //*Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1593         MOV             R0,#1
1594         STRB            R0,[regCPUvar,#SRAMModified_ofs]
1595         LDMFD           R13!,{PC}               //return
1596
1597
1598 .pool