fix line endings

diff --git a/65c816ops.inc b/65c816ops.inc
index e870def..fbc7e71 100644 (file)
--- a/65c816ops.inc
+++ b/65c816ops.inc
@@ -3894,141 +3894,141 @@ static void OpDB ()
 // Reserved S9xOpcode
 static void Op42 ()
 {
-#if defined(CPU_SHUTDOWN) && !defined(SA1_OPCODES)\r
-\r
-       CPU.WaitAddress = NULL;\r
-       if (Settings.SA1) S9xSA1ExecuteDuringSleep ();\r
-\r
-       ApuSync();\r\r#ifdef VAR_CYCLES\r
-       CPU.Cycles += CPU.MemSpeed;\r
+#if defined(CPU_SHUTDOWN) && !defined(SA1_OPCODES)
+
+       CPU.WaitAddress = NULL;
+       if (Settings.SA1) S9xSA1ExecuteDuringSleep ();
+
+       ApuSync();\r\r#ifdef VAR_CYCLES
+       CPU.Cycles += CPU.MemSpeed;
 #endif
 
        //relative
        int8 b = *CPU.PC;
        CPU.PC++;
 
-       int8 BranchOffset = ((b & 0xF) | 0xF0);\r
-       uint16 OpAddress = (int)(CPU.PC - CPU.PCBase) + BranchOffset;\r
+       int8 BranchOffset = ((b & 0xF) | 0xF0);
+       uint16 OpAddress = (int)(CPU.PC - CPU.PCBase) + BranchOffset;
 
        // Assume we're going to branch
-#ifdef VAR_CYCLES\r
-       CPU.Cycles += ONE_CYCLE;\r
+#ifdef VAR_CYCLES
+       CPU.Cycles += ONE_CYCLE;
 #else
-       CPU.Cycles++;\r
+       CPU.Cycles++;
 #endif
-\r
-       switch (b >> 4) {\r
-       case 0x1: //BPL\r
-               BranchCheck1 ();\r
-               if (!CheckNegative ()) {\r
+
+       switch (b >> 4) {
+       case 0x1: //BPL
+               BranchCheck1 ();
+               if (!CheckNegative ()) {
                        CPU.PC = CPU.PCBase + OpAddress;
-#                      ifdef VAR_CYCLES\r
-                               CPU.Cycles += ONE_CYCLE;\r
+#                      ifdef VAR_CYCLES
+                               CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-               }\r
-               return;\r
-       case 0x3: //BMI\r
-               BranchCheck1 ();\r
-               if (CheckNegative ()) {\r
-                       CPU.PC = CPU.PCBase + OpAddress;\r
-#                      ifdef VAR_CYCLES\r
-                               CPU.Cycles += ONE_CYCLE;\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+               }
+               return;
+       case 0x3: //BMI
+               BranchCheck1 ();
+               if (CheckNegative ()) {
+                       CPU.PC = CPU.PCBase + OpAddress;
+#                      ifdef VAR_CYCLES
+                               CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-               }\r
-               return;\r
-       case 0x5: //BVC\r
-               BranchCheck0 ();\r
-               if (!CheckOverflow ()) {\r
-                       CPU.PC = CPU.PCBase + OpAddress;\r
-#                      ifdef VAR_CYCLES\r
-                               CPU.Cycles += ONE_CYCLE;\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+               }
+               return;
+       case 0x5: //BVC
+               BranchCheck0 ();
+               if (!CheckOverflow ()) {
+                       CPU.PC = CPU.PCBase + OpAddress;
+#                      ifdef VAR_CYCLES
+                               CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-               }\r
-               return;\r
-       case 0x7: //BVS\r
-               BranchCheck0 ();\r
-               if (CheckOverflow ()) {\r
-                               CPU.PC = CPU.PCBase + OpAddress;\r
-#                      ifdef VAR_CYCLES\r
-                               CPU.Cycles += ONE_CYCLE;\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+               }
+               return;
+       case 0x7: //BVS
+               BranchCheck0 ();
+               if (CheckOverflow ()) {
+                               CPU.PC = CPU.PCBase + OpAddress;
+#                      ifdef VAR_CYCLES
+                               CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-                       }\r
-               return;\r
-       case 0x8: //BRA\r
-               CPU.PC = CPU.PCBase + OpAddress;\r
-#              ifdef VAR_CYCLES\r
-                       CPU.Cycles += ONE_CYCLE;\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+                       }
+               return;
+       case 0x8: //BRA
+               CPU.PC = CPU.PCBase + OpAddress;
+#              ifdef VAR_CYCLES
+                       CPU.Cycles += ONE_CYCLE;
 #              else
-                       CPU.Cycles++;\r
-#              endif\r
-               CPUShutdown ();\r
-               return;\r
-       case 0x9: //BCC\r
-               BranchCheck0 ();\r
-           if (!CheckCarry ()) {\r
-                       CPU.PC = CPU.PCBase + OpAddress;\r
-#                      ifdef VAR_CYCLES\r
-                               CPU.Cycles += ONE_CYCLE;\r
+                       CPU.Cycles++;
+#              endif
+               CPUShutdown ();
+               return;
+       case 0x9: //BCC
+               BranchCheck0 ();
+           if (!CheckCarry ()) {
+                       CPU.PC = CPU.PCBase + OpAddress;
+#                      ifdef VAR_CYCLES
+                               CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-               }\r
-               return;\r
-       case 0xB: //BCS\r
-               BranchCheck0 ();\r
-               if (CheckCarry ()) {\r
-                       CPU.PC = CPU.PCBase + OpAddress;\r
-#                      ifdef VAR_CYCLES\r
-                               CPU.Cycles += ONE_CYCLE;\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+               }
+               return;
+       case 0xB: //BCS
+               BranchCheck0 ();
+               if (CheckCarry ()) {
+                       CPU.PC = CPU.PCBase + OpAddress;
+#                      ifdef VAR_CYCLES
+                               CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-               }\r
-               return;\r
-       case 0xD: //BNE\r
-               BranchCheck1 ();\r
-               if (!CheckZero ()) {\r
-                       CPU.PC = CPU.PCBase + OpAddress;\r
-#                      ifdef VAR_CYCLES\r
-                       CPU.Cycles += ONE_CYCLE;\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+               }
+               return;
+       case 0xD: //BNE
+               BranchCheck1 ();
+               if (!CheckZero ()) {
+                       CPU.PC = CPU.PCBase + OpAddress;
+#                      ifdef VAR_CYCLES
+                       CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-               }\r
-               return;\r
-       case 0xF: //BEQ\r
-               BranchCheck2 ();\r
-               if (CheckZero ()) {\r
-                       CPU.PC = CPU.PCBase + OpAddress;\r
-#                      ifdef VAR_CYCLES\r
-                               CPU.Cycles += ONE_CYCLE;\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+               }
+               return;
+       case 0xF: //BEQ
+               BranchCheck2 ();
+               if (CheckZero ()) {
+                       CPU.PC = CPU.PCBase + OpAddress;
+#                      ifdef VAR_CYCLES
+                               CPU.Cycles += ONE_CYCLE;
 #                      else
-                               CPU.Cycles++;\r
-#                      endif\r
-                       CPUShutdown ();\r
-                       }\r
+                               CPU.Cycles++;
+#                      endif
+                       CPUShutdown ();
+                       }
                return;
 #ifdef DEBUG
        default:
                printf("Invalid Op42 branch type %hx\n", b >> 4);
                return;
-#endif\r
-       }\r
+#endif
+       }
 #endif
 }
 

diff --git a/sa1cpu.cpp b/sa1cpu.cpp
index cbe0b50..3c9dcc3 100644 (file)
--- a/sa1cpu.cpp
+++ b/sa1cpu.cpp
@@ -53,7 +53,7 @@
 #define CPU SA1
 #define ICPU SA1
 
-#undef Registers\r
+#undef Registers
 
 #define Registers SA1Registers
 #define S9xGetByte S9xSA1GetByte
@@ -69,7 +69,7 @@
 #define S9xOpcode_NMI S9xSA1Opcode_NMI
 #define S9xUnpackStatus S9xSA1UnpackStatus
 #define S9xPackStatus S9xSA1PackStatus
-#define S9xFixCycles S9xSA1FixCycles\r
+#define S9xFixCycles S9xSA1FixCycles
 
 #if 0
 #define Immediate8 SA1Immediate8
@@ -93,7 +93,7 @@
 #define DirectIndirect SA1DirectIndirect
 #define DirectIndirectLong SA1DirectIndirectLong
 #define StackRelative SA1StackRelative
-#define StackRelativeIndirectIndexed SA1StackRelativeIndirectIndexed\r
+#define StackRelativeIndirectIndexed SA1StackRelativeIndirectIndexed
 #endif
 
 //#undef CPU_SHUTDOWN