git.maemo.org Git - kernel-bfs/blob - kernel-bfs-2.6.28/debian/patches/overclock_smartreflex_805.diff

   1 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/omap3-opp.h kernel-power-2.6.28.SR/arch/arm/mach-omap2/omap3-opp.h
   2 --- kernel-power-2.6.28/arch/arm/mach-omap2/omap3-opp.h 2011-10-11 13:51:21.441301622 +0100
   3 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/omap3-opp.h      2011-10-22 16:31:45.291911000 +0100
   4 @@ -11,8 +11,7 @@
   5  #define S900M   900000000
   6  #define S850M   850000000
   7  #define S805M   805000000
   8 -#define S750M   750000000
   9 -#define S700M   700000000
  10 +#define S720M   720000000
  11  #define S600M   600000000
  12  #define S550M   550000000
  13  #define S500M   500000000
  14 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/pm.c kernel-power-2.6.28.SR/arch/arm/mach-omap2/pm.c
  15 --- kernel-power-2.6.28/arch/arm/mach-omap2/pm.c        2011-10-11 13:51:21.444897248 +0100
  16 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/pm.c     2011-10-30 07:29:47.355582000 +0000
  17 @@ -44,25 +44,23 @@
  18
  19  struct omap_opp omap3_mpu_rate_table[] = {
  20         {0, 0, 0},
  21 -       {0, 1, 0x1E},
  22 -       /*underclocking*/
  23 -       {S125M, 2, 0x1E},
  24         /*default*/
  25 -       {S250M, 3, 0x26},
  26 -       {S500M, 4, 0x30},
  27 -       {S550M, 5, 0x36},
  28 -       {S600M, 6, 0x3C},
  29 +       {S125M, VDD1_OPP1,  0x1E},
  30 +       {S250M, VDD1_OPP2,  0x26},
  31 +       {S500M, VDD1_OPP3,  0x30},
  32 +       {S550M, VDD1_OPP4,  0x36},
  33 +       {S600M, VDD1_OPP5,  0x3C},
  34         /*overclocking*/
  35 -       {S700M, 7, 0x3C},
  36 -       {S750M, 8, 0x3C},
  37 -       {S805M, 9, 0x3C},
  38 -       {S850M, 10, 0x3C},
  39 -       {S900M, 11, 0x3C},
  40 -       {S950M, 12, 0x3C},
  41 -       {S1000M, 13, 0x3C},
  42 -       {S1100M, 14, 0x48},
  43 -       {S1150M, 15, 0x48},
  44 +       {S720M, VDD1_OPP6,  0x3C},
  45 +       {S805M, VDD1_OPP7,  0x3C},
  46 +       {S850M, VDD1_OPP8,  0x3C},
  47 +       {S900M, VDD1_OPP9,  0x3C},
  48 +       {S950M, VDD1_OPP10, 0x3C},
  49 +       {S1000M,VDD1_OPP11, 0x3C},
  50 +       {S1100M,VDD1_OPP12, 0x48},
  51 +       {S1150M,VDD1_OPP13, 0x48},
  52  };
  53 +EXPORT_SYMBOL(omap3_mpu_rate_table);
  54
  55  struct omap_opp omap3_l3_rate_table[] = {
  56         {0, 0, 0},
  57 @@ -76,25 +74,23 @@
  58
  59  struct omap_opp omap3_dsp_rate_table[] = {
  60         {0, 0, 0},
  61 -       /*underclocking*/
  62 -       {S90M,  1, 0x1E},
  63         /*default*/
  64 -       {S90M,  2, 0x1E},
  65 -       {S180M, 3, 0x26},
  66 -       {S360M, 4, 0x30},
  67 -       {S400M, 5, 0x36},
  68 -       {S430M, 6, 0x3C},
  69 +       {S90M,  VDD1_OPP1,  0x1E},
  70 +       {S180M, VDD1_OPP2,  0x26},
  71 +       {S360M, VDD1_OPP3,  0x30},
  72 +       {S400M, VDD1_OPP4,  0x36},
  73 +       {S430M, VDD1_OPP5,  0x3C},
  74         /*overclocking*/
  75 -       {S430M, 7, 0x3C},
  76 -       {S430M, 8, 0x3C},
  77 -       {S430M, 9, 0x3C},/*800MHz*/
  78 -       {S500M, 10, 0x3C},
  79 -       {S500M, 11, 0x3C},
  80 -       {S500M, 12, 0x3C},
  81 -       {S500M, 13, 0x3C},
  82 -       {S520M, 14, 0x48},
  83 -       {S520M, 15, 0x48},
  84 +       {S520M, VDD1_OPP6,  0x3C},
  85 +       {S520M, VDD1_OPP7,  0x3C},
  86 +       {S520M, VDD1_OPP8,  0x3C},
  87 +       {S520M, VDD1_OPP9,  0x3C},
  88 +       {S520M, VDD1_OPP10, 0x3C},
  89 +       {S520M, VDD1_OPP11, 0x3C},
  90 +       {S520M, VDD1_OPP12, 0x48},
  91 +       {S520M, VDD1_OPP13, 0x48},
  92  };
  93 +EXPORT_SYMBOL(omap3_dsp_rate_table);
  94
  95  unsigned short enable_dyn_sleep;
  96  unsigned short clocks_off_while_idle;
  97 @@ -342,13 +338,13 @@
  98         }
  99
 100         if (attr == &vdd1_opp_attr) {
 101 -               if (value < 1 || value > 5) {
 102 +               if (value < MIN_VDD1_OPP || value > MAX_VDD1_OPP) {
 103                         printk(KERN_ERR "vdd_opp_store: Invalid value\n");
 104                         return -EINVAL;
 105                 }
 106                 resource_set_opp_level(PRCM_VDD1, value, flags);
 107         } else if (attr == &vdd2_opp_attr) {
 108 -               if (value < 1 || value > 3) {
 109 +               if (value < MIN_VDD2_OPP || value > MAX_VDD2_OPP) {
 110                         printk(KERN_ERR "vdd_opp_store: Invalid value\n");
 111                         return -EINVAL;
 112                 }
 113 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.c kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.c
 114 --- kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.c       2011-10-11 13:51:21.441301622 +0100
 115 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.c    2011-10-22 14:15:45.469275000 +0100
 116 @@ -81,7 +81,8 @@
 117         u32             clk_length;
 118         u32             req_opp_no;
 119         u32             opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue;
 120 -       u32             opp5_nvalue;
 121 +       u32             opp5_nvalue;\r
 122 +       u32             opp6_nvalue, opp7_nvalue;
 123         u32             senp_mod, senn_mod;
 124         void __iomem    *srbase_addr;
 125         void __iomem    *vpbase_addr;
 126 @@ -164,6 +165,29 @@
 127                 }
 128         }
 129  }
 130 +void sr_calculate_rg(u32 rfuse, u32 gain_fuse, u32 delta_nt,\r
 131 +       u32 *rnsen, u32 *sengain)\r
 132 +{\r
 133 +       u32 nadj;\r
 134 +       nadj = ((1 << (gain_fuse + 8)) / rfuse) + delta_nt;\r
 135 +       cal_reciprocal(nadj, sengain, rnsen);\r
 136 +}\r
 137 +\r
 138 +static u32 calculate_opp_nvalue(u32 opp5_nvalue, u32 delta_p, u32 delta_n)\r
 139 +{\r
 140 +       u32 sen_pgain_fuse, sen_ngain_fuse, sen_prn_fuse, sen_nrn_fuse;\r
 141 +       u32 sen_nrn, sen_ngain, sen_prn, sen_pgain;\r
 142 +       sen_pgain_fuse = (opp5_nvalue & 0x00F0000) >> 0x14;\r
 143 +       sen_ngain_fuse = (opp5_nvalue & 0x000F0000) >> 0x10;\r
 144 +       sen_prn_fuse = (opp5_nvalue & 0x0000FF00) >> 0x08;\r
 145 +       sen_nrn_fuse = (opp5_nvalue & 0x000000FF);\r
 146 +       sr_calculate_rg(sen_nrn_fuse, sen_ngain_fuse, delta_n, &sen_nrn,\r
 147 +       &sen_ngain);\r
 148 +       sr_calculate_rg(sen_prn_fuse, sen_pgain_fuse, delta_p, &sen_prn,\r
 149 +       &sen_pgain);\r
 150 +       return (sen_pgain << 0x14) | (sen_ngain << 0x10)\r
 151 +       | (sen_prn << 0x08) | (sen_nrn);\r
 152 +}\r
 153
 154  static u32 cal_test_nvalue(u32 sennval, u32 senpval)
 155  {
 156 @@ -231,6 +255,10 @@
 157                                         OMAP343X_CONTROL_FUSE_OPP2_VDD1);
 158                 sr->opp1_nvalue = omap_ctrl_readl(
 159                                         OMAP343X_CONTROL_FUSE_OPP1_VDD1);
 160 +               if (sr->opp5_nvalue) {\r
 161 +                       sr->opp6_nvalue = calculate_opp_nvalue(sr->opp5_nvalue, 227, 379);\r
 162 +                       sr->opp7_nvalue = calculate_opp_nvalue(sr->opp5_nvalue, 434, 730);\r
 163 +               }\r
 164         } else if (sr->srid == SR2) {
 165                 sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
 166                                         OMAP343X_SR2_SENNENABLE_MASK) >>
 167 @@ -262,6 +290,10 @@
 168                 sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200);
 169                 sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0);
 170                 sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100);
 171 +               if (sr->opp5_nvalue) {\r
 172 +                       sr->opp6_nvalue = calculate_opp_nvalue(sr->opp5_nvalue, 227, 379);\r
 173 +                       sr->opp7_nvalue = calculate_opp_nvalue(sr->opp5_nvalue, 434, 730);\r
 174 +               }\r
 175         } else if (sr->srid == SR2) {
 176                 sr->senp_mod = 0x03;
 177                 sr->senn_mod = 0x03;
 178 @@ -513,7 +545,13 @@
 179         sr->req_opp_no = target_opp_no;
 180
 181         if (sr->srid == SR1) {
 182 -               switch (min(target_opp_no-1,5)) {
 183 +               switch (min(target_opp_no-1,7)) {
 184 +               case 7:\r
 185 +                       nvalue_reciprocal = sr->opp7_nvalue;\r
 186 +                       break;\r
 187 +               case 6:\r
 188 +                       nvalue_reciprocal = sr->opp6_nvalue;\r
 189 +                       break;\r
 190                 case 5:
 191                         nvalue_reciprocal = sr->opp5_nvalue;
 192                         break;
 193 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.h kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.h
 194 --- kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.h       2011-10-11 13:51:21.441301622 +0100
 195 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.h    2011-10-22 13:52:40.850113000 +0100
 196 @@ -240,7 +240,11 @@
 197                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
 198  #define PRCM_VDD1_OPP5         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 199                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
 200 -#define PRCM_NO_VDD1_OPPS      5
 201 +#define PRCM_VDD1_OPP6         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \\r
 202 +                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x6))\r
 203 +#define PRCM_VDD1_OPP7         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \\r
 204 +                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x7))\r
 205 +#define PRCM_NO_VDD1_OPPS      7
 206
 207
 208  /* VDD2 OPPs */
 209 diff -urN kernel-power-2.6.28/arch/arm/plat-omap/include/mach/omap34xx.h kernel-power-2.6.28.SR/arch/arm/plat-omap/include/mach/omap34xx.h
 210 --- kernel-power-2.6.28/arch/arm/plat-omap/include/mach/omap34xx.h      2011-10-11 13:51:21.441301622 +0100
 211 +++ kernel-power-2.6.28.SR/arch/arm/plat-omap/include/mach/omap34xx.h   2011-10-22 15:52:18.063235000 +0100
 212 @@ -107,6 +107,14 @@
 213  #define VDD1_OPP3      0x3
 214  #define VDD1_OPP4      0x4
 215  #define VDD1_OPP5      0x5
 216 +#define VDD1_OPP6      0x6\r
 217 +#define VDD1_OPP7      0x7\r
 218 +#define VDD1_OPP8      0x8\r
 219 +#define VDD1_OPP9      0x9\r
 220 +#define VDD1_OPP10     0xA\r
 221 +#define VDD1_OPP11     0xB\r
 222 +#define VDD1_OPP12     0xC\r
 223 +#define VDD1_OPP13     0xD\r
 224
 225  /* VDD2 OPPS */
 226  #define VDD2_OPP1      0x1
 227 @@ -114,8 +122,7 @@
 228  #define VDD2_OPP3      0x3
 229
 230  #define MIN_VDD1_OPP   VDD1_OPP1
 231 -/*#define MAX_VDD1_OPP VDD1_OPP5*/
 232 -#define MAX_VDD1_OPP   15
 233 +#define MAX_VDD1_OPP   VDD1_OPP13
 234  #define MIN_VDD2_OPP   VDD2_OPP1
 235  #define MAX_VDD2_OPP   VDD2_OPP3
 236