2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
14 #include "qemu-timer.h"
21 /* Only a single "CPU" interface is present. */
23 gic_get_current_cpu(void)
28 static uint32_t nvic_readl(void *opaque, uint32_t offset);
29 static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
43 /* qemu timers run at 1GHz. We want something closer to 1MHz. */
44 #define SYSTICK_SCALE 1000ULL
46 #define SYSTICK_ENABLE (1 << 0)
47 #define SYSTICK_TICKINT (1 << 1)
48 #define SYSTICK_CLKSOURCE (1 << 2)
49 #define SYSTICK_COUNTFLAG (1 << 16)
51 /* Conversion factor from qemu timer to SysTick frequencies.
52 QEMU uses a base of 1GHz, so these give 20MHz and 1MHz for core and
53 reference frequencies. */
55 static inline int64_t systick_scale(nvic_state *s)
57 if (s->systick.control & SYSTICK_CLKSOURCE)
63 static void systick_reload(nvic_state *s, int reset)
66 s->systick.tick = qemu_get_clock(vm_clock);
67 s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
68 qemu_mod_timer(s->systick.timer, s->systick.tick);
71 static void systick_timer_tick(void * opaque)
73 nvic_state *s = (nvic_state *)opaque;
74 s->systick.control |= SYSTICK_COUNTFLAG;
75 if (s->systick.control & SYSTICK_TICKINT) {
76 /* Trigger the interrupt. */
77 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
79 if (s->systick.reload == 0) {
80 s->systick.control &= ~SYSTICK_ENABLE;
86 /* The external routines use the hardware vector numbering, ie. the first
87 IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
88 void armv7m_nvic_set_pending(void *opaque, int irq)
90 nvic_state *s = (nvic_state *)opaque;
93 gic_set_pending_private(s->gic, 0, irq);
96 /* Make pending IRQ active. */
97 int armv7m_nvic_acknowledge_irq(void *opaque)
99 nvic_state *s = (nvic_state *)opaque;
102 irq = gic_acknowledge_irq(s->gic, 0);
104 cpu_abort(cpu_single_env, "Interrupt but no vector\n");
110 void armv7m_nvic_complete_irq(void *opaque, int irq)
112 nvic_state *s = (nvic_state *)opaque;
115 gic_complete_irq(s->gic, 0, irq);
118 static uint32_t nvic_readl(void *opaque, uint32_t offset)
120 nvic_state *s = (nvic_state *)opaque;
125 case 4: /* Interrupt Control Type. */
126 return (GIC_NIRQ / 32) - 1;
127 case 0x10: /* SysTick Control and Status. */
128 val = s->systick.control;
129 s->systick.control &= ~SYSTICK_COUNTFLAG;
131 case 0x14: /* SysTick Reload Value. */
132 return s->systick.reload;
133 case 0x18: /* SysTick Current Value. */
136 if ((s->systick.control & SYSTICK_ENABLE) == 0)
138 t = qemu_get_clock(vm_clock);
139 if (t >= s->systick.tick)
141 val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
142 /* The interrupt in triggered when the timer reaches zero.
143 However the counter is not reloaded until the next clock
144 tick. This is a hack to return zero during the first tick. */
145 if (val > s->systick.reload)
149 case 0x1c: /* SysTick Calibration Value. */
151 case 0xd00: /* CPUID Base. */
152 return cpu_single_env->cp15.c0_cpuid;
153 case 0xd04: /* Interrypt Control State. */
155 val = s->gic->running_irq[0];
158 } else if (val >= 32) {
162 if (s->gic->running_irq[0] == 1023
163 || s->gic->last_active[s->gic->running_irq[0]][0] == 1023) {
167 if (s->gic->current_pending[0] != 1023)
168 val |= (s->gic->current_pending[0] << 12);
170 for (irq = 32; irq < GIC_NIRQ; irq++) {
171 if (s->gic->irq_state[irq].pending) {
177 if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending)
180 if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending)
183 if (s->gic->irq_state[ARMV7M_EXCP_NMI].pending)
186 case 0xd08: /* Vector Table Offset. */
187 return cpu_single_env->v7m.vecbase;
188 case 0xd0c: /* Application Interrupt/Reset Control. */
190 case 0xd10: /* System Control. */
191 /* TODO: Implement SLEEPONEXIT. */
193 case 0xd14: /* Configuration Control. */
194 /* TODO: Implement Configuration Control bits. */
196 case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
197 irq = offset - 0xd14;
199 val = s->gic->priority1[irq++][0];
200 val = s->gic->priority1[irq++][0] << 8;
201 val = s->gic->priority1[irq++][0] << 16;
202 val = s->gic->priority1[irq][0] << 24;
204 case 0xd24: /* System Handler Status. */
206 if (s->gic->irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
207 if (s->gic->irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
208 if (s->gic->irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
209 if (s->gic->irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
210 if (s->gic->irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
211 if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
212 if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
213 if (s->gic->irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
214 if (s->gic->irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
215 if (s->gic->irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
216 if (s->gic->irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
217 if (s->gic->irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
218 if (s->gic->irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
219 if (s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
221 case 0xd28: /* Configurable Fault Status. */
222 /* TODO: Implement Fault Status. */
223 cpu_abort(cpu_single_env,
224 "Not implemented: Configurable Fault Status.");
226 case 0xd2c: /* Hard Fault Status. */
227 case 0xd30: /* Debug Fault Status. */
228 case 0xd34: /* Mem Manage Address. */
229 case 0xd38: /* Bus Fault Address. */
230 case 0xd3c: /* Aux Fault Status. */
231 /* TODO: Implement fault status registers. */
233 case 0xd40: /* PFR0. */
235 case 0xd44: /* PRF1. */
237 case 0xd48: /* DFR0. */
239 case 0xd4c: /* AFR0. */
241 case 0xd50: /* MMFR0. */
243 case 0xd54: /* MMFR1. */
245 case 0xd58: /* MMFR2. */
247 case 0xd5c: /* MMFR3. */
249 case 0xd60: /* ISAR0. */
251 case 0xd64: /* ISAR1. */
253 case 0xd68: /* ISAR2. */
255 case 0xd6c: /* ISAR3. */
257 case 0xd70: /* ISAR4. */
259 /* TODO: Implement debug registers. */
262 cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
266 static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
268 nvic_state *s = (nvic_state *)opaque;
271 case 0x10: /* SysTick Control and Status. */
272 oldval = s->systick.control;
273 s->systick.control &= 0xfffffff8;
274 s->systick.control |= value & 7;
275 if ((oldval ^ value) & SYSTICK_ENABLE) {
276 int64_t now = qemu_get_clock(vm_clock);
277 if (value & SYSTICK_ENABLE) {
278 if (s->systick.tick) {
279 s->systick.tick += now;
280 qemu_mod_timer(s->systick.timer, s->systick.tick);
282 systick_reload(s, 1);
285 qemu_del_timer(s->systick.timer);
286 s->systick.tick -= now;
287 if (s->systick.tick < 0)
290 } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
291 /* This is a hack. Force the timer to be reloaded
292 when the reference clock is changed. */
293 systick_reload(s, 1);
296 case 0x14: /* SysTick Reload Value. */
297 s->systick.reload = value;
299 case 0x18: /* SysTick Current Value. Writes reload the timer. */
300 systick_reload(s, 1);
301 s->systick.control &= ~SYSTICK_COUNTFLAG;
303 case 0xd04: /* Interrupt Control State. */
304 if (value & (1 << 31)) {
305 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
307 if (value & (1 << 28)) {
308 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
309 } else if (value & (1 << 27)) {
310 s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
313 if (value & (1 << 26)) {
314 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
315 } else if (value & (1 << 25)) {
316 s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
320 case 0xd08: /* Vector Table Offset. */
321 cpu_single_env->v7m.vecbase = value & 0xffffff80;
323 case 0xd0c: /* Application Interrupt/Reset Control. */
324 if ((value >> 16) == 0x05fa) {
326 cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
329 cpu_abort(cpu_single_env, "System reset");
333 case 0xd10: /* System Control. */
334 case 0xd14: /* Configuration Control. */
335 /* TODO: Implement control registers. */
337 case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
340 irq = offset - 0xd14;
341 s->gic->priority1[irq++][0] = value & 0xff;
342 s->gic->priority1[irq++][0] = (value >> 8) & 0xff;
343 s->gic->priority1[irq++][0] = (value >> 16) & 0xff;
344 s->gic->priority1[irq][0] = (value >> 24) & 0xff;
348 case 0xd24: /* System Handler Control. */
349 /* TODO: Real hardware allows you to set/clear the active bits
350 under some circumstances. We don't implement this. */
351 s->gic->irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
352 s->gic->irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
353 s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
355 case 0xd28: /* Configurable Fault Status. */
356 case 0xd2c: /* Hard Fault Status. */
357 case 0xd30: /* Debug Fault Status. */
358 case 0xd34: /* Mem Manage Address. */
359 case 0xd38: /* Bus Fault Address. */
360 case 0xd3c: /* Aux Fault Status. */
364 cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
368 qemu_irq *armv7m_nvic_init(CPUState *env)
373 parent = arm_pic_init_cpu(env);
374 s = (nvic_state *)qemu_mallocz(sizeof(nvic_state));
375 s->gic = gic_init(0xe000e000, &parent[ARM_PIC_CPU_IRQ]);
377 s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
379 cpu_abort(env, "CPU can only have one NVIC\n");