git.maemo.org Git - qemu/blob - hw/etraxfs_ser.c

   1 /*
   2  * QEMU ETRAX System Emulator
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <ctype.h>
  27 #include "hw.h"
  28 #include "qemu-char.h"
  29 #include "etraxfs.h"
  30
  31 #define D(x)
  32
  33 #define RW_TR_CTRL     0x00
  34 #define RW_TR_DMA_EN   0x04
  35 #define RW_REC_CTRL    0x08
  36 #define RW_DOUT        0x1c
  37 #define RS_STAT_DIN    0x20
  38 #define R_STAT_DIN     0x24
  39 #define RW_INTR_MASK   0x2c
  40 #define RW_ACK_INTR    0x30
  41 #define R_INTR         0x34
  42 #define R_MASKED_INTR  0x38
  43
  44 #define STAT_DAV     16
  45 #define STAT_TR_IDLE 22
  46 #define STAT_TR_RDY  24
  47
  48 struct etrax_serial
  49 {
  50         CPUState *env;
  51         CharDriverState *chr;
  52         qemu_irq *irq;
  53
  54         int pending_tx;
  55
  56         /* Control registers.  */
  57         uint32_t rw_tr_ctrl;
  58         uint32_t rw_tr_dma_en;
  59         uint32_t rw_rec_ctrl;
  60         uint32_t rs_stat_din;
  61         uint32_t r_stat_din;
  62         uint32_t rw_intr_mask;
  63         uint32_t rw_ack_intr;
  64         uint32_t r_intr;
  65         uint32_t r_masked_intr;
  66 };
  67
  68 static void ser_update_irq(struct etrax_serial *s)
  69 {
  70         s->r_intr &= ~(s->rw_ack_intr);
  71         s->r_masked_intr = s->r_intr & s->rw_intr_mask;
  72
  73         D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
  74                  s->rw_intr_mask, s->r_intr,
  75                  s->r_masked_intr, s->rw_ack_intr));
  76         qemu_set_irq(s->irq[0], !!s->r_masked_intr);
  77         s->rw_ack_intr = 0;
  78 }
  79
  80 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
  81 {
  82         struct etrax_serial *s = opaque;
  83         D(CPUState *env = s->env);
  84         uint32_t r = 0;
  85
  86         switch (addr)
  87         {
  88                 case RW_TR_CTRL:
  89                         r = s->rw_tr_ctrl;
  90                         break;
  91                 case RW_TR_DMA_EN:
  92                         r = s->rw_tr_dma_en;
  93                         break;
  94                 case RS_STAT_DIN:
  95                         r = s->rs_stat_din;
  96                         /* clear dav.  */
  97                         s->rs_stat_din &= ~(1 << STAT_DAV);
  98                         break;
  99                 case R_STAT_DIN:
 100                         r = s->rs_stat_din;
 101                         break;
 102                 case RW_ACK_INTR:
 103                         D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
 104                         r = s->rw_ack_intr;
 105                         break;
 106                 case RW_INTR_MASK:
 107                         r = s->rw_intr_mask;
 108                         break;
 109                 case R_INTR:
 110                         D(printf("load r_intr=%x\n", s->r_intr));
 111                         r = s->r_intr;
 112                         break;
 113                 case R_MASKED_INTR:
 114                         D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
 115                         r = s->r_masked_intr;
 116                         break;
 117
 118                 default:
 119                         D(printf ("%s %x\n", __func__, addr));
 120                         break;
 121         }
 122         return r;
 123 }
 124
 125 static void
 126 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 127 {
 128         struct etrax_serial *s = opaque;
 129         unsigned char ch = value;
 130         D(CPUState *env = s->env);
 131
 132         switch (addr)
 133         {
 134                 case RW_TR_CTRL:
 135                         D(printf("rw_tr_ctrl=%x\n", value));
 136                         s->rw_tr_ctrl = value;
 137                         break;
 138                 case RW_TR_DMA_EN:
 139                         D(printf("rw_tr_dma_en=%x\n", value));
 140                         s->rw_tr_dma_en = value;
 141                         break;
 142                 case RW_DOUT:
 143                         qemu_chr_write(s->chr, &ch, 1);
 144                         s->r_intr |= 1;
 145                         s->pending_tx = 1;
 146                         break;
 147                 case RW_ACK_INTR:
 148                         D(printf("rw_ack_intr=%x\n", value));
 149                         s->rw_ack_intr = value;
 150                         if (s->pending_tx && (s->rw_ack_intr & 1)) {
 151                                 s->r_intr |= 1;
 152                                 s->pending_tx = 0;
 153                                 s->rw_ack_intr &= ~1;
 154                         }
 155                         break;
 156                 case RW_INTR_MASK:
 157                         D(printf("r_intr_mask=%x\n", value));
 158                         s->rw_intr_mask = value;
 159                         break;
 160                 default:
 161                         D(printf ("%s %x %x\n",  __func__, addr, value));
 162                         break;
 163         }
 164         ser_update_irq(s);
 165 }
 166
 167 static CPUReadMemoryFunc *ser_read[] = {
 168         NULL, NULL,
 169         &ser_readl,
 170 };
 171
 172 static CPUWriteMemoryFunc *ser_write[] = {
 173         NULL, NULL,
 174         &ser_writel,
 175 };
 176
 177 static void serial_receive(void *opaque, const uint8_t *buf, int size)
 178 {
 179         struct etrax_serial *s = opaque;
 180
 181         s->r_intr |= 8;
 182         s->rs_stat_din &= ~0xff;
 183         s->rs_stat_din |= (buf[0] & 0xff);
 184         s->rs_stat_din |= (1 << STAT_DAV); /* dav.  */
 185         ser_update_irq(s);
 186 }
 187
 188 static int serial_can_receive(void *opaque)
 189 {
 190         struct etrax_serial *s = opaque;
 191         int r;
 192
 193         /* Is the receiver enabled?  */
 194         r = s->rw_rec_ctrl & 1;
 195
 196         /* Pending rx data?  */
 197         r |= !(s->r_intr & 8);
 198         return r;
 199 }
 200
 201 static void serial_event(void *opaque, int event)
 202 {
 203
 204 }
 205
 206 void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
 207                       target_phys_addr_t base)
 208 {
 209         struct etrax_serial *s;
 210         int ser_regs;
 211
 212         s = qemu_mallocz(sizeof *s);
 213
 214         s->env = env;
 215         s->irq = irq;
 216         s->chr = chr;
 217
 218         /* transmitter begins ready and idle.  */
 219         s->rs_stat_din |= (1 << STAT_TR_RDY);
 220         s->rs_stat_din |= (1 << STAT_TR_IDLE);
 221
 222         qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
 223                               serial_event, s);
 224
 225         ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
 226         cpu_register_physical_memory (base, 0x3c, ser_regs);
 227 }