git.maemo.org Git - qemu/blob - hw/omap3.c

   1 /*
   2  * TI OMAP3 processors emulation.
   3  *
   4  * Copyright (C) 2008 yajin <yajin@vm-kernel.org>
   5  * Copyright (C) 2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include "hw.h"
  24 #include "arm-misc.h"
  25 #include "omap.h"
  26 #include "sysemu.h"
  27 #include "qemu-timer.h"
  28 #include "qemu-char.h"
  29 #include "flash.h"
  30 #include "soc_dma.h"
  31 #include "audio/audio.h"
  32 #include "block.h"
  33
  34 //#define OMAP3_DEBUG_
  35
  36 #ifdef OMAP3_DEBUG_
  37 #define TRACE(fmt, ...) fprintf(stderr, "%s " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
  38 #else
  39 #define TRACE(...)
  40 #endif
  41
  42 typedef enum {
  43     /* 68000000-680003FF */ L3ID_L3RT = 0,
  44     /* 68000400-680007FF */ L3ID_L3SI,
  45     /* 68000800-680013FF */
  46     /* 68001400-680017FF */ L3ID_MPUSS_IA,
  47     /* 68001800-68001BFF */ L3ID_IVASS_IA,
  48     /* 68001C00-68001FFF */ L3ID_SGXSS_IA,
  49     /* 68002000-680023FF */ L3ID_SMS_TA,
  50     /* 68002400-680027FF */ L3ID_GPMC_TA,
  51     /* 68002800-68002BFF */ L3ID_OCM_RAM_TA,
  52     /* 68002C00-68002FFF */ L3ID_OCM_ROM_TA,
  53     /* 68003000-680033FF */ L3ID_D2D_IA,
  54     /* 68003400-680037FF */ L3ID_D2D_TA,
  55     /* 68003800-68003FFF */
  56     /* 68004000-680043FF */ L3ID_HSUSB_HOST_IA,
  57     /* 68004400-680047FF */ L3ID_HSUSB_OTG_IA,
  58     /* 68004800-68004BFF */
  59     /* 68004C00-68004FFF */ L3ID_SDMA_RD_IA,
  60     /* 68005000-680053FF */ L3ID_SDMA_WR_IA,
  61     /* 68005400-680057FF */ L3ID_DSS_IA,
  62     /* 68005800-68005BFF */ L3ID_CAMISP_IA,
  63     /* 68005C00-68005FFF */ L3ID_DAP_IA,
  64     /* 68006000-680063FF */ L3ID_IVASS_TA,
  65     /* 68006400-680067FF */ L3ID_SGXSS_TA,
  66     /* 68006800-68006BFF */ L3ID_L4_CORE_TA,
  67     /* 68006C00-68006FFF */ L3ID_L4_PER_TA,
  68     /* 68007000-680073FF */ L3ID_L4_EMU_TA,
  69     /* 68007400-6800FFFF */
  70     /* 68010000-680103FF */ L3ID_RT_PM,
  71     /* 68010400-680123FF */
  72     /* 68012400-680127FF */ L3ID_GPMC_PM,
  73     /* 68012800-68012BFF */ L3ID_OCM_RAM_PM,
  74     /* 68012C00-68012FFF */ L3ID_OCM_ROM_PM,
  75     /* 68013000-680133FF */ L3ID_D2D_PM,
  76     /* 68013400-68013FFF */
  77     /* 68014000-680143FF */ L3ID_IVA_PM,
  78     /* 68014400-68FFFFFF */
  79 } omap3_l3_region_id_t;
  80
  81 struct omap_l3_region_s {
  82     target_phys_addr_t offset;
  83     size_t size;
  84     enum {
  85         L3TYPE_GENERIC = 0, /* needs to be mapped separately */
  86         L3TYPE_IA,          /* initiator agent */
  87         L3TYPE_TA,          /* target agent */
  88         L3TYPE_PM,          /* protection mechanism */
  89         L3TYPE_UNDEFINED,   /* every access will emit an error message */
  90     } type;
  91 };
  92
  93 struct omap3_l3_initiator_agent_s {
  94     target_phys_addr_t base;
  95
  96     uint32_t component;
  97     uint32_t control;
  98     uint32_t status;
  99 };
 100
 101 struct omap3_l3pm_s {
 102     target_phys_addr_t base;
 103
 104     uint32_t error_log;
 105     uint8_t  control;
 106     uint16_t req_info_permission[8];
 107     uint16_t read_permission[8];
 108     uint16_t write_permission[8];
 109     uint32_t addr_match[7];
 110 };
 111
 112 union omap3_l3_port_s {
 113     struct omap_target_agent_s ta;
 114     struct omap3_l3_initiator_agent_s ia;
 115     struct omap3_l3pm_s pm;
 116 };
 117
 118 struct omap_l3_s {
 119     target_phys_addr_t base;
 120     int region_count;
 121     union omap3_l3_port_s region[0];
 122 };
 123
 124 static struct omap_l3_region_s omap3_l3_region[] = {
 125     [L3ID_L3RT         ] = {0x00000000, 0x0400, L3TYPE_UNDEFINED},
 126     [L3ID_L3SI         ] = {0x00000400, 0x0400, L3TYPE_UNDEFINED},
 127     [L3ID_MPUSS_IA     ] = {0x00001400, 0x0400, L3TYPE_IA},
 128     [L3ID_IVASS_IA     ] = {0x00001800, 0x0400, L3TYPE_IA},
 129     [L3ID_SGXSS_IA     ] = {0x00001c00, 0x0400, L3TYPE_IA},
 130     [L3ID_SMS_TA       ] = {0x00002000, 0x0400, L3TYPE_TA},
 131     [L3ID_GPMC_TA      ] = {0x00002400, 0x0400, L3TYPE_TA},
 132     [L3ID_OCM_RAM_TA   ] = {0x00002800, 0x0400, L3TYPE_TA},
 133     [L3ID_OCM_ROM_TA   ] = {0x00002c00, 0x0400, L3TYPE_TA},
 134     [L3ID_D2D_IA       ] = {0x00003000, 0x0400, L3TYPE_IA},
 135     [L3ID_D2D_TA       ] = {0x00003400, 0x0400, L3TYPE_TA},
 136     [L3ID_HSUSB_HOST_IA] = {0x00004000, 0x0400, L3TYPE_IA},
 137     [L3ID_HSUSB_OTG_IA ] = {0x00004400, 0x0400, L3TYPE_IA},
 138     [L3ID_SDMA_RD_IA   ] = {0x00004c00, 0x0400, L3TYPE_IA},
 139     [L3ID_SDMA_WR_IA   ] = {0x00005000, 0x0400, L3TYPE_IA},
 140     [L3ID_DSS_IA       ] = {0x00005400, 0x0400, L3TYPE_IA},
 141     [L3ID_CAMISP_IA    ] = {0x00005800, 0x0400, L3TYPE_IA},
 142     [L3ID_DAP_IA       ] = {0x00005c00, 0x0400, L3TYPE_IA},
 143     [L3ID_IVASS_TA     ] = {0x00006000, 0x0400, L3TYPE_TA},
 144     [L3ID_SGXSS_TA     ] = {0x00006400, 0x0400, L3TYPE_TA},
 145     [L3ID_L4_CORE_TA   ] = {0x00006800, 0x0400, L3TYPE_TA},
 146     [L3ID_L4_PER_TA    ] = {0x00006c00, 0x0400, L3TYPE_TA},
 147     [L3ID_L4_EMU_TA    ] = {0x00007000, 0x0400, L3TYPE_TA},
 148     [L3ID_RT_PM        ] = {0x00010000, 0x0400, L3TYPE_PM},
 149     [L3ID_GPMC_PM      ] = {0x00012400, 0x0400, L3TYPE_PM},
 150     [L3ID_OCM_RAM_PM   ] = {0x00012800, 0x0400, L3TYPE_PM},
 151     [L3ID_OCM_ROM_PM   ] = {0x00012c00, 0x0400, L3TYPE_PM},
 152     [L3ID_D2D_PM       ] = {0x00013000, 0x0400, L3TYPE_PM},
 153     [L3ID_IVA_PM       ] = {0x00014000, 0x0400, L3TYPE_PM},
 154 };
 155
 156 static uint32_t omap3_l3ia_read(void *opaque, target_phys_addr_t addr)
 157 {
 158     struct omap3_l3_initiator_agent_s *s = (struct omap3_l3_initiator_agent_s *)opaque;
 159
 160     switch (addr) {
 161         case 0x00: /* COMPONENT_L */
 162             return s->component;
 163         case 0x04: /* COMPONENT_H */
 164             return 0;
 165         case 0x18: /* CORE_L */
 166             return s->component;
 167         case 0x1c: /* CORE_H */
 168             return (s->component >> 16);
 169         case 0x20: /* AGENT_CONTROL_L */
 170             return s->control;
 171         case 0x24: /* AGENT_CONTROL_H */
 172             return 0;
 173         case 0x28: /* AGENT_STATUS_L */
 174             return s->status;
 175         case 0x2c: /* AGENT_STATUS_H */
 176             return 0;
 177         case 0x58: /* ERROR_LOG_L */
 178             return 0;
 179         case 0x5c: /* ERROR_LOG_H */
 180             return 0;
 181         case 0x60: /* ERROR_LOG_ADDR_L */
 182             return 0;
 183         case 0x64: /* ERROR_LOG_ADDR_H */
 184             return 0;
 185         default:
 186             break;
 187     }
 188
 189     OMAP_BAD_REG(s->base + addr);
 190     return 0;
 191 }
 192
 193 static void omap3_l3ia_write(void *opaque, target_phys_addr_t addr,
 194                              uint32_t value)
 195 {
 196     struct omap3_l3_initiator_agent_s *s = (struct omap3_l3_initiator_agent_s *)opaque;
 197
 198     switch (addr) {
 199         case 0x00: /* COMPONENT_L */
 200         case 0x04: /* COMPONENT_H */
 201         case 0x18: /* CORE_L */
 202         case 0x1c: /* CORE_H */
 203         case 0x60: /* ERROR_LOG_ADDR_L */
 204         case 0x64: /* ERROR_LOG_ADDR_H */
 205             OMAP_RO_REG(s->base + addr);
 206             break;
 207         case 0x24: /* AGENT_CONTROL_H */
 208         case 0x2c: /* AGENT_STATUS_H */
 209         case 0x5c: /* ERROR_LOG_H */
 210             /* RW register but all bits are reserved/read-only */
 211             break;
 212         case 0x20: /* AGENT_CONTROL_L */
 213             s->control = value & 0x3e070711;
 214             /* TODO: some bits are reserved for some IA instances */
 215             break;
 216         case 0x28: /* AGENT_STATUS_L */
 217             s->status &= ~(value & 0x30000000);
 218             break;
 219         case 0x58: /* ERROR_LOG_L */
 220             /* error logging is not implemented, so ignore */
 221             break;
 222         default:
 223             OMAP_BAD_REG(s->base + addr);
 224             break;
 225     }
 226 }
 227
 228 static void omap3_l3ia_init(struct omap3_l3_initiator_agent_s *s)
 229 {
 230     s->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
 231     s->control = 0x3e000000;
 232     s->status = 0;
 233 }
 234
 235 static CPUReadMemoryFunc *omap3_l3ia_readfn[] = {
 236     omap_badwidth_read32,
 237     omap_badwidth_read32,
 238     omap3_l3ia_read,
 239 };
 240
 241 static CPUWriteMemoryFunc *omap3_l3ia_writefn[] = {
 242     omap_badwidth_write32,
 243     omap_badwidth_write32,
 244     omap3_l3ia_write,
 245 };
 246
 247 static uint32_t omap3_l3ta_read(void *opaque, target_phys_addr_t addr)
 248 {
 249     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
 250
 251     switch (addr) {
 252         case 0x00: /* COMPONENT_L */
 253             return s->component;
 254         case 0x04: /* COMPONENT_H */
 255             return 0;
 256         case 0x18: /* CORE_L */
 257             return s->component;
 258         case 0x1c: /* CORE_H */
 259             return (s->component >> 16);
 260         case 0x20: /* AGENT_CONTROL_L */
 261             return s->control;
 262         case 0x24: /* AGENT_CONTROL_H */
 263             return s->control_h;
 264         case 0x28: /* AGENT_STATUS_L */
 265             return s->status;
 266         case 0x2c: /* AGENT_STATUS_H */
 267             return 0;
 268         case 0x58: /* ERROR_LOG_L */
 269             return 0;
 270         case 0x5c: /* ERROR_LOG_H */
 271             return 0;
 272         case 0x60: /* ERROR_LOG_ADDR_L */
 273             return 0;
 274         case 0x64: /* ERROR_LOG_ADDR_H */
 275             return 0;
 276         default:
 277             break;
 278     }
 279
 280     OMAP_BAD_REG(s->base + addr);
 281     return 0;
 282 }
 283
 284 static void omap3_l3ta_write(void *opaque, target_phys_addr_t addr,
 285                              uint32_t value)
 286 {
 287     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
 288
 289     switch (addr) {
 290         case 0x00: /* COMPONENT_L */
 291         case 0x04: /* COMPONENT_H */
 292         case 0x18: /* CORE_L */
 293         case 0x1c: /* CORE_H */
 294         case 0x60: /* ERROR_LOG_ADDR_L */
 295         case 0x64: /* ERROR_LOG_ADDR_H */
 296             OMAP_RO_REG(s->base + addr);
 297             break;
 298         case 0x24: /* AGENT_CONTROL_H */
 299         case 0x5c: /* ERROR_LOG_H */
 300             /* RW register but all bits are reserved/read-only */
 301             break;
 302         case 0x20: /* AGENT_CONTROL_L */
 303             s->control = value & 0x03000711;
 304             break;
 305         case 0x28: /* AGENT_STATUS_L */
 306             if (s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_CORE_TA].offset
 307                 || s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_PER_TA].offset
 308                 || s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_EMU_TA].offset) {
 309                 s->status &= ~(value & (1 << 24));
 310             } else
 311                 OMAP_RO_REG(s->base + addr);
 312             break;
 313         case 0x2c: /* AGENT_STATUS_H */
 314             if (s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_CORE_TA].offset
 315                 && s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_PER_TA].offset
 316                 && s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_EMU_TA].offset)
 317                 OMAP_RO_REG(s->base + addr);
 318             /* for L4 core, per, emu TAs this is RW reg */
 319             break;
 320         case 0x58: /* ERROR_LOG_L */
 321             /* error logging is not implemented, so ignore */
 322             break;
 323         default:
 324             OMAP_BAD_REG(s->base + addr);
 325             break;
 326     }
 327 }
 328
 329 static void omap3_l3ta_init(struct omap_target_agent_s *s)
 330 {
 331     s->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
 332     s->control = 0x03000000;
 333     s->status = 0;
 334 }
 335
 336 static CPUReadMemoryFunc *omap3_l3ta_readfn[] = {
 337     omap_badwidth_read32,
 338     omap_badwidth_read32,
 339     omap3_l3ta_read,
 340 };
 341
 342 static CPUWriteMemoryFunc *omap3_l3ta_writefn[] = {
 343     omap_badwidth_write32,
 344     omap_badwidth_write32,
 345     omap3_l3ta_write,
 346 };
 347
 348 static uint32_t omap3_l3pm_read8(void *opaque, target_phys_addr_t addr)
 349 {
 350     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 351     int i;
 352
 353     switch (addr) {
 354         case 0x00 ... 0x1f:
 355         case 0x40 ... 0x47:
 356             OMAP_BAD_REG(s->base + addr);
 357             return 0;
 358         /* ERROR_LOG */
 359         case 0x20: return s->error_log & 0xff;
 360         case 0x21: return (s->error_log >> 8) & 0xff;
 361         case 0x22: return (s->error_log >> 16) & 0xff;
 362         case 0x23: return (s->error_log >> 24) & 0xff;
 363         case 0x24 ... 0x27: return 0;
 364         /* CONTROL */
 365         case 0x28 ... 0x2a: return 0;
 366         case 0x2b: return s->control;
 367         case 0x2c ... 0x2f: return 0;
 368         /* ERROR_CLEAR_SINGLE */
 369         case 0x30: return 0; /* TODO: clear single error from log */
 370         case 0x31 ... 0x37: return 0;
 371         /* ERROR_CLEAR_MULTI */
 372         case 0x38: return 0; /* TODO: clear multiple errors from log */
 373         case 0x39 ... 0x3f: return 0;
 374         default:
 375             break;
 376     }
 377
 378     i = (addr - 0x48) / 0x20;
 379     addr -= i * 0x20;
 380     if (i < 7 || (i < 8 && addr < 0x60))
 381         switch (addr) {
 382             /* REQ_INFO_PERMISSION_i */
 383             case 0x48: return s->req_info_permission[i] & 0xff;
 384             case 0x49: return (s->req_info_permission[i] >> 8) & 0xff;
 385             case 0x4a ... 0x4f: return 0;
 386             /* READ_PERMISSION_i */
 387             case 0x50: return s->read_permission[i] & 0xff;
 388             case 0x51: return (s->read_permission[i] >> 8) & 0xff;
 389             case 0x52 ... 0x57: return 0;
 390             /* WRITE_PERMISSION_i */
 391             case 0x58: return s->write_permission[i] & 0xff;
 392             case 0x59: return (s->write_permission[i] >> 8) & 0xff;
 393             case 0x5a ... 0x5f: return 0;
 394             /* ADDR_MATCH_i */
 395             case 0x60: return s->addr_match[i] & 0xff;
 396             case 0x61: return (s->addr_match[i] >> 8) & 0xff;
 397             case 0x62: return (s->addr_match[i] >> 16) & 0xff;
 398             case 0x63 ... 0x67: return 0;
 399             default:
 400                 break;
 401         }
 402
 403     OMAP_BAD_REG(s->base + addr);
 404     return 0;
 405 }
 406
 407 static uint32_t omap3_l3pm_read16(void *opaque, target_phys_addr_t addr)
 408 {
 409     return omap3_l3pm_read8(opaque, addr)
 410         | (omap3_l3pm_read8(opaque, addr + 1) << 8);
 411 }
 412
 413 static uint32_t omap3_l3pm_read32(void *opaque, target_phys_addr_t addr)
 414 {
 415     return omap3_l3pm_read16(opaque, addr)
 416         | (omap3_l3pm_read16(opaque, addr + 2) << 16);
 417 }
 418
 419 static void omap3_l3pm_write8(void *opaque, target_phys_addr_t addr,
 420                               uint32_t value)
 421 {
 422     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 423     int i;
 424
 425     switch (addr) {
 426         case 0x00 ... 0x1f:
 427         case 0x40 ... 0x47:
 428             OMAP_BAD_REGV(s->base + addr, value);
 429             return;
 430         /* ERROR_LOG */
 431         case 0x23:
 432             s->error_log &= ~((value & 0xcf) << 24);
 433         case 0x20 ... 0x22:
 434         case 0x24 ... 0x27:
 435             return;
 436         /* CONTROL */
 437         case 0x2b:
 438             s->control = value & 3;
 439         case 0x28 ... 0x2a:
 440         case 0x2c ... 0x2f:
 441             return;
 442         /* ERROR_CLEAR_SINGLE / ERROR_CLEAR_MULTI */
 443         case 0x30 ... 0x3f:
 444             OMAP_RO_REGV(s->base + addr, value);
 445             return;
 446         default:
 447             break;
 448     }
 449
 450     i = (addr - 0x48) / 0x20;
 451     addr -= i * 0x20;
 452     if (i < 7 || (i < 8 && addr < 0x60))
 453         switch (addr) {
 454             /* REQ_INFO_PERMISSION_i */
 455             case 0x48:
 456                 s->req_info_permission[i] =
 457                     (s->req_info_permission[i] & ~0xff) | (value & 0xff);
 458                 return;
 459             case 0x49:
 460                 s->req_info_permission[i] =
 461                     (s->req_info_permission[i] & ~0xff00) | ((value & 0xff) << 8);
 462                 return;
 463             case 0x4a ... 0x4f:
 464                 return;
 465             /* READ_PERMISSION_i */
 466             case 0x50:
 467                 s->read_permission[i] =
 468                     (s->read_permission[i] & ~0xff) | (value & 0x3e);
 469                 return;
 470             case 0x51:
 471                 s->read_permission[i] =
 472                     (s->read_permission[i] & ~0xff00) | ((value & 0x5f) << 8);
 473                 return;
 474             case 0x52 ... 0x57:
 475                 return;
 476             /* WRITE_PERMISSION_i */
 477             case 0x58:
 478                 s->write_permission[i] =
 479                     (s->write_permission[i] & ~0xff) | (value & 0x3e);
 480                 return;
 481             case 0x59:
 482                 s->write_permission[i] =
 483                     (s->write_permission[i] & ~0xff00) | ((value & 0x5f) << 8);
 484                 return;
 485             case 0x5a ... 0x5f:
 486                 return;
 487             /* ADDR_MATCH_i */
 488             case 0x60:
 489                 s->addr_match[i] = (s->addr_match[i] & ~0xff) | (value & 0xff);
 490                 return;
 491             case 0x61:
 492                 s->addr_match[i] =
 493                     (s->addr_match[i] & ~0xfe00) | ((value & 0xfe) << 8);
 494                 return;
 495             case 0x62:
 496                 s->addr_match[i] =
 497                     (s->addr_match[i] & ~0x0f0000) | ((value & 0x0f) << 16);
 498                 return;
 499             case 0x63 ... 0x67:
 500                 return;
 501             default:
 502                 break;
 503         }
 504
 505     OMAP_BAD_REGV(s->base + addr, value);
 506 }
 507
 508 static void omap3_l3pm_write16(void *opaque, target_phys_addr_t addr,
 509                                uint32_t value)
 510 {
 511     omap3_l3pm_write8(opaque, addr + 0, value & 0xff);
 512     omap3_l3pm_write8(opaque, addr + 1, (value >> 8) & 0xff);
 513 }
 514
 515 static void omap3_l3pm_write32(void *opaque, target_phys_addr_t addr,
 516                                uint32_t value)
 517 {
 518     omap3_l3pm_write16(opaque, addr + 0, value & 0xffff);
 519     omap3_l3pm_write16(opaque, addr + 2, (value >> 16) & 0xffff);
 520 }
 521
 522 static void omap3_l3pm_init(struct omap3_l3pm_s *s)
 523 {
 524     int i;
 525
 526     s->error_log = 0;
 527     s->control = 0x03;
 528     switch (s->base) {
 529         case 0x68010000: /* PM_RT */
 530             s->req_info_permission[0] = 0xffff;
 531             s->req_info_permission[1] = 0;
 532             for (i = 0; i < 2; i++)
 533                 s->read_permission[i] = s->write_permission[i] = 0x1406;
 534             s->addr_match[0] = 0x10230;
 535             break;
 536         case 0x68012400: /* PM_GPMC */
 537             s->req_info_permission[0] = 0;
 538             for (i = 3; i < 8; i++)
 539                 s->req_info_permission[i] = 0xffff;
 540             for (i = 0; i < 8; i++)
 541                 s->read_permission[i] = s->write_permission[i] = 0x563e;
 542             s->addr_match[0] = 0x00098;
 543             break;
 544         case 0x68012800: /* PM_OCM_RAM */
 545             s->req_info_permission[0] = 0;
 546             for (i = 1; i < 8; i++)
 547                 s->req_info_permission[i] = 0xffff;
 548             for (i = 0; i < 8; i++)
 549                 s->read_permission[i] = s->write_permission[i] = 0x5f3e;
 550             s->addr_match[1] = 0x0f810;
 551             break;
 552         case 0x68012C00: /* PM_OCM_ROM */
 553             s->req_info_permission[1] = 0xffff;
 554             for (i = 0; i < 2; i++) {
 555                 s->read_permission[i] = 0x1002;
 556                 s->write_permission[i] = 0;
 557             }
 558             s->addr_match[0] = 0x14028;
 559             break;
 560         case 0x68013000: /* PM_MAD2D */
 561             s->req_info_permission[0] = 0;
 562             for (i = 1; i < 8; i++)
 563                 s->req_info_permission[i] = 0xffff;
 564             for (i = 0; i < 8; i++)
 565                 s->read_permission[i] = s->write_permission[i] = 0x5f1e;
 566             break;
 567         case 0x68014000: /* PM_IVA2.2 */
 568             s->req_info_permission[0] = 0;
 569             for (i = 1; i < 4; i++)
 570                 s->req_info_permission[i] = 0xffff;
 571             for (i = 0; i < 4; i++)
 572                 s->read_permission[i] = s->write_permission[i] = 0x140e;
 573             break;
 574         default:
 575             fprintf(stderr, "%s: unknown PM region (0x%08llx)\n",
 576                     __FUNCTION__, s->base);
 577             exit(-1);
 578             break;
 579     }
 580 }
 581
 582 static CPUReadMemoryFunc *omap3_l3pm_readfn[] = {
 583     omap3_l3pm_read8,
 584     omap3_l3pm_read16,
 585     omap3_l3pm_read32,
 586 };
 587
 588 static CPUWriteMemoryFunc *omap3_l3pm_writefn[] = {
 589     omap3_l3pm_write8,
 590     omap3_l3pm_write16,
 591     omap3_l3pm_write32,
 592 };
 593
 594 static uint32_t omap3_l3undef_read8(void *opaque, target_phys_addr_t addr)
 595 {
 596     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 597             __FUNCTION__, addr);
 598     return 0;
 599 }
 600
 601 static uint32_t omap3_l3undef_read16(void *opaque, target_phys_addr_t addr)
 602 {
 603     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 604             __FUNCTION__, addr);
 605     return 0;
 606 }
 607
 608 static uint32_t omap3_l3undef_read32(void *opaque, target_phys_addr_t addr)
 609 {
 610     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 611             __FUNCTION__, addr);
 612     return 0;
 613 }
 614
 615 static void omap3_l3undef_write8(void *opaque, target_phys_addr_t addr,
 616                                uint32_t value)
 617 {
 618     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %02x\n",
 619             __FUNCTION__, addr, value);
 620 }
 621
 622 static void omap3_l3undef_write16(void *opaque, target_phys_addr_t addr,
 623                                 uint32_t value)
 624 {
 625     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %04x\n",
 626             __FUNCTION__, addr, value);
 627 }
 628
 629 static void omap3_l3undef_write32(void *opaque, target_phys_addr_t addr,
 630                                 uint32_t value)
 631 {
 632     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %08x\n",
 633             __FUNCTION__, addr, value);
 634 }
 635
 636 static CPUReadMemoryFunc *omap3_l3undef_readfn[] = {
 637     omap3_l3undef_read8,
 638     omap3_l3undef_read16,
 639     omap3_l3undef_read32,
 640 };
 641
 642 static CPUWriteMemoryFunc *omap3_l3undef_writefn[] = {
 643     omap3_l3undef_write8,
 644     omap3_l3undef_write16,
 645     omap3_l3undef_write32,
 646 };
 647
 648 static struct omap_l3_s *omap3_l3_init(target_phys_addr_t base,
 649                                        struct omap_l3_region_s *regions,
 650                                        int n)
 651 {
 652     int i, iomemtype = 0;
 653
 654     struct omap_l3_s *bus = qemu_mallocz(sizeof(*bus) + n * sizeof(*bus->region));
 655     bus->region_count = n;
 656     bus->base = base;
 657
 658     for (i = 0; i < n; i++) {
 659         switch (regions[i].type) {
 660             case L3TYPE_GENERIC:
 661                 /* not mapped for now, mapping will be done later by
 662                    specialized code */
 663                 break;
 664             case L3TYPE_IA:
 665                 iomemtype = cpu_register_io_memory(0, omap3_l3ia_readfn,
 666                                                    omap3_l3ia_writefn,
 667                                                    &bus->region[i].ia);
 668                 bus->region[i].ia.base = base + regions[i].offset;
 669                 omap3_l3ia_init(&bus->region[i].ia);
 670                 break;
 671             case L3TYPE_TA:
 672                 iomemtype = cpu_register_io_memory(0, omap3_l3ta_readfn,
 673                                                    omap3_l3ta_writefn,
 674                                                    &bus->region[i].ta);
 675                 bus->region[i].ta.base = base + regions[i].offset;
 676                 omap3_l3ta_init(&bus->region[i].ta);
 677                 break;
 678             case L3TYPE_PM:
 679                 iomemtype = cpu_register_io_memory(0, omap3_l3pm_readfn,
 680                                                    omap3_l3pm_writefn,
 681                                                    &bus->region[i].pm);
 682                 bus->region[i].pm.base = base + regions[i].offset;
 683                 omap3_l3pm_init(&bus->region[i].pm);
 684                 break;
 685             case L3TYPE_UNDEFINED:
 686                 iomemtype = cpu_register_io_memory(0, omap3_l3undef_readfn,
 687                                                    omap3_l3undef_writefn,
 688                                                    &bus->region[i]);
 689                 break;
 690             default:
 691                 fprintf(stderr, "%s: unknown L3 region type: %d\n",
 692                         __FUNCTION__, regions[i].type);
 693                 exit(-1);
 694                 break;
 695         }
 696         cpu_register_physical_memory(base + regions[i].offset,
 697                                      regions[i].size,
 698                                      iomemtype);
 699     }
 700
 701     return bus;
 702 }
 703
 704 typedef enum {
 705     /* 48000000-48001FFF */
 706     /* 48002000-48002FFF */ L4ID_SCM = 0,
 707     /* 48003000-48003FFF */ L4ID_SCM_TA,
 708     /* 48004000-48005FFF */ L4ID_CM_A,
 709     /* 48006000-480067FF */ L4ID_CM_B,
 710     /* 48006800-48006FFF */
 711     /* 48007000-48007FFF */ L4ID_CM_TA,
 712     /* 48008000-48023FFF */
 713     /* 48024000-48024FFF */
 714     /* 48025000-48025FFF */
 715     /* 48026000-4803FFFF */
 716     /* 48040000-480407FF */ L4ID_CORE_AP,
 717     /* 48040800-48040FFF */ L4ID_CORE_IP,
 718     /* 48041000-48041FFF */ L4ID_CORE_LA,
 719     /* 48042000-4804FBFF */
 720     /* 4804FC00-4804FFFF */ L4ID_DSI,
 721     /* 48050000-480503FF */ L4ID_DSS,
 722     /* 48050400-480507FF */ L4ID_DISPC,
 723     /* 48050800-48050BFF */ L4ID_RFBI,
 724     /* 48050C00-48050FFF */ L4ID_VENC,
 725     /* 48051000-48051FFF */ L4ID_DSS_TA,
 726     /* 48052000-48055FFF */
 727     /* 48056000-48056FFF */ L4ID_SDMA,
 728     /* 48057000-48057FFF */ L4ID_SDMA_TA,
 729     /* 48058000-4805FFFF */
 730     /* 48060000-48060FFF */ L4ID_I2C3,
 731     /* 48061000-48061FFF */ L4ID_I2C3_TA,
 732     /* 48062000-48062FFF */ L4ID_USBTLL,
 733     /* 48063000-48063FFF */ L4ID_USBTLL_TA,
 734     /* 48064000-48064FFF */ L4ID_HSUSBHOST,
 735     /* 48065000-48065FFF */ L4ID_HSUSBHOST_TA,
 736     /* 48066000-48069FFF */
 737     /* 4806A000-4806AFFF */ L4ID_UART1,
 738     /* 4806B000-4806BFFF */ L4ID_UART1_TA,
 739     /* 4806C000-4806CFFF */ L4ID_UART2,
 740     /* 4806D000-4806DFFF */ L4ID_UART2_TA,
 741     /* 4806E000-4806FFFF */
 742     /* 48070000-48070FFF */ L4ID_I2C1,
 743     /* 48071000-48071FFF */ L4ID_I2C1_TA,
 744     /* 48072000-48072FFF */ L4ID_I2C2,
 745     /* 48073000-48073FFF */ L4ID_I2C2_TA,
 746     /* 48074000-48074FFF */ L4ID_MCBSP1,
 747     /* 48075000-48075FFF */ L4ID_MCBSP1_TA,
 748     /* 48076000-48085FFF */
 749     /* 48086000-48086FFF */ L4ID_GPTIMER10,
 750     /* 48087000-48087FFF */ L4ID_GPTIMER10_TA,
 751     /* 48088000-48088FFF */ L4ID_GPTIMER11,
 752     /* 48089000-48089FFF */ L4ID_GPTIMER11_TA,
 753     /* 4808A000-4808AFFF */
 754     /* 4808B000-4808BFFF */
 755     /* 4808C000-48093FFF */
 756     /* 48094000-48094FFF */ L4ID_MAILBOX,
 757     /* 48095000-48095FFF */ L4ID_MAILBOX_TA,
 758     /* 48096000-48096FFF */ L4ID_MCBSP5,
 759     /* 48097000-48097FFF */ L4ID_MCBSP5_TA,
 760     /* 48098000-48098FFF */ L4ID_MCSPI1,
 761     /* 48099000-48099FFF */ L4ID_MCSPI1_TA,
 762     /* 4809A000-4809AFFF */ L4ID_MCSPI2,
 763     /* 4809B000-4809BFFF */ L4ID_MCSPI2_TA,
 764     /* 4809C000-4809CFFF */ L4ID_MMCSDIO1,
 765     /* 4809D000-4809DFFF */ L4ID_MMCSDIO1_TA,
 766     /* 4809E000-4809EFFF */ L4ID_MSPRO,
 767     /* 4809F000-4809FFFF */ L4ID_MSPRO_TA,
 768     /* 480A0000-480AAFFF */
 769     /* 480AB000-480ABFFF */ L4ID_HSUSBOTG,
 770     /* 480AC000-480ACFFF */ L4ID_HSUSBOTG_TA,
 771     /* 480AD000-480ADFFF */ L4ID_MMCSDIO3,
 772     /* 480AE000-480AEFFF */ L4ID_MMCSDIO3_TA,
 773     /* 480AF000-480AFFFF */
 774     /* 480B0000-480B0FFF */
 775     /* 480B1000-480B1FFF */
 776     /* 480B2000-480B2FFF */ L4ID_HDQ1WIRE,
 777     /* 480B3000-480B2FFF */ L4ID_HDQ1WIRE_TA,
 778     /* 480B4000-480B4FFF */ L4ID_MMCSDIO2,
 779     /* 480B5000-480B5FFF */ L4ID_MMCSDIO2_TA,
 780     /* 480B6000-480B6FFF */ L4ID_ICRMPU,
 781     /* 480B7000-480B7FFF */ L4ID_ICRMPU_TA,
 782     /* 480B8000-480B8FFF */ L4ID_MCSPI3,
 783     /* 480B9000-480B9FFF */ L4ID_MCSPI3_TA,
 784     /* 480BA000-480BAFFF */ L4ID_MCSPI4,
 785     /* 480BB000-480BBFFF */ L4ID_MCSPI4_TA,
 786     /* 480BC000-480BFFFF */ L4ID_CAMERAISP,
 787     /* 480C0000-480C0FFF */ L4ID_CAMERAISP_TA,
 788     /* 480C1000-480CCFFF */
 789     /* 480CD000-480CDFFF */ L4ID_ICRMODEM,
 790     /* 480CE000-480CEFFF */ L4ID_ICRMODEM_TA,
 791     /* 480CF000-482FFFFF */
 792     /* 48300000-48303FFF */
 793     /* 48304000-48304FFF */ L4ID_GPTIMER12,
 794     /* 48305000-48305FFF */ L4ID_GPTIMER12_TA,
 795     /* 48306000-48307FFF */ L4ID_PRM_A,
 796     /* 48308000-483087FF */ L4ID_PRM_B,
 797     /* 48308800-48308FFF */
 798     /* 48309000-48309FFF */ L4ID_PRM_TA,
 799     /* 4830A000-4830AFFF */ L4ID_TAP,
 800     /* 4830B000-4830BFFF */ L4ID_TAP_TA,
 801     /* 4830C000-4830FFFF */
 802     /* 48310000-48310FFF */ L4ID_GPIO1,
 803     /* 48311000-48311FFF */ L4ID_GPIO1_TA,
 804     /* 48312000-48313FFF */
 805     /* 48314000-48314FFF */ L4ID_WDTIMER2,
 806     /* 48315000-48315FFF */ L4ID_WDTIMER2_TA,
 807     /* 48316000-48317FFF */
 808     /* 48318000-48318FFF */ L4ID_GPTIMER1,
 809     /* 48319000-48319FFF */ L4ID_GPTIMER1_TA,
 810     /* 4831A000-4831FFFF */
 811     /* 48320000-48320FFF */ L4ID_32KTIMER,
 812     /* 48321000-48321FFF */ L4ID_32KTIMER_TA,
 813     /* 48322000-48327FFF */
 814     /* 48328000-483287FF */ L4ID_WAKEUP_AP,
 815     /* 48328800-48328FFF */ L4ID_WAKEUP_C_IP,
 816     /* 48329000-48329FFF */ L4ID_WAKEUP_LA,
 817     /* 4832A000-4832A7FF */ L4ID_WAKEUP_E_IP,
 818     /* 4832A800-4833FFFF */
 819     /* 48340000-48340FFF */
 820     /* 48341000-48FFFFFF */
 821     /* 49000000-490007FF */ L4ID_PER_AP,
 822     /* 49000800-49000FFF */ L4ID_PER_IP,
 823     /* 49001000-49001FFF */ L4ID_PER_LA,
 824     /* 49002000-4901FFFF */
 825     /* 49020000-49020FFF */ L4ID_UART3,
 826     /* 49021000-49021FFF */ L4ID_UART3_TA,
 827     /* 49022000-49022FFF */ L4ID_MCBSP2,
 828     /* 49023000-49023FFF */ L4ID_MCBSP2_TA,
 829     /* 49024000-49024FFF */ L4ID_MCBSP3,
 830     /* 49025000-49025FFF */ L4ID_MCBSP3_TA,
 831     /* 49026000-49026FFF */ L4ID_MCBSP4,
 832     /* 49027000-49027FFF */ L4ID_MCBSP4_TA,
 833     /* 49028000-49028FFF */ L4ID_MCBSP2S,
 834     /* 49029000-49029FFF */ L4ID_MCBSP2S_TA,
 835     /* 4902A000-4902AFFF */ L4ID_MCBSP3S,
 836     /* 4902B000-4902BFFF */ L4ID_MCBSP3S_TA,
 837     /* 4902C000-4902FFFF */
 838     /* 49030000-49030FFF */ L4ID_WDTIMER3,
 839     /* 49031000-49031FFF */ L4ID_WDTIMER3_TA,
 840     /* 49032000-49032FFF */ L4ID_GPTIMER2,
 841     /* 49033000-49033FFF */ L4ID_GPTIMER2_TA,
 842     /* 49034000-49034FFF */ L4ID_GPTIMER3,
 843     /* 49035000-49035FFF */ L4ID_GPTIMER3_TA,
 844     /* 49036000-49036FFF */ L4ID_GPTIMER4,
 845     /* 49037000-49037FFF */ L4ID_GPTIMER4_TA,
 846     /* 49038000-49038FFF */ L4ID_GPTIMER5,
 847     /* 49039000-49039FFF */ L4ID_GPTIMER5_TA,
 848     /* 4903A000-4903AFFF */ L4ID_GPTIMER6,
 849     /* 4903B000-4903BFFF */ L4ID_GPTIMER6_TA,
 850     /* 4903C000-4903CFFF */ L4ID_GPTIMER7,
 851     /* 4903D000-4903DFFF */ L4ID_GPTIMER7_TA,
 852     /* 4903E000-4903EFFF */ L4ID_GPTIMER8,
 853     /* 4903F000-4903FFFF */ L4ID_GPTIMER8_TA,
 854     /* 49040000-49040FFF */ L4ID_GPTIMER9,
 855     /* 49041000-49041FFF */ L4ID_GPTIMER9_TA,
 856     /* 49042000-4904FFFF */
 857     /* 49050000-49050FFF */ L4ID_GPIO2,
 858     /* 49051000-49051FFF */ L4ID_GPIO2_TA,
 859     /* 49052000-49052FFF */ L4ID_GPIO3,
 860     /* 49053000-49053FFF */ L4ID_GPIO3_TA,
 861     /* 49054000-49054FFF */ L4ID_GPIO4,
 862     /* 49055000-49055FFF */ L4ID_GPIO4_TA,
 863     /* 49056000-49056FFF */ L4ID_GPIO5,
 864     /* 49057000-49057FFF */ L4ID_GPIO5_TA,
 865     /* 49058000-49058FFF */ L4ID_GPIO6,
 866     /* 49059000-49059FFF */ L4ID_GPIO6_TA,
 867     /* 4905A000-490FFFFF */
 868     /* 54000000-54003FFF */
 869     /* 54004000-54005FFF */
 870     /* 54006000-540067FF */ L4ID_EMU_AP,
 871     /* 54006800-54006FFF */ L4ID_EMU_IP_C,
 872     /* 54007000-54007FFF */ L4ID_EMU_LA,
 873     /* 54008000-540087FF */ L4ID_EMU_IP_DAP,
 874     /* 54008800-5400FFFF */
 875     /* 54010000-54017FFF */ L4ID_MPUEMU,
 876     /* 54018000-54018FFF */ L4ID_MPUEMU_TA,
 877     /* 54019000-54019FFF */ L4ID_TPIU,
 878     /* 5401A000-5401AFFF */ L4ID_TPIU_TA,
 879     /* 5401B000-5401BFFF */ L4ID_ETB,
 880     /* 5401C000-5401CFFF */ L4ID_ETB_TA,
 881     /* 5401D000-5401DFFF */ L4ID_DAPCTL,
 882     /* 5401E000-5401EFFF */ L4ID_DAPCTL_TA,
 883     /* 5401F000-5401FFFF */ L4ID_SDTI_TA,
 884     /* 54020000-544FFFFF */
 885     /* 54500000-5450FFFF */ L4ID_SDTI_CFG,
 886     /* 54510000-545FFFFF */
 887     /* 54600000-546FFFFF */ L4ID_SDTI,
 888     /* 54700000-54705FFF */
 889     /* 54706000-54707FFF */ L4ID_EMU_PRM_A,
 890     /* 54708000-547087FF */ L4ID_EMU_PRM_B,
 891     /* 54708800-54708FFF */
 892     /* 54709000-54709FFF */ L4ID_EMU_PRM_TA,
 893     /* 5470A000-5470FFFF */
 894     /* 54710000-54710FFF */ L4ID_EMU_GPIO1,
 895     /* 54711000-54711FFF */ L4ID_EMU_GPIO1_TA,
 896     /* 54712000-54713FFF */
 897     /* 54714000-54714FFF */ L4ID_EMU_WDTM2,
 898     /* 54715000-54715FFF */ L4ID_EMU_WDTM2_TA,
 899     /* 54716000-54717FFF */
 900     /* 54718000-54718FFF */ L4ID_EMU_GPTM1,
 901     /* 54719000-54719FFF */ L4ID_EMU_GPTM1_TA,
 902     /* 5471A000-5471FFFF */
 903     /* 54720000-54720FFF */ L4ID_EMU_32KTM,
 904     /* 54721000-54721FFF */ L4ID_EMU_32KTM_TA,
 905     /* 54722000-54727FFF */
 906     /* 54728000-547287FF */ L4ID_EMU_WKUP_AP,
 907     /* 54728800-54728FFF */ L4ID_EMU_WKUP_IPC,
 908     /* 54729000-54729FFF */ L4ID_EMU_WKUP_LA,
 909     /* 5472A000-5472A7FF */ L4ID_EMU_WKUP_IPE,
 910     /* 5472A800-547FFFFF */
 911 } omap3_l4_region_id_t;
 912
 913 typedef enum {
 914     L4TYPE_GENERIC = 0, /* not mapped by default, must be mapped separately */
 915     L4TYPE_IA,          /* initiator agent */
 916     L4TYPE_TA,          /* target agent */
 917     L4TYPE_LA,          /* link register agent */
 918     L4TYPE_AP           /* address protection */
 919 } omap3_l4_region_type_t;
 920
 921 /* we reuse the "access" member for defining region type -- the original
 922    omap_l4_region_s "access" member is not used anywhere else anyway! */
 923 static struct omap_l4_region_s omap3_l4_region[] = {
 924     /* L4-Core */
 925     [L4ID_SCM         ] = {0x00002000, 0x1000, L4TYPE_GENERIC},
 926     [L4ID_SCM_TA      ] = {0x00003000, 0x1000, L4TYPE_TA},
 927     [L4ID_CM_A        ] = {0x00004000, 0x2000, L4TYPE_GENERIC},
 928     [L4ID_CM_B        ] = {0x00006000, 0x0800, L4TYPE_GENERIC},
 929     [L4ID_CM_TA       ] = {0x00007000, 0x1000, L4TYPE_TA},
 930     [L4ID_CORE_AP     ] = {0x00040000, 0x0800, L4TYPE_AP},
 931     [L4ID_CORE_IP     ] = {0x00040800, 0x0800, L4TYPE_IA},
 932     [L4ID_CORE_LA     ] = {0x00041000, 0x1000, L4TYPE_LA},
 933     [L4ID_DSI         ] = {0x0004fc00, 0x0400, L4TYPE_GENERIC},
 934     [L4ID_DSS         ] = {0x00050000, 0x0400, L4TYPE_GENERIC},
 935     [L4ID_DISPC       ] = {0x00050400, 0x0400, L4TYPE_GENERIC},
 936     [L4ID_RFBI        ] = {0x00050800, 0x0400, L4TYPE_GENERIC},
 937     [L4ID_VENC        ] = {0x00050c00, 0x0400, L4TYPE_GENERIC},
 938     [L4ID_DSS_TA      ] = {0x00051000, 0x1000, L4TYPE_TA},
 939     [L4ID_SDMA        ] = {0x00056000, 0x1000, L4TYPE_GENERIC},
 940     [L4ID_SDMA_TA     ] = {0x00057000, 0x1000, L4TYPE_TA},
 941     [L4ID_I2C3        ] = {0x00060000, 0x1000, L4TYPE_GENERIC},
 942     [L4ID_I2C3_TA     ] = {0x00061000, 0x1000, L4TYPE_TA},
 943     [L4ID_USBTLL      ] = {0x00062000, 0x1000, L4TYPE_GENERIC},
 944     [L4ID_USBTLL_TA   ] = {0x00063000, 0x1000, L4TYPE_TA},
 945     [L4ID_HSUSBHOST   ] = {0x00064000, 0x1000, L4TYPE_GENERIC},
 946     [L4ID_HSUSBHOST_TA] = {0x00065000, 0x1000, L4TYPE_TA},
 947     [L4ID_UART1       ] = {0x0006a000, 0x1000, L4TYPE_GENERIC},
 948     [L4ID_UART1_TA    ] = {0x0006b000, 0x1000, L4TYPE_TA},
 949     [L4ID_UART2       ] = {0x0006c000, 0x1000, L4TYPE_GENERIC},
 950     [L4ID_UART2_TA    ] = {0x0006d000, 0x1000, L4TYPE_TA},
 951     [L4ID_I2C1        ] = {0x00070000, 0x1000, L4TYPE_GENERIC},
 952     [L4ID_I2C1_TA     ] = {0x00071000, 0x1000, L4TYPE_TA},
 953     [L4ID_I2C2        ] = {0x00072000, 0x1000, L4TYPE_GENERIC},
 954     [L4ID_I2C2_TA     ] = {0x00073000, 0x1000, L4TYPE_TA},
 955     [L4ID_MCBSP1      ] = {0x00074000, 0x1000, L4TYPE_GENERIC},
 956     [L4ID_MCBSP1_TA   ] = {0x00075000, 0x1000, L4TYPE_TA},
 957     [L4ID_GPTIMER10   ] = {0x00086000, 0x1000, L4TYPE_GENERIC},
 958     [L4ID_GPTIMER10_TA] = {0x00087000, 0x1000, L4TYPE_TA},
 959     [L4ID_GPTIMER11   ] = {0x00088000, 0x1000, L4TYPE_GENERIC},
 960     [L4ID_GPTIMER11_TA] = {0x00089000, 0x1000, L4TYPE_TA},
 961     [L4ID_MAILBOX     ] = {0x00094000, 0x1000, L4TYPE_GENERIC},
 962     [L4ID_MAILBOX_TA  ] = {0x00095000, 0x1000, L4TYPE_TA},
 963     [L4ID_MCBSP5      ] = {0x00096000, 0x1000, L4TYPE_GENERIC},
 964     [L4ID_MCBSP5_TA   ] = {0x00097000, 0x1000, L4TYPE_TA},
 965     [L4ID_MCSPI1      ] = {0x00098000, 0x1000, L4TYPE_GENERIC},
 966     [L4ID_MCSPI1_TA   ] = {0x00099000, 0x1000, L4TYPE_TA},
 967     [L4ID_MCSPI2      ] = {0x0009a000, 0x1000, L4TYPE_GENERIC},
 968     [L4ID_MCSPI2_TA   ] = {0x0009b000, 0x1000, L4TYPE_TA},
 969     [L4ID_MMCSDIO1    ] = {0x0009c000, 0x1000, L4TYPE_GENERIC},
 970     [L4ID_MMCSDIO1_TA ] = {0x0009d000, 0x1000, L4TYPE_TA},
 971     [L4ID_MSPRO       ] = {0x0009e000, 0x1000, L4TYPE_GENERIC},
 972     [L4ID_MSPRO_TA    ] = {0x0009f000, 0x1000, L4TYPE_TA},
 973     [L4ID_HSUSBOTG    ] = {0x000ab000, 0x1000, L4TYPE_GENERIC},
 974     [L4ID_HSUSBOTG_TA ] = {0x000ac000, 0x1000, L4TYPE_TA},
 975     [L4ID_MMCSDIO3    ] = {0x000ad000, 0x1000, L4TYPE_GENERIC},
 976     [L4ID_MMCSDIO3_TA ] = {0x000ae000, 0x1000, L4TYPE_TA},
 977     [L4ID_HDQ1WIRE    ] = {0x000b2000, 0x1000, L4TYPE_GENERIC},
 978     [L4ID_HDQ1WIRE_TA ] = {0x000b3000, 0x1000, L4TYPE_TA},
 979     [L4ID_MMCSDIO2    ] = {0x000b4000, 0x1000, L4TYPE_GENERIC},
 980     [L4ID_MMCSDIO2_TA ] = {0x000b5000, 0x1000, L4TYPE_TA},
 981     [L4ID_ICRMPU      ] = {0x000b6000, 0x1000, L4TYPE_GENERIC},
 982     [L4ID_ICRMPU_TA   ] = {0x000b7000, 0x1000, L4TYPE_TA},
 983     [L4ID_MCSPI3      ] = {0x000b8000, 0x1000, L4TYPE_GENERIC},
 984     [L4ID_MCSPI3_TA   ] = {0x000b9000, 0x1000, L4TYPE_TA},
 985     [L4ID_MCSPI4      ] = {0x000ba000, 0x1000, L4TYPE_GENERIC},
 986     [L4ID_MCSPI4_TA   ] = {0x000bb000, 0x1000, L4TYPE_TA},
 987     [L4ID_CAMERAISP   ] = {0x000bc000, 0x4000, L4TYPE_GENERIC},
 988     [L4ID_CAMERAISP_TA] = {0x000c0000, 0x1000, L4TYPE_TA},
 989     [L4ID_ICRMODEM    ] = {0x000cd000, 0x1000, L4TYPE_GENERIC},
 990     [L4ID_ICRMODEM_TA ] = {0x000ce000, 0x1000, L4TYPE_TA},
 991     /* L4-Wakeup interconnect region A */
 992     [L4ID_GPTIMER12   ] = {0x00304000, 0x1000, L4TYPE_GENERIC},
 993     [L4ID_GPTIMER12_TA] = {0x00305000, 0x1000, L4TYPE_TA},
 994     [L4ID_PRM_A       ] = {0x00306000, 0x2000, L4TYPE_GENERIC},
 995     [L4ID_PRM_B       ] = {0x00308000, 0x0800, L4TYPE_GENERIC},
 996     [L4ID_PRM_TA      ] = {0x00309000, 0x1000, L4TYPE_TA},
 997     /* L4-Core */
 998     [L4ID_TAP         ] = {0x0030a000, 0x1000, L4TYPE_GENERIC},
 999     [L4ID_TAP_TA      ] = {0x0030b000, 0x1000, L4TYPE_TA},
1000     /* L4-Wakeup interconnect region B */
1001     [L4ID_GPIO1       ] = {0x00310000, 0x1000, L4TYPE_GENERIC},
1002     [L4ID_GPIO1_TA    ] = {0x00311000, 0x1000, L4TYPE_TA},
1003     [L4ID_WDTIMER2    ] = {0x00314000, 0x1000, L4TYPE_GENERIC},
1004     [L4ID_WDTIMER2_TA ] = {0x00315000, 0x1000, L4TYPE_TA},
1005     [L4ID_GPTIMER1    ] = {0x00318000, 0x1000, L4TYPE_GENERIC},
1006     [L4ID_GPTIMER1_TA ] = {0x00319000, 0x1000, L4TYPE_TA},
1007     [L4ID_32KTIMER    ] = {0x00320000, 0x1000, L4TYPE_GENERIC},
1008     [L4ID_32KTIMER_TA ] = {0x00321000, 0x1000, L4TYPE_TA},
1009     [L4ID_WAKEUP_AP   ] = {0x00328000, 0x0800, L4TYPE_AP},
1010     [L4ID_WAKEUP_C_IP ] = {0x00328800, 0x0800, L4TYPE_IA},
1011     [L4ID_WAKEUP_LA   ] = {0x00329000, 0x1000, L4TYPE_LA},
1012     [L4ID_WAKEUP_E_IP ] = {0x0032a000, 0x0800, L4TYPE_IA},
1013     /* L4-Per */
1014     [L4ID_PER_AP      ] = {0x01000000, 0x0800, L4TYPE_AP},
1015     [L4ID_PER_IP      ] = {0x01000800, 0x0800, L4TYPE_IA},
1016     [L4ID_PER_LA      ] = {0x01001000, 0x1000, L4TYPE_LA},
1017     [L4ID_UART3       ] = {0x01020000, 0x1000, L4TYPE_GENERIC},
1018     [L4ID_UART3_TA    ] = {0x01021000, 0x1000, L4TYPE_TA},
1019     [L4ID_MCBSP2      ] = {0x01022000, 0x1000, L4TYPE_GENERIC},
1020     [L4ID_MCBSP2_TA   ] = {0x01023000, 0x1000, L4TYPE_TA},
1021     [L4ID_MCBSP3      ] = {0x01024000, 0x1000, L4TYPE_GENERIC},
1022     [L4ID_MCBSP3_TA   ] = {0x01025000, 0x1000, L4TYPE_TA},
1023     [L4ID_MCBSP4      ] = {0x01026000, 0x1000, L4TYPE_GENERIC},
1024     [L4ID_MCBSP4_TA   ] = {0x01027000, 0x1000, L4TYPE_TA},
1025     [L4ID_MCBSP2S     ] = {0x01028000, 0x1000, L4TYPE_GENERIC},
1026     [L4ID_MCBSP2S_TA  ] = {0x01029000, 0x1000, L4TYPE_TA},
1027     [L4ID_MCBSP3S     ] = {0x0102a000, 0x1000, L4TYPE_GENERIC},
1028     [L4ID_MCBSP3S_TA  ] = {0x0102b000, 0x1000, L4TYPE_TA},
1029     [L4ID_WDTIMER3    ] = {0x01030000, 0x1000, L4TYPE_GENERIC},
1030     [L4ID_WDTIMER3_TA ] = {0x01031000, 0x1000, L4TYPE_TA},
1031     [L4ID_GPTIMER2    ] = {0x01032000, 0x1000, L4TYPE_GENERIC},
1032     [L4ID_GPTIMER2_TA ] = {0x01033000, 0x1000, L4TYPE_TA},
1033     [L4ID_GPTIMER3    ] = {0x01034000, 0x1000, L4TYPE_GENERIC},
1034     [L4ID_GPTIMER3_TA ] = {0x01035000, 0x1000, L4TYPE_TA},
1035     [L4ID_GPTIMER4    ] = {0x01036000, 0x1000, L4TYPE_GENERIC},
1036     [L4ID_GPTIMER4_TA ] = {0x01037000, 0x1000, L4TYPE_TA},
1037     [L4ID_GPTIMER5    ] = {0x01038000, 0x1000, L4TYPE_GENERIC},
1038     [L4ID_GPTIMER5_TA ] = {0x01039000, 0x1000, L4TYPE_TA},
1039     [L4ID_GPTIMER6    ] = {0x0103a000, 0x1000, L4TYPE_GENERIC},
1040     [L4ID_GPTIMER6_TA ] = {0x0103b000, 0x1000, L4TYPE_TA},
1041     [L4ID_GPTIMER7    ] = {0x0103c000, 0x1000, L4TYPE_GENERIC},
1042     [L4ID_GPTIMER7_TA ] = {0x0103d000, 0x1000, L4TYPE_TA},
1043     [L4ID_GPTIMER8    ] = {0x0103e000, 0x1000, L4TYPE_GENERIC},
1044     [L4ID_GPTIMER8_TA ] = {0x0103f000, 0x1000, L4TYPE_TA},
1045     [L4ID_GPTIMER9    ] = {0x01040000, 0x1000, L4TYPE_GENERIC},
1046     [L4ID_GPTIMER9_TA ] = {0x01041000, 0x1000, L4TYPE_TA},
1047     [L4ID_GPIO2       ] = {0x01050000, 0x1000, L4TYPE_GENERIC},
1048     [L4ID_GPIO2_TA    ] = {0x01051000, 0x1000, L4TYPE_TA},
1049     [L4ID_GPIO3       ] = {0x01052000, 0x1000, L4TYPE_GENERIC},
1050     [L4ID_GPIO3_TA    ] = {0x01053000, 0x1000, L4TYPE_TA},
1051     [L4ID_GPIO4       ] = {0x01054000, 0x1000, L4TYPE_GENERIC},
1052     [L4ID_GPIO4_TA    ] = {0x01055000, 0x1000, L4TYPE_TA},
1053     [L4ID_GPIO5       ] = {0x01056000, 0x1000, L4TYPE_GENERIC},
1054     [L4ID_GPIO5_TA    ] = {0x01057000, 0x1000, L4TYPE_TA},
1055     [L4ID_GPIO6       ] = {0x01058000, 0x1000, L4TYPE_GENERIC},
1056     [L4ID_GPIO6_TA    ] = {0x01059000, 0x1000, L4TYPE_TA},
1057     /* L4-Emu */
1058     [L4ID_EMU_AP      ] = {0x0c006000, 0x0800, L4TYPE_AP},
1059     [L4ID_EMU_IP_C    ] = {0x0c006800, 0x0800, L4TYPE_IA},
1060     [L4ID_EMU_LA      ] = {0x0c007000, 0x1000, L4TYPE_LA},
1061     [L4ID_EMU_IP_DAP  ] = {0x0c008000, 0x0800, L4TYPE_IA},
1062     [L4ID_MPUEMU      ] = {0x0c010000, 0x8000, L4TYPE_GENERIC},
1063     [L4ID_MPUEMU_TA   ] = {0x0c018000, 0x1000, L4TYPE_TA},
1064     [L4ID_TPIU        ] = {0x0c019000, 0x1000, L4TYPE_GENERIC},
1065     [L4ID_TPIU_TA     ] = {0x0c01a000, 0x1000, L4TYPE_TA},
1066     [L4ID_ETB         ] = {0x0c01b000, 0x1000, L4TYPE_GENERIC},
1067     [L4ID_ETB_TA      ] = {0x0c01c000, 0x1000, L4TYPE_TA},
1068     [L4ID_DAPCTL      ] = {0x0c01d000, 0x1000, L4TYPE_GENERIC},
1069     [L4ID_DAPCTL_TA   ] = {0x0c01e000, 0x1000, L4TYPE_TA},
1070     [L4ID_EMU_PRM_A   ] = {0x0c706000, 0x2000, L4TYPE_GENERIC},
1071     [L4ID_EMU_PRM_B   ] = {0x0c706800, 0x0800, L4TYPE_GENERIC},
1072     [L4ID_EMU_PRM_TA  ] = {0x0c709000, 0x1000, L4TYPE_TA},
1073     [L4ID_EMU_GPIO1   ] = {0x0c710000, 0x1000, L4TYPE_GENERIC},
1074     [L4ID_EMU_GPIO1_TA] = {0x0c711000, 0x1000, L4TYPE_TA},
1075     [L4ID_EMU_WDTM2   ] = {0x0c714000, 0x1000, L4TYPE_GENERIC},
1076     [L4ID_EMU_WDTM2_TA] = {0x0c715000, 0x1000, L4TYPE_TA},
1077     [L4ID_EMU_GPTM1   ] = {0x0c718000, 0x1000, L4TYPE_GENERIC},
1078     [L4ID_EMU_GPTM1_TA] = {0x0c719000, 0x1000, L4TYPE_TA},
1079     [L4ID_EMU_32KTM   ] = {0x0c720000, 0x1000, L4TYPE_GENERIC},
1080     [L4ID_EMU_32KTM_TA] = {0x0c721000, 0x1000, L4TYPE_TA},
1081     [L4ID_EMU_WKUP_AP ] = {0x0c728000, 0x0800, L4TYPE_AP},
1082     [L4ID_EMU_WKUP_IPC] = {0x0c728800, 0x0800, L4TYPE_IA},
1083     [L4ID_EMU_WKUP_LA ] = {0x0c729000, 0x1000, L4TYPE_LA},
1084     [L4ID_EMU_WKUP_IPE] = {0x0c72a000, 0x0800, L4TYPE_IA},
1085 };
1086
1087 typedef enum {
1088     L4A_SCM = 0,
1089     L4A_CM,
1090     L4A_PRM,
1091     L4A_GPTIMER1,
1092     L4A_GPTIMER2,
1093     L4A_GPTIMER3,
1094     L4A_GPTIMER4,
1095     L4A_GPTIMER5,
1096     L4A_GPTIMER6,
1097     L4A_GPTIMER7,
1098     L4A_GPTIMER8,
1099     L4A_GPTIMER9,
1100     L4A_GPTIMER10,
1101     L4A_GPTIMER11,
1102     L4A_GPTIMER12,
1103     L4A_WDTIMER2,
1104     L4A_32KTIMER,
1105     L4A_UART1,
1106     L4A_UART2,
1107     L4A_UART3,
1108     L4A_DSS,
1109     L4A_GPIO1,
1110     L4A_GPIO2,
1111     L4A_GPIO3,
1112     L4A_GPIO4,
1113     L4A_GPIO5,
1114     L4A_GPIO6,
1115     L4A_MMC1,
1116     L4A_MMC2,
1117     L4A_MMC3,
1118     L4A_I2C1,
1119     L4A_I2C2,
1120     L4A_I2C3,
1121     L4A_TAP,
1122     L4A_USBHS_OTG,
1123     L4A_USBHS_HOST,
1124     L4A_USBHS_TLL
1125 } omap3_l4_agent_info_id_t;
1126
1127 struct omap3_l4_agent_info_s {
1128     omap3_l4_agent_info_id_t agent_id;
1129     omap3_l4_region_id_t     first_region_id;
1130     int                      region_count;
1131 };
1132
1133 static const struct omap3_l4_agent_info_s omap3_l4_agent_info[] = {
1134     /* L4-Core Agents */
1135     {L4A_DSS,        L4ID_DSI,       6},
1136     /* TODO: camera */
1137     {L4A_USBHS_OTG,  L4ID_HSUSBOTG,  2},
1138     {L4A_USBHS_HOST, L4ID_HSUSBHOST, 2},
1139     {L4A_USBHS_TLL,  L4ID_USBTLL,    2},
1140     {L4A_UART1,      L4ID_UART1,     2},
1141     {L4A_UART2,      L4ID_UART2,     2},
1142     {L4A_I2C1,       L4ID_I2C1,      2},
1143     {L4A_I2C2,       L4ID_I2C2,      2},
1144     {L4A_I2C3,       L4ID_I2C3,      2},
1145     /* TODO: McBSP1 */
1146     /* TODO: McBSP5 */
1147     {L4A_GPTIMER10,  L4ID_GPTIMER10, 2},
1148     {L4A_GPTIMER11,  L4ID_GPTIMER11, 2},
1149     /* TODO: SPI1 */
1150     /* TODO: SPI2 */
1151     {L4A_MMC1,       L4ID_MMCSDIO1,  2},
1152     {L4A_MMC2,       L4ID_MMCSDIO2,  2},
1153     {L4A_MMC3,       L4ID_MMCSDIO3,  2},
1154     /* TODO: HDQ/1-Wire */
1155     /* TODO: Mailbox */
1156     /* TODO: SPI3 */
1157     /* TODO: SPI4 */
1158     /* TODO: SDMA */
1159     {L4A_CM,         L4ID_CM_A,      3},
1160     {L4A_SCM,        L4ID_SCM,       2},
1161     {L4A_TAP,        L4ID_TAP,       2},
1162     /* L4-Wakeup Agents */
1163     {L4A_GPTIMER12,  L4ID_GPTIMER12, 2},
1164     {L4A_PRM,        L4ID_PRM_A,     3},
1165     {L4A_GPIO1,      L4ID_GPIO1,     2},
1166     {L4A_WDTIMER2,   L4ID_WDTIMER2,  2},
1167     {L4A_GPTIMER1,   L4ID_GPTIMER1,  2},
1168     {L4A_32KTIMER,   L4ID_32KTIMER,  2},
1169     /* L4-Per Agents */
1170     {L4A_UART3,      L4ID_UART3,     2},
1171     /* TODO: McBSP2 */
1172     /* TODO: McBSP3 */
1173     {L4A_GPTIMER2,   L4ID_GPTIMER2,  2},
1174     {L4A_GPTIMER3,   L4ID_GPTIMER3,  2},
1175     {L4A_GPTIMER4,   L4ID_GPTIMER4,  2},
1176     {L4A_GPTIMER5,   L4ID_GPTIMER5,  2},
1177     {L4A_GPTIMER6,   L4ID_GPTIMER6,  2},
1178     {L4A_GPTIMER7,   L4ID_GPTIMER7,  2},
1179     {L4A_GPTIMER8,   L4ID_GPTIMER8,  2},
1180     {L4A_GPTIMER9,   L4ID_GPTIMER9,  2},
1181     {L4A_GPIO2,      L4ID_GPIO2,     2},
1182     {L4A_GPIO3,      L4ID_GPIO3,     2},
1183     {L4A_GPIO4,      L4ID_GPIO4,     2},
1184     {L4A_GPIO5,      L4ID_GPIO5,     2},
1185     {L4A_GPIO6,      L4ID_GPIO6,     2},
1186 };
1187
1188 static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)
1189 {
1190     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1191
1192     switch (addr) {
1193         case 0x00: /* COMPONENT_L */
1194             return s->component;
1195         case 0x04: /* COMPONENT_H */
1196             return 0;
1197         case 0x18: /* CORE_L */
1198             return s->component;
1199         case 0x1c: /* CORE_H */
1200             return (s->component >> 16);
1201         case 0x20: /* AGENT_CONTROL_L */
1202             return s->control;
1203         case 0x24: /* AGENT_CONTROL_H */
1204             return s->control_h;
1205         case 0x28: /* AGENT_STATUS_L */
1206             return s->status;
1207         case 0x2c: /* AGENT_STATUS_H */
1208             return 0;
1209         default:
1210             break;
1211     }
1212
1213     OMAP_BAD_REG(s->base + addr);
1214     return 0;
1215 }
1216
1217 static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr,
1218                              uint32_t value)
1219 {
1220     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1221
1222     switch (addr) {
1223         case 0x00: /* COMPONENT_L */
1224         case 0x04: /* COMPONENT_H */
1225         case 0x18: /* CORE_L */
1226         case 0x1c: /* CORE_H */
1227             OMAP_RO_REG(s->base + addr);
1228             break;
1229         case 0x20: /* AGENT_CONTROL_L */
1230             s->control = value & 0x00000701;
1231             break;
1232         case 0x24: /* AGENT_CONTROL_H */
1233             s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */
1234             break;
1235         case 0x28: /* AGENT_STATUS_L */
1236             if (value & 0x100)
1237                 s->status &= ~0x100; /* REQ_TIMEOUT */
1238             break;
1239         case 0x2c: /* AGENT_STATUS_H */
1240             /* no writable bits although the register is listed as RW */
1241             break;
1242         default:
1243             OMAP_BAD_REG(s->base + addr);
1244             break;
1245     }
1246 }
1247
1248 static CPUReadMemoryFunc *omap3_l4ta_readfn[] = {
1249     omap_badwidth_read32,
1250     omap_badwidth_read32,
1251     omap3_l4ta_read,
1252 };
1253
1254 static CPUWriteMemoryFunc *omap3_l4ta_writefn[] = {
1255     omap_badwidth_write32,
1256     omap_badwidth_write32,
1257     omap3_l4ta_write,
1258 };
1259
1260 static struct omap_target_agent_s *omap3_l4ta_init(struct omap_l4_s *bus, int cs)
1261 {
1262     int i, iomemtype;
1263     struct omap_target_agent_s *ta = 0;
1264     const struct omap3_l4_agent_info_s *info = 0;
1265
1266     for (i = 0; i < bus->ta_num; i++)
1267         if (omap3_l4_agent_info[i].agent_id == cs) {
1268             ta = &bus->ta[i];
1269             info = &omap3_l4_agent_info[i];
1270             break;
1271         }
1272     if (!ta) {
1273         fprintf(stderr, "%s: invalid agent id (%i)\n", __FUNCTION__, cs);
1274         exit(-1);
1275     }
1276     if (ta->bus) {
1277         fprintf(stderr, "%s: target agent (%d) already initialized\n",
1278                 __FUNCTION__, cs);
1279         exit(-1);
1280     }
1281
1282     ta->bus = bus;
1283     ta->start = &omap3_l4_region[info->first_region_id];
1284     ta->regions = info->region_count;
1285
1286     ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1287     ta->status = 0x00000000;
1288     ta->control = 0x00000200;
1289
1290     for (i = 0; i < info->region_count; i++)
1291         if (omap3_l4_region[info->first_region_id + i].access == L4TYPE_TA)
1292             break;
1293     if (i >= info->region_count) {
1294         fprintf(stderr, "%s: specified agent (%d) has no TA region\n",
1295                 __FUNCTION__, cs);
1296         exit(-1);
1297     }
1298
1299     iomemtype = l4_register_io_memory(0, omap3_l4ta_readfn,
1300                                       omap3_l4ta_writefn, ta);
1301     ta->base = omap_l4_attach(ta, i, iomemtype);
1302
1303     return ta;
1304 }
1305
1306 /* common PRM domain registers */
1307 struct omap3_prm_domain_s {
1308     uint32_t rm_rstctrl;     /* 50 */
1309     uint32_t rm_rstst;       /* 58 */
1310     uint32_t pm_wken;        /* a0 */
1311     uint32_t pm_mpugrpsel;   /* a4 */
1312     uint32_t pm_ivagrpsel;   /* a8 */
1313     uint32_t pm_wkst;        /* b0 */
1314     uint32_t pm_wkst3;       /* b8 */
1315     uint32_t pm_wkdep;       /* c8 */
1316     uint32_t pm_evgenctrl;   /* d4 */
1317     uint32_t pm_evgenontim;  /* d8 */
1318     uint32_t pm_evgenofftim; /* dc */
1319     uint32_t pm_pwstctrl;    /* e0 */
1320     uint32_t pm_pwstst;      /* e4 */
1321     uint32_t pm_prepwstst;   /* e8 */
1322     uint32_t pm_wken3;       /* f0 */
1323 };
1324
1325 struct omap3_prm_s {
1326     qemu_irq mpu_irq;
1327     qemu_irq iva_irq;
1328     struct omap_mpu_state_s *omap;
1329
1330     struct omap3_prm_domain_s iva2;
1331     struct omap3_prm_domain_s mpu;
1332     struct omap3_prm_domain_s core;
1333     struct omap3_prm_domain_s sgx;
1334     struct omap3_prm_domain_s wkup;
1335     struct omap3_prm_domain_s dss;
1336     struct omap3_prm_domain_s cam;
1337     struct omap3_prm_domain_s per;
1338     struct omap3_prm_domain_s emu;
1339     struct omap3_prm_domain_s neon;
1340     struct omap3_prm_domain_s usbhost;
1341
1342     uint32_t prm_irqstatus_iva2;
1343     uint32_t prm_irqenable_iva2;
1344
1345     uint32_t pm_iva2grpsel3_core;
1346     uint32_t pm_mpugrpsel3_core;
1347
1348     struct {
1349         uint32_t prm_revision;
1350         uint32_t prm_sysconfig;
1351         uint32_t prm_irqstatus_mpu;
1352         uint32_t prm_irqenable_mpu;
1353     } ocp;
1354
1355     struct {
1356         uint32_t prm_clksel;
1357         uint32_t prm_clkout_ctrl;
1358     } ccr; /* clock_control_reg */
1359
1360     struct {
1361         uint32_t prm_vc_smps_sa;
1362         uint32_t prm_vc_smps_vol_ra;
1363         uint32_t prm_vc_smps_cmd_ra;
1364         uint32_t prm_vc_cmd_val_0;
1365         uint32_t prm_vc_cmd_val_1;
1366         uint32_t prm_vc_hc_conf;
1367         uint32_t prm_vc_i2c_cfg;
1368         uint32_t prm_vc_bypass_val;
1369         uint32_t prm_rstctrl;
1370         uint32_t prm_rsttimer;
1371         uint32_t prm_rstst;
1372         uint32_t prm_voltctrl;
1373         uint32_t prm_sram_pcharge;
1374         uint32_t prm_clksrc_ctrl;
1375         uint32_t prm_obs;
1376         uint32_t prm_voltsetup1;
1377         uint32_t prm_voltoffset;
1378         uint32_t prm_clksetup;
1379         uint32_t prm_polctrl;
1380         uint32_t prm_voltsetup2;
1381     } gr; /* global_reg */
1382 };
1383
1384 static void omap3_prm_int_update(struct omap3_prm_s *s)
1385 {
1386     qemu_set_irq(s->mpu_irq, s->ocp.prm_irqstatus_mpu & s->ocp.prm_irqenable_mpu);
1387     qemu_set_irq(s->iva_irq, s->prm_irqstatus_iva2 & s->prm_irqenable_iva2);
1388 }
1389
1390 static void omap3_prm_reset(struct omap3_prm_s *s)
1391 {
1392     bzero(&s->iva2, sizeof(s->iva2));
1393     s->iva2.rm_rstctrl    = 0x7;
1394     s->iva2.rm_rstst      = 0x1;
1395     s->iva2.pm_wkdep      = 0xb3;
1396     s->iva2.pm_pwstctrl   = 0xff0f07;
1397     s->iva2.pm_pwstst     = 0xff7;
1398     s->prm_irqstatus_iva2 = 0x0;
1399     s->prm_irqenable_iva2 = 0x0;
1400
1401     bzero(&s->ocp, sizeof(s->ocp));
1402     s->ocp.prm_revision      = 0x10;
1403     s->ocp.prm_sysconfig     = 0x1;
1404
1405     bzero(&s->mpu, sizeof(s->mpu));
1406     s->mpu.rm_rstst       = 0x1;
1407     s->mpu.pm_wkdep       = 0xa5;
1408     s->mpu.pm_pwstctrl    = 0x30107;
1409     s->mpu.pm_pwstst      = 0xc7;
1410     s->mpu.pm_evgenctrl   = 0x12;
1411
1412     bzero(&s->core, sizeof(s->core));
1413     s->core.rm_rstst       = 0x1;
1414     s->core.pm_wken        = 0xc33ffe18;
1415     s->core.pm_mpugrpsel   = 0xc33ffe18;
1416     s->core.pm_ivagrpsel   = 0xc33ffe18;
1417     s->core.pm_pwstctrl    = 0xf0307;
1418     s->core.pm_pwstst      = 0xf7;
1419     s->core.pm_wken3       = 0x4;
1420     s->pm_iva2grpsel3_core = 0x4;
1421     s->pm_mpugrpsel3_core  = 0x4;
1422
1423     bzero(&s->sgx, sizeof(s->sgx));
1424     s->sgx.rm_rstst     = 0x1;
1425     s->sgx.pm_wkdep     = 0x16;
1426     s->sgx.pm_pwstctrl  = 0x30107;
1427     s->sgx.pm_pwstst    = 0x3;
1428
1429     bzero(&s->wkup, sizeof(s->wkup));
1430     s->wkup.pm_wken      = 0x3cb;
1431     s->wkup.pm_mpugrpsel = 0x3cb;
1432     s->wkup.pm_pwstst    = 0x3; /* TODO: check on real hardware */
1433
1434     bzero(&s->ccr, sizeof(s->ccr));
1435     s->ccr.prm_clksel      = 0x3; /* TRM says 0x4, but on HW this is 0x3 */
1436     s->ccr.prm_clkout_ctrl = 0x80;
1437
1438     bzero(&s->dss, sizeof(s->dss));
1439     s->dss.rm_rstst     = 0x1;
1440     s->dss.pm_wken      = 0x1;
1441     s->dss.pm_wkdep     = 0x16;
1442     s->dss.pm_pwstctrl  = 0x30107;
1443     s->dss.pm_pwstst    = 0x3;
1444
1445     bzero(&s->cam, sizeof(s->cam));
1446     s->cam.rm_rstst     = 0x1;
1447     s->cam.pm_wkdep     = 0x16;
1448     s->cam.pm_pwstctrl  = 0x30107;
1449     s->cam.pm_pwstst    = 0x3;
1450
1451     bzero(&s->per, sizeof(s->per));
1452     s->per.rm_rstst     = 0x1;
1453     s->per.pm_wken      = 0x3efff;
1454     s->per.pm_mpugrpsel = 0x3efff;
1455     s->per.pm_ivagrpsel = 0x3efff;
1456     s->per.pm_wkdep     = 0x17;
1457     s->per.pm_pwstctrl  = 0x30107;
1458     s->per.pm_pwstst    = 0x7;
1459
1460     bzero(&s->emu, sizeof(s->emu));
1461     s->emu.rm_rstst  = 0x1;
1462     s->emu.pm_pwstst = 0x13;
1463
1464     bzero(&s->gr, sizeof(s->gr));
1465     s->gr.prm_vc_i2c_cfg     = 0x18;
1466     s->gr.prm_rsttimer       = 0x1006;
1467     s->gr.prm_rstst          = 0x1;
1468     s->gr.prm_sram_pcharge   = 0x50;
1469     s->gr.prm_clksrc_ctrl    = 0x43;
1470     s->gr.prm_polctrl        = 0xa;
1471
1472     bzero(&s->neon, sizeof(s->neon));
1473     s->neon.rm_rstst     = 0x1;
1474     s->neon.pm_wkdep     = 0x2;
1475     s->neon.pm_pwstctrl  = 0x7;
1476     s->neon.pm_pwstst    = 0x3;
1477
1478     bzero(&s->usbhost, sizeof(s->usbhost));
1479     s->usbhost.rm_rstst     = 0x1;
1480     s->usbhost.pm_wken      = 0x1;
1481     s->usbhost.pm_mpugrpsel = 0x1;
1482     s->usbhost.pm_ivagrpsel = 0x1;
1483     s->usbhost.pm_wkdep     = 0x17;
1484     s->usbhost.pm_pwstctrl  = 0x30107;
1485     s->usbhost.pm_pwstst    = 0x3;
1486
1487     omap3_prm_int_update(s);
1488 }
1489
1490 static uint32_t omap3_prm_read(void *opaque, target_phys_addr_t addr)
1491 {
1492     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1493     struct omap3_prm_domain_s *d = 0;
1494
1495     TRACE("%04x", addr);
1496
1497     /* handle common domain registers first - all domains may not
1498        have all common registers though but we're returning zeroes there */
1499     switch ((addr >> 8) & 0xff) {
1500         case 0x00: d = &s->iva2; break;
1501         case 0x09: d = &s->mpu; break;
1502         case 0x0a: d = &s->core; break;
1503         case 0x0b: d = &s->sgx; break;
1504         case 0x0c: d = &s->wkup; break;
1505         case 0x0e: d = &s->dss; break;
1506         case 0x0f: d = &s->cam; break;
1507         case 0x10: d = &s->per; break;
1508         case 0x11: d = &s->emu; break;
1509         case 0x13: d = &s->neon; break;
1510         case 0x14: d = &s->usbhost; break;
1511         default: break;
1512     }
1513     if (d)
1514         switch (addr & 0xff) {
1515             case 0x50: return d->rm_rstctrl;
1516             case 0x58: return d->rm_rstst;
1517             case 0xa0: return d->pm_wken;
1518             case 0xa4: return d->pm_mpugrpsel;
1519             case 0xa8: return d->pm_ivagrpsel;
1520             case 0xb0: return d->pm_wkst;
1521             case 0xb8: return d->pm_wkst3;
1522             case 0xc8: return d->pm_wkdep;
1523             case 0xd4: return d->pm_evgenctrl;
1524             case 0xd8: return d->pm_evgenontim;
1525             case 0xdc: return d->pm_evgenofftim;
1526             case 0xe0: return d->pm_pwstctrl;
1527             case 0xe4: return d->pm_pwstst;
1528             case 0xe8: return d->pm_prepwstst;
1529             case 0xf0: return d->pm_wken3;
1530             default: break;
1531         }
1532
1533     /* okay, not a common domain register so let's take a closer look */
1534     switch (addr) {
1535         case 0x00f8: return s->prm_irqstatus_iva2;
1536         case 0x00fc: return s->prm_irqenable_iva2;
1537         case 0x0804: return s->ocp.prm_revision;
1538         case 0x0814: return s->ocp.prm_sysconfig;
1539         case 0x0818: return s->ocp.prm_irqstatus_mpu;
1540         case 0x081c: return s->ocp.prm_irqenable_mpu;
1541         case 0x0af4: return s->pm_iva2grpsel3_core;
1542         case 0x0af8: return s->pm_mpugrpsel3_core;
1543         case 0x0d40: return s->ccr.prm_clksel;
1544         case 0x0d70: return s->ccr.prm_clkout_ctrl;
1545         case 0x0de4: return 0x3; /* TODO: check on real hardware */
1546         case 0x1220: return s->gr.prm_vc_smps_sa;
1547         case 0x1224: return s->gr.prm_vc_smps_vol_ra;
1548         case 0x1228: return s->gr.prm_vc_smps_cmd_ra;
1549         case 0x122c: return s->gr.prm_vc_cmd_val_0;
1550         case 0x1230: return s->gr.prm_vc_cmd_val_1;
1551         case 0x1234: return s->gr.prm_vc_hc_conf;
1552         case 0x1238: return s->gr.prm_vc_i2c_cfg;
1553         case 0x123c: return s->gr.prm_vc_bypass_val;
1554         case 0x1250: return s->gr.prm_rstctrl;
1555         case 0x1254: return s->gr.prm_rsttimer;
1556         case 0x1258: return s->gr.prm_rstst;
1557         case 0x1260: return s->gr.prm_voltctrl;
1558         case 0x1264: return s->gr.prm_sram_pcharge;
1559         case 0x1270: return s->gr.prm_clksrc_ctrl;
1560         case 0x1280: return s->gr.prm_obs;
1561         case 0x1290: return s->gr.prm_voltsetup1;
1562         case 0x1294: return s->gr.prm_voltoffset;
1563         case 0x1298: return s->gr.prm_clksetup;
1564         case 0x129c: return s->gr.prm_polctrl;
1565         case 0x12a0: return s->gr.prm_voltsetup2;
1566         default: break;
1567     }
1568
1569     OMAP_BAD_REG(addr);
1570     return 0;
1571 }
1572
1573 static inline void omap3_prm_clksrc_ctrl_update(struct omap3_prm_s *s,
1574                                                 uint32_t value)
1575 {
1576     if ((value & 0xd0) == 0x40)
1577         omap_clk_setrate(omap_findclk(s->omap, "omap3_sys_clk"), 1, 1);
1578     else if ((value & 0xd0) == 0x80)
1579         omap_clk_setrate(omap_findclk(s->omap, "omap3_sys_clk"), 2, 1);
1580 }
1581
1582 static void omap3_prm_clksel_update(struct omap3_prm_s *s)
1583 {
1584     omap_clk newparent = 0;
1585
1586     switch (s->ccr.prm_clksel & 7) {
1587         case 0: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk12"); break;
1588         case 1: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk13"); break;
1589         case 2: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk192"); break;
1590         case 3: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk26"); break;
1591         case 4: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk384"); break;
1592         case 5: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk168"); break;
1593         default:
1594             fprintf(stderr, "%s: invalid sys_clk input selection (%d) - ignored\n",
1595                     __FUNCTION__, s->ccr.prm_clksel & 7);
1596             break;
1597     }
1598     if (newparent) {
1599         omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clk"), newparent);
1600         omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clkout1"), newparent);
1601     }
1602 }
1603
1604 static void omap3_prm_write(void *opaque, target_phys_addr_t addr,
1605                             uint32_t value)
1606 {
1607     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1608
1609     TRACE("%04x = %08x", addr, value);
1610     switch (addr) {
1611         /* IVA2_PRM */
1612         case 0x0050: s->iva2.rm_rstctrl = value & 0x7; break;
1613         case 0x0058: s->iva2.rm_rstst &= ~(value & 0x3f0f); break;
1614         case 0x00c8: s->iva2.pm_wkdep = value & 0xb3; break;
1615         case 0x00e0: s->iva2.pm_pwstctrl = 0xcff000 | (value & 0x300f0f); break;
1616         case 0x00e4: OMAP_RO_REG(addr); break;
1617         case 0x00e8: s->iva2.pm_prepwstst = value & 0xff7;
1618         case 0x00f8:
1619             s->prm_irqstatus_iva2 &= ~(value & 0x7);
1620             omap3_prm_int_update(s);
1621             break;
1622         case 0x00fc:
1623             s->prm_irqenable_iva2 = value & 0x7;
1624             omap3_prm_int_update(s);
1625             break;
1626         /* OCP_System_Reg_PRM */
1627         case 0x0804: OMAP_RO_REG(addr); break;
1628         case 0x0814: s->ocp.prm_sysconfig = value & 0x1; break;
1629         case 0x0818:
1630             s->ocp.prm_irqstatus_mpu &= ~(value & 0x03c003fd);
1631             omap3_prm_int_update(s);
1632             break;
1633         case 0x081c:
1634             s->ocp.prm_irqenable_mpu = value & 0x03c003fd;
1635             omap3_prm_int_update(s);
1636             break;
1637         /* MPU_PRM */
1638         case 0x0958: s->mpu.rm_rstst &= ~(value & 0x080f); break;
1639         case 0x09c8: s->mpu.pm_wkdep = value & 0xa5; break;
1640         case 0x09d4: s->mpu.pm_evgenctrl = value & 0x1f; break;
1641         case 0x09d8: s->mpu.pm_evgenontim = value; break;
1642         case 0x09dc: s->mpu.pm_evgenofftim = value; break;
1643         case 0x09e0: s->mpu.pm_pwstctrl = value & 0x3010f; break;
1644         case 0x09e4: OMAP_RO_REG(addr); break;
1645         case 0x09e8: s->mpu.pm_prepwstst = value & 0xc7; break;
1646         /* CORE_PRM */
1647         case 0x0a50: s->core.rm_rstctrl = value & 0x3; break; /* TODO: check if available on real hw */
1648         case 0x0a58: s->core.rm_rstst &= ~(value & 0x7); break;
1649         case 0x0aa0: s->core.pm_wken = 0x80000008 | (value & 0x433ffe10); break;
1650         case 0x0aa4: s->core.pm_mpugrpsel = 0x80000008 | (value & 0x433ffe10); break;
1651         case 0x0aa8: s->core.pm_ivagrpsel = 0x80000008 | (value & 0x433ffe10); break;
1652         case 0x0ab0: s->core.pm_wkst = value & 0x433ffe10; break;
1653         case 0x0ab8: s->core.pm_wkst3 &= ~(value & 0x4); break;
1654         case 0x0ae0: s->core.pm_pwstctrl = (value & 0x0f031f); break;
1655         case 0x0ae4: OMAP_RO_REG(addr); break;
1656         case 0x0ae8: s->core.pm_prepwstst = value & 0xf7; break;
1657         case 0x0af0: s->core.pm_wken3 = value & 0x4; break;
1658         case 0x0af4: s->pm_iva2grpsel3_core = value & 0x4; break;
1659         case 0x0af8: s->pm_mpugrpsel3_core = value & 0x4; break;
1660         /* SGX_PRM */
1661         case 0x0b58: s->sgx.rm_rstst &= ~(value & 0xf); break;
1662         case 0x0bc8: s->sgx.pm_wkdep = value & 0x16; break;
1663         case 0x0be0: s->sgx.pm_pwstctrl = 0x030104 | (value & 0x3); break;
1664         case 0x0be4: OMAP_RO_REG(addr); break;
1665         case 0x0be8: s->sgx.pm_prepwstst = value & 0x3; break;
1666         /* WKUP_PRM */
1667         case 0x0ca0: s->wkup.pm_wken = 0x2 | (value & 0x0103c9); break;
1668         case 0x0ca4: s->wkup.pm_mpugrpsel = 0x0102 | (value & 0x02c9); break;
1669         case 0x0ca8: s->wkup.pm_ivagrpsel = value & 0x03cb; break;
1670         case 0x0cb0: s->wkup.pm_wkst &= ~(value & 0x0103cb); break;
1671         /* Clock_Control_Reg_PRM */
1672         case 0x0d40:
1673             s->ccr.prm_clksel = value & 0x7;
1674             omap3_prm_clksel_update(s);
1675             break;
1676         case 0x0d70:
1677             s->ccr.prm_clkout_ctrl = value & 0x80;
1678             omap_clk_onoff(omap_findclk(s->omap, "omap3_sys_clkout1"),
1679                            s->ccr.prm_clkout_ctrl & 0x80);
1680             break;
1681         /* DSS_PRM */
1682         case 0x0e58: s->dss.rm_rstst &= ~(value & 0xf); break;
1683         case 0x0ea0: s->dss.pm_wken = value & 1; break;
1684         case 0x0ec8: s->dss.pm_wkdep = value & 0x16; break;
1685         case 0x0ee0: s->dss.pm_pwstctrl = 0x030104 | (value & 3); break;
1686         case 0x0ee4: OMAP_RO_REG(addr); break;
1687         case 0x0ee8: s->dss.pm_prepwstst = value & 3; break;
1688         /* CAM_PRM */
1689         case 0x0f58: s->cam.rm_rstst &= (value & 0xf); break;
1690         case 0x0fc8: s->cam.pm_wkdep = value & 0x16; break;
1691         case 0x0fe0: s->cam.pm_pwstctrl = 0x030104 | (value & 3); break;
1692         case 0x0fe4: OMAP_RO_REG(addr); break;
1693         case 0x0fe8: s->cam.pm_prepwstst = value & 0x3; break;
1694         /* PER_PRM */
1695         case 0x1058: s->per.rm_rstst &= ~(value & 0xf); break;
1696         case 0x10a0: s->per.pm_wken = value & 0x03efff; break;
1697         case 0x10a4: s->per.pm_mpugrpsel = value & 0x03efff; break;
1698         case 0x10a8: s->per.pm_ivagrpsel = value & 0x03efff; break;
1699         case 0x10b0: s->per.pm_wkst &= ~(value & 0x03efff); break;
1700         case 0x10c8: s->per.pm_wkdep = value & 0x17; break;
1701         case 0x10e0: s->per.pm_pwstctrl = 0x030100 | (value & 7); break;
1702         case 0x10e4: OMAP_RO_REG(addr); break;
1703         case 0x10e8: s->per.pm_prepwstst = value & 0x7; break;
1704         /* EMU_PRM */
1705         case 0x1158: s->emu.rm_rstst &= ~(value & 7); break;
1706         case 0x11e4: OMAP_RO_REG(addr); break;
1707         /* Global_Reg_PRM */
1708         case 0x1220: s->gr.prm_vc_smps_sa = value & 0x7f007f; break;
1709         case 0x1224: s->gr.prm_vc_smps_vol_ra = value & 0xff00ff; break;
1710         case 0x1228: s->gr.prm_vc_smps_cmd_ra = value & 0xff00ff; break;
1711         case 0x122c: s->gr.prm_vc_cmd_val_0 = value; break;
1712         case 0x1230: s->gr.prm_vc_cmd_val_1 = value; break;
1713         case 0x1234: s->gr.prm_vc_hc_conf = value & 0x1f001f; break;
1714         case 0x1238: s->gr.prm_vc_i2c_cfg = value & 0x3f; break;
1715         case 0x123c: s->gr.prm_vc_bypass_val = value & 0x01ffff7f; break;
1716         case 0x1250: s->gr.prm_rstctrl = 0; break; /* TODO: resets */
1717         case 0x1254: s->gr.prm_rsttimer = value & 0x1fff; break;
1718         case 0x1258: s->gr.prm_rstst &= ~(value & 0x7fb); break;
1719         case 0x1260: s->gr.prm_voltctrl = value & 0x1f; break;
1720         case 0x1264: s->gr.prm_sram_pcharge = value & 0xff; break;
1721         case 0x1270:
1722             s->gr.prm_clksrc_ctrl = value & 0xd8; /* set osc bypass mode */
1723             omap3_prm_clksrc_ctrl_update(s, s->gr.prm_clksrc_ctrl);
1724             break;
1725         case 0x1280: OMAP_RO_REG(addr); break;
1726         case 0x1290: s->gr.prm_voltsetup1 = value; break;
1727         case 0x1294: s->gr.prm_voltoffset = value & 0xffff; break;
1728         case 0x1298: s->gr.prm_clksetup = value & 0xffff; break;
1729         case 0x129c: s->gr.prm_polctrl = value & 0xf; break;
1730         case 0x12a0: s->gr.prm_voltsetup2 = value & 0xffff; break;
1731         /* NEON_PRM */
1732         case 0x1358: s->neon.rm_rstst &= ~(value & 0xf); break;
1733         case 0x13c8: s->neon.pm_wkdep = value & 0x2; break;
1734         case 0x13e0: s->neon.pm_pwstctrl = 0x4 | (value & 3); break;
1735         case 0x13e4: OMAP_RO_REG(addr); break;
1736         case 0x13e8: s->neon.pm_prepwstst = value & 3; break;
1737         /* USBHOST_PRM */
1738         case 0x1458: s->usbhost.rm_rstst &= ~(value & 0xf); break;
1739         case 0x14a0: s->usbhost.pm_wken = value & 1; break;
1740         case 0x14a4: s->usbhost.pm_mpugrpsel = value & 1; break;
1741         case 0x14a8: s->usbhost.pm_ivagrpsel = value & 1; break;
1742         case 0x14b0: s->usbhost.pm_wkst &= ~(value & 1); break;
1743         case 0x14c8: s->usbhost.pm_wkdep = value & 0x17; break;
1744         case 0x14e0: s->usbhost.pm_pwstctrl = 0x030104 | (value & 0x13); break;
1745         case 0x14e4: OMAP_RO_REG(addr); break;
1746         case 0x14e8: s->usbhost.pm_prepwstst = value & 3; break;
1747         default:
1748             OMAP_BAD_REGV(addr, value);
1749             break;
1750     }
1751 }
1752
1753 static CPUReadMemoryFunc *omap3_prm_readfn[] = {
1754     omap_badwidth_read32,
1755     omap_badwidth_read32,
1756     omap3_prm_read,
1757 };
1758
1759 static CPUWriteMemoryFunc *omap3_prm_writefn[] = {
1760     omap_badwidth_write32,
1761     omap_badwidth_write32,
1762     omap3_prm_write,
1763 };
1764
1765 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
1766                                    qemu_irq mpu_int, qemu_irq iva_int,
1767                                    struct omap_mpu_state_s *mpu)
1768 {
1769     int iomemtype;
1770     struct omap3_prm_s *s = (struct omap3_prm_s *) qemu_mallocz(sizeof(*s));
1771
1772     s->mpu_irq = mpu_int;
1773     s->iva_irq = iva_int;
1774     s->omap = mpu;
1775     omap3_prm_reset(s);
1776
1777     iomemtype = l4_register_io_memory(0, omap3_prm_readfn,
1778                                       omap3_prm_writefn, s);
1779     omap_l4_attach(ta, 0, iomemtype);
1780     omap_l4_attach(ta, 1, iomemtype);
1781
1782     return s;
1783 }
1784
1785 struct omap3_cm_s {
1786     qemu_irq irq[3];
1787     struct omap_mpu_state_s *mpu;
1788
1789     /* IVA2_CM: base + 0x0000 */
1790     uint32_t cm_fclken_iva2;       /* 00 */
1791     uint32_t cm_clken_pll_iva2;    /* 04 */
1792     uint32_t cm_idlest_iva2;       /* 20 */
1793     uint32_t cm_idlest_pll_iva2;   /* 24 */
1794     uint32_t cm_autoidle_pll_iva2; /* 34 */
1795     uint32_t cm_clksel1_pll_iva2;  /* 40 */
1796     uint32_t cm_clksel2_pll_iva2;  /* 44 */
1797     uint32_t cm_clkstctrl_iva2;    /* 48 */
1798     uint32_t cm_clkstst_iva2;      /* 4c */
1799
1800     /* OCP_System_Reg_CM: base + 0x0800 */
1801     uint32_t cm_revision;  /* 00 */
1802     uint32_t cm_sysconfig; /* 10 */
1803
1804     /* MPU_CM: base + 0x0900 */
1805     uint32_t cm_clken_pll_mpu;    /* 04 */
1806     uint32_t cm_idlest_mpu;       /* 20 */
1807     uint32_t cm_idlest_pll_mpu;   /* 24 */
1808     uint32_t cm_autoidle_pll_mpu; /* 34 */
1809     uint32_t cm_clksel1_pll_mpu;  /* 40 */
1810     uint32_t cm_clksel2_pll_mpu;  /* 44 */
1811     uint32_t cm_clkstctrl_mpu;    /* 48 */
1812     uint32_t cm_clkstst_mpu;      /* 4c */
1813
1814     /* CORE_CM: base + 0x0a00 */
1815     uint32_t cm_fclken1_core;   /* 0a00 */
1816     uint32_t cm_fclken3_core;   /* 0a08 */
1817     uint32_t cm_iclken1_core;   /* 0a10 */
1818     uint32_t cm_iclken2_core;   /* 0a14 */
1819     uint32_t cm_iclken3_core;   /* 0a18 */
1820     uint32_t cm_idlest1_core;   /* 0a20 */
1821     uint32_t cm_idlest2_core;   /* 0a24 */
1822     uint32_t cm_idlest3_core;   /* 0a28 */
1823     uint32_t cm_autoidle1_core; /* 0a30 */
1824     uint32_t cm_autoidle2_core; /* 0a34 */
1825     uint32_t cm_autoidle3_core; /* 0a38 */
1826     uint32_t cm_clksel_core;    /* 0a40 */
1827     uint32_t cm_clkstctrl_core; /* 0a48 */
1828     uint32_t cm_clkstst_core;   /* 0a4c */
1829
1830     /* SGX_CM: base + 0x0b00 */
1831     uint32_t cm_fclken_sgx;    /* 00 */
1832     uint32_t cm_iclken_sgx;    /* 10 */
1833     uint32_t cm_idlest_sgx;    /* 20 */
1834     uint32_t cm_clksel_sgx;    /* 40 */
1835     uint32_t cm_sleepdep_sgx;  /* 44 */
1836     uint32_t cm_clkstctrl_sgx; /* 48 */
1837     uint32_t cm_clkstst_sgx;   /* 4c */
1838
1839     /* WKUP_CM: base + 0x0c00 */
1840     uint32_t cm_fclken_wkup;   /* 00 */
1841     uint32_t cm_iclken_wkup;   /* 10 */
1842     uint32_t cm_idlest_wkup;   /* 20 */
1843     uint32_t cm_autoidle_wkup; /* 30 */
1844     uint32_t cm_clksel_wkup;   /* 40 */
1845     uint32_t cm_c48;           /* 48 */
1846
1847     /* Clock_Control_Reg_CM: base + 0x0d00 */
1848     uint32_t cm_clken_pll;     /* 00 */
1849     uint32_t cm_clken2_pll;    /* 04 */
1850     uint32_t cm_idlest_ckgen;  /* 20 */
1851     uint32_t cm_idlest2_ckgen; /* 24 */
1852     uint32_t cm_autoidle_pll;  /* 30 */
1853     uint32_t cm_autoidle2_pll; /* 34 */
1854     uint32_t cm_clksel1_pll;   /* 40 */
1855     uint32_t cm_clksel2_pll;   /* 44 */
1856     uint32_t cm_clksel3_pll;   /* 48 */
1857     uint32_t cm_clksel4_pll;   /* 4c */
1858     uint32_t cm_clksel5_pll;   /* 50 */
1859     uint32_t cm_clkout_ctrl;   /* 70 */
1860
1861     /* DSS_CM: base + 0x0e00 */
1862     uint32_t cm_fclken_dss;    /* 00 */
1863     uint32_t cm_iclken_dss;    /* 10 */
1864     uint32_t cm_idlest_dss;    /* 20 */
1865     uint32_t cm_autoidle_dss;  /* 30 */
1866     uint32_t cm_clksel_dss;    /* 40 */
1867     uint32_t cm_sleepdep_dss;  /* 44 */
1868     uint32_t cm_clkstctrl_dss; /* 48 */
1869     uint32_t cm_clkstst_dss;   /* 4c */
1870
1871    /* CAM_CM: base + 0x0f00 */
1872     uint32_t cm_fclken_cam;    /* 00 */
1873     uint32_t cm_iclken_cam;    /* 10 */
1874     uint32_t cm_idlest_cam;    /* 20 */
1875     uint32_t cm_autoidle_cam;  /* 30 */
1876     uint32_t cm_clksel_cam;    /* 40 */
1877     uint32_t cm_sleepdep_cam;  /* 44 */
1878     uint32_t cm_clkstctrl_cam; /* 48 */
1879     uint32_t cm_clkstst_cam;   /* 4c */
1880
1881     /* PER_CM: base + 0x1000 */
1882     uint32_t cm_fclken_per;    /* 00 */
1883     uint32_t cm_iclken_per;    /* 10 */
1884     uint32_t cm_idlest_per;    /* 20 */
1885     uint32_t cm_autoidle_per;  /* 30 */
1886     uint32_t cm_clksel_per;    /* 40 */
1887     uint32_t cm_sleepdep_per;  /* 44 */
1888     uint32_t cm_clkstctrl_per; /* 48 */
1889     uint32_t cm_clkstst_per;   /* 4c */
1890
1891     /* EMU_CM: base + 0x1100 */
1892     uint32_t cm_clksel1_emu;   /* 40 */
1893     uint32_t cm_clkstctrl_emu; /* 48 */
1894     uint32_t cm_clkstst_emu;   /* 4c */
1895     uint32_t cm_clksel2_emu;   /* 50 */
1896     uint32_t cm_clksel3_emu;   /* 54 */
1897
1898     /* Global_Reg_CM: base + 0x1200 */
1899     uint32_t cm_polctrl; /* 9c */
1900
1901     /* NEON_CM: base + 0x1300 */
1902     uint32_t cm_idlest_neon;    /* 20 */
1903     uint32_t cm_clkstctrl_neon; /* 48 */
1904
1905     /* USBHOST_CM: base + 0x1400 */
1906     uint32_t cm_fclken_usbhost;    /* 00 */
1907     uint32_t cm_iclken_usbhost;    /* 10 */
1908     uint32_t cm_idlest_usbhost;    /* 20 */
1909     uint32_t cm_autoidle_usbhost;  /* 30 */
1910     uint32_t cm_sleepdep_usbhost;  /* 44 */
1911     uint32_t cm_clkstctrl_usbhost; /* 48 */
1912     uint32_t cm_clkstst_usbhost;   /* 4c */
1913 };
1914
1915 static inline void omap3_cm_clksel_wkup_update(struct omap3_cm_s *s)
1916 {
1917     omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp1_fclk"),
1918                       omap_findclk(s->mpu,
1919                                    (s->cm_clksel_wkup & 1) /* CLKSEL_GPT1 */
1920                                    ? "omap3_sys_clk"
1921                                    : "omap3_32k_fclk"));
1922     omap_clk_setrate(omap_findclk(s->mpu, "omap3_rm_iclk"),
1923                      (s->cm_clksel_wkup >> 1) & 3, /* CLKSEL_RM */
1924                      1);
1925
1926     /* Tell GPTIMER to generate new clk rate */
1927     omap_gp_timer_change_clk(s->mpu->gptimer[0]);
1928
1929     TRACE("gptimer1 fclk=%lld",
1930           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp1_fclk")));
1931
1932     /* TODO: CM_USIM_CLK */
1933 }
1934
1935 static inline void omap3_cm_iva2_update(struct omap3_cm_s *s)
1936 {
1937     uint32_t iva2_dpll_mul = ((s->cm_clksel1_pll_iva2 >> 8) & 0x7ff);
1938     uint32_t iva2_dpll_div, iva2_dpll_clkout_div, iva2_clk_src;
1939     omap_clk iva2_clk = omap_findclk(s->mpu, "omap3_iva2_clk");
1940
1941     omap_clk_onoff(iva2_clk, s->cm_fclken_iva2 & 1);
1942
1943     switch ((s->cm_clken_pll_iva2 & 0x7)) {
1944         case 0x01: /* low power stop mode */
1945         case 0x05: /* low power bypass mode */
1946             s->cm_idlest_pll_iva2 &= ~1;
1947             break;
1948         case 0x07: /* locked */
1949             if (iva2_dpll_mul < 2)
1950                 s->cm_idlest_pll_iva2 &= ~1;
1951             else
1952                 s->cm_idlest_pll_iva2 |= 1;
1953             break;
1954         default:
1955             break;
1956     }
1957
1958     if (s->cm_idlest_pll_iva2 & 1) {
1959         iva2_dpll_div = s->cm_clksel1_pll_iva2 & 0x7f;
1960         iva2_dpll_clkout_div = s->cm_clksel2_pll_iva2 & 0x1f;
1961         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
1962         omap_clk_setrate(iva2_clk,
1963                          (iva2_dpll_div + 1) * iva2_dpll_clkout_div,
1964                          iva2_dpll_mul);
1965     } else {
1966         /* bypass mode */
1967         iva2_clk_src = (s->cm_clksel1_pll_iva2 >> 19) & 0x07;
1968         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_core_clk"));
1969         omap_clk_setrate(iva2_clk, iva2_clk_src, 1);
1970     }
1971 }
1972
1973 static inline void omap3_cm_mpu_update(struct omap3_cm_s *s)
1974 {
1975     uint32_t mpu_dpll_mul = ((s->cm_clksel1_pll_mpu >> 8) & 0x7ff);
1976     uint32_t mpu_dpll_div, mpu_dpll_clkout_div, mpu_clk_src;
1977     omap_clk mpu_clk = omap_findclk(s->mpu, "omap3_mpu_clk");
1978
1979     switch ((s->cm_clken_pll_mpu & 0x7)) {
1980         case 0x05: /* low power bypass mode */
1981             s->cm_idlest_pll_mpu &= ~1;
1982             break;
1983         case 0x07: /* locked */
1984             if (mpu_dpll_mul < 2)
1985                 s->cm_idlest_pll_mpu &= ~1;
1986             else
1987                 s->cm_idlest_pll_mpu |= 1;
1988             break;
1989         default:
1990             break;
1991     }
1992
1993     if (s->cm_idlest_pll_mpu & 1) {
1994         mpu_dpll_div = s->cm_clksel1_pll_mpu & 0x7f;
1995         mpu_dpll_clkout_div = s->cm_clksel2_pll_mpu & 0x1f;
1996         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
1997         omap_clk_setrate(mpu_clk,
1998                          (mpu_dpll_div + 1) * mpu_dpll_clkout_div,
1999                          mpu_dpll_mul);
2000     } else {
2001         /* bypass mode */
2002         mpu_clk_src = (s->cm_clksel1_pll_mpu >> 19) & 0x07;
2003         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_core_clk"));
2004         omap_clk_setrate(mpu_clk, mpu_clk_src, 1);
2005     }
2006 }
2007
2008 static inline void omap3_cm_dpll3_update(struct omap3_cm_s *s)
2009 {
2010     uint32_t core_dpll_mul = ((s->cm_clksel1_pll >> 16) & 0x7ff);
2011     uint32_t core_dpll_div, core_dpll_clkout_div, div_dpll3;
2012
2013     switch ((s->cm_clken_pll & 0x7)) {
2014         case 0x05: /* low power bypass */
2015         case 0x06: /* fast relock bypass */
2016             s->cm_idlest_ckgen &= ~1;
2017             break;
2018         case 0x07: /* locked */
2019             if (core_dpll_mul < 2)
2020                 s->cm_idlest_ckgen &= ~1;
2021             else
2022                 s->cm_idlest_ckgen |= 1;
2023             break;
2024         default:
2025             break;
2026     }
2027
2028     if (s->cm_idlest_ckgen & 1) {
2029         core_dpll_div = (s->cm_clksel1_pll >> 8) & 0x7f;
2030         core_dpll_clkout_div = (s->cm_clksel1_pll >> 27) & 0x1f;
2031         div_dpll3 = (s->cm_clksel1_emu >> 16) & 0x1f;
2032
2033         if (s->cm_clksel2_emu & 0x80000) { /* OVERRIDE_ENABLE */
2034                 core_dpll_mul = (s->cm_clksel2_emu >> 8) & 0x7ff;
2035                 core_dpll_div = s->cm_clksel2_emu & 0x7f;
2036         }
2037
2038         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"),
2039                          (core_dpll_div + 1) * core_dpll_clkout_div,
2040                          core_dpll_mul);
2041         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"),
2042                          (core_dpll_div + 1) * core_dpll_clkout_div,
2043                          core_dpll_mul * 2);
2044         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"),
2045                          (core_dpll_div + 1) * div_dpll3,
2046                          core_dpll_mul * 2);
2047     } else {
2048         /* bypass mode */
2049         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), 1, 1);
2050         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), 1, 1);
2051         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"), 1, 1);
2052     }
2053 }
2054
2055 static inline void omap3_cm_dpll4_update(struct omap3_cm_s *s)
2056 {
2057     uint32_t per_dpll_mul = ((s->cm_clksel2_pll >> 8) & 0x7ff);
2058     uint32_t per_dpll_div, div_96m, clksel_tv, clksel_dss1, clksel_cam, div_dpll4;
2059
2060     switch (((s->cm_clken_pll >> 16) & 0x7)) {
2061         case 0x01: /* lower power stop mode */
2062             s->cm_idlest_ckgen &= ~2;
2063             break;
2064         case 0x07: /* locked */
2065             if (per_dpll_mul < 2)
2066                 s->cm_idlest_ckgen &= ~2;
2067             else
2068                 s->cm_idlest_ckgen |= 2;
2069             break;
2070         default:
2071             break;
2072     }
2073
2074     if (s->cm_idlest_ckgen & 2) {
2075         per_dpll_div = s->cm_clksel2_pll & 0x7f;
2076         div_96m = s->cm_clksel3_pll & 0x1f;
2077         clksel_tv = (s->cm_clksel_dss >> 8) & 0x1f;
2078         clksel_dss1 = s->cm_clksel_dss & 0x1f;
2079         clksel_cam = s->cm_clksel_cam & 0x1f;
2080         div_dpll4 = (s->cm_clksel1_emu >> 24) & 0x1f;
2081
2082         if (s->cm_clksel3_emu & 0x80000) { /* OVERRIDE_ENABLE */
2083                 per_dpll_mul = (s->cm_clksel3_emu >> 8) & 0x7ff;
2084                 per_dpll_div =  s->cm_clksel3_emu & 0x7f;
2085         }
2086
2087         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"),
2088                          (per_dpll_div + 1) * div_96m,
2089                          per_dpll_mul * 2);
2090         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"),
2091                          (per_dpll_div + 1) * clksel_tv,
2092                          per_dpll_mul * 2);
2093         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"),
2094                          (per_dpll_div + 1) * clksel_dss1,
2095                          per_dpll_mul * 2);
2096         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"),
2097                          (per_dpll_div + 1) * clksel_cam,
2098                          per_dpll_mul * 2);
2099         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"),
2100                          (per_dpll_div + 1) * div_dpll4,
2101                          per_dpll_mul * 2);
2102     } else {
2103         /* bypass mode */
2104         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), 1, 1);
2105         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), 1, 1);
2106         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"), 1, 1);
2107         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), 1, 1);
2108         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"), 1, 1);
2109     }
2110 }
2111
2112 static inline void omap3_cm_dpll5_update(struct omap3_cm_s *s)
2113 {
2114     uint32_t per2_dpll_mul = ((s->cm_clksel4_pll >> 8) & 0x7ff);
2115     uint32_t per2_dpll_div, div_120m;
2116
2117     switch ((s->cm_clken2_pll & 0x7)) {
2118         case 0x01: /* low power stop mode */
2119             s->cm_idlest2_ckgen &= ~1;
2120             break;
2121         case 0x07: /* locked */
2122             if (per2_dpll_mul < 2)
2123                 s->cm_idlest2_ckgen &= ~1;
2124             else
2125                 s->cm_idlest2_ckgen |= 1;
2126             break;
2127         default:
2128             break;
2129     }
2130
2131     if (s->cm_idlest2_ckgen & 1) {
2132         per2_dpll_div = s->cm_clksel4_pll & 0x7f;
2133         div_120m = s->cm_clksel5_pll & 0x1f;
2134
2135         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"),
2136                          (per2_dpll_div + 1) * div_120m,
2137                          per2_dpll_mul);
2138     } else {
2139         /* bypass mode */
2140         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), 1, 1);
2141     }
2142 }
2143
2144 static inline void omap3_cm_48m_update(struct omap3_cm_s *s)
2145 {
2146     omap_clk pclk = omap_findclk(s->mpu,
2147                                  (s->cm_clksel1_pll & 0x8) /* SOURCE_48M */
2148                                  ? "omap3_sys_altclk"
2149                                  : "omap3_96m_fclk");
2150
2151     omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"), pclk);
2152     omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"), pclk);
2153 }
2154
2155 static inline void omap3_cm_gp10gp11_update(struct omap3_cm_s *s)
2156 {
2157     omap_clk gp10 = omap_findclk(s->mpu, "omap3_gp10_fclk");
2158     omap_clk gp11 = omap_findclk(s->mpu, "omap3_gp11_fclk");
2159     omap_clk sys  = omap_findclk(s->mpu, "omap3_sys_clk");
2160     omap_clk f32k = omap_findclk(s->mpu, "omap3_32k_fclk");
2161
2162     omap_clk_reparent(gp10, (s->cm_clksel_core & 0x40) ? sys : f32k);
2163     omap_clk_reparent(gp11, (s->cm_clksel_core & 0x80) ? sys : f32k);
2164     omap_gp_timer_change_clk(s->mpu->gptimer[9]);
2165     omap_gp_timer_change_clk(s->mpu->gptimer[10]);
2166
2167     TRACE("gptimer10 fclk = %lld", omap_clk_getrate(gp10));
2168     TRACE("gptimer11 fclk = %lld", omap_clk_getrate(gp11));
2169 }
2170
2171 static inline void omap3_cm_per_gptimer_update(struct omap3_cm_s *s)
2172 {
2173     omap_clk sys = omap_findclk(s->mpu, "omap3_sys_clk");
2174     omap_clk f32k = omap_findclk(s->mpu, "omap3_32k_fclk");
2175     uint32_t cm_clksel_per = s->cm_clksel_per;
2176     uint32_t n;
2177     char clkname[] = "omap3_gp#_fclk";
2178
2179     for (n = 1; n < 9; n++, cm_clksel_per >>= 1) {
2180         clkname[8] = '1' + n; /* 2 - 9 */
2181         omap_clk_reparent(omap_findclk(s->mpu, clkname),
2182                           (cm_clksel_per & 1) ? sys : f32k);
2183         omap_gp_timer_change_clk(s->mpu->gptimer[n]);
2184         TRACE("gptimer%d fclk = %lld", n + 1,
2185               omap_clk_getrate(omap_findclk(s->mpu, clkname)));
2186     }
2187 }
2188
2189 static inline void omap3_cm_clkout2_update(struct omap3_cm_s *s)
2190 {
2191     omap_clk c = omap_findclk(s->mpu, "omap3_sys_clkout2");
2192
2193     omap_clk_onoff(c, (s->cm_clkout_ctrl >> 7) & 1);
2194     switch (s->cm_clkout_ctrl & 0x3) {
2195         case 0:
2196             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_core_clk"));
2197             break;
2198         case 1:
2199             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_sys_clk"));
2200             break;
2201         case 2:
2202             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_96m_fclk"));
2203             break;
2204         case 3:
2205             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_54m_fclk"));
2206             break;
2207         default:
2208             break;
2209     }
2210     omap_clk_setrate(c, 1 << ((s->cm_clkout_ctrl >> 3) & 7), 1);
2211 }
2212
2213 static inline void omap3_cm_fclken1_core_update(struct omap3_cm_s *s)
2214 {
2215     uint32_t v = s->cm_fclken1_core;
2216
2217     /* TODO: EN_MCBSP1,5 */
2218     omap_clk_onoff(omap_findclk(s->mpu, "omap3_gp10_fclk"),  (v >> 11) & 1);
2219     omap_clk_onoff(omap_findclk(s->mpu, "omap3_gp11_fclk"),  (v >> 12) & 1);
2220     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart1_fclk"), (v >> 13) & 1);
2221     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart2_fclk"), (v >> 14) & 1);
2222     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c1_fclk"),  (v >> 15) & 1);
2223     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c2_fclk"),  (v >> 16) & 1);
2224     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c3_fclk"),  (v >> 17) & 1);
2225     /* TODO: EN_HDQ, EN_SPI1-4 */
2226     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc1_fclk"),  (v >> 24) & 1);
2227     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc2_fclk"),  (v >> 25) & 1);
2228     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc3_fclk"),  (v >> 30) & 1);
2229 }
2230
2231 static inline void omap3_cm_iclken1_core_update(struct omap3_cm_s *s)
2232 {
2233     uint32_t v = s->cm_iclken1_core;
2234
2235     /* TODO: EN_SDRC, EN_HSOTGUSB, EN_OMAPCTRL, EN_MAILBOXES, EN_MCBSP1,5 */
2236     /* TODO: EN_GPT10, EN_GPT11 */
2237     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart1_iclk"), (v >> 13) & 1);
2238     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart2_iclk"), (v >> 14) & 1);
2239     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c1_iclk"),  (v >> 15) & 1);
2240     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c2_iclk"),  (v >> 16) & 1);
2241     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c3_iclk"),  (v >> 17) & 1);
2242     /* TODO: EN_HDQ, EN_SPI1-4 */
2243     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc1_iclk"),  (v >> 24) & 1);
2244     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc2_iclk"),  (v >> 25) & 1);
2245     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc3_iclk"),  (v >> 30) & 1);
2246     /* set USB OTG idle if iclk is enabled and SDMA always in standby */
2247     v &= ~0x24;
2248     v |= (v & 0x10) << 1;
2249     s->cm_idlest1_core = ~v;
2250 }
2251
2252 static void omap3_cm_reset(struct omap3_cm_s *s)
2253 {
2254     s->cm_fclken_iva2 = 0x0;
2255     s->cm_clken_pll_iva2 = 0x11;
2256     s->cm_idlest_iva2 = 0x1;
2257     s->cm_idlest_pll_iva2 = 0;
2258     s->cm_autoidle_pll_iva2 = 0x0;
2259     s->cm_clksel1_pll_iva2 = 0x80000;
2260     s->cm_clksel2_pll_iva2 = 0x1;
2261     s->cm_clkstctrl_iva2 = 0x0;
2262     s->cm_clkstst_iva2 = 0x0;
2263
2264     s->cm_revision = 0x10;
2265     s->cm_sysconfig = 0x1;
2266
2267     s->cm_clken_pll_mpu = 0x15;
2268     s->cm_idlest_mpu = 0x1;
2269     s->cm_idlest_pll_mpu = 0;
2270     s->cm_autoidle_pll_mpu = 0x0;
2271     s->cm_clksel1_pll_mpu = 0x80000;
2272     s->cm_clksel2_pll_mpu = 0x1;
2273     s->cm_clkstctrl_mpu = 0x0;
2274     s->cm_clkstst_mpu = 0x0;
2275
2276     s->cm_fclken1_core = 0x0;
2277     s->cm_fclken3_core = 0x0;
2278     s->cm_iclken1_core = 0x42;
2279     s->cm_iclken2_core = 0x0;
2280     s->cm_iclken3_core = 0x0;
2281     /*allow access to devices*/
2282     s->cm_idlest1_core = 0x0;
2283     s->cm_idlest2_core = 0x0;
2284     /*ide status =0 */
2285     s->cm_idlest3_core = 0xa;
2286     s->cm_autoidle1_core = 0x0;
2287     s->cm_autoidle2_core = 0x0;
2288     s->cm_autoidle3_core = 0x0;
2289     s->cm_clksel_core = 0x105;
2290     s->cm_clkstctrl_core = 0x0;
2291     s->cm_clkstst_core = 0x0;
2292
2293     s->cm_fclken_sgx = 0x0;
2294     s->cm_iclken_sgx = 0x0;
2295     s->cm_idlest_sgx = 0x1;
2296     s->cm_clksel_sgx = 0x0;
2297     s->cm_sleepdep_sgx = 0x0;
2298     s->cm_clkstctrl_sgx = 0x0;
2299     s->cm_clkstst_sgx = 0x0;
2300
2301     s->cm_fclken_wkup = 0x0;
2302     s->cm_iclken_wkup = 0x0;
2303     /*assume all clock can be accessed*/
2304     s->cm_idlest_wkup = 0x0;
2305     s->cm_autoidle_wkup = 0x0;
2306     s->cm_clksel_wkup = 0x12;
2307
2308     s->cm_clken_pll = 0x110015;
2309     s->cm_clken2_pll = 0x11;
2310     s->cm_idlest_ckgen = 0x3f3c; /* FIXME: provide real clock statuses */
2311     s->cm_idlest2_ckgen = 0xa; /* FIXME: provide real clock statuses */
2312     s->cm_autoidle_pll = 0x0;
2313     s->cm_autoidle2_pll = 0x0;
2314     s->cm_clksel1_pll = 0x8000040;
2315     s->cm_clksel2_pll = 0x0;
2316     s->cm_clksel3_pll = 0x1;
2317     s->cm_clksel4_pll = 0x0;
2318     s->cm_clksel5_pll = 0x1;
2319     s->cm_clkout_ctrl = 0x3;
2320
2321
2322     s->cm_fclken_dss = 0x0;
2323     s->cm_iclken_dss = 0x0;
2324     /*dss can be accessed*/
2325     s->cm_idlest_dss = 0x0;
2326     s->cm_autoidle_dss = 0x0;
2327     s->cm_clksel_dss = 0x1010;
2328     s->cm_sleepdep_dss = 0x0;
2329     s->cm_clkstctrl_dss = 0x0;
2330     s->cm_clkstst_dss = 0x0;
2331
2332     s->cm_fclken_cam = 0x0;
2333     s->cm_iclken_cam = 0x0;
2334     s->cm_idlest_cam = 0x1;
2335     s->cm_autoidle_cam = 0x0;
2336     s->cm_clksel_cam = 0x10;
2337     s->cm_sleepdep_cam = 0x0;
2338     s->cm_clkstctrl_cam = 0x0;
2339     s->cm_clkstst_cam = 0x0;
2340
2341     s->cm_fclken_per = 0x0;
2342     s->cm_iclken_per = 0x0;
2343     //s->cm_idlest_per = 0x3ffff;
2344     s->cm_idlest_per = 0x0; //enable GPIO access
2345     s->cm_autoidle_per = 0x0;
2346     s->cm_clksel_per = 0x0;
2347     s->cm_sleepdep_per = 0x0;
2348     s->cm_clkstctrl_per = 0x0;
2349     s->cm_clkstst_per = 0x0;
2350
2351     s->cm_clksel1_emu = 0x10100a50;
2352     s->cm_clkstctrl_emu = 0x2;
2353     s->cm_clkstst_emu = 0x0;
2354     s->cm_clksel2_emu = 0x0;
2355     s->cm_clksel3_emu = 0x0;
2356
2357     s->cm_polctrl = 0x0;
2358
2359     s->cm_idlest_neon = 0x1;
2360     s->cm_clkstctrl_neon = 0x0;
2361
2362     s->cm_fclken_usbhost = 0x0;
2363     s->cm_iclken_usbhost = 0x0;
2364     s->cm_idlest_usbhost = 0x3;
2365     s->cm_autoidle_usbhost = 0x0;
2366     s->cm_sleepdep_usbhost = 0x0;
2367     s->cm_clkstctrl_usbhost = 0x0;
2368     s->cm_clkstst_usbhost = 0x0;
2369 }
2370
2371 static uint32_t omap3_cm_read(void *opaque, target_phys_addr_t addr)
2372 {
2373     struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;
2374
2375     switch (addr) {
2376         /* IVA2_CM */
2377         case 0x0000: return s->cm_fclken_iva2;
2378         case 0x0004: return s->cm_clken_pll_iva2;
2379         case 0x0020: return s->cm_idlest_iva2;
2380         case 0x0024: return s->cm_idlest_pll_iva2;
2381         case 0x0034: return s->cm_autoidle_pll_iva2;
2382         case 0x0040: return s->cm_clksel1_pll_iva2;
2383         case 0x0044: return s->cm_clksel2_pll_iva2;
2384         case 0x0048: return s->cm_clkstctrl_iva2;
2385         case 0x004c: return s->cm_clkstst_iva2;
2386         /* OCP_System_Reg_CM */
2387         case 0x0800: return s->cm_revision;
2388         case 0x0810: return s->cm_sysconfig;
2389         /* MPU_CM */
2390         case 0x0904: return s->cm_clken_pll_mpu;
2391         case 0x0920: return s->cm_idlest_mpu & 0x0; /*MPU is active*/
2392         case 0x0924: return s->cm_idlest_pll_mpu;
2393         case 0x0934: return s->cm_autoidle_pll_mpu;
2394         case 0x0940: return s->cm_clksel1_pll_mpu;
2395         case 0x0944: return s->cm_clksel2_pll_mpu;
2396         case 0x0948: return s->cm_clkstctrl_mpu;
2397         case 0x094c: return s->cm_clkstst_mpu;
2398         /* CORE_CM */
2399         case 0x0a00: return s->cm_fclken1_core;
2400         case 0x0a08: return s->cm_fclken3_core;
2401         case 0x0a10: return s->cm_iclken1_core;
2402         case 0x0a14: return s->cm_iclken2_core;
2403         case 0x0a20: return s->cm_idlest1_core;
2404         case 0x0a24: return s->cm_idlest2_core;
2405         case 0x0a28: return s->cm_idlest3_core;
2406         case 0x0a30: return s->cm_autoidle1_core;
2407         case 0x0a34: return s->cm_autoidle2_core;
2408         case 0x0a38: return s->cm_autoidle3_core;
2409         case 0x0a40: return s->cm_clksel_core;
2410         case 0x0a48: return s->cm_clkstctrl_core;
2411         case 0x0a4c: return s->cm_clkstst_core;
2412         /* SGX_CM */
2413         case 0x0b00: return s->cm_fclken_sgx;
2414         case 0x0b10: return s->cm_iclken_sgx;
2415         case 0x0b20: return s->cm_idlest_sgx & 0x0;
2416         case 0x0b40: return s->cm_clksel_sgx;
2417         case 0x0b48: return s->cm_clkstctrl_sgx;
2418         case 0x0b4c: return s->cm_clkstst_sgx;
2419         /* WKUP_CM */
2420         case 0x0c00: return s->cm_fclken_wkup;
2421         case 0x0c10: return s->cm_iclken_wkup;
2422         case 0x0c20: return 0; /* TODO: Check if the timer can be accessed. */
2423         case 0x0c30: return s->cm_idlest_wkup;
2424         case 0x0c40: return s->cm_clksel_wkup;
2425         case 0x0c48: return s->cm_c48;
2426         /* Clock_Control_Reg_CM */
2427         case 0x0d00: return s->cm_clken_pll;
2428         case 0x0d04: return s->cm_clken2_pll;
2429         case 0x0d20: return s->cm_idlest_ckgen;
2430         case 0x0d24: return s->cm_idlest2_ckgen;
2431         case 0x0d30: return s->cm_autoidle_pll;
2432         case 0x0d34: return s->cm_autoidle2_pll;
2433         case 0x0d40: return s->cm_clksel1_pll;
2434         case 0x0d44: return s->cm_clksel2_pll;
2435         case 0x0d48: return s->cm_clksel3_pll;
2436         case 0x0d4c: return s->cm_clksel4_pll;
2437         case 0x0d50: return s->cm_clksel5_pll;
2438         case 0x0d70: return s->cm_clkout_ctrl;
2439         /* DSS_CM */
2440         case 0x0e00: return s->cm_fclken_dss;
2441         case 0x0e10: return s->cm_iclken_dss;
2442         case 0x0e20: return s->cm_idlest_dss;
2443         case 0x0e30: return s->cm_autoidle_dss;
2444         case 0x0e40: return s->cm_clksel_dss;
2445         case 0x0e44: return s->cm_sleepdep_dss;
2446         case 0x0e48: return s->cm_clkstctrl_dss;
2447         case 0x0e4c: return s->cm_clkstst_dss;
2448         /* CAM_CM */
2449         case 0x0f00: return s->cm_fclken_cam;
2450         case 0x0f10: return s->cm_iclken_cam;
2451         case 0x0f20: return s->cm_idlest_cam & 0x0;
2452         case 0x0f30: return s->cm_autoidle_cam;
2453         case 0x0f40: return s->cm_clksel_cam;
2454         case 0x0f44: return s->cm_sleepdep_cam;
2455         case 0x0f48: return s->cm_clkstctrl_cam;
2456         case 0x0f4c: return s->cm_clkstst_cam;
2457         /* PER_CM */
2458         case 0x1000: return s->cm_fclken_per;
2459         case 0x1010: return s->cm_iclken_per;
2460         case 0x1020: return s->cm_idlest_per ;
2461         case 0x1030: return s->cm_autoidle_per;
2462         case 0x1040: return s->cm_clksel_per;
2463         case 0x1044: return s->cm_sleepdep_per;
2464         case 0x1048: return s->cm_clkstctrl_per;
2465         case 0x104c: return s->cm_clkstst_per;
2466         /* EMU_CM */
2467         case 0x1140: return s->cm_clksel1_emu;
2468         case 0x1148: return s->cm_clkstctrl_emu;
2469         case 0x114c: return s->cm_clkstst_emu & 0x0;
2470         case 0x1150: return s->cm_clksel2_emu;
2471         case 0x1154: return s->cm_clksel3_emu;
2472         /* Global_Reg_CM */
2473         case 0x129c: return s->cm_polctrl;
2474         /* NEON_CM */
2475         case 0x1320: return s->cm_idlest_neon & 0x0;
2476         case 0x1348: return s->cm_clkstctrl_neon;
2477         /* USBHOST_CM */
2478         case 0x1400: return s->cm_fclken_usbhost;
2479         case 0x1410: return s->cm_iclken_usbhost;
2480         case 0x1420: return s->cm_idlest_usbhost & 0x0;
2481         case 0x1430: return s->cm_autoidle_usbhost;
2482         case 0x1444: return s->cm_sleepdep_usbhost;
2483         case 0x1448: return s->cm_clkstctrl_usbhost;
2484         case 0x144c: return s->cm_clkstst_usbhost;
2485         /* unknown */
2486         default: break;
2487     }
2488     OMAP_BAD_REG(addr);
2489     return 0;
2490 }
2491
2492 static void omap3_cm_write(void *opaque,
2493                            target_phys_addr_t addr,
2494                            uint32_t value)
2495 {
2496     struct omap3_cm_s *s = (struct omap3_cm_s *)opaque;
2497
2498     switch (addr) {
2499         case 0x0020:
2500         case 0x0024:
2501         case 0x004c:
2502         case 0x0800:
2503         case 0x0920:
2504         case 0x0924:
2505         case 0x094c:
2506         case 0x0a20:
2507         case 0x0a24:
2508         case 0x0a28:
2509         case 0x0a4c:
2510         case 0x0b20:
2511         case 0x0b4c:
2512         case 0x0c20:
2513         case 0x0d20:
2514         case 0x0d24:
2515         case 0x0e20:
2516         case 0x0e4c:
2517         case 0x0f20:
2518         case 0x0f4c:
2519         case 0x1020:
2520         case 0x104c:
2521         case 0x114c:
2522         case 0x1320:
2523         case 0x1420:
2524         case 0x144c:
2525             OMAP_RO_REGV(addr, value);
2526             break;
2527         /* IVA2_CM */
2528         case 0x0000:
2529             s->cm_fclken_iva2 = value & 0x1;
2530             omap3_cm_iva2_update(s);
2531             break;
2532         case 0x0004:
2533             s->cm_clken_pll_iva2 = value & 0x7ff;
2534             omap3_cm_iva2_update(s);
2535             break;
2536         case 0x0034:
2537             s->cm_autoidle_pll_iva2 = value & 0x7;
2538             break;
2539         case 0x0040:
2540             s->cm_clksel1_pll_iva2 = value & 0x3fff7f;
2541             omap3_cm_iva2_update(s);
2542             break;
2543         case 0x0044:
2544             s->cm_clksel2_pll_iva2 = value & 0x1f;
2545             omap3_cm_iva2_update(s);
2546             break;
2547         case 0x0048:
2548             s->cm_clkstctrl_iva2 = value & 0x3;
2549             break;
2550         /* OCP_System_Reg_CM */
2551         case 0x0810:
2552             s->cm_sysconfig = value & 0x1;
2553             break;
2554         /* MPU_CM */
2555         case 0x0904:
2556             s->cm_clken_pll_mpu = value & 0x7ff;
2557             omap3_cm_mpu_update(s);
2558             break;
2559         case 0x0934:
2560             s->cm_autoidle_pll_mpu = value & 0x7;
2561             break;
2562         case 0x0940:
2563             s->cm_clksel1_pll_mpu = value & 0x3fff7f;
2564             omap3_cm_mpu_update(s);
2565             break;
2566         case 0x0944:
2567             s->cm_clksel2_pll_mpu = value & 0x1f;
2568             omap3_cm_mpu_update(s);
2569             break;
2570         case 0x0948:
2571             s->cm_clkstctrl_mpu = value & 0x3;
2572             break;
2573         /* CORE_CM */
2574         case 0xa00:
2575             s->cm_fclken1_core = value & 0x43fffe00;
2576             omap3_cm_fclken1_core_update(s);
2577             break;
2578         case 0xa08:
2579             s->cm_fclken3_core = value & 0x7;
2580             /* TODO: EN_USBTLL, EN_TS */
2581             break;
2582         case 0xa10:
2583             s->cm_iclken1_core = value & 0x637ffed2;
2584             omap3_cm_iclken1_core_update(s);
2585             break;
2586         case 0xa14:
2587             s->cm_iclken2_core = value & 0x1f;
2588             break;
2589         case 0xa18:
2590             s->cm_iclken3_core = value & 0x4;
2591             s->cm_idlest3_core = 0xd & ~(s->cm_iclken3_core & 4);
2592             break;
2593         case 0xa30:
2594             s->cm_autoidle1_core = value & 0x7ffffed0;
2595             break;
2596         case 0xa34:
2597             s->cm_autoidle2_core = value & 0x1f;
2598             break;
2599         case 0xa38:
2600             s->cm_autoidle3_core = value & 0x2;
2601             break;
2602         case 0xa40:
2603             s->cm_clksel_core = (value & 0xff) | 0x100;
2604             omap3_cm_gp10gp11_update(s);
2605             omap_clk_setrate(omap_findclk(s->mpu, "omap3_l3_iclk"),
2606                              s->cm_clksel_core & 0x3, 1);
2607             omap_clk_setrate(omap_findclk(s->mpu, "omap3_l4_iclk"),
2608                              (s->cm_clksel_core >> 2) & 0x3, 1);
2609             break;
2610         case 0xa48:
2611             s->cm_clkstctrl_core = value & 0xf;
2612             break;
2613         /* SGX_CM */
2614         case 0xb00: s->cm_fclken_sgx = value & 0x2; break;
2615         case 0xb10: s->cm_iclken_sgx = value & 0x1; break;
2616         case 0xb40: s->cm_clksel_sgx = value; break; /* TODO: SGX clock */
2617         case 0xb44: s->cm_sleepdep_sgx = value &0x2; break;
2618         case 0xb48: s->cm_clkstctrl_sgx = value & 0x3; break;
2619         /* WKUP_CM */
2620         case 0xc00:
2621             s->cm_fclken_wkup = value & 0x2e9;
2622             omap_clk_onoff(omap_findclk(s->mpu, "omap3_gp1_fclk"),
2623                            s->cm_fclken_wkup & 1);
2624             /* TODO: EN_GPIO1 */
2625             /* TODO: EN_WDT2 */
2626             break;
2627         case 0xc10:
2628             s->cm_iclken_wkup = value & 0x23f;
2629             omap_clk_onoff(omap_findclk(s->mpu, "omap3_wkup_l4_iclk"),
2630                            s->cm_iclken_wkup ? 1 : 0);
2631             break;
2632         case 0xc30: s->cm_autoidle_wkup = value & 0x23f; break;
2633         case 0xc40:
2634             s->cm_clksel_wkup = value & 0x7f;
2635             omap3_cm_clksel_wkup_update(s);
2636             break;
2637         /* Clock_Control_Reg_CM */
2638         case 0xd00:
2639             s->cm_clken_pll = value & 0xffff17ff;
2640             omap3_cm_dpll3_update(s);
2641             omap3_cm_dpll4_update(s);
2642             break;
2643         case 0xd04:
2644             s->cm_clken2_pll = value & 0x7ff;
2645             omap3_cm_dpll5_update(s);
2646             break;
2647         case 0xd30: s->cm_autoidle_pll = value & 0x3f; break;
2648         case 0xd34: s->cm_autoidle2_pll = value & 0x7; break;
2649         case 0xd40:
2650             s->cm_clksel1_pll = value & 0xffffbffc;
2651             omap3_cm_dpll3_update(s);
2652             omap3_cm_48m_update(s);
2653             /* TODO: 96m and 54m update */
2654             break;
2655         case 0xd44:
2656             s->cm_clksel2_pll = value & 0x7ff7f;
2657             omap3_cm_dpll4_update(s);
2658             break;
2659         case 0xd48:
2660             s->cm_clksel3_pll = value & 0x1f;
2661             omap3_cm_dpll4_update(s);
2662             break;
2663         case 0xd4c:
2664             s->cm_clksel4_pll = value & 0x7ff7f;
2665             omap3_cm_dpll5_update(s);
2666             break;
2667         case 0xd50:
2668             s->cm_clksel5_pll = value & 0x1f;
2669             omap3_cm_dpll5_update(s);
2670             break;
2671         case 0xd70:
2672             s->cm_clkout_ctrl = value & 0xbb;
2673             omap3_cm_clkout2_update(s);
2674             break;
2675         /* DSS_CM */
2676         case 0xe00: s->cm_fclken_dss = value & 0x7; break;
2677         case 0xe10: s->cm_iclken_dss = value & 0x1; break;
2678         case 0xe30: s->cm_autoidle_dss = value & 0x1; break;
2679         case 0xe40:
2680             s->cm_clksel_dss = value & 0x1f1f;
2681             omap3_cm_dpll4_update(s);
2682             break;
2683         case 0xe44: s->cm_sleepdep_dss = value & 0x7; break;
2684         case 0xe48: s->cm_clkstctrl_dss = value & 0x3; break;
2685         /* CAM_CM */
2686         case 0xf00: s->cm_fclken_cam = value & 0x3; break;
2687         case 0xf10: s->cm_iclken_cam = value & 0x1; break;
2688         case 0xf30: s->cm_autoidle_cam = value & 0x1; break;
2689         case 0xf40:
2690             s->cm_clksel_cam = value & 0x1f;
2691             omap3_cm_dpll4_update(s);
2692             break;
2693         case 0xf44: s->cm_sleepdep_cam = value & 0x2; break;
2694         case 0xf48: s->cm_clkstctrl_cam = value & 0x3; break;
2695         /* PER_CM */
2696         case 0x1000: s->cm_fclken_per = value & 0x3ffff; break;
2697         case 0x1010: s->cm_iclken_per = value & 0x3ffff; break;
2698         case 0x1030: s->cm_autoidle_per = value &0x3ffff; break;
2699         case 0x1040:
2700             s->cm_clksel_per = value & 0xff;
2701             omap3_cm_per_gptimer_update(s);
2702             break;
2703         case 0x1044: s->cm_sleepdep_per = value & 0x6; break;
2704         case 0x1048: s->cm_clkstctrl_per = value &0x7; break;
2705         /* EMU_CM */
2706         case 0x1140:
2707             s->cm_clksel1_emu = value & 0x1f1f3fff;
2708             omap3_cm_dpll3_update(s);
2709             omap3_cm_dpll4_update(s);
2710             break;
2711         case 0x1148: s->cm_clkstctrl_emu = value & 0x3; break;
2712         case 0x1150:
2713             s->cm_clksel2_emu = value & 0xfff7f;
2714             omap3_cm_dpll3_update(s);
2715             break;
2716         case 0x1154:
2717             s->cm_clksel3_emu = value & 0xfff7f;
2718             omap3_cm_dpll4_update(s);
2719             break;
2720         /* Global_Reg_CM */
2721         case 0x129c: s->cm_polctrl = value & 0x1; break;
2722         /* NEON_CM */
2723         case 0x1348: s->cm_clkstctrl_neon = value & 0x3; break;
2724         /* USBHOST_CM */
2725         case 0x1400: s->cm_fclken_usbhost = value & 0x3; break;
2726         case 0x1410: s->cm_iclken_usbhost = value & 0x1; break;
2727         case 0x1430: s->cm_autoidle_usbhost = value & 0x1; break;
2728         case 0x1444: s->cm_sleepdep_usbhost = value & 0x6; break;
2729         case 0x1448: s->cm_clkstctrl_usbhost = value & 0x3; break;
2730         /* unknown */
2731         default: OMAP_BAD_REGV(addr, value); break;
2732     }
2733 }
2734
2735
2736
2737 static CPUReadMemoryFunc *omap3_cm_readfn[] = {
2738     omap_badwidth_read32,
2739     omap_badwidth_read32,
2740     omap3_cm_read,
2741 };
2742
2743 static CPUWriteMemoryFunc *omap3_cm_writefn[] = {
2744     omap_badwidth_write32,
2745     omap_badwidth_write32,
2746     omap3_cm_write,
2747 };
2748
2749 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
2750                                  qemu_irq mpu_int, qemu_irq dsp_int,
2751                                  qemu_irq iva_int, struct omap_mpu_state_s *mpu)
2752 {
2753     int iomemtype;
2754     struct omap3_cm_s *s = (struct omap3_cm_s *) qemu_mallocz(sizeof(*s));
2755
2756     s->irq[0] = mpu_int;
2757     s->irq[1] = dsp_int;
2758     s->irq[2] = iva_int;
2759     s->mpu = mpu;
2760     omap3_cm_reset(s);
2761
2762     iomemtype = l4_register_io_memory(0, omap3_cm_readfn, omap3_cm_writefn, s);
2763     omap_l4_attach(ta, 0, iomemtype);
2764     omap_l4_attach(ta, 1, iomemtype);
2765
2766     return s;
2767 }
2768
2769 #define OMAP3_SEC_WDT          1
2770 #define OMAP3_MPU_WDT         2
2771 #define OMAP3_IVA2_WDT        3
2772 /*omap3 watchdog timer*/
2773 struct omap3_wdt_s
2774 {
2775     qemu_irq irq;               /*IVA2 IRQ */
2776     struct omap_mpu_state_s *mpu;
2777     omap_clk clk;
2778     QEMUTimer *timer;
2779
2780     int active;
2781     int64_t rate;
2782     int64_t time;
2783     //int64_t ticks_per_sec;
2784
2785     uint32_t wd_sysconfig;
2786     uint32_t wd_sysstatus;
2787     uint32_t wisr;
2788     uint32_t wier;
2789     uint32_t wclr;
2790     uint32_t wcrr;
2791     uint32_t wldr;
2792     uint32_t wtgr;
2793     uint32_t wwps;
2794     uint32_t wspr;
2795
2796     /*pre and ptv in wclr */
2797     uint32_t pre;
2798     uint32_t ptv;
2799     //uint32_t val;
2800
2801     uint16_t writeh;            /* LSB */
2802     uint16_t readh;             /* MSB */
2803 };
2804
2805 static inline void omap3_wdt_timer_update(struct omap3_wdt_s *wdt_timer)
2806 {
2807     int64_t expires;
2808     if (wdt_timer->active) {
2809         expires = muldiv64(0xffffffffll - wdt_timer->wcrr,
2810                            ticks_per_sec, wdt_timer->rate);
2811         qemu_mod_timer(wdt_timer->timer, wdt_timer->time + expires);
2812     } else
2813         qemu_del_timer(wdt_timer->timer);
2814 }
2815
2816 static void omap3_wdt_clk_setup(struct omap3_wdt_s *timer)
2817 {
2818     /*TODO: Add irq as user to clk */
2819 }
2820
2821 static inline uint32_t omap3_wdt_timer_read(struct omap3_wdt_s *timer)
2822 {
2823     uint64_t distance;
2824
2825     if (timer->active) {
2826         distance = qemu_get_clock(vm_clock) - timer->time;
2827         distance = muldiv64(distance, timer->rate, ticks_per_sec);
2828
2829         if (distance >= 0xffffffff - timer->wcrr)
2830             return 0xffffffff;
2831         else
2832             return timer->wcrr + distance;
2833     } else
2834         return timer->wcrr;
2835 }
2836
2837 /*
2838 static inline void omap3_wdt_timer_sync(struct omap3_wdt_s *timer)
2839 {
2840     if (timer->active) {
2841         timer->val = omap3_wdt_timer_read(timer);
2842         timer->time = qemu_get_clock(vm_clock);
2843     }
2844 }*/
2845
2846 static void omap3_wdt_reset(struct omap3_wdt_s *s, int wdt_index)
2847 {
2848     s->wd_sysconfig = 0x0;
2849     s->wd_sysstatus = 0x0;
2850     s->wisr = 0x0;
2851     s->wier = 0x0;
2852     s->wclr = 0x20;
2853     s->wcrr = 0x0;
2854     switch (wdt_index) {
2855         case OMAP3_MPU_WDT:
2856         case OMAP3_IVA2_WDT:
2857             s->wldr = 0xfffb0000;
2858             break;
2859         case OMAP3_SEC_WDT:
2860             s->wldr = 0xffa60000;
2861             break;
2862         default:
2863             break;
2864     }
2865     s->wtgr = 0x0;
2866     s->wwps = 0x0;
2867     s->wspr = 0x0;
2868
2869     switch (wdt_index) {
2870         case OMAP3_SEC_WDT:
2871         case OMAP3_MPU_WDT:
2872             s->active = 1;
2873             break;
2874         case OMAP3_IVA2_WDT:
2875             s->active = 0;
2876             break;
2877         default:
2878             break;
2879     }
2880     s->pre = s->wclr & (1 << 5);
2881     s->ptv = (s->wclr & 0x1c) >> 2;
2882     s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
2883
2884     s->active = 1;
2885     s->time = qemu_get_clock(vm_clock);
2886     omap3_wdt_timer_update(s);
2887 }
2888
2889 static uint32_t omap3_wdt_read32(void *opaque, target_phys_addr_t addr,
2890                                  int wdt_index)
2891 {
2892     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2893
2894     switch (addr) {
2895         case 0x10: return s->wd_sysconfig;
2896         case 0x14: return s->wd_sysstatus;
2897         case 0x18: return s->wisr & 0x1;
2898         case 0x1c: return s->wier & 0x1;
2899         case 0x24: return s->wclr & 0x3c;
2900         case 0x28: /* WCRR */
2901             s->wcrr = omap3_wdt_timer_read(s);
2902             s->time = qemu_get_clock(vm_clock);
2903             return s->wcrr;
2904         case 0x2c: return s->wldr;
2905         case 0x30: return s->wtgr;
2906         case 0x34: return s->wwps;
2907         case 0x48: return s->wspr;
2908         default: break;
2909     }
2910     OMAP_BAD_REG(addr);
2911     return 0;
2912 }
2913
2914 static uint32_t omap3_mpu_wdt_read16(void *opaque, target_phys_addr_t addr)
2915 {
2916     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2917     uint32_t ret;
2918
2919     if (addr & 2)
2920         return s->readh;
2921
2922     ret = omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
2923     s->readh = ret >> 16;
2924     return ret & 0xffff;
2925 }
2926
2927 static uint32_t omap3_mpu_wdt_read32(void *opaque, target_phys_addr_t addr)
2928 {
2929     return omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
2930 }
2931
2932 static void omap3_wdt_write32(void *opaque, target_phys_addr_t addr,
2933                               uint32_t value, int wdt_index)
2934 {
2935     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2936
2937     switch (addr) {
2938     case 0x14: /* WD_SYSSTATUS */
2939     case 0x34: /* WWPS */
2940         OMAP_RO_REGV(addr, value);
2941         break;
2942     case 0x10: /*WD_SYSCONFIG */
2943         s->wd_sysconfig = value & 0x33f;
2944         break;
2945     case 0x18: /* WISR */
2946          s->wisr = value & 0x1;
2947         break;
2948     case 0x1c: /* WIER */
2949         s->wier = value & 0x1;
2950         break;
2951     case 0x24: /* WCLR */
2952         s->wclr = value & 0x3c;
2953         break;
2954     case 0x28: /* WCRR */
2955         s->wcrr = value;
2956         s->time = qemu_get_clock(vm_clock);
2957         omap3_wdt_timer_update(s);
2958         break;
2959     case 0x2c: /* WLDR */
2960         s->wldr = value; /* It will take effect after next overflow */
2961         break;
2962     case 0x30: /* WTGR */
2963         if (value != s->wtgr) {
2964             s->wcrr = s->wldr;
2965             s->pre = s->wclr & (1 << 5);
2966             s->ptv = (s->wclr & 0x1c) >> 2;
2967             s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
2968             s->time = qemu_get_clock(vm_clock);
2969             omap3_wdt_timer_update(s);
2970         }
2971         s->wtgr = value;
2972         break;
2973     case 0x48: /* WSPR */
2974         if (((value & 0xffff) == 0x5555) && ((s->wspr & 0xffff) == 0xaaaa)) {
2975             s->active = 0;
2976             s->wcrr = omap3_wdt_timer_read(s);
2977             omap3_wdt_timer_update(s);
2978         }
2979         if (((value & 0xffff) == 0x4444) && ((s->wspr & 0xffff) == 0xbbbb)) {
2980             s->active = 1;
2981             s->time = qemu_get_clock(vm_clock);
2982             omap3_wdt_timer_update(s);
2983         }
2984         s->wspr = value;
2985         break;
2986     default:
2987         OMAP_BAD_REGV(addr, value);
2988         break;
2989     }
2990 }
2991
2992 static void omap3_mpu_wdt_write16(void *opaque, target_phys_addr_t addr,
2993                                   uint32_t value)
2994 {
2995     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2996
2997     if (addr & 2)
2998         return omap3_wdt_write32(opaque, addr, (value << 16) | s->writeh,
2999                                  OMAP3_MPU_WDT);
3000     else
3001         s->writeh = (uint16_t) value;
3002 }
3003
3004 static void omap3_mpu_wdt_write32(void *opaque, target_phys_addr_t addr,
3005                                   uint32_t value)
3006 {
3007     omap3_wdt_write32(opaque, addr, value, OMAP3_MPU_WDT);
3008 }
3009
3010 static CPUReadMemoryFunc *omap3_mpu_wdt_readfn[] = {
3011     omap_badwidth_read32,
3012     omap3_mpu_wdt_read16,
3013     omap3_mpu_wdt_read32,
3014 };
3015
3016 static CPUWriteMemoryFunc *omap3_mpu_wdt_writefn[] = {
3017     omap_badwidth_write32,
3018     omap3_mpu_wdt_write16,
3019     omap3_mpu_wdt_write32,
3020 };
3021
3022 static void omap3_mpu_wdt_timer_tick(void *opaque)
3023 {
3024     struct omap3_wdt_s *wdt_timer = (struct omap3_wdt_s *) opaque;
3025
3026     /*TODO:Sent reset pulse to PRCM */
3027     wdt_timer->wcrr = wdt_timer->wldr;
3028
3029     /*after overflow, generate the new wdt_timer->rate */
3030     wdt_timer->pre = wdt_timer->wclr & (1 << 5);
3031     wdt_timer->ptv = (wdt_timer->wclr & 0x1c) >> 2;
3032     wdt_timer->rate =
3033         omap_clk_getrate(wdt_timer->clk) >> (wdt_timer->pre ? wdt_timer->
3034                                              ptv : 0);
3035
3036     wdt_timer->time = qemu_get_clock(vm_clock);
3037     omap3_wdt_timer_update(wdt_timer);
3038 }
3039
3040 static struct omap3_wdt_s *omap3_mpu_wdt_init(struct omap_target_agent_s *ta,
3041                                               qemu_irq irq, omap_clk fclk,
3042                                               omap_clk iclk,
3043                                               struct omap_mpu_state_s *mpu)
3044 {
3045     int iomemtype;
3046     struct omap3_wdt_s *s = (struct omap3_wdt_s *) qemu_mallocz(sizeof(*s));
3047
3048     s->irq = irq;
3049     s->clk = fclk;
3050     s->timer = qemu_new_timer(vm_clock, omap3_mpu_wdt_timer_tick, s);
3051
3052     omap3_wdt_reset(s, OMAP3_MPU_WDT);
3053     if (irq != NULL)
3054         omap3_wdt_clk_setup(s);
3055
3056     iomemtype = l4_register_io_memory(0, omap3_mpu_wdt_readfn,
3057                                       omap3_mpu_wdt_writefn, s);
3058     omap_l4_attach(ta, 0, iomemtype);
3059
3060     return s;
3061
3062 }
3063
3064 struct omap3_scm_s {
3065     struct omap_mpu_state_s *mpu;
3066
3067         uint8 interface[48];     /*0x4800 2000*/
3068         uint8 padconfs[576];     /*0x4800 2030*/
3069         uint32 general[228];     /*0x4800 2270*/
3070         uint8 mem_wkup[1024];    /*0x4800 2600*/
3071         uint8 padconfs_wkup[84]; /*0x4800 2a00*/
3072         uint32 general_wkup[8];  /*0x4800 2a60*/
3073 };
3074
3075 #define PADCONFS_VALUE(wakeup0,wakeup1,offmode0,offmode1, \
3076                                                 inputenable0,inputenable1,pupd0,pupd1,muxmode0,muxmode1,offset) \
3077         do { \
3078                  *(padconfs+offset/4) = (wakeup0 <<14)|(offmode0<<9)|(inputenable0<<8)|(pupd0<<3)|(muxmode0); \
3079                  *(padconfs+offset/4) |= (wakeup1 <<30)|(offmode1<<25)|(inputenable1<<24)|(pupd1<<19)|(muxmode1<<16); \
3080 } while (0)
3081
3082
3083 static void omap3_scm_reset(struct omap3_scm_s *s)
3084 {
3085     uint32 * padconfs;
3086     padconfs = (uint32 *)(s->padconfs);
3087     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x0);
3088     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
3089     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x8);
3090     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
3091     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
3092     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
3093     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x18);
3094     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x1c);
3095     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x20);
3096     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x24);
3097     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x28);
3098     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x2c);
3099     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x30);
3100     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x34);
3101     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x38);
3102     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x3c);
3103     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x40);
3104     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x44);
3105     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,7,0x48);
3106     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x4c);
3107     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x50);
3108     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x54);
3109     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x58);
3110     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,0,0x5c);
3111     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x60);
3112     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x64);
3113     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x68);
3114     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x6c);
3115     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x70);
3116     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x74);
3117     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x78);
3118     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x7c);
3119     PADCONFS_VALUE(0,0,0,0,1,1,0,3,0,7,0x80);
3120     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x84);
3121     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x88);
3122     PADCONFS_VALUE(0,0,0,0,1,1,3,0,7,0,0x8c);
3123     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x90);
3124     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x94);
3125     PADCONFS_VALUE(0,0,0,0,1,1,1,0,7,0,0x98);
3126     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,7,0x9c);
3127     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa0);
3128     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa4);
3129     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0xa8);
3130     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xac);
3131     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb0);
3132     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb4);
3133     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb8);
3134     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xbc);
3135     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc0);
3136     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc4);
3137     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc8);
3138     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xcc);
3139     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd0);
3140     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd4);
3141     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd8);
3142     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xdc);
3143     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe0);
3144     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe4);
3145     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe8);
3146     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xec);
3147     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf0);
3148     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf4);
3149     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf8);
3150     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xfc);
3151     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x100);
3152     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x104);
3153     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x108);
3154     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x10c);
3155     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x110);
3156     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x114);
3157     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x118);
3158     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x11c);
3159     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x120);
3160     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x124);
3161     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x128);
3162     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x12c);
3163     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x130);
3164     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x134);
3165     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x138);
3166     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x13c);
3167     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x140);
3168     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x144);
3169     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x148);
3170     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x14c);
3171     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x150);
3172     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x154);
3173     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x158);
3174     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x15c);
3175     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x160);
3176     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x164);
3177     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x168);
3178     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x16c);
3179     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x170);
3180     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x174);
3181     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x178);
3182     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x17c);
3183     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x180);
3184     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x184);
3185     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x188);
3186     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x18c);
3187     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x190);
3188     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x194);
3189     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x198);
3190     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x19c);
3191     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x1a0);
3192     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1a4);
3193     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x1a8);
3194     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1ac);
3195     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1b0);
3196     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b4);
3197     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b8);
3198     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1bc);
3199     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c0);
3200     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c4);
3201     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c8);
3202     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1cc);
3203     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d0);
3204     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d4);
3205     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d8);
3206     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1dc);
3207     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e0);
3208     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e4);
3209     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e8);
3210     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1ec);
3211     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f0);
3212     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f4);
3213     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f8);
3214     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1fc);
3215     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x200);
3216     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x204);
3217     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x208);
3218     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x20c);
3219     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x210);
3220     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x214);
3221     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x218);
3222     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x21c);
3223     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x220);
3224     PADCONFS_VALUE(0,0,0,0,1,1,3,1,0,0,0x224);
3225     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x228);
3226     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x22c);
3227     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x230);
3228     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x234);
3229
3230         padconfs = (uint32 *)(s->general);
3231     memset(s->general, 0, sizeof(s->general));
3232         s->general[0x01] = 0x4000000;  /* CONTROL_DEVCONF_0 */
3233         s->general[0x1c] = 0x1;        /* 0x480022e0?? */
3234     s->general[0x20] = 0x30f;      /* CONTROL_STATUS:
3235                                     * - device type  = GP Device
3236                                     * - sys_boot:6   = oscillator bypass mode
3237                                     * - sys_boot:0-5 = NAND, USB, UART3, MMC1*/
3238         s->general[0x75] = 0x7fc0;     /* CONTROL_PROG_IO0 */
3239         s->general[0x76] = 0xaa;       /* CONTROL_PROG_IO1 */
3240         s->general[0x7c] = 0x2700;     /* CONTROL_SDRC_SHARING */
3241         s->general[0x7d] = 0x300000;   /* CONTROL_SDRC_MCFG0 */
3242         s->general[0x7e] = 0x300000;   /* CONTROL_SDRC_MCFG1 */
3243         s->general[0x81] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_REQ_INFO */
3244         s->general[0x82] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_RD */
3245         s->general[0x83] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_WR */
3246         s->general[0x84] = 0x6;        /* CONTROL_MODEM_GPMC_BOOT_CODE */
3247         s->general[0x85] = 0xffffffff; /* CONTROL_MODEM_SMS_RG_ATT1 */
3248         s->general[0x86] = 0xffff;     /* CONTROL_MODEM_SMS_RG_RDPERM1 */
3249         s->general[0x87] = 0xffff;     /* CONTROL_MODEM_SMS_RG_WRPERM1 */
3250         s->general[0x88] = 0x1;        /* CONTROL_MODEM_D2D_FW_DEBUG_MODE */
3251         s->general[0x8b] = 0xffffffff; /* CONTROL_DPF_OCM_RAM_FW_REQINFO */
3252         s->general[0x8c] = 0xffff;     /* CONTROL_DPF_OCM_RAM_FW_WR */
3253         s->general[0x8e] = 0xffff;     /* CONTROL_DPF_REGION4_GPMC_FW_REQINFO */
3254         s->general[0x8f] = 0xffff;     /* CONTROL_DPF_REGION4_GPMC_FW_WR */
3255         s->general[0x91] = 0xffff;     /* CONTROL_DPF_REGION1_IVA2_FW_REQINFO */
3256         s->general[0x92] = 0xffff;     /* CONTROL_DPF_REGION1_IVA2_FW_WR */
3257         s->general[0xac] = 0x109;      /* CONTROL_PBIAS_LITE */
3258         s->general[0xb2] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_ADDR_MATCH */
3259         s->general[0xb3] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_REQINFO */
3260         s->general[0xb4] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_WR */
3261         PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x368); /* PADCONF_ETK_CLK */
3262     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x36c); /* PADCONF_ETK_D0 */
3263     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x370); /* PADCONF_ETK_D2 */
3264     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x374); /* PADCONF_ETK_D4 */
3265     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x378); /* PADCONF_ETK_D6 */
3266     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x37c); /* PADCONF_ETK_D8 */
3267     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x380); /* PADCONF_ETK_D10 */
3268     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x384); /* PADCONF_ETK_D12 */
3269     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x388); /* PADCONF_ETK_D14 */
3270
3271         padconfs = (uint32 *)(s->padconfs_wkup);
3272         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x0);
3273         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
3274         PADCONFS_VALUE(0,0,0,0,1,1,3,0,0,0,0x8);
3275         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
3276         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
3277         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
3278         PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x18);
3279         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c);
3280         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x20);
3281         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x24);
3282         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x2c);
3283
3284         s->general_wkup[0] = 0x66ff; /* 0x48002A60?? */
3285 }
3286
3287 static uint32_t omap3_scm_read8(void *opaque, target_phys_addr_t addr)
3288 {
3289     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3290     uint8_t* temp;
3291
3292     switch (addr) {
3293         case 0x000 ... 0x02f: return s->interface[addr];
3294         case 0x030 ... 0x26f: return s->padconfs[addr - 0x30];
3295         case 0x270 ... 0x5ff: temp = (uint8_t *)s->general; return temp[addr - 0x270];
3296         case 0x600 ... 0x9ff: return s->mem_wkup[addr - 0x600];
3297         case 0xa00 ... 0xa5f: return s->padconfs_wkup[addr - 0xa00];
3298         case 0xa60 ... 0xa7f: temp = (uint8_t *)s->general_wkup; return temp[addr - 0xa60];
3299         default: break;
3300     }
3301     OMAP_BAD_REG(addr);
3302     return 0;
3303 }
3304
3305 static uint32_t omap3_scm_read16(void *opaque, target_phys_addr_t addr)
3306 {
3307     uint32_t v;
3308     v = omap3_scm_read8(opaque, addr);
3309     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3310     return v;
3311 }
3312
3313 static uint32_t omap3_scm_read32(void *opaque, target_phys_addr_t addr)
3314 {
3315     uint32_t v;
3316     v = omap3_scm_read8(opaque, addr);
3317     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3318     v |= omap3_scm_read8(opaque, addr + 2) << 16;
3319     v |= omap3_scm_read8(opaque, addr + 3) << 24;
3320     return v;
3321 }
3322
3323 static void omap3_scm_write8(void *opaque, target_phys_addr_t addr,
3324                              uint32_t value)
3325 {
3326     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3327     uint8_t* temp;
3328
3329     switch (addr) {
3330         case 0x000 ... 0x02f: s->interface[addr] = value; break;
3331         case 0x030 ... 0x26f: s->padconfs[addr-0x30] = value; break;
3332         case 0x270 ... 0x5ff: temp = (uint8_t *)s->general; temp[addr-0x270] = value; break;
3333         case 0x600 ... 0x9ff: s->mem_wkup[addr-0x600] = value; break;
3334         case 0xa00 ... 0xa5f: s->padconfs_wkup[addr-0xa00] = value; break;
3335         case 0xa60 ... 0xa7f: temp = (uint8_t *)s->general_wkup; temp[addr-0xa60] = value; break;
3336         default: OMAP_BAD_REGV(addr, value); break;
3337     }
3338 }
3339
3340 static void omap3_scm_write16(void *opaque, target_phys_addr_t addr,
3341                               uint32_t value)
3342 {
3343     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
3344     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3345 }
3346
3347 static void omap3_scm_write32(void *opaque, target_phys_addr_t addr,
3348                               uint32_t value)
3349 {
3350     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
3351     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3352     omap3_scm_write8(opaque, addr + 2, (value >> 16) & 0xff);
3353     omap3_scm_write8(opaque, addr + 3, (value >> 24) & 0xff);
3354 }
3355
3356 static CPUReadMemoryFunc *omap3_scm_readfn[] = {
3357     omap3_scm_read8,
3358     omap3_scm_read16,
3359     omap3_scm_read32,
3360 };
3361
3362 static CPUWriteMemoryFunc *omap3_scm_writefn[] = {
3363     omap3_scm_write8,
3364     omap3_scm_write16,
3365     omap3_scm_write32,
3366 };
3367
3368 static struct omap3_scm_s *omap3_scm_init(struct omap_target_agent_s *ta,
3369                                           struct omap_mpu_state_s *mpu)
3370 {
3371     int iomemtype;
3372     struct omap3_scm_s *s = (struct omap3_scm_s *) qemu_mallocz(sizeof(*s));
3373
3374     s->mpu = mpu;
3375
3376     omap3_scm_reset(s);
3377
3378     iomemtype = l4_register_io_memory(0, omap3_scm_readfn,
3379                                       omap3_scm_writefn, s);
3380     omap_l4_attach(ta, 0, iomemtype);
3381
3382     return s;
3383 }
3384
3385 /*dummy SDRAM Memory Scheduler emulation*/
3386 struct omap3_sms_s
3387 {
3388     struct omap_mpu_state_s *mpu;
3389
3390     uint32 sms_sysconfig;
3391     uint32 sms_sysstatus;
3392     uint32 sms_rg_att[8];
3393     uint32 sms_rg_rdperm[8];
3394     uint32 sms_rg_wrperm[8];
3395     uint32 sms_rg_start[7];
3396     uint32 sms_rg_end[7];
3397     uint32 sms_security_control;
3398     uint32 sms_class_arbiter0;
3399     uint32 sms_class_arbiter1;
3400     uint32 sms_class_arbiter2;
3401     uint32 sms_interclass_arbiter;
3402     uint32 sms_class_rotation[3];
3403     uint32 sms_err_addr;
3404     uint32 sms_err_type;
3405     uint32 sms_pow_ctrl;
3406     uint32 sms_rot_control[12];
3407     uint32 sms_rot_size[12];
3408     uint32 sms_rot_physical_ba[12];
3409 };
3410
3411 static uint32_t omap3_sms_read32(void *opaque, target_phys_addr_t addr)
3412 {
3413     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
3414
3415     switch (addr)
3416     {
3417     case 0x10:
3418         return s->sms_sysconfig;
3419     case 0x14:
3420         return s->sms_sysstatus;
3421     case 0x48:
3422     case 0x68:
3423     case 0x88:
3424     case 0xa8:
3425     case 0xc8:
3426     case 0xe8:
3427     case 0x108:
3428     case 0x128:
3429         return s->sms_rg_att[(addr-0x48)/0x20];
3430     case 0x50:
3431     case 0x70:
3432     case 0x90:
3433     case 0xb0:
3434     case 0xd0:
3435     case 0xf0:
3436     case 0x110:
3437     case 0x130:
3438         return s->sms_rg_rdperm[(addr-0x50)/0x20];
3439     case 0x58:
3440     case 0x78:
3441     case 0x98:
3442     case 0xb8:
3443     case 0xd8:
3444     case 0xf8:
3445     case 0x118:
3446         return s->sms_rg_wrperm[(addr-0x58)/0x20];
3447     case 0x60:
3448     case 0x80:
3449     case 0xa0:
3450     case 0xc0:
3451     case 0xe0:
3452     case 0x100:
3453     case 0x120:
3454         return s->sms_rg_start[(addr-0x60)/0x20];
3455
3456     case 0x64:
3457     case 0x84:
3458     case 0xa4:
3459     case 0xc4:
3460     case 0xe4:
3461     case 0x104:
3462     case 0x124:
3463         return s->sms_rg_end[(addr-0x64)/0x20];
3464     case 0x140:
3465         return s->sms_security_control;
3466     case 0x150:
3467         return s->sms_class_arbiter0;
3468         case 0x154:
3469                 return s->sms_class_arbiter1;
3470         case 0x158:
3471                 return s->sms_class_arbiter2;
3472         case 0x160:
3473                 return s->sms_interclass_arbiter;
3474         case 0x164:
3475         case 0x168:
3476         case 0x16c:
3477                 return s->sms_class_rotation[(addr-0x164)/4];
3478         case 0x170:
3479                 return s->sms_err_addr;
3480         case 0x174:
3481                 return s->sms_err_type;
3482         case 0x178:
3483                 return s->sms_pow_ctrl;
3484         case 0x180:
3485         case 0x190:
3486         case 0x1a0:
3487         case 0x1b0:
3488         case 0x1c0:
3489         case 0x1d0:
3490         case 0x1e0:
3491         case 0x1f0:
3492         case 0x200:
3493         case 0x210:
3494         case 0x220:
3495         case 0x230:
3496                 return s->sms_rot_control[(addr-0x180)/0x10];
3497         case 0x184:
3498         case 0x194:
3499         case 0x1a4:
3500         case 0x1b4:
3501         case 0x1c4:
3502         case 0x1d4:
3503         case 0x1e4:
3504         case 0x1f4:
3505         case 0x204:
3506         case 0x214:
3507         case 0x224:
3508         case 0x234:
3509                 return s->sms_rot_size[(addr-0x184)/0x10];
3510
3511         case 0x188:
3512         case 0x198:
3513         case 0x1a8:
3514         case 0x1b8:
3515         case 0x1c8:
3516         case 0x1d8:
3517         case 0x1e8:
3518         case 0x1f8:
3519         case 0x208:
3520         case 0x218:
3521         case 0x228:
3522         case 0x238:
3523                 return s->sms_rot_size[(addr-0x188)/0x10];
3524
3525     default:
3526         break;
3527     }
3528     OMAP_BAD_REG(addr);
3529     return 0;
3530 }
3531
3532 static void omap3_sms_write32(void *opaque, target_phys_addr_t addr,
3533                               uint32_t value)
3534 {
3535     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
3536     //int i;
3537
3538     switch (addr)
3539     {
3540     case 0x14:
3541         OMAP_RO_REG(addr);
3542         return;
3543     case 0x10:
3544         s->sms_sysconfig = value & 0x1f;
3545         break;
3546
3547     case 0x48:
3548     case 0x68:
3549     case 0x88:
3550     case 0xa8:
3551     case 0xc8:
3552     case 0xe8:
3553     case 0x108:
3554     case 0x128:
3555         s->sms_rg_att[(addr-0x48)/0x20] = value;
3556         break;
3557     case 0x50:
3558     case 0x70:
3559     case 0x90:
3560     case 0xb0:
3561     case 0xd0:
3562     case 0xf0:
3563     case 0x110:
3564     case 0x130:
3565         s->sms_rg_rdperm[(addr-0x50)/0x20] = value&0xffff;
3566         break;
3567     case 0x58:
3568     case 0x78:
3569     case 0x98:
3570     case 0xb8:
3571     case 0xd8:
3572     case 0xf8:
3573     case 0x118:
3574         s->sms_rg_wrperm[(addr-0x58)/0x20] = value&0xffff;
3575         break;
3576     case 0x60:
3577     case 0x80:
3578     case 0xa0:
3579     case 0xc0:
3580     case 0xe0:
3581     case 0x100:
3582     case 0x120:
3583         s->sms_rg_start[(addr-0x60)/0x20] = value;
3584         break;
3585     case 0x64:
3586     case 0x84:
3587     case 0xa4:
3588     case 0xc4:
3589     case 0xe4:
3590     case 0x104:
3591     case 0x124:
3592         s->sms_rg_end[(addr-0x64)/0x20] = value;
3593         break;
3594     case 0x140:
3595         s->sms_security_control = value &0xfffffff;
3596         break;
3597     case 0x150:
3598         s->sms_class_arbiter0 = value;
3599         break;
3600         case 0x154:
3601                 s->sms_class_arbiter1 = value;
3602                 break;
3603         case 0x158:
3604                 s->sms_class_arbiter2 = value;
3605                 break;
3606         case 0x160:
3607                 s->sms_interclass_arbiter = value;
3608                 break;
3609         case 0x164:
3610         case 0x168:
3611         case 0x16c:
3612                 s->sms_class_rotation[(addr-0x164)/4] = value;
3613                 break;
3614         case 0x170:
3615                 s->sms_err_addr = value;
3616                 break;
3617         case 0x174:
3618                 s->sms_err_type = value;
3619                 break;
3620         case 0x178:
3621                 s->sms_pow_ctrl = value;
3622                 break;
3623         case 0x180:
3624         case 0x190:
3625         case 0x1a0:
3626         case 0x1b0:
3627         case 0x1c0:
3628         case 0x1d0:
3629         case 0x1e0:
3630         case 0x1f0:
3631         case 0x200:
3632         case 0x210:
3633         case 0x220:
3634         case 0x230:
3635                 s->sms_rot_control[(addr-0x180)/0x10] = value;
3636                 break;
3637         case 0x184:
3638         case 0x194:
3639         case 0x1a4:
3640         case 0x1b4:
3641         case 0x1c4:
3642         case 0x1d4:
3643         case 0x1e4:
3644         case 0x1f4:
3645         case 0x204:
3646         case 0x214:
3647         case 0x224:
3648         case 0x234:
3649                 s->sms_rot_size[(addr-0x184)/0x10] = value;
3650                 break;
3651
3652         case 0x188:
3653         case 0x198:
3654         case 0x1a8:
3655         case 0x1b8:
3656         case 0x1c8:
3657         case 0x1d8:
3658         case 0x1e8:
3659         case 0x1f8:
3660         case 0x208:
3661         case 0x218:
3662         case 0x228:
3663         case 0x238:
3664                 s->sms_rot_size[(addr-0x188)/0x10] = value;
3665                 break;
3666         default:
3667         OMAP_BAD_REGV(addr, value);
3668         break;
3669     }
3670 }
3671
3672 static CPUReadMemoryFunc *omap3_sms_readfn[] = {
3673     omap_badwidth_read32,
3674     omap_badwidth_read32,
3675     omap3_sms_read32,
3676 };
3677
3678 static CPUWriteMemoryFunc *omap3_sms_writefn[] = {
3679     omap_badwidth_write32,
3680     omap_badwidth_write32,
3681     omap3_sms_write32,
3682 };
3683
3684 static void omap3_sms_reset(struct omap3_sms_s *s)
3685 {
3686         s->sms_sysconfig = 0x1;
3687         s->sms_class_arbiter0 = 0x500000;
3688         s->sms_class_arbiter1 = 0x500;
3689         s->sms_class_arbiter2 = 0x55000;
3690         s->sms_interclass_arbiter = 0x400040;
3691         s->sms_class_rotation[0] = 0x1;
3692         s->sms_class_rotation[1] = 0x1;
3693         s->sms_class_rotation[2] = 0x1;
3694         s->sms_pow_ctrl = 0x80;
3695 }
3696
3697 static struct omap3_sms_s *omap3_sms_init(struct omap_mpu_state_s *mpu)
3698 {
3699     int iomemtype;
3700     struct omap3_sms_s *s = (struct omap3_sms_s *) qemu_mallocz(sizeof(*s));
3701
3702     s->mpu = mpu;
3703
3704     omap3_sms_reset(s);
3705
3706     iomemtype = cpu_register_io_memory(0, omap3_sms_readfn,
3707                                        omap3_sms_writefn, s);
3708     cpu_register_physical_memory(0x6c000000, 0x10000, iomemtype);
3709
3710     return s;
3711 }
3712
3713 #define OMAP3_BOOT_ROM_SIZE 0x1c000 /* 80 + 32 kB */
3714
3715 static const struct dma_irq_map omap3_dma_irq_map[] = {
3716     {0, OMAP_INT_3XXX_SDMA_IRQ0},
3717     {0, OMAP_INT_3XXX_SDMA_IRQ1},
3718     {0, OMAP_INT_3XXX_SDMA_IRQ2},
3719     {0, OMAP_INT_3XXX_SDMA_IRQ3},
3720 };
3721
3722 static int omap3_validate_addr(struct omap_mpu_state_s *s,
3723                                target_phys_addr_t addr)
3724 {
3725     return 1;
3726 }
3727
3728 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
3729                                            const char *core)
3730 {
3731     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
3732         qemu_mallocz(sizeof(struct omap_mpu_state_s));
3733     ram_addr_t sram_base, q2_base, bootrom_base;
3734     qemu_irq *cpu_irq;
3735     qemu_irq dma_irqs[4];
3736     int i;
3737
3738     s->mpu_model = omap3530;
3739     s->env = cpu_init("cortex-a8-r2");
3740     if (!s->env) {
3741         fprintf(stderr, "Unable to find CPU definition\n");
3742         exit(1);
3743     }
3744     s->sdram_size = sdram_size;
3745     s->sram_size = OMAP3XXX_SRAM_SIZE;
3746
3747     /* Clocks */
3748     omap_clk_init(s);
3749
3750     /* Memory-mapped stuff */
3751
3752     q2_base = qemu_ram_alloc(s->sdram_size);
3753     cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,
3754                                  q2_base | IO_MEM_RAM);
3755     sram_base = qemu_ram_alloc(s->sram_size);
3756     cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,
3757                                  sram_base | IO_MEM_RAM);
3758     bootrom_base = qemu_ram_alloc(OMAP3XXX_BOOTROM_SIZE);
3759     cpu_register_physical_memory(OMAP3_Q1_BASE + 0x14000, OMAP3_BOOT_ROM_SIZE,
3760                                  bootrom_base | IO_MEM_ROM);
3761     cpu_register_physical_memory(0, OMAP3_BOOT_ROM_SIZE,
3762                                  bootrom_base | IO_MEM_ROM);
3763
3764     s->l4 = omap_l4_init(OMAP3_L4_BASE,
3765                          sizeof(omap3_l4_agent_info)
3766                          / sizeof(struct omap3_l4_agent_info_s));
3767
3768     cpu_irq = arm_pic_init_cpu(s->env);
3769     s->ih[0] = omap2_inth_init(s, 0x48200000, 0x1000, 3, &s->irq[0],
3770                                cpu_irq[ARM_PIC_CPU_IRQ],
3771                                cpu_irq[ARM_PIC_CPU_FIQ],
3772                                omap_findclk(s, "omap3_mpu_intc_fclk"),
3773                                omap_findclk(s, "omap3_mpu_intc_iclk"));
3774
3775     for (i = 0; i < 4; i++)
3776         dma_irqs[i] =
3777             s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];
3778     s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
3779                             omap_findclk(s, "omap3_sdma_fclk"),
3780                             omap_findclk(s, "omap3_sdma_iclk"));
3781     s->port->addr_valid = omap3_validate_addr;
3782
3783     /* Register SDRAM and SRAM ports for fast DMA transfers.  */
3784     soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
3785     soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
3786
3787
3788     s->omap3_cm = omap3_cm_init(omap3_l4ta_init(s->l4, L4A_CM), NULL, NULL, NULL, s);
3789
3790     s->omap3_prm = omap3_prm_init(omap3_l4ta_init(s->l4, L4A_PRM),
3791                                   s->irq[0][OMAP_INT_3XXX_PRCM_MPU_IRQ],
3792                                   NULL, s);
3793
3794     s->omap3_mpu_wdt = omap3_mpu_wdt_init(omap3_l4ta_init(s->l4, L4A_WDTIMER2),
3795                                           NULL,
3796                                           omap_findclk(s, "omap3_wkup_32k_fclk"),
3797                                           omap_findclk(s, "omap3_wkup_l4_iclk"),
3798                                           s);
3799
3800     s->omap3_l3 = omap3_l3_init(OMAP3_L3_BASE,
3801                                 omap3_l3_region,
3802                                 sizeof(omap3_l3_region)
3803                                 / sizeof(struct omap_l3_region_s));
3804     s->omap3_scm = omap3_scm_init(omap3_l4ta_init(s->l4, L4A_SCM), s);
3805
3806     s->omap3_sms = omap3_sms_init(s);
3807
3808     s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER1),
3809                                        s->irq[0][OMAP_INT_3XXX_GPT1_IRQ],
3810                                        omap_findclk(s, "omap3_gp1_fclk"),
3811                                        omap_findclk(s, "omap3_wkup_l4_iclk"));
3812     s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER2),
3813                                        s->irq[0][OMAP_INT_3XXX_GPT2_IRQ],
3814                                        omap_findclk(s, "omap3_gp2_fclk"),
3815                                        omap_findclk(s, "omap3_per_l4_iclk"));
3816     s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER3),
3817                                        s->irq[0][OMAP_INT_3XXX_GPT3_IRQ],
3818                                        omap_findclk(s, "omap3_gp3_fclk"),
3819                                        omap_findclk(s, "omap3_per_l4_iclk"));
3820     s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER4),
3821                                        s->irq[0][OMAP_INT_3XXX_GPT4_IRQ],
3822                                        omap_findclk(s, "omap3_gp4_fclk"),
3823                                        omap_findclk(s, "omap3_per_l4_iclk"));
3824     s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER5),
3825                                        s->irq[0][OMAP_INT_3XXX_GPT5_IRQ],
3826                                        omap_findclk(s, "omap3_gp5_fclk"),
3827                                        omap_findclk(s, "omap3_per_l4_iclk"));
3828     s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER6),
3829                                        s->irq[0][OMAP_INT_3XXX_GPT6_IRQ],
3830                                        omap_findclk(s, "omap3_gp6_fclk"),
3831                                        omap_findclk(s, "omap3_per_l4_iclk"));
3832     s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER7),
3833                                        s->irq[0][OMAP_INT_3XXX_GPT7_IRQ],
3834                                        omap_findclk(s, "omap3_gp7_fclk"),
3835                                        omap_findclk(s, "omap3_per_l4_iclk"));
3836     s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER8),
3837                                        s->irq[0][OMAP_INT_3XXX_GPT8_IRQ],
3838                                        omap_findclk(s, "omap3_gp8_fclk"),
3839                                        omap_findclk(s, "omap3_per_l4_iclk"));
3840     s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER9),
3841                                        s->irq[0][OMAP_INT_3XXX_GPT9_IRQ],
3842                                        omap_findclk(s, "omap3_gp9_fclk"),
3843                                        omap_findclk(s, "omap3_per_l4_iclk"));
3844     s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER10),
3845                                        s->irq[0][OMAP_INT_3XXX_GPT10_IRQ],
3846                                        omap_findclk(s, "omap3_gp10_fclk"),
3847                                        omap_findclk(s, "omap3_core_l4_iclk"));
3848     s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER11),
3849                                        s->irq[0][OMAP_INT_3XXX_GPT11_IRQ],
3850                                        omap_findclk(s, "omap3_gp12_fclk"),
3851                                        omap_findclk(s, "omap3_core_l4_iclk"));
3852     s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER12),
3853                                         s->irq[0][OMAP_INT_3XXX_GPT12_IRQ],
3854                                         omap_findclk(s, "omap3_gp12_fclk"),
3855                                         omap_findclk(s, "omap3_wkup_l4_iclk"));
3856
3857
3858     omap_synctimer_init(omap3_l4ta_init(s->l4, L4A_32KTIMER), s,
3859                         omap_findclk(s, "omap3_sys_32k"), NULL);
3860
3861     s->sdrc = omap_sdrc_init(0x6d000000);
3862
3863     s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_3XXX_GPMC_IRQ]);
3864
3865
3866     s->uart[0] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART1),
3867                                  s->irq[0][OMAP_INT_3XXX_UART1_IRQ],
3868                                  omap_findclk(s, "omap3_uart1_fclk"),
3869                                  omap_findclk(s, "omap3_uart1_iclk"),
3870                                  s->drq[OMAP3XXX_DMA_UART1_TX],
3871                                  s->drq[OMAP3XXX_DMA_UART1_RX], 0);
3872     s->uart[1] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART2),
3873                                  s->irq[0][OMAP_INT_3XXX_UART2_IRQ],
3874                                  omap_findclk(s, "omap3_uart2_fclk"),
3875                                  omap_findclk(s, "omap3_uart2_iclk"),
3876                                  s->drq[OMAP3XXX_DMA_UART2_TX],
3877                                  s->drq[OMAP3XXX_DMA_UART2_RX], 0);
3878     s->uart[2] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART3),
3879                                  s->irq[0][OMAP_INT_3XXX_UART3_IRQ],
3880                                  omap_findclk(s, "omap3_uart2_fclk"),
3881                                  omap_findclk(s, "omap3_uart3_iclk"),
3882                                  s->drq[OMAP3XXX_DMA_UART3_TX],
3883                                  s->drq[OMAP3XXX_DMA_UART3_RX], 0);
3884
3885     s->dss = omap_dss_init(s, omap3_l4ta_init(s->l4, L4A_DSS),
3886                     s->irq[0][OMAP_INT_3XXX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
3887                    NULL,NULL,NULL,NULL,NULL);
3888
3889     s->gpif = omap3_gpif_init();
3890     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO1),
3891                     &s->irq[0][OMAP_INT_3XXX_GPIO1_MPU_IRQ],
3892                     NULL,NULL,0);
3893     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO2),
3894                     &s->irq[0][OMAP_INT_3XXX_GPIO2_MPU_IRQ],
3895                     NULL,NULL,1);
3896     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO3),
3897                     &s->irq[0][OMAP_INT_3XXX_GPIO3_MPU_IRQ],
3898                     NULL,NULL,2);
3899     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO4),
3900                     &s->irq[0][OMAP_INT_3XXX_GPIO4_MPU_IRQ],
3901                     NULL,NULL,3);
3902     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO5),
3903                     &s->irq[0][OMAP_INT_3XXX_GPIO5_MPU_IRQ],
3904                     NULL,NULL,4);
3905     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO6),
3906                     &s->irq[0][OMAP_INT_3XXX_GPIO6_MPU_IRQ],
3907                     NULL,NULL,5);
3908
3909     omap_tap_init(omap3_l4ta_init(s->l4, L4A_TAP), s);
3910
3911     s->omap3_mmc[0] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC1),
3912                                      s->irq[0][OMAP_INT_3XXX_MMC1_IRQ],
3913                                      &s->drq[OMAP3XXX_DMA_MMC1_TX],
3914                                      omap_findclk(s, "omap3_mmc1_fclk"),
3915                                      omap_findclk(s, "omap3_mmc1_iclk"));
3916
3917     s->omap3_mmc[1] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC2),
3918                                      s->irq[0][OMAP_INT_3XXX_MMC2_IRQ],
3919                                      &s->drq[OMAP3XXX_DMA_MMC2_TX],
3920                                      omap_findclk(s, "omap3_mmc2_fclk"),
3921                                      omap_findclk(s, "omap3_mmc2_iclk"));
3922
3923     s->omap3_mmc[2] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC3),
3924                                      s->irq[0][OMAP_INT_3XXX_MMC3_IRQ],
3925                                      &s->drq[OMAP3XXX_DMA_MMC3_TX],
3926                                      omap_findclk(s, "omap3_mmc3_fclk"),
3927                                      omap_findclk(s, "omap3_mmc3_iclk"));
3928
3929     s->i2c[0] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C1),
3930                                s->irq[0][OMAP_INT_3XXX_I2C1_IRQ],
3931                                &s->drq[OMAP3XXX_DMA_I2C1_TX],
3932                                omap_findclk(s, "omap3_i2c1_fclk"),
3933                                omap_findclk(s, "omap3_i2c1_iclk"),
3934                                8);
3935     s->i2c[1] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C2),
3936                                s->irq[0][OMAP_INT_3XXX_I2C2_IRQ],
3937                                &s->drq[OMAP3XXX_DMA_I2C2_TX],
3938                                omap_findclk(s, "omap3_i2c2_fclk"),
3939                                omap_findclk(s, "omap3_i2c2_iclk"),
3940                                8);
3941     s->i2c[2] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C3),
3942                                s->irq[0][OMAP_INT_3XXX_I2C3_IRQ],
3943                                &s->drq[OMAP3XXX_DMA_I2C3_TX],
3944                                omap_findclk(s, "omap3_i2c3_fclk"),
3945                                omap_findclk(s, "omap3_i2c3_iclk"),
3946                                64);
3947
3948     s->omap3_usb = omap3_hsusb_init(omap3_l4ta_init(s->l4, L4A_USBHS_OTG),
3949                                     omap3_l4ta_init(s->l4, L4A_USBHS_HOST),
3950                                     omap3_l4ta_init(s->l4, L4A_USBHS_TLL),
3951                                     s->irq[0][OMAP_INT_3XXX_HSUSB_MC],
3952                                     s->irq[0][OMAP_INT_3XXX_HSUSB_DMA],
3953                                     s->irq[0][OMAP_INT_3XXX_OHCI_IRQ],
3954                                     s->irq[0][OMAP_INT_3XXX_EHCI_IRQ],
3955                                     s->irq[0][OMAP_INT_3XXX_TLL_IRQ]);
3956     return s;
3957 }