2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
26 //#define PPC_DUMP_CPU
27 //#define PPC_DEBUG_SPR
28 //#define PPC_DEBUG_IRQ
31 const unsigned char *name;
39 /* For user-mode emulation, we don't emulate any IRQ controller */
40 #if defined(CONFIG_USER_ONLY)
41 #define PPC_IRQ_INIT_FN(name) \
42 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
46 #define PPC_IRQ_INIT_FN(name) \
47 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
54 * do nothing but store/retrieve spr value
56 #ifdef PPC_DUMP_SPR_ACCESSES
57 static void spr_read_generic (void *opaque, int sprn)
59 gen_op_load_dump_spr(sprn);
62 static void spr_write_generic (void *opaque, int sprn)
64 gen_op_store_dump_spr(sprn);
67 static void spr_read_generic (void *opaque, int sprn)
69 gen_op_load_spr(sprn);
72 static void spr_write_generic (void *opaque, int sprn)
74 gen_op_store_spr(sprn);
78 #if !defined(CONFIG_USER_ONLY)
79 static void spr_write_clear (void *opaque, int sprn)
81 gen_op_mask_spr(sprn);
85 /* SPR common to all PowerPC */
87 static void spr_read_xer (void *opaque, int sprn)
92 static void spr_write_xer (void *opaque, int sprn)
98 static void spr_read_lr (void *opaque, int sprn)
103 static void spr_write_lr (void *opaque, int sprn)
109 static void spr_read_ctr (void *opaque, int sprn)
114 static void spr_write_ctr (void *opaque, int sprn)
119 /* User read access to SPR */
125 static void spr_read_ureg (void *opaque, int sprn)
127 gen_op_load_spr(sprn + 0x10);
130 /* SPR common to all non-embedded PowerPC */
132 #if !defined(CONFIG_USER_ONLY)
133 static void spr_read_decr (void *opaque, int sprn)
138 static void spr_write_decr (void *opaque, int sprn)
144 /* SPR common to all non-embedded PowerPC, except 601 */
146 static void spr_read_tbl (void *opaque, int sprn)
151 static void spr_read_tbu (void *opaque, int sprn)
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_write_tbl (void *opaque, int sprn)
162 static void spr_write_tbu (void *opaque, int sprn)
168 #if !defined(CONFIG_USER_ONLY)
169 /* IBAT0U...IBAT0U */
170 /* IBAT0L...IBAT7L */
171 static void spr_read_ibat (void *opaque, int sprn)
173 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
176 static void spr_read_ibat_h (void *opaque, int sprn)
178 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
181 static void spr_write_ibatu (void *opaque, int sprn)
183 DisasContext *ctx = opaque;
185 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
189 static void spr_write_ibatu_h (void *opaque, int sprn)
191 DisasContext *ctx = opaque;
193 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
197 static void spr_write_ibatl (void *opaque, int sprn)
199 DisasContext *ctx = opaque;
201 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
205 static void spr_write_ibatl_h (void *opaque, int sprn)
207 DisasContext *ctx = opaque;
209 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
213 /* DBAT0U...DBAT7U */
214 /* DBAT0L...DBAT7L */
215 static void spr_read_dbat (void *opaque, int sprn)
217 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
220 static void spr_read_dbat_h (void *opaque, int sprn)
222 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
225 static void spr_write_dbatu (void *opaque, int sprn)
227 DisasContext *ctx = opaque;
229 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
233 static void spr_write_dbatu_h (void *opaque, int sprn)
235 DisasContext *ctx = opaque;
237 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
241 static void spr_write_dbatl (void *opaque, int sprn)
243 DisasContext *ctx = opaque;
245 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
249 static void spr_write_dbatl_h (void *opaque, int sprn)
251 DisasContext *ctx = opaque;
253 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
258 static void spr_read_sdr1 (void *opaque, int sprn)
263 static void spr_write_sdr1 (void *opaque, int sprn)
265 DisasContext *ctx = opaque;
271 /* 64 bits PowerPC specific SPRs */
273 /* Currently unused */
274 #if 0 && defined(TARGET_PPC64)
275 static void spr_read_asr (void *opaque, int sprn)
280 static void spr_write_asr (void *opaque, int sprn)
282 DisasContext *ctx = opaque;
288 #endif /* !defined(CONFIG_USER_ONLY) */
290 /* PowerPC 601 specific registers */
292 static void spr_read_601_rtcl (void *opaque, int sprn)
294 gen_op_load_601_rtcl();
297 static void spr_read_601_rtcu (void *opaque, int sprn)
299 gen_op_load_601_rtcu();
302 #if !defined(CONFIG_USER_ONLY)
303 static void spr_write_601_rtcu (void *opaque, int sprn)
305 gen_op_store_601_rtcu();
308 static void spr_write_601_rtcl (void *opaque, int sprn)
310 gen_op_store_601_rtcl();
315 #if !defined(CONFIG_USER_ONLY)
316 static void spr_read_601_ubat (void *opaque, int sprn)
318 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
321 static void spr_write_601_ubatu (void *opaque, int sprn)
323 DisasContext *ctx = opaque;
325 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
329 static void spr_write_601_ubatl (void *opaque, int sprn)
331 DisasContext *ctx = opaque;
333 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
338 /* PowerPC 40x specific registers */
339 #if !defined(CONFIG_USER_ONLY)
340 static void spr_read_40x_pit (void *opaque, int sprn)
342 gen_op_load_40x_pit();
345 static void spr_write_40x_pit (void *opaque, int sprn)
347 gen_op_store_40x_pit();
350 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
352 DisasContext *ctx = opaque;
354 gen_op_store_40x_dbcr0();
355 /* We must stop translation as we may have rebooted */
359 static void spr_write_40x_sler (void *opaque, int sprn)
361 DisasContext *ctx = opaque;
363 gen_op_store_40x_sler();
364 /* We must stop the translation as we may have changed
365 * some regions endianness
370 static void spr_write_booke_tcr (void *opaque, int sprn)
372 gen_op_store_booke_tcr();
375 static void spr_write_booke_tsr (void *opaque, int sprn)
377 gen_op_store_booke_tsr();
381 /* PowerPC 403 specific registers */
382 /* PBL1 / PBU1 / PBL2 / PBU2 */
383 #if !defined(CONFIG_USER_ONLY)
384 static void spr_read_403_pbr (void *opaque, int sprn)
386 gen_op_load_403_pb(sprn - SPR_403_PBL1);
389 static void spr_write_403_pbr (void *opaque, int sprn)
391 DisasContext *ctx = opaque;
393 gen_op_store_403_pb(sprn - SPR_403_PBL1);
397 static void spr_write_pir (void *opaque, int sprn)
403 #if defined(CONFIG_USER_ONLY)
404 #define spr_register(env, num, name, uea_read, uea_write, \
405 oea_read, oea_write, initial_value) \
407 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
409 static inline void _spr_register (CPUPPCState *env, int num,
410 const unsigned char *name,
411 void (*uea_read)(void *opaque, int sprn),
412 void (*uea_write)(void *opaque, int sprn),
413 target_ulong initial_value)
415 static inline void spr_register (CPUPPCState *env, int num,
416 const unsigned char *name,
417 void (*uea_read)(void *opaque, int sprn),
418 void (*uea_write)(void *opaque, int sprn),
419 void (*oea_read)(void *opaque, int sprn),
420 void (*oea_write)(void *opaque, int sprn),
421 target_ulong initial_value)
426 spr = &env->spr_cb[num];
427 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
428 #if !defined(CONFIG_USER_ONLY)
429 spr->oea_read != NULL || spr->oea_write != NULL ||
431 spr->uea_read != NULL || spr->uea_write != NULL) {
432 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
435 #if defined(PPC_DEBUG_SPR)
436 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
440 spr->uea_read = uea_read;
441 spr->uea_write = uea_write;
442 #if !defined(CONFIG_USER_ONLY)
443 spr->oea_read = oea_read;
444 spr->oea_write = oea_write;
446 env->spr[num] = initial_value;
449 /* Generic PowerPC SPRs */
450 static void gen_spr_generic (CPUPPCState *env)
452 /* Integer processing */
453 spr_register(env, SPR_XER, "XER",
454 &spr_read_xer, &spr_write_xer,
455 &spr_read_xer, &spr_write_xer,
458 spr_register(env, SPR_LR, "LR",
459 &spr_read_lr, &spr_write_lr,
460 &spr_read_lr, &spr_write_lr,
462 spr_register(env, SPR_CTR, "CTR",
463 &spr_read_ctr, &spr_write_ctr,
464 &spr_read_ctr, &spr_write_ctr,
466 /* Interrupt processing */
467 spr_register(env, SPR_SRR0, "SRR0",
468 SPR_NOACCESS, SPR_NOACCESS,
469 &spr_read_generic, &spr_write_generic,
471 spr_register(env, SPR_SRR1, "SRR1",
472 SPR_NOACCESS, SPR_NOACCESS,
473 &spr_read_generic, &spr_write_generic,
475 /* Processor control */
476 spr_register(env, SPR_SPRG0, "SPRG0",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
480 spr_register(env, SPR_SPRG1, "SPRG1",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
484 spr_register(env, SPR_SPRG2, "SPRG2",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
488 spr_register(env, SPR_SPRG3, "SPRG3",
489 SPR_NOACCESS, SPR_NOACCESS,
490 &spr_read_generic, &spr_write_generic,
494 /* SPR common to all non-embedded PowerPC, including 601 */
495 static void gen_spr_ne_601 (CPUPPCState *env)
497 /* Exception processing */
498 spr_register(env, SPR_DSISR, "DSISR",
499 SPR_NOACCESS, SPR_NOACCESS,
500 &spr_read_generic, &spr_write_generic,
502 spr_register(env, SPR_DAR, "DAR",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
507 spr_register(env, SPR_DECR, "DECR",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_decr, &spr_write_decr,
511 /* Memory management */
512 spr_register(env, SPR_SDR1, "SDR1",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_sdr1, &spr_write_sdr1,
519 static void gen_low_BATs (CPUPPCState *env)
521 spr_register(env, SPR_IBAT0U, "IBAT0U",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_ibat, &spr_write_ibatu,
525 spr_register(env, SPR_IBAT0L, "IBAT0L",
526 SPR_NOACCESS, SPR_NOACCESS,
527 &spr_read_ibat, &spr_write_ibatl,
529 spr_register(env, SPR_IBAT1U, "IBAT1U",
530 SPR_NOACCESS, SPR_NOACCESS,
531 &spr_read_ibat, &spr_write_ibatu,
533 spr_register(env, SPR_IBAT1L, "IBAT1L",
534 SPR_NOACCESS, SPR_NOACCESS,
535 &spr_read_ibat, &spr_write_ibatl,
537 spr_register(env, SPR_IBAT2U, "IBAT2U",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_ibat, &spr_write_ibatu,
541 spr_register(env, SPR_IBAT2L, "IBAT2L",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_ibat, &spr_write_ibatl,
545 spr_register(env, SPR_IBAT3U, "IBAT3U",
546 SPR_NOACCESS, SPR_NOACCESS,
547 &spr_read_ibat, &spr_write_ibatu,
549 spr_register(env, SPR_IBAT3L, "IBAT3L",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_ibat, &spr_write_ibatl,
553 spr_register(env, SPR_DBAT0U, "DBAT0U",
554 SPR_NOACCESS, SPR_NOACCESS,
555 &spr_read_dbat, &spr_write_dbatu,
557 spr_register(env, SPR_DBAT0L, "DBAT0L",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_dbat, &spr_write_dbatl,
561 spr_register(env, SPR_DBAT1U, "DBAT1U",
562 SPR_NOACCESS, SPR_NOACCESS,
563 &spr_read_dbat, &spr_write_dbatu,
565 spr_register(env, SPR_DBAT1L, "DBAT1L",
566 SPR_NOACCESS, SPR_NOACCESS,
567 &spr_read_dbat, &spr_write_dbatl,
569 spr_register(env, SPR_DBAT2U, "DBAT2U",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_dbat, &spr_write_dbatu,
573 spr_register(env, SPR_DBAT2L, "DBAT2L",
574 SPR_NOACCESS, SPR_NOACCESS,
575 &spr_read_dbat, &spr_write_dbatl,
577 spr_register(env, SPR_DBAT3U, "DBAT3U",
578 SPR_NOACCESS, SPR_NOACCESS,
579 &spr_read_dbat, &spr_write_dbatu,
581 spr_register(env, SPR_DBAT3L, "DBAT3L",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_dbat, &spr_write_dbatl,
589 static void gen_high_BATs (CPUPPCState *env)
591 spr_register(env, SPR_IBAT4U, "IBAT4U",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_ibat_h, &spr_write_ibatu_h,
595 spr_register(env, SPR_IBAT4L, "IBAT4L",
596 SPR_NOACCESS, SPR_NOACCESS,
597 &spr_read_ibat_h, &spr_write_ibatl_h,
599 spr_register(env, SPR_IBAT5U, "IBAT5U",
600 SPR_NOACCESS, SPR_NOACCESS,
601 &spr_read_ibat_h, &spr_write_ibatu_h,
603 spr_register(env, SPR_IBAT5L, "IBAT5L",
604 SPR_NOACCESS, SPR_NOACCESS,
605 &spr_read_ibat_h, &spr_write_ibatl_h,
607 spr_register(env, SPR_IBAT6U, "IBAT6U",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_ibat_h, &spr_write_ibatu_h,
611 spr_register(env, SPR_IBAT6L, "IBAT6L",
612 SPR_NOACCESS, SPR_NOACCESS,
613 &spr_read_ibat_h, &spr_write_ibatl_h,
615 spr_register(env, SPR_IBAT7U, "IBAT7U",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_ibat_h, &spr_write_ibatu_h,
619 spr_register(env, SPR_IBAT7L, "IBAT7L",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_ibat_h, &spr_write_ibatl_h,
623 spr_register(env, SPR_DBAT4U, "DBAT4U",
624 SPR_NOACCESS, SPR_NOACCESS,
625 &spr_read_dbat_h, &spr_write_dbatu_h,
627 spr_register(env, SPR_DBAT4L, "DBAT4L",
628 SPR_NOACCESS, SPR_NOACCESS,
629 &spr_read_dbat_h, &spr_write_dbatl_h,
631 spr_register(env, SPR_DBAT5U, "DBAT5U",
632 SPR_NOACCESS, SPR_NOACCESS,
633 &spr_read_dbat_h, &spr_write_dbatu_h,
635 spr_register(env, SPR_DBAT5L, "DBAT5L",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_dbat_h, &spr_write_dbatl_h,
639 spr_register(env, SPR_DBAT6U, "DBAT6U",
640 SPR_NOACCESS, SPR_NOACCESS,
641 &spr_read_dbat_h, &spr_write_dbatu_h,
643 spr_register(env, SPR_DBAT6L, "DBAT6L",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_dbat_h, &spr_write_dbatl_h,
647 spr_register(env, SPR_DBAT7U, "DBAT7U",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_dbat_h, &spr_write_dbatu_h,
651 spr_register(env, SPR_DBAT7L, "DBAT7L",
652 SPR_NOACCESS, SPR_NOACCESS,
653 &spr_read_dbat_h, &spr_write_dbatl_h,
658 /* Generic PowerPC time base */
659 static void gen_tbl (CPUPPCState *env)
661 spr_register(env, SPR_VTBL, "TBL",
662 &spr_read_tbl, SPR_NOACCESS,
663 &spr_read_tbl, SPR_NOACCESS,
665 spr_register(env, SPR_TBL, "TBL",
666 SPR_NOACCESS, SPR_NOACCESS,
667 SPR_NOACCESS, &spr_write_tbl,
669 spr_register(env, SPR_VTBU, "TBU",
670 &spr_read_tbu, SPR_NOACCESS,
671 &spr_read_tbu, SPR_NOACCESS,
673 spr_register(env, SPR_TBU, "TBU",
674 SPR_NOACCESS, SPR_NOACCESS,
675 SPR_NOACCESS, &spr_write_tbu,
679 /* Softare table search registers */
680 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
682 env->nb_tlb = nb_tlbs;
683 env->nb_ways = nb_ways;
685 spr_register(env, SPR_DMISS, "DMISS",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, SPR_NOACCESS,
689 spr_register(env, SPR_DCMP, "DCMP",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, SPR_NOACCESS,
693 spr_register(env, SPR_HASH1, "HASH1",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, SPR_NOACCESS,
697 spr_register(env, SPR_HASH2, "HASH2",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_generic, SPR_NOACCESS,
701 spr_register(env, SPR_IMISS, "IMISS",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_generic, SPR_NOACCESS,
705 spr_register(env, SPR_ICMP, "ICMP",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, SPR_NOACCESS,
709 spr_register(env, SPR_RPA, "RPA",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
715 /* SPR common to MPC755 and G2 */
716 static void gen_spr_G2_755 (CPUPPCState *env)
719 spr_register(env, SPR_SPRG4, "SPRG4",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
723 spr_register(env, SPR_SPRG5, "SPRG5",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_generic, &spr_write_generic,
727 spr_register(env, SPR_SPRG6, "SPRG6",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_generic, &spr_write_generic,
731 spr_register(env, SPR_SPRG7, "SPRG7",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_generic, &spr_write_generic,
735 /* External access control */
736 /* XXX : not implemented */
737 spr_register(env, SPR_EAR, "EAR",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_generic, &spr_write_generic,
743 /* SPR common to all 7xx PowerPC implementations */
744 static void gen_spr_7xx (CPUPPCState *env)
747 /* XXX : not implemented */
748 spr_register(env, SPR_DABR, "DABR",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
752 /* XXX : not implemented */
753 spr_register(env, SPR_IABR, "IABR",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
757 /* Cache management */
758 /* XXX : not implemented */
759 spr_register(env, SPR_ICTC, "ICTC",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
763 /* XXX : not implemented */
764 spr_register(env, SPR_L2CR, "L2CR",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_generic, &spr_write_generic,
768 /* Performance monitors */
769 /* XXX : not implemented */
770 spr_register(env, SPR_MMCR0, "MMCR0",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
774 /* XXX : not implemented */
775 spr_register(env, SPR_MMCR1, "MMCR1",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
779 /* XXX : not implemented */
780 spr_register(env, SPR_PMC1, "PMC1",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
784 /* XXX : not implemented */
785 spr_register(env, SPR_PMC2, "PMC2",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
789 /* XXX : not implemented */
790 spr_register(env, SPR_PMC3, "PMC3",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, &spr_write_generic,
794 /* XXX : not implemented */
795 spr_register(env, SPR_PMC4, "PMC4",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_generic, &spr_write_generic,
799 /* XXX : not implemented */
800 spr_register(env, SPR_SIA, "SIA",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_generic, SPR_NOACCESS,
804 spr_register(env, SPR_UMMCR0, "UMMCR0",
805 &spr_read_ureg, SPR_NOACCESS,
806 &spr_read_ureg, SPR_NOACCESS,
808 spr_register(env, SPR_UMMCR1, "UMMCR1",
809 &spr_read_ureg, SPR_NOACCESS,
810 &spr_read_ureg, SPR_NOACCESS,
812 spr_register(env, SPR_UPMC1, "UPMC1",
813 &spr_read_ureg, SPR_NOACCESS,
814 &spr_read_ureg, SPR_NOACCESS,
816 spr_register(env, SPR_UPMC2, "UPMC2",
817 &spr_read_ureg, SPR_NOACCESS,
818 &spr_read_ureg, SPR_NOACCESS,
820 spr_register(env, SPR_UPMC3, "UPMC3",
821 &spr_read_ureg, SPR_NOACCESS,
822 &spr_read_ureg, SPR_NOACCESS,
824 spr_register(env, SPR_UPMC4, "UPMC4",
825 &spr_read_ureg, SPR_NOACCESS,
826 &spr_read_ureg, SPR_NOACCESS,
828 spr_register(env, SPR_USIA, "USIA",
829 &spr_read_ureg, SPR_NOACCESS,
830 &spr_read_ureg, SPR_NOACCESS,
832 /* Thermal management */
833 /* XXX : not implemented */
834 spr_register(env, SPR_THRM1, "THRM1",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, &spr_write_generic,
838 /* XXX : not implemented */
839 spr_register(env, SPR_THRM2, "THRM2",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_generic, &spr_write_generic,
843 /* XXX : not implemented */
844 spr_register(env, SPR_THRM3, "THRM3",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_generic, &spr_write_generic,
848 /* External access control */
849 /* XXX : not implemented */
850 spr_register(env, SPR_EAR, "EAR",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_generic, &spr_write_generic,
856 /* SPR specific to PowerPC 604 implementation */
857 static void gen_spr_604 (CPUPPCState *env)
859 /* Processor identification */
860 spr_register(env, SPR_PIR, "PIR",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, &spr_write_pir,
865 /* XXX : not implemented */
866 spr_register(env, SPR_IABR, "IABR",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_generic, &spr_write_generic,
870 /* XXX : not implemented */
871 spr_register(env, SPR_DABR, "DABR",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
875 /* Performance counters */
876 /* XXX : not implemented */
877 spr_register(env, SPR_MMCR0, "MMCR0",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, &spr_write_generic,
881 /* XXX : not implemented */
882 spr_register(env, SPR_MMCR1, "MMCR1",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
886 /* XXX : not implemented */
887 spr_register(env, SPR_PMC1, "PMC1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
891 /* XXX : not implemented */
892 spr_register(env, SPR_PMC2, "PMC2",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
896 /* XXX : not implemented */
897 spr_register(env, SPR_PMC3, "PMC3",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, &spr_write_generic,
901 /* XXX : not implemented */
902 spr_register(env, SPR_PMC4, "PMC4",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
906 /* XXX : not implemented */
907 spr_register(env, SPR_SIA, "SIA",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, SPR_NOACCESS,
911 /* XXX : not implemented */
912 spr_register(env, SPR_SDA, "SDA",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, SPR_NOACCESS,
916 /* External access control */
917 /* XXX : not implemented */
918 spr_register(env, SPR_EAR, "EAR",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
924 /* SPR specific to PowerPC 603 implementation */
925 static void gen_spr_603 (CPUPPCState *env)
927 /* External access control */
928 /* XXX : not implemented */
929 spr_register(env, SPR_EAR, "EAR",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
935 /* SPR specific to PowerPC G2 implementation */
936 static void gen_spr_G2 (CPUPPCState *env)
938 /* Memory base address */
940 spr_register(env, SPR_MBAR, "MBAR",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
944 /* System version register */
946 spr_register(env, SPR_SVR, "SVR",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, SPR_NOACCESS,
950 /* Exception processing */
951 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
955 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
960 /* XXX : not implemented */
961 spr_register(env, SPR_DABR, "DABR",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
965 /* XXX : not implemented */
966 spr_register(env, SPR_DABR2, "DABR2",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
970 /* XXX : not implemented */
971 spr_register(env, SPR_IABR, "IABR",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
975 /* XXX : not implemented */
976 spr_register(env, SPR_IABR2, "IABR2",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
980 /* XXX : not implemented */
981 spr_register(env, SPR_IBCR, "IBCR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
985 /* XXX : not implemented */
986 spr_register(env, SPR_DBCR, "DBCR",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
992 /* SPR specific to PowerPC 602 implementation */
993 static void gen_spr_602 (CPUPPCState *env)
996 /* XXX : not implemented */
997 spr_register(env, SPR_SER, "SER",
998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, &spr_write_generic,
1001 /* XXX : not implemented */
1002 spr_register(env, SPR_SEBR, "SEBR",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_ESASR, "ESASR",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1011 /* Floating point status */
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_SP, "SP",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1017 /* XXX : not implemented */
1018 spr_register(env, SPR_LT, "LT",
1019 SPR_NOACCESS, SPR_NOACCESS,
1020 &spr_read_generic, &spr_write_generic,
1022 /* Watchdog timer */
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_TCR, "TCR",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_generic,
1028 /* Interrupt base */
1029 spr_register(env, SPR_IBR, "IBR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1035 /* SPR specific to PowerPC 601 implementation */
1036 static void gen_spr_601 (CPUPPCState *env)
1038 /* Multiplication/division register */
1040 spr_register(env, SPR_MQ, "MQ",
1041 &spr_read_generic, &spr_write_generic,
1042 &spr_read_generic, &spr_write_generic,
1045 spr_register(env, SPR_601_RTCU, "RTCU",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 SPR_NOACCESS, &spr_write_601_rtcu,
1049 spr_register(env, SPR_601_VRTCU, "RTCU",
1050 &spr_read_601_rtcu, SPR_NOACCESS,
1051 &spr_read_601_rtcu, SPR_NOACCESS,
1053 spr_register(env, SPR_601_RTCL, "RTCL",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 SPR_NOACCESS, &spr_write_601_rtcl,
1057 spr_register(env, SPR_601_VRTCL, "RTCL",
1058 &spr_read_601_rtcl, SPR_NOACCESS,
1059 &spr_read_601_rtcl, SPR_NOACCESS,
1063 spr_register(env, SPR_601_UDECR, "UDECR",
1064 &spr_read_decr, SPR_NOACCESS,
1065 &spr_read_decr, SPR_NOACCESS,
1068 /* External access control */
1069 /* XXX : not implemented */
1070 spr_register(env, SPR_EAR, "EAR",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 &spr_read_generic, &spr_write_generic,
1074 /* Memory management */
1075 spr_register(env, SPR_IBAT0U, "IBAT0U",
1076 SPR_NOACCESS, SPR_NOACCESS,
1077 &spr_read_601_ubat, &spr_write_601_ubatu,
1079 spr_register(env, SPR_IBAT0L, "IBAT0L",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_601_ubat, &spr_write_601_ubatl,
1083 spr_register(env, SPR_IBAT1U, "IBAT1U",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_601_ubat, &spr_write_601_ubatu,
1087 spr_register(env, SPR_IBAT1L, "IBAT1L",
1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_601_ubat, &spr_write_601_ubatl,
1091 spr_register(env, SPR_IBAT2U, "IBAT2U",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_601_ubat, &spr_write_601_ubatu,
1095 spr_register(env, SPR_IBAT2L, "IBAT2L",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_601_ubat, &spr_write_601_ubatl,
1099 spr_register(env, SPR_IBAT3U, "IBAT3U",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_601_ubat, &spr_write_601_ubatu,
1103 spr_register(env, SPR_IBAT3L, "IBAT3L",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_601_ubat, &spr_write_601_ubatl,
1109 /* PowerPC BookE SPR */
1110 static void gen_spr_BookE (CPUPPCState *env)
1112 /* Processor identification */
1113 spr_register(env, SPR_BOOKE_PIR, "PIR",
1114 SPR_NOACCESS, SPR_NOACCESS,
1115 &spr_read_generic, &spr_write_pir,
1117 /* Interrupt processing */
1118 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_generic,
1122 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1126 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1130 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1134 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1135 SPR_NOACCESS, SPR_NOACCESS,
1136 &spr_read_generic, &spr_write_generic,
1138 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
1139 SPR_NOACCESS, SPR_NOACCESS,
1140 &spr_read_generic, &spr_write_generic,
1143 /* XXX : not implemented */
1144 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1145 SPR_NOACCESS, SPR_NOACCESS,
1146 &spr_read_generic, &spr_write_generic,
1148 /* XXX : not implemented */
1149 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1150 SPR_NOACCESS, SPR_NOACCESS,
1151 &spr_read_generic, &spr_write_generic,
1153 /* XXX : not implemented */
1154 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_generic,
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1163 /* XXX : not implemented */
1164 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1168 /* XXX : not implemented */
1169 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1173 /* XXX : not implemented */
1174 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1183 /* XXX : not implemented */
1184 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1185 SPR_NOACCESS, SPR_NOACCESS,
1186 &spr_read_generic, &spr_write_generic,
1188 /* XXX : not implemented */
1189 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_generic, &spr_write_generic,
1193 /* XXX : not implemented */
1194 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1198 /* XXX : not implemented */
1199 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_clear,
1203 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 &spr_read_generic, &spr_write_generic,
1207 spr_register(env, SPR_BOOKE_ESR, "ESR",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1211 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1215 /* Exception vectors */
1216 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1220 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1224 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1228 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1232 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1236 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_generic,
1240 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_generic,
1244 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_generic, &spr_write_generic,
1248 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1252 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1256 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, &spr_write_generic,
1260 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1264 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1268 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1272 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 &spr_read_generic, &spr_write_generic,
1276 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1280 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1284 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1288 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1292 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1296 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1300 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1304 spr_register(env, SPR_BOOKE_PID, "PID",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1308 spr_register(env, SPR_BOOKE_TCR, "TCR",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_booke_tcr,
1312 spr_register(env, SPR_BOOKE_TSR, "TSR",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_booke_tsr,
1317 spr_register(env, SPR_DECR, "DECR",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_decr, &spr_write_decr,
1321 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 SPR_NOACCESS, &spr_write_generic,
1326 spr_register(env, SPR_USPRG0, "USPRG0",
1327 &spr_read_generic, &spr_write_generic,
1328 &spr_read_generic, &spr_write_generic,
1330 spr_register(env, SPR_SPRG4, "SPRG4",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1334 spr_register(env, SPR_USPRG4, "USPRG4",
1335 &spr_read_ureg, SPR_NOACCESS,
1336 &spr_read_ureg, SPR_NOACCESS,
1338 spr_register(env, SPR_SPRG5, "SPRG5",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1342 spr_register(env, SPR_USPRG5, "USPRG5",
1343 &spr_read_ureg, SPR_NOACCESS,
1344 &spr_read_ureg, SPR_NOACCESS,
1346 spr_register(env, SPR_SPRG6, "SPRG6",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1350 spr_register(env, SPR_USPRG6, "USPRG6",
1351 &spr_read_ureg, SPR_NOACCESS,
1352 &spr_read_ureg, SPR_NOACCESS,
1354 spr_register(env, SPR_SPRG7, "SPRG7",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1358 spr_register(env, SPR_USPRG7, "USPRG7",
1359 &spr_read_ureg, SPR_NOACCESS,
1360 &spr_read_ureg, SPR_NOACCESS,
1364 /* FSL storage control registers */
1365 static void gen_spr_BookE_FSL (CPUPPCState *env)
1367 /* TLB assist registers */
1368 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1372 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1376 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1380 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1384 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1388 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_generic,
1392 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1396 if (env->nb_pids > 1) {
1397 spr_register(env, SPR_BOOKE_PID1, "PID1",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1402 if (env->nb_pids > 2) {
1403 spr_register(env, SPR_BOOKE_PID2, "PID2",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1408 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, SPR_NOACCESS,
1411 0x00000000); /* TOFIX */
1412 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_generic,
1415 0x00000000); /* TOFIX */
1416 switch (env->nb_ways) {
1418 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, SPR_NOACCESS,
1421 0x00000000); /* TOFIX */
1424 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, SPR_NOACCESS,
1427 0x00000000); /* TOFIX */
1430 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_generic, SPR_NOACCESS,
1433 0x00000000); /* TOFIX */
1436 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, SPR_NOACCESS,
1439 0x00000000); /* TOFIX */
1447 /* SPR specific to PowerPC 440 implementation */
1448 static void gen_spr_440 (CPUPPCState *env)
1451 /* XXX : not implemented */
1452 spr_register(env, SPR_440_DNV0, "DNV0",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1456 /* XXX : not implemented */
1457 spr_register(env, SPR_440_DNV1, "DNV1",
1458 SPR_NOACCESS, SPR_NOACCESS,
1459 &spr_read_generic, &spr_write_generic,
1461 /* XXX : not implemented */
1462 spr_register(env, SPR_440_DNV2, "DNV2",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_generic,
1466 /* XXX : not implemented */
1467 spr_register(env, SPR_440_DNV3, "DNV3",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_generic,
1471 /* XXX : not implemented */
1472 spr_register(env, SPR_440_DVT0, "DVT0",
1473 SPR_NOACCESS, SPR_NOACCESS,
1474 &spr_read_generic, &spr_write_generic,
1476 /* XXX : not implemented */
1477 spr_register(env, SPR_440_DVT1, "DVT1",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1481 /* XXX : not implemented */
1482 spr_register(env, SPR_440_DVT2, "DVT2",
1483 SPR_NOACCESS, SPR_NOACCESS,
1484 &spr_read_generic, &spr_write_generic,
1486 /* XXX : not implemented */
1487 spr_register(env, SPR_440_DVT3, "DVT3",
1488 SPR_NOACCESS, SPR_NOACCESS,
1489 &spr_read_generic, &spr_write_generic,
1491 /* XXX : not implemented */
1492 spr_register(env, SPR_440_DVLIM, "DVLIM",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_generic, &spr_write_generic,
1496 /* XXX : not implemented */
1497 spr_register(env, SPR_440_INV0, "INV0",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1501 /* XXX : not implemented */
1502 spr_register(env, SPR_440_INV1, "INV1",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1506 /* XXX : not implemented */
1507 spr_register(env, SPR_440_INV2, "INV2",
1508 SPR_NOACCESS, SPR_NOACCESS,
1509 &spr_read_generic, &spr_write_generic,
1511 /* XXX : not implemented */
1512 spr_register(env, SPR_440_INV3, "INV3",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1516 /* XXX : not implemented */
1517 spr_register(env, SPR_440_IVT0, "IVT0",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic,
1521 /* XXX : not implemented */
1522 spr_register(env, SPR_440_IVT1, "IVT1",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1526 /* XXX : not implemented */
1527 spr_register(env, SPR_440_IVT2, "IVT2",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_generic,
1531 /* XXX : not implemented */
1532 spr_register(env, SPR_440_IVT3, "IVT3",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1536 /* XXX : not implemented */
1537 spr_register(env, SPR_440_IVLIM, "IVLIM",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, SPR_NOACCESS,
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, SPR_NOACCESS,
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, SPR_NOACCESS,
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, SPR_NOACCESS,
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, SPR_NOACCESS,
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_440_DBDR, "DBDR",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1572 /* Processor control */
1573 spr_register(env, SPR_4xx_CCR0, "CCR0",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1577 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, SPR_NOACCESS,
1581 /* Storage control */
1582 spr_register(env, SPR_440_MMUCR, "MMUCR",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1588 /* SPR shared between PowerPC 40x implementations */
1589 static void gen_spr_40x (CPUPPCState *env)
1592 /* XXX : not implemented */
1593 spr_register(env, SPR_40x_DCCR, "DCCR",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1597 /* XXX : not implemented */
1598 spr_register(env, SPR_40x_DCWR, "DCWR",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_40x_ICCR, "ICCR",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1607 /* XXX : not implemented */
1608 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, SPR_NOACCESS,
1612 /* Bus access control */
1613 spr_register(env, SPR_40x_SGR, "SGR",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic,
1617 spr_register(env, SPR_40x_ZPR, "ZPR",
1618 SPR_NOACCESS, SPR_NOACCESS,
1619 &spr_read_generic, &spr_write_generic,
1622 spr_register(env, SPR_40x_PID, "PID",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, &spr_write_generic,
1627 spr_register(env, SPR_40x_DEAR, "DEAR",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_generic,
1631 spr_register(env, SPR_40x_ESR, "ESR",
1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, &spr_write_generic,
1635 spr_register(env, SPR_40x_EVPR, "EVPR",
1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_generic,
1639 spr_register(env, SPR_40x_SRR2, "SRR2",
1640 &spr_read_generic, &spr_write_generic,
1641 &spr_read_generic, &spr_write_generic,
1643 spr_register(env, SPR_40x_SRR3, "SRR3",
1644 &spr_read_generic, &spr_write_generic,
1645 &spr_read_generic, &spr_write_generic,
1648 spr_register(env, SPR_40x_PIT, "PIT",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_40x_pit, &spr_write_40x_pit,
1652 spr_register(env, SPR_40x_TCR, "TCR",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_booke_tcr,
1656 spr_register(env, SPR_40x_TSR, "TSR",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_booke_tsr,
1660 /* Debug interface */
1661 /* XXX : not implemented */
1662 spr_register(env, SPR_40x_DAC1, "DAC1",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1666 spr_register(env, SPR_40x_DAC2, "DAC2",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1670 /* XXX : not implemented */
1671 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_40x_dbcr0,
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_40x_DBSR, "DBSR",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_clear,
1679 /* Last reset was system reset */
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_40x_IAC1, "IAC1",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1686 spr_register(env, SPR_40x_IAC2, "IAC2",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1692 /* SPR specific to PowerPC 405 implementation */
1693 static void gen_spr_405 (CPUPPCState *env)
1695 spr_register(env, SPR_4xx_CCR0, "CCR0",
1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic,
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_405_DBCR1, "DBCR1",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1705 /* XXX : not implemented */
1706 spr_register(env, SPR_405_DVC1, "DVC1",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1710 /* XXX : not implemented */
1711 spr_register(env, SPR_405_DVC2, "DVC2",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, &spr_write_generic,
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_405_IAC3, "IAC3",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1720 /* XXX : not implemented */
1721 spr_register(env, SPR_405_IAC4, "IAC4",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1725 /* Storage control */
1726 spr_register(env, SPR_405_SLER, "SLER",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_40x_sler,
1730 /* XXX : not implemented */
1731 spr_register(env, SPR_405_SU0R, "SU0R",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1736 spr_register(env, SPR_USPRG0, "USPRG0",
1737 &spr_read_ureg, SPR_NOACCESS,
1738 &spr_read_ureg, SPR_NOACCESS,
1740 spr_register(env, SPR_SPRG4, "SPRG4",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, &spr_write_generic,
1744 spr_register(env, SPR_USPRG4, "USPRG4",
1745 &spr_read_ureg, SPR_NOACCESS,
1746 &spr_read_ureg, SPR_NOACCESS,
1748 spr_register(env, SPR_SPRG5, "SPRG5",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 spr_read_generic, &spr_write_generic,
1752 spr_register(env, SPR_USPRG5, "USPRG5",
1753 &spr_read_ureg, SPR_NOACCESS,
1754 &spr_read_ureg, SPR_NOACCESS,
1756 spr_register(env, SPR_SPRG6, "SPRG6",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 spr_read_generic, &spr_write_generic,
1760 spr_register(env, SPR_USPRG6, "USPRG6",
1761 &spr_read_ureg, SPR_NOACCESS,
1762 &spr_read_ureg, SPR_NOACCESS,
1764 spr_register(env, SPR_SPRG7, "SPRG7",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 spr_read_generic, &spr_write_generic,
1768 spr_register(env, SPR_USPRG7, "USPRG7",
1769 &spr_read_ureg, SPR_NOACCESS,
1770 &spr_read_ureg, SPR_NOACCESS,
1774 /* SPR shared between PowerPC 401 & 403 implementations */
1775 static void gen_spr_401_403 (CPUPPCState *env)
1778 spr_register(env, SPR_403_VTBL, "TBL",
1779 &spr_read_tbl, SPR_NOACCESS,
1780 &spr_read_tbl, SPR_NOACCESS,
1782 spr_register(env, SPR_403_TBL, "TBL",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 SPR_NOACCESS, &spr_write_tbl,
1786 spr_register(env, SPR_403_VTBU, "TBU",
1787 &spr_read_tbu, SPR_NOACCESS,
1788 &spr_read_tbu, SPR_NOACCESS,
1790 spr_register(env, SPR_403_TBU, "TBU",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 SPR_NOACCESS, &spr_write_tbu,
1795 /* XXX: not implemented */
1796 spr_register(env, SPR_403_CDBCR, "CDBCR",
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, &spr_write_generic,
1802 /* SPR specific to PowerPC 403 implementation */
1803 static void gen_spr_403 (CPUPPCState *env)
1806 spr_register(env, SPR_403_PBL1, "PBL1",
1807 SPR_NOACCESS, SPR_NOACCESS,
1808 &spr_read_403_pbr, &spr_write_403_pbr,
1810 spr_register(env, SPR_403_PBU1, "PBU1",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_403_pbr, &spr_write_403_pbr,
1814 spr_register(env, SPR_403_PBL2, "PBL2",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_403_pbr, &spr_write_403_pbr,
1818 spr_register(env, SPR_403_PBU2, "PBU2",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_403_pbr, &spr_write_403_pbr,
1823 /* XXX : not implemented */
1824 spr_register(env, SPR_40x_DAC2, "DAC2",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1828 /* XXX : not implemented */
1829 spr_register(env, SPR_40x_IAC2, "IAC2",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1835 /* SPR specific to PowerPC compression coprocessor extension */
1837 static void gen_spr_compress (CPUPPCState *env)
1839 spr_register(env, SPR_401_SKR, "SKR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1846 // XXX: TODO (64 bits PowerPC SPRs)
1848 * ASR => SPR 280 (64 bits)
1849 * FPECR => SPR 1022 (?)
1850 * VRSAVE => SPR 256 (Altivec)
1851 * SCOMC => SPR 276 (64 bits ?)
1852 * SCOMD => SPR 277 (64 bits ?)
1853 * HSPRG0 => SPR 304 (hypervisor)
1854 * HSPRG1 => SPR 305 (hypervisor)
1855 * HDEC => SPR 310 (hypervisor)
1856 * HIOR => SPR 311 (hypervisor)
1857 * RMOR => SPR 312 (970)
1858 * HRMOR => SPR 313 (hypervisor)
1859 * HSRR0 => SPR 314 (hypervisor)
1860 * HSRR1 => SPR 315 (hypervisor)
1861 * LPCR => SPR 316 (970)
1862 * LPIDR => SPR 317 (970)
1863 * ... and more (thermal management, performance counters, ...)
1866 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1869 /* Default MMU definitions */
1877 * - RCPU (same as MPC5xx ?)
1879 spr_register(env, SPR_PVR, "PVR",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, SPR_NOACCESS,
1883 printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1884 def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1886 /* Embedded PowerPC from IBM */
1887 case CPU_PPC_401A1: /* 401 A1 family */
1888 case CPU_PPC_401B2: /* 401 B2 family */
1889 case CPU_PPC_401C2: /* 401 C2 family */
1890 case CPU_PPC_401D2: /* 401 D2 family */
1891 case CPU_PPC_401E2: /* 401 E2 family */
1892 case CPU_PPC_401F2: /* 401 F2 family */
1893 case CPU_PPC_401G2: /* 401 G2 family */
1894 case CPU_PPC_IOP480: /* IOP 480 family */
1895 case CPU_PPC_COBRA: /* IBM Processor for Network Resources */
1896 gen_spr_generic(env);
1898 gen_spr_401_403(env);
1900 /* XXX: optional ? */
1901 gen_spr_compress(env);
1907 /* XXX: TODO: allocate internal IRQ controller */
1910 case CPU_PPC_403GA: /* 403 GA family */
1911 case CPU_PPC_403GB: /* 403 GB family */
1912 case CPU_PPC_403GC: /* 403 GC family */
1913 case CPU_PPC_403GCX: /* 403 GCX family */
1914 gen_spr_generic(env);
1916 gen_spr_401_403(env);
1922 /* XXX: TODO: allocate internal IRQ controller */
1925 case CPU_PPC_405CR: /* 405 GP/CR family */
1926 case CPU_PPC_405EP: /* 405 EP family */
1927 case CPU_PPC_405GPR: /* 405 GPR family */
1928 case CPU_PPC_405D2: /* 405 D2 family */
1929 case CPU_PPC_405D4: /* 405 D4 family */
1930 gen_spr_generic(env);
1939 /* Allocate hardware IRQ controller */
1940 ppc405_irq_init(env);
1943 case CPU_PPC_NPE405H: /* NPe405 H family */
1944 case CPU_PPC_NPE405H2:
1945 case CPU_PPC_NPE405L: /* Npe405 L family */
1946 gen_spr_generic(env);
1955 /* Allocate hardware IRQ controller */
1956 ppc405_irq_init(env);
1960 case CPU_PPC_STB01000:
1963 case CPU_PPC_STB01010:
1966 case CPU_PPC_STB0210:
1968 case CPU_PPC_STB03: /* STB03 family */
1970 case CPU_PPC_STB043: /* STB043 family */
1973 case CPU_PPC_STB045: /* STB045 family */
1975 case CPU_PPC_STB25: /* STB25 family */
1977 case CPU_PPC_STB130: /* STB130 family */
1979 gen_spr_generic(env);
1988 /* Allocate hardware IRQ controller */
1989 ppc405_irq_init(env);
1992 case CPU_PPC_440EP: /* 440 EP family */
1993 case CPU_PPC_440GP: /* 440 GP family */
1994 case CPU_PPC_440GX: /* 440 GX family */
1995 case CPU_PPC_440GXc: /* 440 GXc family */
1996 case CPU_PPC_440GXf: /* 440 GXf family */
1997 case CPU_PPC_440SP: /* 440 SP family */
1998 case CPU_PPC_440SP2:
1999 case CPU_PPC_440SPE: /* 440 SPE family */
2000 gen_spr_generic(env);
2009 /* XXX: TODO: allocate internal IRQ controller */
2012 /* Embedded PowerPC from Freescale */
2018 case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */
2022 case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */
2023 case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */
2027 case CPU_PPC_827x: /* MPC 827x / 828x */
2031 /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
2032 case CPU_PPC_e500v110:
2033 case CPU_PPC_e500v120:
2034 case CPU_PPC_e500v210:
2035 case CPU_PPC_e500v220:
2036 gen_spr_generic(env);
2040 gen_spr_BookE_FSL(env);
2045 /* XXX: TODO: allocate internal IRQ controller */
2053 /* 32 bits PowerPC */
2054 case CPU_PPC_601: /* PowerPC 601 */
2055 gen_spr_generic(env);
2056 gen_spr_ne_601(env);
2058 /* Hardware implementation registers */
2059 /* XXX : not implemented */
2060 spr_register(env, SPR_HID0, "HID0",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2064 /* XXX : not implemented */
2065 spr_register(env, SPR_HID1, "HID1",
2066 SPR_NOACCESS, SPR_NOACCESS,
2067 &spr_read_generic, &spr_write_generic,
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_601_HID2, "HID2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2074 /* XXX : not implemented */
2075 spr_register(env, SPR_601_HID5, "HID5",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_generic,
2079 /* XXX : not implemented */
2081 spr_register(env, SPR_601_HID15, "HID15",
2082 SPR_NOACCESS, SPR_NOACCESS,
2083 &spr_read_generic, &spr_write_generic,
2090 /* XXX: TODO: allocate internal IRQ controller */
2093 case CPU_PPC_602: /* PowerPC 602 */
2094 gen_spr_generic(env);
2095 gen_spr_ne_601(env);
2096 /* Memory management */
2100 gen_6xx_7xx_soft_tlb(env, 64, 2);
2102 /* hardware implementation registers */
2103 /* XXX : not implemented */
2104 spr_register(env, SPR_HID0, "HID0",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2108 /* XXX : not implemented */
2109 spr_register(env, SPR_HID1, "HID1",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_generic,
2113 /* Allocate hardware IRQ controller */
2114 ppc6xx_irq_init(env);
2117 case CPU_PPC_603: /* PowerPC 603 */
2118 case CPU_PPC_603E: /* PowerPC 603e */
2119 case CPU_PPC_603E7v:
2120 case CPU_PPC_603E7v2:
2121 case CPU_PPC_603P: /* PowerPC 603p */
2122 case CPU_PPC_603R: /* PowerPC 603r */
2123 gen_spr_generic(env);
2124 gen_spr_ne_601(env);
2125 /* Memory management */
2129 gen_6xx_7xx_soft_tlb(env, 64, 2);
2131 /* hardware implementation registers */
2132 /* XXX : not implemented */
2133 spr_register(env, SPR_HID0, "HID0",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_generic,
2137 /* XXX : not implemented */
2138 spr_register(env, SPR_HID1, "HID1",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2142 /* Allocate hardware IRQ controller */
2143 ppc6xx_irq_init(env);
2146 case CPU_PPC_G2: /* PowerPC G2 family */
2150 case CPU_PPC_G2LE: /* PowerPC G2LE family */
2151 case CPU_PPC_G2LEgp:
2152 case CPU_PPC_G2LEls:
2153 gen_spr_generic(env);
2154 gen_spr_ne_601(env);
2155 /* Memory management */
2159 /* Memory management */
2161 gen_6xx_7xx_soft_tlb(env, 64, 2);
2162 gen_spr_G2_755(env);
2164 /* Hardware implementation register */
2165 /* XXX : not implemented */
2166 spr_register(env, SPR_HID0, "HID0",
2167 SPR_NOACCESS, SPR_NOACCESS,
2168 &spr_read_generic, &spr_write_generic,
2170 /* XXX : not implemented */
2171 spr_register(env, SPR_HID1, "HID1",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2175 /* XXX : not implemented */
2176 spr_register(env, SPR_HID2, "HID2",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_generic, &spr_write_generic,
2180 /* Allocate hardware IRQ controller */
2181 ppc6xx_irq_init(env);
2184 case CPU_PPC_604: /* PowerPC 604 */
2185 case CPU_PPC_604E: /* PowerPC 604e */
2186 case CPU_PPC_604R: /* PowerPC 604r */
2187 gen_spr_generic(env);
2188 gen_spr_ne_601(env);
2189 /* Memory management */
2194 /* Hardware implementation registers */
2195 /* XXX : not implemented */
2196 spr_register(env, SPR_HID0, "HID0",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_HID1, "HID1",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2205 /* Allocate hardware IRQ controller */
2206 ppc6xx_irq_init(env);
2209 case CPU_PPC_74x: /* PowerPC 740 / 750 */
2212 case CPU_PPC_74xP: /* PowerPC 740P / 750P */
2213 case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */
2214 case CPU_PPC_750CXE22:
2215 case CPU_PPC_750CXE23:
2216 case CPU_PPC_750CXE24:
2217 case CPU_PPC_750CXE24b:
2218 case CPU_PPC_750CXE31:
2219 case CPU_PPC_750CXE31b:
2220 case CPU_PPC_750CXR:
2221 gen_spr_generic(env);
2222 gen_spr_ne_601(env);
2223 /* Memory management */
2228 /* Hardware implementation registers */
2229 /* XXX : not implemented */
2230 spr_register(env, SPR_HID0, "HID0",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_generic, &spr_write_generic,
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_HID1, "HID1",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2239 /* Allocate hardware IRQ controller */
2240 ppc6xx_irq_init(env);
2243 case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */
2244 case CPU_PPC_750FX20:
2245 case CPU_PPC_750FX21:
2246 case CPU_PPC_750FX22:
2247 case CPU_PPC_750FX23:
2248 case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */
2249 case CPU_PPC_750GX11:
2250 case CPU_PPC_750GX12:
2251 gen_spr_generic(env);
2252 gen_spr_ne_601(env);
2253 /* Memory management */
2255 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2260 /* Hardware implementation registers */
2261 /* XXX : not implemented */
2262 spr_register(env, SPR_HID0, "HID0",
2263 SPR_NOACCESS, SPR_NOACCESS,
2264 &spr_read_generic, &spr_write_generic,
2266 /* XXX : not implemented */
2267 spr_register(env, SPR_HID1, "HID1",
2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_generic, &spr_write_generic,
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_750_HID2, "HID2",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2276 /* Allocate hardware IRQ controller */
2277 ppc6xx_irq_init(env);
2280 case CPU_PPC_755_10: /* PowerPC 755 */
2281 case CPU_PPC_755_11:
2282 case CPU_PPC_755_20:
2285 gen_spr_generic(env);
2286 gen_spr_ne_601(env);
2287 /* Memory management */
2291 /* Memory management */
2293 gen_6xx_7xx_soft_tlb(env, 64, 2);
2294 gen_spr_G2_755(env);
2295 /* L2 cache control */
2296 /* XXX : not implemented */
2297 spr_register(env, SPR_ICTC, "ICTC",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 &spr_read_generic, &spr_write_generic,
2301 /* XXX : not implemented */
2302 spr_register(env, SPR_L2PM, "L2PM",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2306 /* Hardware implementation registers */
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_HID0, "HID0",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_HID1, "HID1",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_HID2, "HID2",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2322 /* Allocate hardware IRQ controller */
2323 ppc6xx_irq_init(env);
2328 case CPU_PPC_7400: /* PowerPC 7400 */
2329 case CPU_PPC_7410C: /* PowerPC 7410 */
2332 case CPU_PPC_7441: /* PowerPC 7441 */
2333 case CPU_PPC_7445: /* PowerPC 7445 */
2334 case CPU_PPC_7447: /* PowerPC 7447 */
2335 case CPU_PPC_7447A: /* PowerPC 7447A */
2336 case CPU_PPC_7448: /* PowerPC 7448 */
2337 case CPU_PPC_7450: /* PowerPC 7450 */
2339 case CPU_PPC_7451: /* PowerPC 7451 */
2341 case CPU_PPC_7455: /* PowerPC 7455 */
2344 case CPU_PPC_7457: /* PowerPC 7457 */
2346 case CPU_PPC_7457A: /* PowerPC 7457A */
2350 /* 64 bits PowerPC */
2351 #if defined (TARGET_PPC64)
2353 case CPU_PPC_620: /* PowerPC 620 */
2354 case CPU_PPC_630: /* PowerPC 630 (Power 3) */
2355 case CPU_PPC_631: /* PowerPC 631 (Power 3+) */
2356 case CPU_PPC_POWER4: /* Power 4 */
2357 case CPU_PPC_POWER4P: /* Power 4+ */
2358 case CPU_PPC_POWER5: /* Power 5 */
2359 case CPU_PPC_POWER5P: /* Power 5+ */
2363 case CPU_PPC_970: /* PowerPC 970 */
2364 case CPU_PPC_970FX10: /* PowerPC 970 FX */
2365 case CPU_PPC_970FX20:
2366 case CPU_PPC_970FX21:
2367 case CPU_PPC_970FX30:
2368 case CPU_PPC_970FX31:
2369 case CPU_PPC_970MP10: /* PowerPC 970 MP */
2370 case CPU_PPC_970MP11:
2371 gen_spr_generic(env);
2372 gen_spr_ne_601(env);
2373 /* XXX: not correct */
2378 /* Hardware implementation registers */
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_HID0, "HID0",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_HID1, "HID1",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2389 /* XXX : not implemented */
2390 spr_register(env, SPR_750_HID2, "HID2",
2391 SPR_NOACCESS, SPR_NOACCESS,
2392 &spr_read_generic, &spr_write_generic,
2394 /* Allocate hardware IRQ controller */
2395 ppc970_irq_init(env);
2399 case CPU_PPC_CELL10: /* Cell family */
2400 case CPU_PPC_CELL20:
2401 case CPU_PPC_CELL30:
2402 case CPU_PPC_CELL31:
2407 case CPU_PPC_RS64: /* Apache (RS64/A35) */
2408 case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
2409 case CPU_PPC_RS64III: /* Pulsar (RS64-III) */
2410 case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */
2413 #endif /* defined (TARGET_PPC64) */
2417 case CPU_POWER: /* POWER */
2418 case CPU_POWER2: /* POWER2 */
2423 gen_spr_generic(env);
2424 /* XXX: TODO: allocate internal IRQ controller */
2427 if (env->nb_BATs == -1)
2429 /* Allocate TLBs buffer when needed */
2430 if (env->nb_tlb != 0) {
2431 int nb_tlb = env->nb_tlb;
2432 if (env->id_tlbs != 0)
2434 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2435 /* Pre-compute some useful values */
2436 env->tlb_per_way = env->nb_tlb / env->nb_ways;
2440 #if defined(PPC_DUMP_CPU)
2441 static void dump_sprs (CPUPPCState *env)
2444 uint32_t pvr = env->spr[SPR_PVR];
2445 uint32_t sr, sw, ur, uw;
2448 printf("* SPRs for PVR=%08x\n", pvr);
2449 for (i = 0; i < 32; i++) {
2450 for (j = 0; j < 32; j++) {
2452 spr = &env->spr_cb[n];
2453 #if !defined(CONFIG_USER_ONLY)
2454 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2455 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
2460 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2461 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2462 if (sw || sr || uw || ur) {
2463 printf("%4d (%03x) %8s s%c%c u%c%c\n",
2464 (i << 5) | j, (i << 5) | j, spr->name,
2465 sw ? 'w' : '-', sr ? 'r' : '-',
2466 uw ? 'w' : '-', ur ? 'r' : '-');
2475 /*****************************************************************************/
2479 int fflush (FILE *stream);
2483 PPC_DIRECT = 0, /* Opcode routine */
2484 PPC_INDIRECT = 1, /* Indirect opcode table */
2487 static inline int is_indirect_opcode (void *handler)
2489 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2492 static inline opc_handler_t **ind_table(void *handler)
2494 return (opc_handler_t **)((unsigned long)handler & ~3);
2497 /* Instruction table creation */
2498 /* Opcodes tables creation */
2499 static void fill_new_table (opc_handler_t **table, int len)
2503 for (i = 0; i < len; i++)
2504 table[i] = &invalid_handler;
2507 static int create_new_table (opc_handler_t **table, unsigned char idx)
2509 opc_handler_t **tmp;
2511 tmp = malloc(0x20 * sizeof(opc_handler_t));
2514 fill_new_table(tmp, 0x20);
2515 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2520 static int insert_in_table (opc_handler_t **table, unsigned char idx,
2521 opc_handler_t *handler)
2523 if (table[idx] != &invalid_handler)
2525 table[idx] = handler;
2530 static int register_direct_insn (opc_handler_t **ppc_opcodes,
2531 unsigned char idx, opc_handler_t *handler)
2533 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2534 printf("*** ERROR: opcode %02x already assigned in main "
2535 "opcode table\n", idx);
2542 static int register_ind_in_table (opc_handler_t **table,
2543 unsigned char idx1, unsigned char idx2,
2544 opc_handler_t *handler)
2546 if (table[idx1] == &invalid_handler) {
2547 if (create_new_table(table, idx1) < 0) {
2548 printf("*** ERROR: unable to create indirect table "
2549 "idx=%02x\n", idx1);
2553 if (!is_indirect_opcode(table[idx1])) {
2554 printf("*** ERROR: idx %02x already assigned to a direct "
2559 if (handler != NULL &&
2560 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2561 printf("*** ERROR: opcode %02x already assigned in "
2562 "opcode table %02x\n", idx2, idx1);
2569 static int register_ind_insn (opc_handler_t **ppc_opcodes,
2570 unsigned char idx1, unsigned char idx2,
2571 opc_handler_t *handler)
2575 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2580 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2581 unsigned char idx1, unsigned char idx2,
2582 unsigned char idx3, opc_handler_t *handler)
2584 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2585 printf("*** ERROR: unable to join indirect table idx "
2586 "[%02x-%02x]\n", idx1, idx2);
2589 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2591 printf("*** ERROR: unable to insert opcode "
2592 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2599 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2601 if (insn->opc2 != 0xFF) {
2602 if (insn->opc3 != 0xFF) {
2603 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2604 insn->opc3, &insn->handler) < 0)
2607 if (register_ind_insn(ppc_opcodes, insn->opc1,
2608 insn->opc2, &insn->handler) < 0)
2612 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2619 static int test_opcode_table (opc_handler_t **table, int len)
2623 for (i = 0, count = 0; i < len; i++) {
2624 /* Consistency fixup */
2625 if (table[i] == NULL)
2626 table[i] = &invalid_handler;
2627 if (table[i] != &invalid_handler) {
2628 if (is_indirect_opcode(table[i])) {
2629 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2632 table[i] = &invalid_handler;
2645 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2647 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2648 printf("*** WARNING: no opcode defined !\n");
2651 /*****************************************************************************/
2652 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2654 opcode_t *opc, *start, *end;
2656 fill_new_table(env->opcodes, 0x40);
2657 #if defined(PPC_DUMP_CPU)
2658 printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
2660 def->pvr, def->name, def->insns_flags, def->flags);
2662 if (&opc_start < &opc_end) {
2669 for (opc = start + 1; opc != end; opc++) {
2670 if ((opc->handler.type & def->insns_flags) != 0) {
2671 if (register_insn(env->opcodes, opc) < 0) {
2672 printf("*** ERROR initializing PowerPC instruction "
2673 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2677 #if defined(PPC_DUMP_CPU)
2679 if (opc->opc3 == 0xFF) {
2680 if (opc->opc2 == 0xFF) {
2681 printf(" %02x -- -- (%2d ----) : %s\n",
2682 opc->opc1, opc->opc1, opc->oname);
2684 printf(" %02x %02x -- (%2d %4d) : %s\n",
2685 opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2689 printf(" %02x %02x %02x (%2d %4d) : %s\n",
2690 opc->opc1, opc->opc2, opc->opc3,
2691 opc->opc1, (opc->opc3 << 5) | opc->opc2,
2698 fix_opcode_tables(env->opcodes);
2705 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2707 env->msr_mask = def->msr_mask;
2708 env->flags = def->flags;
2709 if (create_ppc_opcodes(env, def) < 0)
2711 init_ppc_proc(env, def);
2712 #if defined(PPC_DUMP_CPU)
2714 if (env->tlb != NULL) {
2715 printf("%d %s TLB in %d ways\n", env->nb_tlb,
2716 env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2723 /*****************************************************************************/
2724 /* PowerPC CPU definitions */
2725 static ppc_def_t ppc_defs[] = {
2726 /* Embedded PowerPC */
2732 .pvr_mask = 0xFFFF0000,
2733 .insns_flags = PPC_INSNS_401,
2734 .flags = PPC_FLAGS_401,
2739 /* IOP480 (401 microcontroler) */
2742 .pvr = CPU_PPC_IOP480,
2743 .pvr_mask = 0xFFFF0000,
2744 .insns_flags = PPC_INSNS_401,
2745 .flags = PPC_FLAGS_401,
2750 /* IBM Processor for Network Resources */
2753 .pvr = CPU_PPC_COBRA,
2754 .pvr_mask = 0xFFFF0000,
2755 .insns_flags = PPC_INSNS_401,
2756 .flags = PPC_FLAGS_401,
2761 /* Generic PowerPC 403 */
2765 .pvr_mask = 0xFFFFFF00,
2766 .insns_flags = PPC_INSNS_403,
2767 .flags = PPC_FLAGS_403,
2768 .msr_mask = 0x000000000007D23DULL,
2772 /* PowerPC 403 GA */
2775 .pvr = CPU_PPC_403GA,
2776 .pvr_mask = 0xFFFFFF00,
2777 .insns_flags = PPC_INSNS_403,
2778 .flags = PPC_FLAGS_403,
2779 .msr_mask = 0x000000000007D23DULL,
2783 /* PowerPC 403 GB */
2786 .pvr = CPU_PPC_403GB,
2787 .pvr_mask = 0xFFFFFF00,
2788 .insns_flags = PPC_INSNS_403,
2789 .flags = PPC_FLAGS_403,
2790 .msr_mask = 0x000000000007D23DULL,
2794 /* PowerPC 403 GC */
2797 .pvr = CPU_PPC_403GC,
2798 .pvr_mask = 0xFFFFFF00,
2799 .insns_flags = PPC_INSNS_403,
2800 .flags = PPC_FLAGS_403,
2801 .msr_mask = 0x000000000007D23DULL,
2805 /* PowerPC 403 GCX */
2808 .pvr = CPU_PPC_403GCX,
2809 .pvr_mask = 0xFFFFFF00,
2810 .insns_flags = PPC_INSNS_403,
2811 .flags = PPC_FLAGS_403,
2812 .msr_mask = 0x000000000007D23DULL,
2815 /* Generic PowerPC 405 */
2819 .pvr_mask = 0xFFFF0000,
2820 .insns_flags = PPC_INSNS_405,
2821 .flags = PPC_FLAGS_405,
2822 .msr_mask = 0x00000000020EFF30ULL,
2824 /* PowerPC 405 CR */
2828 .pvr_mask = 0xFFFFFFFF,
2829 .insns_flags = PPC_INSNS_405,
2830 .flags = PPC_FLAGS_405,
2831 .msr_mask = 0x00000000020EFF30ULL,
2834 /* PowerPC 405 GP */
2838 .pvr_mask = 0xFFFFFFFF,
2839 .insns_flags = PPC_INSNS_405,
2840 .flags = PPC_FLAGS_405,
2841 .msr_mask = 0x00000000020EFF30ULL,
2844 /* PowerPC 405 EP */
2847 .pvr = CPU_PPC_405EP,
2848 .pvr_mask = 0xFFFFFFFF,
2849 .insns_flags = PPC_INSNS_405,
2850 .flags = PPC_FLAGS_405,
2851 .msr_mask = 0x00000000000ED630ULL,
2854 /* PowerPC 405 EZ */
2857 .pvr = CPU_PPC_405EZ,
2858 .pvr_mask = 0xFFFFFFFF,
2859 .insns_flags = PPC_INSNS_405,
2860 .flags = PPC_FLAGS_405,
2861 .msr_mask = 0x00000000020EFF30ULL,
2865 /* PowerPC 405 GPR */
2868 .pvr = CPU_PPC_405GPR,
2869 .pvr_mask = 0xFFFFFFFF,
2870 .insns_flags = PPC_INSNS_405,
2871 .flags = PPC_FLAGS_405,
2872 .msr_mask = 0x00000000020EFF30ULL,
2875 /* PowerPC 405 D2 */
2878 .pvr = CPU_PPC_405D2,
2879 .pvr_mask = 0xFFFFFFFF,
2880 .insns_flags = PPC_INSNS_405,
2881 .flags = PPC_FLAGS_405,
2882 .msr_mask = 0x00000000020EFF30ULL,
2884 /* PowerPC 405 D4 */
2887 .pvr = CPU_PPC_405D4,
2888 .pvr_mask = 0xFFFFFFFF,
2889 .insns_flags = PPC_INSNS_405,
2890 .flags = PPC_FLAGS_405,
2891 .msr_mask = 0x00000000020EFF30ULL,
2897 .pvr = CPU_PPC_NPE405H,
2898 .pvr_mask = 0xFFFFFFFF,
2899 .insns_flags = PPC_INSNS_405,
2900 .flags = PPC_FLAGS_405,
2901 .msr_mask = 0x00000000020EFF30ULL,
2908 .pvr = CPU_PPC_NPE405L,
2909 .pvr_mask = 0xFFFFFFFF,
2910 .insns_flags = PPC_INSNS_405,
2911 .flags = PPC_FLAGS_405,
2912 .msr_mask = 0x00000000020EFF30ULL,
2919 .pvr = CPU_PPC_STB01000,
2920 .pvr_mask = 0xFFFFFFFF,
2921 .insns_flags = PPC_INSNS_405,
2922 .flags = PPC_FLAGS_405,
2923 .msr_mask = 0x00000000020EFF30ULL,
2930 .pvr = CPU_PPC_STB01010,
2931 .pvr_mask = 0xFFFFFFFF,
2932 .insns_flags = PPC_INSNS_405,
2933 .flags = PPC_FLAGS_405,
2934 .msr_mask = 0x00000000020EFF30ULL,
2941 .pvr = CPU_PPC_STB0210,
2942 .pvr_mask = 0xFFFFFFFF,
2943 .insns_flags = PPC_INSNS_405,
2944 .flags = PPC_FLAGS_405,
2945 .msr_mask = 0x00000000020EFF30ULL,
2952 .pvr = CPU_PPC_STB03,
2953 .pvr_mask = 0xFFFFFFFF,
2954 .insns_flags = PPC_INSNS_405,
2955 .flags = PPC_FLAGS_405,
2956 .msr_mask = 0x00000000020EFF30ULL,
2963 .pvr = CPU_PPC_STB043,
2964 .pvr_mask = 0xFFFFFFFF,
2965 .insns_flags = PPC_INSNS_405,
2966 .flags = PPC_FLAGS_405,
2967 .msr_mask = 0x00000000020EFF30ULL,
2974 .pvr = CPU_PPC_STB045,
2975 .pvr_mask = 0xFFFFFFFF,
2976 .insns_flags = PPC_INSNS_405,
2977 .flags = PPC_FLAGS_405,
2978 .msr_mask = 0x00000000020EFF30ULL,
2985 .pvr = CPU_PPC_STB25,
2986 .pvr_mask = 0xFFFFFFFF,
2987 .insns_flags = PPC_INSNS_405,
2988 .flags = PPC_FLAGS_405,
2989 .msr_mask = 0x00000000020EFF30ULL,
2996 .pvr = CPU_PPC_STB130,
2997 .pvr_mask = 0xFFFFFFFF,
2998 .insns_flags = PPC_INSNS_405,
2999 .flags = PPC_FLAGS_405,
3000 .msr_mask = 0x00000000020EFF30ULL,
3003 /* Xilinx PowerPC 405 cores */
3007 .pvr = CPU_PPC_X2VP4,
3008 .pvr_mask = 0xFFFFFFFF,
3009 .insns_flags = PPC_INSNS_405,
3010 .flags = PPC_FLAGS_405,
3011 .msr_mask = 0x00000000020EFF30ULL,
3015 .pvr = CPU_PPC_X2VP7,
3016 .pvr_mask = 0xFFFFFFFF,
3017 .insns_flags = PPC_INSNS_405,
3018 .flags = PPC_FLAGS_405,
3019 .msr_mask = 0x00000000020EFF30ULL,
3023 .pvr = CPU_PPC_X2VP20,
3024 .pvr_mask = 0xFFFFFFFF,
3025 .insns_flags = PPC_INSNS_405,
3026 .flags = PPC_FLAGS_405,
3027 .msr_mask = 0x00000000020EFF30ULL,
3031 .pvr = CPU_PPC_X2VP50,
3032 .pvr_mask = 0xFFFFFFFF,
3033 .insns_flags = PPC_INSNS_405,
3034 .flags = PPC_FLAGS_405,
3035 .msr_mask = 0x00000000020EFF30ULL,
3039 /* PowerPC 440 EP */
3042 .pvr = CPU_PPC_440EP,
3043 .pvr_mask = 0xFFFF0000,
3044 .insns_flags = PPC_INSNS_440,
3045 .flags = PPC_FLAGS_440,
3046 .msr_mask = 0x000000000006D630ULL,
3050 /* PowerPC 440 GR */
3053 .pvr = CPU_PPC_440GR,
3054 .pvr_mask = 0xFFFF0000,
3055 .insns_flags = PPC_INSNS_440,
3056 .flags = PPC_FLAGS_440,
3057 .msr_mask = 0x000000000006D630ULL,
3061 /* PowerPC 440 GP */
3064 .pvr = CPU_PPC_440GP,
3065 .pvr_mask = 0xFFFFFF00,
3066 .insns_flags = PPC_INSNS_440,
3067 .flags = PPC_FLAGS_440,
3068 .msr_mask = 0x000000000006D630ULL,
3072 /* PowerPC 440 GX */
3075 .pvr = CPU_PPC_440GX,
3076 .pvr_mask = 0xFFFF0000,
3077 .insns_flags = PPC_INSNS_405,
3078 .flags = PPC_FLAGS_440,
3079 .msr_mask = 0x000000000006D630ULL,
3083 /* PowerPC 440 GXc */
3086 .pvr = CPU_PPC_440GXC,
3087 .pvr_mask = 0xFFFF0000,
3088 .insns_flags = PPC_INSNS_405,
3089 .flags = PPC_FLAGS_440,
3090 .msr_mask = 0x000000000006D630ULL,
3094 /* PowerPC 440 GXf */
3097 .pvr = CPU_PPC_440GXF,
3098 .pvr_mask = 0xFFFF0000,
3099 .insns_flags = PPC_INSNS_405,
3100 .flags = PPC_FLAGS_440,
3101 .msr_mask = 0x000000000006D630ULL,
3105 /* PowerPC 440 SP */
3108 .pvr = CPU_PPC_440SP,
3109 .pvr_mask = 0xFFFF0000,
3110 .insns_flags = PPC_INSNS_405,
3111 .flags = PPC_FLAGS_440,
3112 .msr_mask = 0x000000000006D630ULL,
3116 /* PowerPC 440 SP2 */
3119 .pvr = CPU_PPC_440SP2,
3120 .pvr_mask = 0xFFFF0000,
3121 .insns_flags = PPC_INSNS_405,
3122 .flags = PPC_FLAGS_440,
3123 .msr_mask = 0x000000000006D630ULL,
3127 /* PowerPC 440 SPE */
3130 .pvr = CPU_PPC_440SPE,
3131 .pvr_mask = 0xFFFF0000,
3132 .insns_flags = PPC_INSNS_405,
3133 .flags = PPC_FLAGS_440,
3134 .msr_mask = 0x000000000006D630ULL,
3137 /* Fake generic BookE PowerPC */
3140 .pvr = CPU_PPC_e500,
3141 .pvr_mask = 0xFFFFFFFF,
3142 .insns_flags = PPC_INSNS_BOOKE,
3143 .flags = PPC_FLAGS_BOOKE,
3144 .msr_mask = 0x000000000006D630ULL,
3146 /* PowerPC 460 cores - TODO */
3147 /* PowerPC MPC 5xx cores - TODO */
3148 /* PowerPC MPC 8xx cores - TODO */
3149 /* PowerPC MPC 8xxx cores - TODO */
3150 /* e200 cores - TODO */
3151 /* e500 cores - TODO */
3152 /* e600 cores - TODO */
3154 /* 32 bits "classic" PowerPC */
3160 .pvr_mask = 0xFFFF0000,
3161 .insns_flags = PPC_INSNS_601,
3162 .flags = PPC_FLAGS_601,
3163 .msr_mask = 0x000000000000FD70ULL,
3171 .pvr_mask = 0xFFFF0000,
3172 .insns_flags = PPC_INSNS_602,
3173 .flags = PPC_FLAGS_602,
3174 .msr_mask = 0x0000000000C7FF73ULL,
3181 .pvr_mask = 0xFFFFFFFF,
3182 .insns_flags = PPC_INSNS_603,
3183 .flags = PPC_FLAGS_603,
3184 .msr_mask = 0x000000000007FF73ULL,
3189 .pvr = CPU_PPC_603E,
3190 .pvr_mask = 0xFFFFFFFF,
3191 .insns_flags = PPC_INSNS_603,
3192 .flags = PPC_FLAGS_603,
3193 .msr_mask = 0x000000000007FF73ULL,
3197 .pvr = CPU_PPC_603E,
3198 .pvr_mask = 0xFFFFFFFF,
3199 .insns_flags = PPC_INSNS_603,
3200 .flags = PPC_FLAGS_603,
3201 .msr_mask = 0x000000000007FF73ULL,
3206 .pvr = CPU_PPC_603P,
3207 .pvr_mask = 0xFFFFFFFF,
3208 .insns_flags = PPC_INSNS_603,
3209 .flags = PPC_FLAGS_603,
3210 .msr_mask = 0x000000000007FF73ULL,
3215 .pvr = CPU_PPC_603E7,
3216 .pvr_mask = 0xFFFFFFFF,
3217 .insns_flags = PPC_INSNS_603,
3218 .flags = PPC_FLAGS_603,
3219 .msr_mask = 0x000000000007FF73ULL,
3221 /* PowerPC 603e7v */
3224 .pvr = CPU_PPC_603E7v,
3225 .pvr_mask = 0xFFFFFFFF,
3226 .insns_flags = PPC_INSNS_603,
3227 .flags = PPC_FLAGS_603,
3228 .msr_mask = 0x000000000007FF73ULL,
3230 /* PowerPC 603e7v2 */
3233 .pvr = CPU_PPC_603E7v2,
3234 .pvr_mask = 0xFFFFFFFF,
3235 .insns_flags = PPC_INSNS_603,
3236 .flags = PPC_FLAGS_603,
3237 .msr_mask = 0x000000000007FF73ULL,
3242 .pvr = CPU_PPC_603R,
3243 .pvr_mask = 0xFFFFFFFF,
3244 .insns_flags = PPC_INSNS_603,
3245 .flags = PPC_FLAGS_603,
3246 .msr_mask = 0x000000000007FF73ULL,
3249 .name = "Goldeneye",
3250 .pvr = CPU_PPC_603R,
3251 .pvr_mask = 0xFFFFFFFF,
3252 .insns_flags = PPC_INSNS_603,
3253 .flags = PPC_FLAGS_603,
3254 .msr_mask = 0x000000000007FF73ULL,
3257 /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3261 .pvr_mask = 0xFFFF0000,
3262 .insns_flags = PPC_INSNS_G2,
3263 .flags = PPC_FLAGS_G2,
3264 .msr_mask = 0x000000000006FFF2ULL,
3268 .pvr = CPU_PPC_G2H4,
3269 .pvr_mask = 0xFFFF0000,
3270 .insns_flags = PPC_INSNS_G2,
3271 .flags = PPC_FLAGS_G2,
3272 .msr_mask = 0x000000000006FFF2ULL,
3276 .pvr = CPU_PPC_G2gp,
3277 .pvr_mask = 0xFFFF0000,
3278 .insns_flags = PPC_INSNS_G2,
3279 .flags = PPC_FLAGS_G2,
3280 .msr_mask = 0x000000000006FFF2ULL,
3284 .pvr = CPU_PPC_G2ls,
3285 .pvr_mask = 0xFFFF0000,
3286 .insns_flags = PPC_INSNS_G2,
3287 .flags = PPC_FLAGS_G2,
3288 .msr_mask = 0x000000000006FFF2ULL,
3290 { /* Same as G2, with LE mode support */
3292 .pvr = CPU_PPC_G2LE,
3293 .pvr_mask = 0xFFFF0000,
3294 .insns_flags = PPC_INSNS_G2,
3295 .flags = PPC_FLAGS_G2,
3296 .msr_mask = 0x000000000007FFF3ULL,
3300 .pvr = CPU_PPC_G2LEgp,
3301 .pvr_mask = 0xFFFF0000,
3302 .insns_flags = PPC_INSNS_G2,
3303 .flags = PPC_FLAGS_G2,
3304 .msr_mask = 0x000000000007FFF3ULL,
3308 .pvr = CPU_PPC_G2LEls,
3309 .pvr_mask = 0xFFFF0000,
3310 .insns_flags = PPC_INSNS_G2,
3311 .flags = PPC_FLAGS_G2,
3312 .msr_mask = 0x000000000007FFF3ULL,
3319 .pvr_mask = 0xFFFFFFFF,
3320 .insns_flags = PPC_INSNS_604,
3321 .flags = PPC_FLAGS_604,
3322 .msr_mask = 0x000000000005FF77ULL,
3327 .pvr = CPU_PPC_604E,
3328 .pvr_mask = 0xFFFFFFFF,
3329 .insns_flags = PPC_INSNS_604,
3330 .flags = PPC_FLAGS_604,
3331 .msr_mask = 0x000000000005FF77ULL,
3336 .pvr = CPU_PPC_604R,
3337 .pvr_mask = 0xFFFFFFFF,
3338 .insns_flags = PPC_INSNS_604,
3339 .flags = PPC_FLAGS_604,
3340 .msr_mask = 0x000000000005FF77ULL,
3346 .pvr_mask = 0xFFFFFFFF,
3347 .insns_flags = PPC_INSNS_7x0,
3348 .flags = PPC_FLAGS_7x0,
3349 .msr_mask = 0x000000000007FF77ULL,
3355 .pvr_mask = 0xFFFFFFFF,
3356 .insns_flags = PPC_INSNS_7x0,
3357 .flags = PPC_FLAGS_7x0,
3358 .msr_mask = 0x000000000007FF77ULL,
3363 .pvr_mask = 0xFFFFFFFF,
3364 .insns_flags = PPC_INSNS_7x0,
3365 .flags = PPC_FLAGS_7x0,
3366 .msr_mask = 0x000000000007FF77ULL,
3373 .pvr_mask = 0xFFFFF000,
3374 .insns_flags = PPC_INSNS_7x5,
3375 .flags = PPC_FLAGS_7x5,
3376 .msr_mask = 0x000000000007FF77ULL,
3379 .name = "Goldfinger",
3381 .pvr_mask = 0xFFFFF000,
3382 .insns_flags = PPC_INSNS_7x5,
3383 .flags = PPC_FLAGS_7x5,
3384 .msr_mask = 0x000000000007FF77ULL,
3391 .pvr_mask = 0xFFFFFFFF,
3392 .insns_flags = PPC_INSNS_7x0,
3393 .flags = PPC_FLAGS_7x0,
3394 .msr_mask = 0x000000000007FF77ULL,
3401 .pvr_mask = 0xFFFFF000,
3402 .insns_flags = PPC_INSNS_7x5,
3403 .flags = PPC_FLAGS_7x5,
3404 .msr_mask = 0x000000000007FF77ULL,
3410 .pvr = CPU_PPC_74xP,
3411 .pvr_mask = 0xFFFFFFFF,
3412 .insns_flags = PPC_INSNS_7x0,
3413 .flags = PPC_FLAGS_7x0,
3414 .msr_mask = 0x000000000007FF77ULL,
3417 .name = "Conan/Doyle",
3418 .pvr = CPU_PPC_74xP,
3419 .pvr_mask = 0xFFFFFFFF,
3420 .insns_flags = PPC_INSNS_7x0,
3421 .flags = PPC_FLAGS_7x0,
3422 .msr_mask = 0x000000000007FF77ULL,
3428 .pvr = CPU_PPC_74xP,
3429 .pvr_mask = 0xFFFFF000,
3430 .insns_flags = PPC_INSNS_7x5,
3431 .flags = PPC_FLAGS_7x5,
3432 .msr_mask = 0x000000000007FF77ULL,
3438 .pvr = CPU_PPC_74xP,
3439 .pvr_mask = 0xFFFFFFFF,
3440 .insns_flags = PPC_INSNS_7x0,
3441 .flags = PPC_FLAGS_7x0,
3442 .msr_mask = 0x000000000007FF77ULL,
3448 .pvr = CPU_PPC_74xP,
3449 .pvr_mask = 0xFFFFF000,
3450 .insns_flags = PPC_INSNS_7x5,
3451 .flags = PPC_FLAGS_7x5,
3452 .msr_mask = 0x000000000007FF77ULL,
3455 /* IBM 750CXe (G3 embedded) */
3458 .pvr = CPU_PPC_750CXE,
3459 .pvr_mask = 0xFFFFFFFF,
3460 .insns_flags = PPC_INSNS_7x0,
3461 .flags = PPC_FLAGS_7x0,
3462 .msr_mask = 0x000000000007FF77ULL,
3464 /* IBM 750FX (G3 embedded) */
3467 .pvr = CPU_PPC_750FX,
3468 .pvr_mask = 0xFFFFFFFF,
3469 .insns_flags = PPC_INSNS_7x0,
3470 .flags = PPC_FLAGS_7x0,
3471 .msr_mask = 0x000000000007FF77ULL,
3473 /* IBM 750GX (G3 embedded) */
3476 .pvr = CPU_PPC_750GX,
3477 .pvr_mask = 0xFFFFFFFF,
3478 .insns_flags = PPC_INSNS_7x0,
3479 .flags = PPC_FLAGS_7x0,
3480 .msr_mask = 0x000000000007FF77ULL,
3486 .pvr = CPU_PPC_7400,
3487 .pvr_mask = 0xFFFF0000,
3488 .insns_flags = PPC_INSNS_74xx,
3489 .flags = PPC_FLAGS_74xx,
3490 .msr_mask = 0x000000000205FF77ULL,
3494 /* PowerPC 7400 (G4) */
3497 .pvr = CPU_PPC_7400,
3498 .pvr_mask = 0xFFFF0000,
3499 .insns_flags = PPC_INSNS_74xx,
3500 .flags = PPC_FLAGS_74xx,
3501 .msr_mask = 0x000000000205FF77ULL,
3505 .pvr = CPU_PPC_7400,
3506 .pvr_mask = 0xFFFF0000,
3507 .insns_flags = PPC_INSNS_74xx,
3508 .flags = PPC_FLAGS_74xx,
3509 .msr_mask = 0x000000000205FF77ULL,
3513 /* PowerPC 7410 (G4) */
3516 .pvr = CPU_PPC_7410,
3517 .pvr_mask = 0xFFFF0000,
3518 .insns_flags = PPC_INSNS_74xx,
3519 .flags = PPC_FLAGS_74xx,
3520 .msr_mask = 0x000000000205FF77ULL,
3524 .pvr = CPU_PPC_7410,
3525 .pvr_mask = 0xFFFF0000,
3526 .insns_flags = PPC_INSNS_74xx,
3527 .flags = PPC_FLAGS_74xx,
3528 .msr_mask = 0x000000000205FF77ULL,
3536 /* PowerPC 7450 (G4) */
3539 .pvr = CPU_PPC_7450,
3540 .pvr_mask = 0xFFFF0000,
3541 .insns_flags = PPC_INSNS_74xx,
3542 .flags = PPC_FLAGS_74xx,
3543 .msr_mask = 0x000000000205FF77ULL,
3547 .pvr = CPU_PPC_7450,
3548 .pvr_mask = 0xFFFF0000,
3549 .insns_flags = PPC_INSNS_74xx,
3550 .flags = PPC_FLAGS_74xx,
3551 .msr_mask = 0x000000000205FF77ULL,
3556 /* PowerPC 7455 (G4) */
3559 .pvr = CPU_PPC_7455,
3560 .pvr_mask = 0xFFFF0000,
3561 .insns_flags = PPC_INSNS_74xx,
3562 .flags = PPC_FLAGS_74xx,
3563 .msr_mask = 0x000000000205FF77ULL,
3567 .pvr = CPU_PPC_7455,
3568 .pvr_mask = 0xFFFF0000,
3569 .insns_flags = PPC_INSNS_74xx,
3570 .flags = PPC_FLAGS_74xx,
3571 .msr_mask = 0x000000000205FF77ULL,
3575 /* PowerPC 7457 (G4) */
3578 .pvr = CPU_PPC_7457,
3579 .pvr_mask = 0xFFFF0000,
3580 .insns_flags = PPC_INSNS_74xx,
3581 .flags = PPC_FLAGS_74xx,
3582 .msr_mask = 0x000000000205FF77ULL,
3586 .pvr = CPU_PPC_7457,
3587 .pvr_mask = 0xFFFF0000,
3588 .insns_flags = PPC_INSNS_74xx,
3589 .flags = PPC_FLAGS_74xx,
3590 .msr_mask = 0x000000000205FF77ULL,
3594 /* PowerPC 7457A (G4) */
3597 .pvr = CPU_PPC_7457A,
3598 .pvr_mask = 0xFFFF0000,
3599 .insns_flags = PPC_INSNS_74xx,
3600 .flags = PPC_FLAGS_74xx,
3601 .msr_mask = 0x000000000205FF77ULL,
3604 .name = "Apollo 7 PM",
3605 .pvr = CPU_PPC_7457A,
3606 .pvr_mask = 0xFFFF0000,
3607 .insns_flags = PPC_INSNS_74xx,
3608 .flags = PPC_FLAGS_74xx,
3609 .msr_mask = 0x000000000205FF77ULL,
3612 /* 64 bits PowerPC */
3613 #if defined (TARGET_PPC64)
3619 .pvr_mask = 0xFFFF0000,
3620 .insns_flags = PPC_INSNS_620,
3621 .flags = PPC_FLAGS_620,
3622 .msr_mask = 0x800000000005FF73ULL,
3626 /* PowerPC 630 (POWER3) */
3630 .pvr_mask = 0xFFFF0000,
3631 .insns_flags = PPC_INSNS_630,
3632 .flags = PPC_FLAGS_630,
3638 .pvr_mask = 0xFFFF0000,
3639 .insns_flags = PPC_INSNS_630,
3640 .flags = PPC_FLAGS_630,
3645 /* PowerPC 631 (Power 3+)*/
3649 .pvr_mask = 0xFFFF0000,
3650 .insns_flags = PPC_INSNS_631,
3651 .flags = PPC_FLAGS_631,
3657 .pvr_mask = 0xFFFF0000,
3658 .insns_flags = PPC_INSNS_631,
3659 .flags = PPC_FLAGS_631,
3667 .pvr = CPU_PPC_POWER4,
3668 .pvr_mask = 0xFFFF0000,
3669 .insns_flags = PPC_INSNS_POWER4,
3670 .flags = PPC_FLAGS_POWER4,
3678 .pvr = CPU_PPC_POWER4P,
3679 .pvr_mask = 0xFFFF0000,
3680 .insns_flags = PPC_INSNS_POWER4,
3681 .flags = PPC_FLAGS_POWER4,
3689 .pvr = CPU_PPC_POWER5,
3690 .pvr_mask = 0xFFFF0000,
3691 .insns_flags = PPC_INSNS_POWER5,
3692 .flags = PPC_FLAGS_POWER5,
3700 .pvr = CPU_PPC_POWER5P,
3701 .pvr_mask = 0xFFFF0000,
3702 .insns_flags = PPC_INSNS_POWER5,
3703 .flags = PPC_FLAGS_POWER5,
3712 .pvr_mask = 0xFFFF0000,
3713 .insns_flags = PPC_INSNS_970,
3714 .flags = PPC_FLAGS_970,
3715 .msr_mask = 0x900000000204FF36ULL,
3719 /* PowerPC 970FX (G5) */
3722 .pvr = CPU_PPC_970FX,
3723 .pvr_mask = 0xFFFF0000,
3724 .insns_flags = PPC_INSNS_970FX,
3725 .flags = PPC_FLAGS_970FX,
3726 .msr_mask = 0x800000000204FF36ULL,
3730 /* RS64 (Apache/A35) */
3731 /* This one seems to support the whole POWER2 instruction set
3732 * and the PowerPC 64 one.
3736 .pvr = CPU_PPC_RS64,
3737 .pvr_mask = 0xFFFF0000,
3738 .insns_flags = PPC_INSNS_RS64,
3739 .flags = PPC_FLAGS_RS64,
3744 .pvr = CPU_PPC_RS64,
3745 .pvr_mask = 0xFFFF0000,
3746 .insns_flags = PPC_INSNS_RS64,
3747 .flags = PPC_FLAGS_RS64,
3752 .pvr = CPU_PPC_RS64,
3753 .pvr_mask = 0xFFFF0000,
3754 .insns_flags = PPC_INSNS_RS64,
3755 .flags = PPC_FLAGS_RS64,
3760 /* RS64-II (NorthStar/A50) */
3763 .pvr = CPU_PPC_RS64II,
3764 .pvr_mask = 0xFFFF0000,
3765 .insns_flags = PPC_INSNS_RS64,
3766 .flags = PPC_FLAGS_RS64,
3771 .pvr = CPU_PPC_RS64II,
3772 .pvr_mask = 0xFFFF0000,
3773 .insns_flags = PPC_INSNS_RS64,
3774 .flags = PPC_FLAGS_RS64,
3779 .pvr = CPU_PPC_RS64II,
3780 .pvr_mask = 0xFFFF0000,
3781 .insns_flags = PPC_INSNS_RS64,
3782 .flags = PPC_FLAGS_RS64,
3787 /* RS64-III (Pulsar) */
3790 .pvr = CPU_PPC_RS64III,
3791 .pvr_mask = 0xFFFF0000,
3792 .insns_flags = PPC_INSNS_RS64,
3793 .flags = PPC_FLAGS_RS64,
3798 .pvr = CPU_PPC_RS64III,
3799 .pvr_mask = 0xFFFF0000,
3800 .insns_flags = PPC_INSNS_RS64,
3801 .flags = PPC_FLAGS_RS64,
3806 /* RS64-IV (IceStar/IStar/SStar) */
3809 .pvr = CPU_PPC_RS64IV,
3810 .pvr_mask = 0xFFFF0000,
3811 .insns_flags = PPC_INSNS_RS64,
3812 .flags = PPC_FLAGS_RS64,
3817 .pvr = CPU_PPC_RS64IV,
3818 .pvr_mask = 0xFFFF0000,
3819 .insns_flags = PPC_INSNS_RS64,
3820 .flags = PPC_FLAGS_RS64,
3825 .pvr = CPU_PPC_RS64IV,
3826 .pvr_mask = 0xFFFF0000,
3827 .insns_flags = PPC_INSNS_RS64,
3828 .flags = PPC_FLAGS_RS64,
3833 .pvr = CPU_PPC_RS64IV,
3834 .pvr_mask = 0xFFFF0000,
3835 .insns_flags = PPC_INSNS_RS64,
3836 .flags = PPC_FLAGS_RS64,
3842 /* Original POWER */
3846 .pvr_mask = 0xFFFF0000,
3847 .insns_flags = PPC_INSNS_POWER,
3848 .flags = PPC_FLAGS_POWER,
3852 #endif /* defined (TARGET_PPC64) */
3858 .pvr_mask = 0xFFFF0000,
3859 .insns_flags = PPC_INSNS_POWER,
3860 .flags = PPC_FLAGS_POWER,
3864 /* Generic PowerPCs */
3869 .pvr_mask = 0xFFFF0000,
3870 .insns_flags = PPC_INSNS_PPC64,
3871 .flags = PPC_FLAGS_PPC64,
3872 .msr_mask = 0xA00000000204FF36ULL,
3878 .pvr_mask = 0xFFFFFFFF,
3879 .insns_flags = PPC_INSNS_PPC32,
3880 .flags = PPC_FLAGS_PPC32,
3881 .msr_mask = 0x000000000005FF77ULL,
3887 .pvr_mask = 0xFFFFFFFF,
3888 .insns_flags = PPC_INSNS_PPC32,
3889 .flags = PPC_FLAGS_PPC32,
3890 .msr_mask = 0x000000000005FF77ULL,
3894 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
3900 for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
3901 if (strcasecmp(name, ppc_defs[i].name) == 0) {
3902 *def = &ppc_defs[i];
3911 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
3917 for (i = 0; ppc_defs[i].name != NULL; i++) {
3918 if ((pvr & ppc_defs[i].pvr_mask) ==
3919 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
3920 *def = &ppc_defs[i];
3929 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3933 for (i = 0; ; i++) {
3934 (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
3936 ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
3937 if (strcmp(ppc_defs[i].name, "ppc") == 0)