4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include "qemu-common.h"
34 //#define DEBUG_FEATURES
37 typedef struct sparc_def_t sparc_def_t;
41 target_ulong iu_version;
45 uint32_t mmu_ctpr_mask;
46 uint32_t mmu_cxr_mask;
47 uint32_t mmu_sfsr_mask;
48 uint32_t mmu_trcr_mask;
53 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
55 /* Sparc MMU emulation */
59 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
63 spin_lock(&global_cpu_lock);
68 spin_unlock(&global_cpu_lock);
71 #if defined(CONFIG_USER_ONLY)
73 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
74 int mmu_idx, int is_softmmu)
77 env1->exception_index = TT_TFAULT;
79 env1->exception_index = TT_DFAULT;
85 #ifndef TARGET_SPARC64
87 * Sparc V8 Reference MMU (SRMMU)
89 static const int access_table[8][8] = {
90 { 0, 0, 0, 0, 8, 0, 12, 12 },
91 { 0, 0, 0, 0, 8, 0, 0, 0 },
92 { 8, 8, 0, 0, 0, 8, 12, 12 },
93 { 8, 8, 0, 0, 0, 8, 0, 0 },
94 { 8, 0, 8, 0, 8, 8, 12, 12 },
95 { 8, 0, 8, 0, 8, 0, 8, 0 },
96 { 8, 8, 8, 0, 8, 8, 12, 12 },
97 { 8, 8, 8, 0, 8, 8, 8, 0 }
100 static const int perm_table[2][8] = {
103 PAGE_READ | PAGE_WRITE,
104 PAGE_READ | PAGE_EXEC,
105 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
107 PAGE_READ | PAGE_WRITE,
108 PAGE_READ | PAGE_EXEC,
109 PAGE_READ | PAGE_WRITE | PAGE_EXEC
113 PAGE_READ | PAGE_WRITE,
114 PAGE_READ | PAGE_EXEC,
115 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
123 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
124 int *prot, int *access_index,
125 target_ulong address, int rw, int mmu_idx)
127 int access_perms = 0;
128 target_phys_addr_t pde_ptr;
130 target_ulong virt_addr;
131 int error_code = 0, is_dirty, is_user;
132 unsigned long page_offset;
134 is_user = mmu_idx == MMU_USER_IDX;
135 virt_addr = address & TARGET_PAGE_MASK;
137 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
138 // Boot mode: instruction fetches are taken from PROM
139 if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
140 *physical = env->prom_addr | (address & 0x7ffffULL);
141 *prot = PAGE_READ | PAGE_EXEC;
145 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
149 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
150 *physical = 0xffffffffffff0000ULL;
152 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
153 /* Context base + context number */
154 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
155 pde = ldl_phys(pde_ptr);
158 switch (pde & PTE_ENTRYTYPE_MASK) {
160 case 0: /* Invalid */
162 case 2: /* L0 PTE, maybe should not happen? */
163 case 3: /* Reserved */
166 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
167 pde = ldl_phys(pde_ptr);
169 switch (pde & PTE_ENTRYTYPE_MASK) {
171 case 0: /* Invalid */
172 return (1 << 8) | (1 << 2);
173 case 3: /* Reserved */
174 return (1 << 8) | (4 << 2);
176 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
177 pde = ldl_phys(pde_ptr);
179 switch (pde & PTE_ENTRYTYPE_MASK) {
181 case 0: /* Invalid */
182 return (2 << 8) | (1 << 2);
183 case 3: /* Reserved */
184 return (2 << 8) | (4 << 2);
186 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
187 pde = ldl_phys(pde_ptr);
189 switch (pde & PTE_ENTRYTYPE_MASK) {
191 case 0: /* Invalid */
192 return (3 << 8) | (1 << 2);
193 case 1: /* PDE, should not happen */
194 case 3: /* Reserved */
195 return (3 << 8) | (4 << 2);
197 virt_addr = address & TARGET_PAGE_MASK;
198 page_offset = (address & TARGET_PAGE_MASK) &
199 (TARGET_PAGE_SIZE - 1);
203 virt_addr = address & ~0x3ffff;
204 page_offset = address & 0x3ffff;
208 virt_addr = address & ~0xffffff;
209 page_offset = address & 0xffffff;
213 /* update page modified and dirty bits */
214 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
215 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
216 pde |= PG_ACCESSED_MASK;
218 pde |= PG_MODIFIED_MASK;
219 stl_phys_notdirty(pde_ptr, pde);
222 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
223 error_code = access_table[*access_index][access_perms];
224 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
227 /* the page can be put in the TLB */
228 *prot = perm_table[is_user][access_perms];
229 if (!(pde & PG_MODIFIED_MASK)) {
230 /* only set write access if already dirty... otherwise wait
232 *prot &= ~PAGE_WRITE;
235 /* Even if large ptes, we map only one 4KB page in the cache to
236 avoid filling it too fast */
237 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
241 /* Perform address translation */
242 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
243 int mmu_idx, int is_softmmu)
245 target_phys_addr_t paddr;
247 int error_code = 0, prot, ret = 0, access_index;
249 error_code = get_physical_address(env, &paddr, &prot, &access_index,
250 address, rw, mmu_idx);
251 if (error_code == 0) {
252 vaddr = address & TARGET_PAGE_MASK;
253 paddr &= TARGET_PAGE_MASK;
255 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
256 TARGET_FMT_lx "\n", address, paddr, vaddr);
258 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
262 if (env->mmuregs[3]) /* Fault status register */
263 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
264 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
265 env->mmuregs[4] = address; /* Fault address register */
267 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
268 // No fault mode: if a mapping is available, just override
269 // permissions. If no mapping is available, redirect accesses to
270 // neverland. Fake/overridden mappings will be flushed when
271 // switching to normal mode.
272 vaddr = address & TARGET_PAGE_MASK;
273 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
274 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
278 env->exception_index = TT_TFAULT;
280 env->exception_index = TT_DFAULT;
285 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
287 target_phys_addr_t pde_ptr;
290 /* Context base + context number */
291 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
292 (env->mmuregs[2] << 2);
293 pde = ldl_phys(pde_ptr);
295 switch (pde & PTE_ENTRYTYPE_MASK) {
297 case 0: /* Invalid */
298 case 2: /* PTE, maybe should not happen? */
299 case 3: /* Reserved */
304 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
305 pde = ldl_phys(pde_ptr);
307 switch (pde & PTE_ENTRYTYPE_MASK) {
309 case 0: /* Invalid */
310 case 3: /* Reserved */
317 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
318 pde = ldl_phys(pde_ptr);
320 switch (pde & PTE_ENTRYTYPE_MASK) {
322 case 0: /* Invalid */
323 case 3: /* Reserved */
330 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
331 pde = ldl_phys(pde_ptr);
333 switch (pde & PTE_ENTRYTYPE_MASK) {
335 case 0: /* Invalid */
336 case 1: /* PDE, should not happen */
337 case 3: /* Reserved */
349 void dump_mmu(CPUState *env)
351 target_ulong va, va1, va2;
352 unsigned int n, m, o;
353 target_phys_addr_t pde_ptr, pa;
356 printf("MMU dump:\n");
357 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
358 pde = ldl_phys(pde_ptr);
359 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
360 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
361 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
362 pde = mmu_probe(env, va, 2);
364 pa = cpu_get_phys_page_debug(env, va);
365 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
366 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
367 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
368 pde = mmu_probe(env, va1, 1);
370 pa = cpu_get_phys_page_debug(env, va1);
371 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
372 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
373 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
374 pde = mmu_probe(env, va2, 0);
376 pa = cpu_get_phys_page_debug(env, va2);
377 printf(" VA: " TARGET_FMT_lx ", PA: "
378 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
386 printf("MMU dump ends\n");
388 #endif /* DEBUG_MMU */
390 #else /* !TARGET_SPARC64 */
392 * UltraSparc IIi I/DMMUs
394 static int get_physical_address_data(CPUState *env,
395 target_phys_addr_t *physical, int *prot,
396 target_ulong address, int rw, int is_user)
401 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
403 *prot = PAGE_READ | PAGE_WRITE;
407 for (i = 0; i < 64; i++) {
408 switch ((env->dtlb_tte[i] >> 61) & 3) {
411 mask = 0xffffffffffffe000ULL;
414 mask = 0xffffffffffff0000ULL;
417 mask = 0xfffffffffff80000ULL;
420 mask = 0xffffffffffc00000ULL;
423 // ctx match, vaddr match?
424 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
425 (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
427 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
428 ((env->dtlb_tte[i] & 0x4) && is_user) ||
429 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
430 if (env->dmmuregs[3]) /* Fault status register */
431 env->dmmuregs[3] = 2; /* overflow (not read before
433 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
434 env->dmmuregs[4] = address; /* Fault address register */
435 env->exception_index = TT_DFAULT;
437 printf("DFAULT at 0x%" PRIx64 "\n", address);
441 *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
442 (address & ~mask & 0x1fffffff000ULL);
444 if (env->dtlb_tte[i] & 0x2)
450 printf("DMISS at 0x%" PRIx64 "\n", address);
452 env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
453 env->exception_index = TT_DMISS;
457 static int get_physical_address_code(CPUState *env,
458 target_phys_addr_t *physical, int *prot,
459 target_ulong address, int is_user)
464 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
470 for (i = 0; i < 64; i++) {
471 switch ((env->itlb_tte[i] >> 61) & 3) {
474 mask = 0xffffffffffffe000ULL;
477 mask = 0xffffffffffff0000ULL;
480 mask = 0xfffffffffff80000ULL;
483 mask = 0xffffffffffc00000ULL;
486 // ctx match, vaddr match?
487 if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
488 (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
490 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
491 ((env->itlb_tte[i] & 0x4) && is_user)) {
492 if (env->immuregs[3]) /* Fault status register */
493 env->immuregs[3] = 2; /* overflow (not read before
495 env->immuregs[3] |= (is_user << 3) | 1;
496 env->exception_index = TT_TFAULT;
498 printf("TFAULT at 0x%" PRIx64 "\n", address);
502 *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
503 (address & ~mask & 0x1fffffff000ULL);
509 printf("TMISS at 0x%" PRIx64 "\n", address);
511 env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
512 env->exception_index = TT_TMISS;
516 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
517 int *prot, int *access_index,
518 target_ulong address, int rw, int mmu_idx)
520 int is_user = mmu_idx == MMU_USER_IDX;
523 return get_physical_address_code(env, physical, prot, address,
526 return get_physical_address_data(env, physical, prot, address, rw,
530 /* Perform address translation */
531 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
532 int mmu_idx, int is_softmmu)
534 target_ulong virt_addr, vaddr;
535 target_phys_addr_t paddr;
536 int error_code = 0, prot, ret = 0, access_index;
538 error_code = get_physical_address(env, &paddr, &prot, &access_index,
539 address, rw, mmu_idx);
540 if (error_code == 0) {
541 virt_addr = address & TARGET_PAGE_MASK;
542 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
543 (TARGET_PAGE_SIZE - 1));
545 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64
546 "\n", address, paddr, vaddr);
548 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
556 void dump_mmu(CPUState *env)
561 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n",
562 env->dmmuregs[1], env->dmmuregs[2]);
563 if ((env->lsu & DMMU_E) == 0) {
564 printf("DMMU disabled\n");
566 printf("DMMU dump:\n");
567 for (i = 0; i < 64; i++) {
568 switch ((env->dtlb_tte[i] >> 61) & 3) {
583 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
584 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
585 ", %s, %s, %s, %s, ctx %" PRId64 "\n",
586 env->dtlb_tag[i] & ~0x1fffULL,
587 env->dtlb_tte[i] & 0x1ffffffe000ULL,
589 env->dtlb_tte[i] & 0x4? "priv": "user",
590 env->dtlb_tte[i] & 0x2? "RW": "RO",
591 env->dtlb_tte[i] & 0x40? "locked": "unlocked",
592 env->dtlb_tag[i] & 0x1fffULL);
596 if ((env->lsu & IMMU_E) == 0) {
597 printf("IMMU disabled\n");
599 printf("IMMU dump:\n");
600 for (i = 0; i < 64; i++) {
601 switch ((env->itlb_tte[i] >> 61) & 3) {
616 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
617 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx
618 ", %s, %s, %s, ctx %" PRId64 "\n",
619 env->itlb_tag[i] & ~0x1fffULL,
620 env->itlb_tte[i] & 0x1ffffffe000ULL,
622 env->itlb_tte[i] & 0x4? "priv": "user",
623 env->itlb_tte[i] & 0x40? "locked": "unlocked",
624 env->itlb_tag[i] & 0x1fffULL);
629 #endif /* DEBUG_MMU */
631 #endif /* TARGET_SPARC64 */
632 #endif /* !CONFIG_USER_ONLY */
635 #if defined(CONFIG_USER_ONLY)
636 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
642 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
644 target_phys_addr_t phys_addr;
645 int prot, access_index;
647 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
648 MMU_KERNEL_IDX) != 0)
649 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
650 0, MMU_KERNEL_IDX) != 0)
652 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
658 #ifdef TARGET_SPARC64
660 static const char * const excp_names[0x80] = {
661 [TT_TFAULT] = "Instruction Access Fault",
662 [TT_TMISS] = "Instruction Access MMU Miss",
663 [TT_CODE_ACCESS] = "Instruction Access Error",
664 [TT_ILL_INSN] = "Illegal Instruction",
665 [TT_PRIV_INSN] = "Privileged Instruction",
666 [TT_NFPU_INSN] = "FPU Disabled",
667 [TT_FP_EXCP] = "FPU Exception",
668 [TT_TOVF] = "Tag Overflow",
669 [TT_CLRWIN] = "Clean Windows",
670 [TT_DIV_ZERO] = "Division By Zero",
671 [TT_DFAULT] = "Data Access Fault",
672 [TT_DMISS] = "Data Access MMU Miss",
673 [TT_DATA_ACCESS] = "Data Access Error",
674 [TT_DPROT] = "Data Protection Error",
675 [TT_UNALIGNED] = "Unaligned Memory Access",
676 [TT_PRIV_ACT] = "Privileged Action",
677 [TT_EXTINT | 0x1] = "External Interrupt 1",
678 [TT_EXTINT | 0x2] = "External Interrupt 2",
679 [TT_EXTINT | 0x3] = "External Interrupt 3",
680 [TT_EXTINT | 0x4] = "External Interrupt 4",
681 [TT_EXTINT | 0x5] = "External Interrupt 5",
682 [TT_EXTINT | 0x6] = "External Interrupt 6",
683 [TT_EXTINT | 0x7] = "External Interrupt 7",
684 [TT_EXTINT | 0x8] = "External Interrupt 8",
685 [TT_EXTINT | 0x9] = "External Interrupt 9",
686 [TT_EXTINT | 0xa] = "External Interrupt 10",
687 [TT_EXTINT | 0xb] = "External Interrupt 11",
688 [TT_EXTINT | 0xc] = "External Interrupt 12",
689 [TT_EXTINT | 0xd] = "External Interrupt 13",
690 [TT_EXTINT | 0xe] = "External Interrupt 14",
691 [TT_EXTINT | 0xf] = "External Interrupt 15",
695 void do_interrupt(CPUState *env)
697 int intno = env->exception_index;
700 if (loglevel & CPU_LOG_INT) {
704 if (intno < 0 || intno >= 0x180)
706 else if (intno >= 0x100)
707 name = "Trap Instruction";
708 else if (intno >= 0xc0)
709 name = "Window Fill";
710 else if (intno >= 0x80)
711 name = "Window Spill";
713 name = excp_names[intno];
718 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
719 " SP=%016" PRIx64 "\n",
722 env->npc, env->regwptr[6]);
723 cpu_dump_state(env, logfile, fprintf, 0);
729 fprintf(logfile, " code=");
730 ptr = (uint8_t *)env->pc;
731 for(i = 0; i < 16; i++) {
732 fprintf(logfile, " %02x", ldub(ptr + i));
734 fprintf(logfile, "\n");
740 #if !defined(CONFIG_USER_ONLY)
741 if (env->tl == MAXTL) {
742 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
743 env->exception_index);
747 if (env->tl < MAXTL - 1) {
750 env->pstate |= PS_RED;
751 if (env->tl != MAXTL)
754 env->tsptr = &env->ts[env->tl];
755 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
756 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
758 env->tsptr->tpc = env->pc;
759 env->tsptr->tnpc = env->npc;
760 env->tsptr->tt = intno;
761 if (!(env->features & CPU_FEATURE_GL)) {
764 change_pstate(PS_PEF | PS_PRIV | PS_IG);
771 change_pstate(PS_PEF | PS_PRIV | PS_MG);
774 change_pstate(PS_PEF | PS_PRIV | PS_AG);
778 if (intno == TT_CLRWIN)
779 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
780 else if ((intno & 0x1c0) == TT_SPILL)
781 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
782 else if ((intno & 0x1c0) == TT_FILL)
783 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
784 env->tbr &= ~0x7fffULL;
785 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
787 env->npc = env->pc + 4;
788 env->exception_index = 0;
792 static const char * const excp_names[0x80] = {
793 [TT_TFAULT] = "Instruction Access Fault",
794 [TT_ILL_INSN] = "Illegal Instruction",
795 [TT_PRIV_INSN] = "Privileged Instruction",
796 [TT_NFPU_INSN] = "FPU Disabled",
797 [TT_WIN_OVF] = "Window Overflow",
798 [TT_WIN_UNF] = "Window Underflow",
799 [TT_UNALIGNED] = "Unaligned Memory Access",
800 [TT_FP_EXCP] = "FPU Exception",
801 [TT_DFAULT] = "Data Access Fault",
802 [TT_TOVF] = "Tag Overflow",
803 [TT_EXTINT | 0x1] = "External Interrupt 1",
804 [TT_EXTINT | 0x2] = "External Interrupt 2",
805 [TT_EXTINT | 0x3] = "External Interrupt 3",
806 [TT_EXTINT | 0x4] = "External Interrupt 4",
807 [TT_EXTINT | 0x5] = "External Interrupt 5",
808 [TT_EXTINT | 0x6] = "External Interrupt 6",
809 [TT_EXTINT | 0x7] = "External Interrupt 7",
810 [TT_EXTINT | 0x8] = "External Interrupt 8",
811 [TT_EXTINT | 0x9] = "External Interrupt 9",
812 [TT_EXTINT | 0xa] = "External Interrupt 10",
813 [TT_EXTINT | 0xb] = "External Interrupt 11",
814 [TT_EXTINT | 0xc] = "External Interrupt 12",
815 [TT_EXTINT | 0xd] = "External Interrupt 13",
816 [TT_EXTINT | 0xe] = "External Interrupt 14",
817 [TT_EXTINT | 0xf] = "External Interrupt 15",
818 [TT_TOVF] = "Tag Overflow",
819 [TT_CODE_ACCESS] = "Instruction Access Error",
820 [TT_DATA_ACCESS] = "Data Access Error",
821 [TT_DIV_ZERO] = "Division By Zero",
822 [TT_NCP_INSN] = "Coprocessor Disabled",
826 void do_interrupt(CPUState *env)
828 int cwp, intno = env->exception_index;
831 if (loglevel & CPU_LOG_INT) {
835 if (intno < 0 || intno >= 0x100)
837 else if (intno >= 0x80)
838 name = "Trap Instruction";
840 name = excp_names[intno];
845 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
848 env->npc, env->regwptr[6]);
849 cpu_dump_state(env, logfile, fprintf, 0);
855 fprintf(logfile, " code=");
856 ptr = (uint8_t *)env->pc;
857 for(i = 0; i < 16; i++) {
858 fprintf(logfile, " %02x", ldub(ptr + i));
860 fprintf(logfile, "\n");
866 #if !defined(CONFIG_USER_ONLY)
867 if (env->psret == 0) {
868 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
869 env->exception_index);
874 cwp = cpu_cwp_dec(env, env->cwp - 1);
875 cpu_set_cwp(env, cwp);
876 env->regwptr[9] = env->pc;
877 env->regwptr[10] = env->npc;
878 env->psrps = env->psrs;
880 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
882 env->npc = env->pc + 4;
883 env->exception_index = 0;
887 void memcpy32(target_ulong *dst, const target_ulong *src)
899 void cpu_reset(CPUSPARCState *env)
904 env->regwptr = env->regbase + (env->cwp * 16);
905 #if defined(CONFIG_USER_ONLY)
906 env->user_mode_only = 1;
907 #ifdef TARGET_SPARC64
908 env->cleanwin = env->nwindows - 2;
909 env->cansave = env->nwindows - 2;
910 env->pstate = PS_RMO | PS_PEF | PS_IE;
911 env->asi = 0x82; // Primary no-fault
917 #ifdef TARGET_SPARC64
918 env->pstate = PS_PRIV;
919 env->hpstate = HS_PRIV;
920 env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset
921 env->tsptr = &env->ts[env->tl];
924 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
925 env->mmuregs[0] |= env->mmu_bm;
927 env->npc = env->pc + 4;
931 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
933 sparc_def_t def1, *def = &def1;
935 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
938 env->features = def->features;
939 env->cpu_model_str = cpu_model;
940 env->version = def->iu_version;
941 env->fsr = def->fpu_version;
942 env->nwindows = def->nwindows;
943 #if !defined(TARGET_SPARC64)
944 env->mmu_bm = def->mmu_bm;
945 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
946 env->mmu_cxr_mask = def->mmu_cxr_mask;
947 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
948 env->mmu_trcr_mask = def->mmu_trcr_mask;
949 env->mmuregs[0] |= def->mmu_version;
950 cpu_sparc_set_id(env, 0);
952 env->mmu_version = def->mmu_version;
953 env->version |= def->nwindows - 1;
958 static void cpu_sparc_close(CPUSPARCState *env)
963 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
967 env = qemu_mallocz(sizeof(CPUSPARCState));
972 gen_intermediate_code_init(env);
974 if (cpu_sparc_register(env, cpu_model) < 0) {
975 cpu_sparc_close(env);
983 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
985 #if !defined(TARGET_SPARC64)
986 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
990 static const sparc_def_t sparc_defs[] = {
991 #ifdef TARGET_SPARC64
993 .name = "Fujitsu Sparc64",
994 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
996 .fpu_version = 0x00000000,
997 .mmu_version = mmu_us_12,
999 .features = CPU_DEFAULT_FEATURES,
1002 .name = "Fujitsu Sparc64 III",
1003 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
1005 .fpu_version = 0x00000000,
1006 .mmu_version = mmu_us_12,
1008 .features = CPU_DEFAULT_FEATURES,
1011 .name = "Fujitsu Sparc64 IV",
1012 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
1014 .fpu_version = 0x00000000,
1015 .mmu_version = mmu_us_12,
1017 .features = CPU_DEFAULT_FEATURES,
1020 .name = "Fujitsu Sparc64 V",
1021 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
1023 .fpu_version = 0x00000000,
1024 .mmu_version = mmu_us_12,
1026 .features = CPU_DEFAULT_FEATURES,
1029 .name = "TI UltraSparc I",
1030 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
1032 .fpu_version = 0x00000000,
1033 .mmu_version = mmu_us_12,
1035 .features = CPU_DEFAULT_FEATURES,
1038 .name = "TI UltraSparc II",
1039 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
1041 .fpu_version = 0x00000000,
1042 .mmu_version = mmu_us_12,
1044 .features = CPU_DEFAULT_FEATURES,
1047 .name = "TI UltraSparc IIi",
1048 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
1050 .fpu_version = 0x00000000,
1051 .mmu_version = mmu_us_12,
1053 .features = CPU_DEFAULT_FEATURES,
1056 .name = "TI UltraSparc IIe",
1057 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
1059 .fpu_version = 0x00000000,
1060 .mmu_version = mmu_us_12,
1062 .features = CPU_DEFAULT_FEATURES,
1065 .name = "Sun UltraSparc III",
1066 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
1068 .fpu_version = 0x00000000,
1069 .mmu_version = mmu_us_12,
1071 .features = CPU_DEFAULT_FEATURES,
1074 .name = "Sun UltraSparc III Cu",
1075 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
1077 .fpu_version = 0x00000000,
1078 .mmu_version = mmu_us_3,
1080 .features = CPU_DEFAULT_FEATURES,
1083 .name = "Sun UltraSparc IIIi",
1084 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
1086 .fpu_version = 0x00000000,
1087 .mmu_version = mmu_us_12,
1089 .features = CPU_DEFAULT_FEATURES,
1092 .name = "Sun UltraSparc IV",
1093 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
1095 .fpu_version = 0x00000000,
1096 .mmu_version = mmu_us_4,
1098 .features = CPU_DEFAULT_FEATURES,
1101 .name = "Sun UltraSparc IV+",
1102 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
1104 .fpu_version = 0x00000000,
1105 .mmu_version = mmu_us_12,
1107 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
1110 .name = "Sun UltraSparc IIIi+",
1111 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
1113 .fpu_version = 0x00000000,
1114 .mmu_version = mmu_us_3,
1116 .features = CPU_DEFAULT_FEATURES,
1119 .name = "Sun UltraSparc T1",
1120 // defined in sparc_ifu_fdp.v and ctu.h
1121 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)
1123 .fpu_version = 0x00000000,
1124 .mmu_version = mmu_sun4v,
1126 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
1130 .name = "Sun UltraSparc T2",
1131 // defined in tlu_asi_ctl.v and n2_revid_cust.v
1132 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)
1134 .fpu_version = 0x00000000,
1135 .mmu_version = mmu_sun4v,
1137 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
1141 .name = "NEC UltraSparc I",
1142 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
1144 .fpu_version = 0x00000000,
1145 .mmu_version = mmu_us_12,
1147 .features = CPU_DEFAULT_FEATURES,
1151 .name = "Fujitsu MB86900",
1152 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
1153 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1154 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
1155 .mmu_bm = 0x00004000,
1156 .mmu_ctpr_mask = 0x007ffff0,
1157 .mmu_cxr_mask = 0x0000003f,
1158 .mmu_sfsr_mask = 0xffffffff,
1159 .mmu_trcr_mask = 0xffffffff,
1161 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
1164 .name = "Fujitsu MB86904",
1165 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
1166 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1167 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
1168 .mmu_bm = 0x00004000,
1169 .mmu_ctpr_mask = 0x00ffffc0,
1170 .mmu_cxr_mask = 0x000000ff,
1171 .mmu_sfsr_mask = 0x00016fff,
1172 .mmu_trcr_mask = 0x00ffffff,
1174 .features = CPU_DEFAULT_FEATURES,
1177 .name = "Fujitsu MB86907",
1178 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
1179 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1180 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
1181 .mmu_bm = 0x00004000,
1182 .mmu_ctpr_mask = 0xffffffc0,
1183 .mmu_cxr_mask = 0x000000ff,
1184 .mmu_sfsr_mask = 0x00016fff,
1185 .mmu_trcr_mask = 0xffffffff,
1187 .features = CPU_DEFAULT_FEATURES,
1190 .name = "LSI L64811",
1191 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
1192 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
1193 .mmu_version = 0x10 << 24,
1194 .mmu_bm = 0x00004000,
1195 .mmu_ctpr_mask = 0x007ffff0,
1196 .mmu_cxr_mask = 0x0000003f,
1197 .mmu_sfsr_mask = 0xffffffff,
1198 .mmu_trcr_mask = 0xffffffff,
1200 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1204 .name = "Cypress CY7C601",
1205 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
1206 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1207 .mmu_version = 0x10 << 24,
1208 .mmu_bm = 0x00004000,
1209 .mmu_ctpr_mask = 0x007ffff0,
1210 .mmu_cxr_mask = 0x0000003f,
1211 .mmu_sfsr_mask = 0xffffffff,
1212 .mmu_trcr_mask = 0xffffffff,
1214 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1218 .name = "Cypress CY7C611",
1219 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
1220 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
1221 .mmu_version = 0x10 << 24,
1222 .mmu_bm = 0x00004000,
1223 .mmu_ctpr_mask = 0x007ffff0,
1224 .mmu_cxr_mask = 0x0000003f,
1225 .mmu_sfsr_mask = 0xffffffff,
1226 .mmu_trcr_mask = 0xffffffff,
1228 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1232 .name = "TI SuperSparc II",
1233 .iu_version = 0x40000000,
1234 .fpu_version = 0 << 17,
1235 .mmu_version = 0x04000000,
1236 .mmu_bm = 0x00002000,
1237 .mmu_ctpr_mask = 0xffffffc0,
1238 .mmu_cxr_mask = 0x0000ffff,
1239 .mmu_sfsr_mask = 0xffffffff,
1240 .mmu_trcr_mask = 0xffffffff,
1242 .features = CPU_DEFAULT_FEATURES,
1245 .name = "TI MicroSparc I",
1246 .iu_version = 0x41000000,
1247 .fpu_version = 4 << 17,
1248 .mmu_version = 0x41000000,
1249 .mmu_bm = 0x00004000,
1250 .mmu_ctpr_mask = 0x007ffff0,
1251 .mmu_cxr_mask = 0x0000003f,
1252 .mmu_sfsr_mask = 0x00016fff,
1253 .mmu_trcr_mask = 0x0000003f,
1255 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
1256 CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
1260 .name = "TI MicroSparc II",
1261 .iu_version = 0x42000000,
1262 .fpu_version = 4 << 17,
1263 .mmu_version = 0x02000000,
1264 .mmu_bm = 0x00004000,
1265 .mmu_ctpr_mask = 0x00ffffc0,
1266 .mmu_cxr_mask = 0x000000ff,
1267 .mmu_sfsr_mask = 0x00016fff,
1268 .mmu_trcr_mask = 0x00ffffff,
1270 .features = CPU_DEFAULT_FEATURES,
1273 .name = "TI MicroSparc IIep",
1274 .iu_version = 0x42000000,
1275 .fpu_version = 4 << 17,
1276 .mmu_version = 0x04000000,
1277 .mmu_bm = 0x00004000,
1278 .mmu_ctpr_mask = 0x00ffffc0,
1279 .mmu_cxr_mask = 0x000000ff,
1280 .mmu_sfsr_mask = 0x00016bff,
1281 .mmu_trcr_mask = 0x00ffffff,
1283 .features = CPU_DEFAULT_FEATURES,
1286 .name = "TI SuperSparc 40", // STP1020NPGA
1287 .iu_version = 0x41000000,
1288 .fpu_version = 0 << 17,
1289 .mmu_version = 0x00000000,
1290 .mmu_bm = 0x00002000,
1291 .mmu_ctpr_mask = 0xffffffc0,
1292 .mmu_cxr_mask = 0x0000ffff,
1293 .mmu_sfsr_mask = 0xffffffff,
1294 .mmu_trcr_mask = 0xffffffff,
1296 .features = CPU_DEFAULT_FEATURES,
1299 .name = "TI SuperSparc 50", // STP1020PGA
1300 .iu_version = 0x40000000,
1301 .fpu_version = 0 << 17,
1302 .mmu_version = 0x04000000,
1303 .mmu_bm = 0x00002000,
1304 .mmu_ctpr_mask = 0xffffffc0,
1305 .mmu_cxr_mask = 0x0000ffff,
1306 .mmu_sfsr_mask = 0xffffffff,
1307 .mmu_trcr_mask = 0xffffffff,
1309 .features = CPU_DEFAULT_FEATURES,
1312 .name = "TI SuperSparc 51",
1313 .iu_version = 0x43000000,
1314 .fpu_version = 0 << 17,
1315 .mmu_version = 0x04000000,
1316 .mmu_bm = 0x00002000,
1317 .mmu_ctpr_mask = 0xffffffc0,
1318 .mmu_cxr_mask = 0x0000ffff,
1319 .mmu_sfsr_mask = 0xffffffff,
1320 .mmu_trcr_mask = 0xffffffff,
1322 .features = CPU_DEFAULT_FEATURES,
1325 .name = "TI SuperSparc 60", // STP1020APGA
1326 .iu_version = 0x40000000,
1327 .fpu_version = 0 << 17,
1328 .mmu_version = 0x03000000,
1329 .mmu_bm = 0x00002000,
1330 .mmu_ctpr_mask = 0xffffffc0,
1331 .mmu_cxr_mask = 0x0000ffff,
1332 .mmu_sfsr_mask = 0xffffffff,
1333 .mmu_trcr_mask = 0xffffffff,
1335 .features = CPU_DEFAULT_FEATURES,
1338 .name = "TI SuperSparc 61",
1339 .iu_version = 0x44000000,
1340 .fpu_version = 0 << 17,
1341 .mmu_version = 0x04000000,
1342 .mmu_bm = 0x00002000,
1343 .mmu_ctpr_mask = 0xffffffc0,
1344 .mmu_cxr_mask = 0x0000ffff,
1345 .mmu_sfsr_mask = 0xffffffff,
1346 .mmu_trcr_mask = 0xffffffff,
1348 .features = CPU_DEFAULT_FEATURES,
1351 .name = "Ross RT625",
1352 .iu_version = 0x1e000000,
1353 .fpu_version = 1 << 17,
1354 .mmu_version = 0x1e000000,
1355 .mmu_bm = 0x00004000,
1356 .mmu_ctpr_mask = 0x007ffff0,
1357 .mmu_cxr_mask = 0x0000003f,
1358 .mmu_sfsr_mask = 0xffffffff,
1359 .mmu_trcr_mask = 0xffffffff,
1361 .features = CPU_DEFAULT_FEATURES,
1364 .name = "Ross RT620",
1365 .iu_version = 0x1f000000,
1366 .fpu_version = 1 << 17,
1367 .mmu_version = 0x1f000000,
1368 .mmu_bm = 0x00004000,
1369 .mmu_ctpr_mask = 0x007ffff0,
1370 .mmu_cxr_mask = 0x0000003f,
1371 .mmu_sfsr_mask = 0xffffffff,
1372 .mmu_trcr_mask = 0xffffffff,
1374 .features = CPU_DEFAULT_FEATURES,
1377 .name = "BIT B5010",
1378 .iu_version = 0x20000000,
1379 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1380 .mmu_version = 0x20000000,
1381 .mmu_bm = 0x00004000,
1382 .mmu_ctpr_mask = 0x007ffff0,
1383 .mmu_cxr_mask = 0x0000003f,
1384 .mmu_sfsr_mask = 0xffffffff,
1385 .mmu_trcr_mask = 0xffffffff,
1387 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
1391 .name = "Matsushita MN10501",
1392 .iu_version = 0x50000000,
1393 .fpu_version = 0 << 17,
1394 .mmu_version = 0x50000000,
1395 .mmu_bm = 0x00004000,
1396 .mmu_ctpr_mask = 0x007ffff0,
1397 .mmu_cxr_mask = 0x0000003f,
1398 .mmu_sfsr_mask = 0xffffffff,
1399 .mmu_trcr_mask = 0xffffffff,
1401 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
1405 .name = "Weitek W8601",
1406 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1407 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1408 .mmu_version = 0x10 << 24,
1409 .mmu_bm = 0x00004000,
1410 .mmu_ctpr_mask = 0x007ffff0,
1411 .mmu_cxr_mask = 0x0000003f,
1412 .mmu_sfsr_mask = 0xffffffff,
1413 .mmu_trcr_mask = 0xffffffff,
1415 .features = CPU_DEFAULT_FEATURES,
1419 .iu_version = 0xf2000000,
1420 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1421 .mmu_version = 0xf2000000,
1422 .mmu_bm = 0x00004000,
1423 .mmu_ctpr_mask = 0x007ffff0,
1424 .mmu_cxr_mask = 0x0000003f,
1425 .mmu_sfsr_mask = 0xffffffff,
1426 .mmu_trcr_mask = 0xffffffff,
1428 .features = CPU_DEFAULT_FEATURES,
1432 .iu_version = 0xf3000000,
1433 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1434 .mmu_version = 0xf3000000,
1435 .mmu_bm = 0x00004000,
1436 .mmu_ctpr_mask = 0x007ffff0,
1437 .mmu_cxr_mask = 0x0000003f,
1438 .mmu_sfsr_mask = 0xffffffff,
1439 .mmu_trcr_mask = 0xffffffff,
1441 .features = CPU_DEFAULT_FEATURES,
1446 static const char * const feature_name[] = {
1463 static void print_features(FILE *f,
1464 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1465 uint32_t features, const char *prefix)
1469 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1470 if (feature_name[i] && (features & (1 << i))) {
1472 (*cpu_fprintf)(f, "%s", prefix);
1473 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1477 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1481 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1482 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1483 *features |= 1 << i;
1486 fprintf(stderr, "CPU feature %s not found\n", flagname);
1489 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1492 const sparc_def_t *def = NULL;
1493 char *s = strdup(cpu_model);
1494 char *featurestr, *name = strtok(s, ",");
1495 uint32_t plus_features = 0;
1496 uint32_t minus_features = 0;
1497 long long iu_version;
1498 uint32_t fpu_version, mmu_version, nwindows;
1500 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1501 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1502 def = &sparc_defs[i];
1507 memcpy(cpu_def, def, sizeof(*def));
1509 featurestr = strtok(NULL, ",");
1510 while (featurestr) {
1513 if (featurestr[0] == '+') {
1514 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1515 } else if (featurestr[0] == '-') {
1516 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1517 } else if ((val = strchr(featurestr, '='))) {
1519 if (!strcmp(featurestr, "iu_version")) {
1522 iu_version = strtoll(val, &err, 0);
1523 if (!*val || *err) {
1524 fprintf(stderr, "bad numerical value %s\n", val);
1527 cpu_def->iu_version = iu_version;
1528 #ifdef DEBUG_FEATURES
1529 fprintf(stderr, "iu_version %llx\n", iu_version);
1531 } else if (!strcmp(featurestr, "fpu_version")) {
1534 fpu_version = strtol(val, &err, 0);
1535 if (!*val || *err) {
1536 fprintf(stderr, "bad numerical value %s\n", val);
1539 cpu_def->fpu_version = fpu_version;
1540 #ifdef DEBUG_FEATURES
1541 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1543 } else if (!strcmp(featurestr, "mmu_version")) {
1546 mmu_version = strtol(val, &err, 0);
1547 if (!*val || *err) {
1548 fprintf(stderr, "bad numerical value %s\n", val);
1551 cpu_def->mmu_version = mmu_version;
1552 #ifdef DEBUG_FEATURES
1553 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1555 } else if (!strcmp(featurestr, "nwindows")) {
1558 nwindows = strtol(val, &err, 0);
1559 if (!*val || *err || nwindows > MAX_NWINDOWS ||
1560 nwindows < MIN_NWINDOWS) {
1561 fprintf(stderr, "bad numerical value %s\n", val);
1564 cpu_def->nwindows = nwindows;
1565 #ifdef DEBUG_FEATURES
1566 fprintf(stderr, "nwindows %d\n", nwindows);
1569 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1573 fprintf(stderr, "feature string `%s' not in format "
1574 "(+feature|-feature|feature=xyz)\n", featurestr);
1577 featurestr = strtok(NULL, ",");
1579 cpu_def->features |= plus_features;
1580 cpu_def->features &= ~minus_features;
1581 #ifdef DEBUG_FEATURES
1582 print_features(stderr, fprintf, cpu_def->features, NULL);
1592 void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1596 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1597 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
1599 sparc_defs[i].iu_version,
1600 sparc_defs[i].fpu_version,
1601 sparc_defs[i].mmu_version,
1602 sparc_defs[i].nwindows);
1603 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
1604 ~sparc_defs[i].features, "-");
1605 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
1606 sparc_defs[i].features, "+");
1607 (*cpu_fprintf)(f, "\n");
1609 (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
1610 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
1611 (*cpu_fprintf)(f, "\n");
1612 (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
1613 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
1614 (*cpu_fprintf)(f, "\n");
1615 (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
1616 "fpu_version mmu_version nwindows\n");
1619 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1621 void cpu_dump_state(CPUState *env, FILE *f,
1622 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1627 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
1629 cpu_fprintf(f, "General Registers:\n");
1630 for (i = 0; i < 4; i++)
1631 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1632 cpu_fprintf(f, "\n");
1634 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1635 cpu_fprintf(f, "\nCurrent Register Window:\n");
1636 for (x = 0; x < 3; x++) {
1637 for (i = 0; i < 4; i++)
1638 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1639 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1640 env->regwptr[i + x * 8]);
1641 cpu_fprintf(f, "\n");
1643 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1644 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1645 env->regwptr[i + x * 8]);
1646 cpu_fprintf(f, "\n");
1648 cpu_fprintf(f, "\nFloating Point Registers:\n");
1649 for (i = 0; i < 32; i++) {
1651 cpu_fprintf(f, "%%f%02d:", i);
1652 cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
1654 cpu_fprintf(f, "\n");
1656 #ifdef TARGET_SPARC64
1657 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1658 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1659 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
1660 "cleanwin %d cwp %d\n",
1661 env->cansave, env->canrestore, env->otherwin, env->wstate,
1662 env->cleanwin, env->nwindows - 1 - env->cwp);
1664 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
1665 GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1666 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1667 env->psrs?'S':'-', env->psrps?'P':'-',
1668 env->psret?'E':'-', env->wim);
1670 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
1673 #ifdef TARGET_SPARC64
1674 #if !defined(CONFIG_USER_ONLY)
1675 #include "qemu-common.h"
1677 #include "qemu-timer.h"
1680 void helper_tick_set_count(void *opaque, uint64_t count)
1682 #if !defined(CONFIG_USER_ONLY)
1683 ptimer_set_count(opaque, -count);
1687 uint64_t helper_tick_get_count(void *opaque)
1689 #if !defined(CONFIG_USER_ONLY)
1690 return -ptimer_get_count(opaque);
1696 void helper_tick_set_limit(void *opaque, uint64_t limit)
1698 #if !defined(CONFIG_USER_ONLY)
1699 ptimer_set_limit(opaque, -limit, 0);