/*
* sparc helpers
*
- * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2003-2005 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include "exec.h"
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <signal.h>
+#include <assert.h>
+
+#include "cpu.h"
+#include "exec-all.h"
-//#define DEBUG_PCALL
//#define DEBUG_MMU
/* Sparc MMU emulation */
int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu)
{
- env->mmuregs[4] = address;
if (rw & 2)
env->exception_index = TT_TFAULT;
else
#else
-#define MMUSUFFIX _mmu
-#define GETPC() (__builtin_return_address(0))
-
-#define SHIFT 0
-#include "softmmu_template.h"
-
-#define SHIFT 1
-#include "softmmu_template.h"
-
-#define SHIFT 2
-#include "softmmu_template.h"
-
-#define SHIFT 3
-#include "softmmu_template.h"
-
-
-/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
-{
- TranslationBlock *tb;
- int ret;
- unsigned long pc;
- CPUState *saved_env;
-
- /* XXX: hack to restore env in all cases, even if not called from
- generated code */
- saved_env = env;
- env = cpu_single_env;
-
- ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
- if (ret) {
- if (retaddr) {
- /* now we have a real cpu fault */
- pc = (unsigned long)retaddr;
- tb = tb_find_pc(pc);
- if (tb) {
- /* the PC is inside the translated code. It means that we have
- a virtual CPU fault */
- cpu_restore_state(tb, env, pc, (void *)T2);
- }
- }
- cpu_loop_exit();
- }
- env = saved_env;
-}
-
+#ifndef TARGET_SPARC64
+/*
+ * Sparc V8 Reference MMU (SRMMU)
+ */
static const int access_table[8][8] = {
{ 0, 0, 0, 0, 2, 0, 3, 3 },
{ 0, 0, 0, 0, 2, 0, 0, 0 },
return 1;
}
}
-#endif
-
-void memcpy32(target_ulong *dst, const target_ulong *src)
+#else
+/*
+ * UltraSparc IIi I/DMMUs
+ */
+static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user)
{
- dst[0] = src[0];
- dst[1] = src[1];
- dst[2] = src[2];
- dst[3] = src[3];
- dst[4] = src[4];
- dst[5] = src[5];
- dst[6] = src[6];
- dst[7] = src[7];
+ target_ulong mask;
+ unsigned int i;
+
+ if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
+ *physical = address;
+ *prot = PAGE_READ | PAGE_WRITE;
+ return 0;
+ }
+
+ for (i = 0; i < 64; i++) {
+ switch ((env->dtlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0: // 8k
+ mask = 0xffffffffffffe000ULL;
+ break;
+ case 0x1: // 64k
+ mask = 0xffffffffffff0000ULL;
+ break;
+ case 0x2: // 512k
+ mask = 0xfffffffffff80000ULL;
+ break;
+ case 0x3: // 4M
+ mask = 0xffffffffffc00000ULL;
+ break;
+ }
+ // ctx match, vaddr match?
+ if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
+ (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
+ // valid, access ok?
+ if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
+ ((env->dtlb_tte[i] & 0x4) && is_user) ||
+ (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
+ if (env->dmmuregs[3]) /* Fault status register */
+ env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
+ env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
+ env->dmmuregs[4] = address; /* Fault address register */
+ env->exception_index = TT_DFAULT;
+#ifdef DEBUG_MMU
+ printf("DFAULT at 0x%llx\n", address);
+#endif
+ return 1;
+ }
+ *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
+ *prot = PAGE_READ;
+ if (env->dtlb_tte[i] & 0x2)
+ *prot |= PAGE_WRITE;
+ return 0;
+ }
+ }
+#ifdef DEBUG_MMU
+ printf("DMISS at 0x%llx\n", address);
+#endif
+ env->exception_index = TT_DMISS;
+ return 1;
}
-void set_cwp(int new_cwp)
+static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user)
{
- /* put the modified wrap registers at their proper location */
- if (env->cwp == (NWINDOWS - 1))
- memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
- env->cwp = new_cwp;
- /* put the wrap registers at their temporary location */
- if (new_cwp == (NWINDOWS - 1))
- memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
- env->regwptr = env->regbase + (new_cwp * 16);
+ target_ulong mask;
+ unsigned int i;
+
+ if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
+ *physical = address;
+ *prot = PAGE_READ;
+ return 0;
+ }
+
+ for (i = 0; i < 64; i++) {
+ switch ((env->itlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0: // 8k
+ mask = 0xffffffffffffe000ULL;
+ break;
+ case 0x1: // 64k
+ mask = 0xffffffffffff0000ULL;
+ break;
+ case 0x2: // 512k
+ mask = 0xfffffffffff80000ULL;
+ break;
+ case 0x3: // 4M
+ mask = 0xffffffffffc00000ULL;
+ break;
+ }
+ // ctx match, vaddr match?
+ if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
+ (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
+ // valid, access ok?
+ if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
+ ((env->itlb_tte[i] & 0x4) && is_user)) {
+ if (env->immuregs[3]) /* Fault status register */
+ env->immuregs[3] = 2; /* overflow (not read before another fault) */
+ env->immuregs[3] |= (is_user << 3) | 1;
+ env->exception_index = TT_TFAULT;
+#ifdef DEBUG_MMU
+ printf("TFAULT at 0x%llx\n", address);
+#endif
+ return 1;
+ }
+ *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
+ *prot = PAGE_READ;
+ return 0;
+ }
+ }
+#ifdef DEBUG_MMU
+ printf("TMISS at 0x%llx\n", address);
+#endif
+ env->exception_index = TT_TMISS;
+ return 1;
}
-void cpu_set_cwp(CPUState *env1, int new_cwp)
+int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user)
{
- CPUState *saved_env;
- saved_env = env;
- env = env1;
- set_cwp(new_cwp);
- env = saved_env;
+ if (rw == 2)
+ return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
+ else
+ return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
}
-void do_interrupt(int intno)
+/* Perform address translation */
+int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu)
{
- int cwp;
-
-#ifdef DEBUG_PCALL
- if (loglevel & CPU_LOG_INT) {
- static int count;
- fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
- count, intno,
- env->pc,
- env->npc, env->regwptr[6]);
- cpu_dump_state(env, logfile, fprintf, 0);
-#if 0
- {
- int i;
- uint8_t *ptr;
-
- fprintf(logfile, " code=");
- ptr = (uint8_t *)env->pc;
- for(i = 0; i < 16; i++) {
- fprintf(logfile, " %02x", ldub(ptr + i));
- }
- fprintf(logfile, "\n");
- }
+ target_ulong virt_addr, vaddr;
+ target_phys_addr_t paddr;
+ int error_code = 0, prot, ret = 0, access_index;
+
+ error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
+ if (error_code == 0) {
+ virt_addr = address & TARGET_PAGE_MASK;
+ vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
+#ifdef DEBUG_MMU
+ printf("Translate at 0x%llx -> 0x%llx, vaddr 0x%llx\n", address, paddr, vaddr);
#endif
- count++;
+ ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
+ return ret;
}
+ // XXX
+ return 1;
+}
+
#endif
-#if !defined(CONFIG_USER_ONLY)
- if (env->psret == 0) {
- cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
- return;
- }
#endif
- env->psret = 0;
- cwp = (env->cwp - 1) & (NWINDOWS - 1);
- set_cwp(cwp);
- env->regwptr[9] = env->pc;
- env->regwptr[10] = env->npc;
- env->psrps = env->psrs;
- env->psrs = 1;
- env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
- env->pc = env->tbr;
- env->npc = env->pc + 4;
- env->exception_index = 0;
+
+void memcpy32(target_ulong *dst, const target_ulong *src)
+{
+ dst[0] = src[0];
+ dst[1] = src[1];
+ dst[2] = src[2];
+ dst[3] = src[3];
+ dst[4] = src[4];
+ dst[5] = src[5];
+ dst[6] = src[6];
+ dst[7] = src[7];
}
-target_ulong mmu_probe(target_ulong address, int mmulev)
+#if !defined(TARGET_SPARC64)
+target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
target_phys_addr_t pde_ptr;
uint32_t pde;
}
#ifdef DEBUG_MMU
-void dump_mmu(void)
+void dump_mmu(CPUState *env)
{
target_ulong va, va1, va2;
unsigned int n, m, o;
pde = ldl_phys(pde_ptr);
printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
- pde_ptr = mmu_probe(va, 2);
+ pde_ptr = mmu_probe(env, va, 2);
if (pde_ptr) {
pa = cpu_get_phys_page_debug(env, va);
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
- pde_ptr = mmu_probe(va1, 1);
+ pde_ptr = mmu_probe(env, va1, 1);
if (pde_ptr) {
pa = cpu_get_phys_page_debug(env, va1);
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
- pde_ptr = mmu_probe(va2, 0);
+ pde_ptr = mmu_probe(env, va2, 0);
if (pde_ptr) {
pa = cpu_get_phys_page_debug(env, va2);
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
printf("MMU dump ends\n");
}
#endif
+#else
+#ifdef DEBUG_MMU
+void dump_mmu(CPUState *env)
+{
+ unsigned int i;
+ const char *mask;
+
+ printf("MMU contexts: Primary: %lld, Secondary: %lld\n", env->dmmuregs[1], env->dmmuregs[2]);
+ if ((env->lsu & DMMU_E) == 0) {
+ printf("DMMU disabled\n");
+ } else {
+ printf("DMMU dump:\n");
+ for (i = 0; i < 64; i++) {
+ switch ((env->dtlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0:
+ mask = " 8k";
+ break;
+ case 0x1:
+ mask = " 64k";
+ break;
+ case 0x2:
+ mask = "512k";
+ break;
+ case 0x3:
+ mask = " 4M";
+ break;
+ }
+ if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
+ printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %lld\n",
+ env->dtlb_tag[i] & ~0x1fffULL,
+ env->dtlb_tte[i] & 0x1ffffffe000ULL,
+ mask,
+ env->dtlb_tte[i] & 0x4? "priv": "user",
+ env->dtlb_tte[i] & 0x2? "RW": "RO",
+ env->dtlb_tte[i] & 0x40? "locked": "unlocked",
+ env->dtlb_tag[i] & 0x1fffULL);
+ }
+ }
+ }
+ if ((env->lsu & IMMU_E) == 0) {
+ printf("IMMU disabled\n");
+ } else {
+ printf("IMMU dump:\n");
+ for (i = 0; i < 64; i++) {
+ switch ((env->itlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0:
+ mask = " 8k";
+ break;
+ case 0x1:
+ mask = " 64k";
+ break;
+ case 0x2:
+ mask = "512k";
+ break;
+ case 0x3:
+ mask = " 4M";
+ break;
+ }
+ if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
+ printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %lld\n",
+ env->itlb_tag[i] & ~0x1fffULL,
+ env->itlb_tte[i] & 0x1ffffffe000ULL,
+ mask,
+ env->itlb_tte[i] & 0x4? "priv": "user",
+ env->itlb_tte[i] & 0x40? "locked": "unlocked",
+ env->itlb_tag[i] & 0x1fffULL);
+ }
+ }
+ }
+}
+#endif
+#endif
projects / qemu / blobdiff