X-Git-Url: http://git.maemo.org/git/?p=qemu;a=blobdiff_plain;f=hw%2Farm_timer.c;fp=hw%2Farm_timer.c;h=226ecc472297e1c822f6cc4b567707da84c2d88e;hp=c93f333d7a3239a6b74f1a01e60eb27ec595f12d;hb=759b334a9739814df2883aa4c41b1c0f5670e90a;hpb=7e2198fc87e878b8ce5df965477e21713ebf7834

diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index c93f333..226ecc4 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -7,9 +7,8 @@
  * This code is licenced under the GPL.
  */
 
-#include "hw.h"
+#include "sysbus.h"
 #include "qemu-timer.h"
-#include "primecell.h"
 
 /* Common timer implementation.  */
 
@@ -62,8 +61,7 @@ static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
             return 0;
         return s->int_level;
     default:
-        cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
-                   (int)offset);
+        hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -130,8 +128,7 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset,
         arm_timer_recalibrate(s, 0);
         break;
     default:
-        cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
-                   (int)offset);
+        hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
     }
     arm_timer_update(s);
 }
@@ -166,13 +163,12 @@ static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
-static void *arm_timer_init(uint32_t freq, qemu_irq irq)
+static arm_timer_state *arm_timer_init(uint32_t freq)
 {
     arm_timer_state *s;
     QEMUBH *bh;
 
     s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
-    s->irq = irq;
     s->freq = freq;
     s->control = TIMER_CTRL_IE;
 
@@ -188,7 +184,8 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq)
    Integrator/CP timer modules.  */
 
 typedef struct {
-    void *timer[2];
+    SysBusDevice busdev;
+    arm_timer_state *timer[2];
     int level[2];
     qemu_irq irq;
 } sp804_state;
@@ -257,22 +254,23 @@ static int sp804_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
-void sp804_init(uint32_t base, qemu_irq irq)
+static void sp804_init(SysBusDevice *dev)
 {
     int iomemtype;
-    sp804_state *s;
+    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
     qemu_irq *qi;
 
-    s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
-    s->irq = irq;
+    sysbus_init_irq(dev, &s->irq);
     /* ??? The timers are actually configurable between 32kHz and 1MHz, but
        we don't implement that.  */
-    s->timer[0] = arm_timer_init(1000000, qi[0]);
-    s->timer[1] = arm_timer_init(1000000, qi[1]);
+    s->timer[0] = arm_timer_init(1000000);
+    s->timer[1] = arm_timer_init(1000000);
+    s->timer[0]->irq = qi[0];
+    s->timer[1]->irq = qi[1];
     iomemtype = cpu_register_io_memory(0, sp804_readfn,
                                        sp804_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+    sysbus_init_mmio(dev, 0x1000, iomemtype);
     register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
 }
 
@@ -280,7 +278,8 @@ void sp804_init(uint32_t base, qemu_irq irq)
 /* Integrator/CP timer module.  */
 
 typedef struct {
-    void *timer[3];
+    SysBusDevice busdev;
+    arm_timer_state *timer[3];
 } icp_pit_state;
 
 static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
@@ -290,8 +289,9 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
 
     /* ??? Don't know the PrimeCell ID for this device.  */
     n = offset >> 8;
-    if (n > 3)
-        cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
+    if (n > 3) {
+        hw_error("sp804_read: Bad timer %d\n", n);
+    }
 
     return arm_timer_read(s->timer[n], offset & 0xff);
 }
@@ -303,8 +303,9 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset,
     int n;
 
     n = offset >> 8;
-    if (n > 3)
-        cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
+    if (n > 3) {
+        hw_error("sp804_write: Bad timer %d\n", n);
+    }
 
     arm_timer_write(s->timer[n], offset & 0xff, value);
 }
@@ -322,21 +323,32 @@ static CPUWriteMemoryFunc *icp_pit_writefn[] = {
    icp_pit_write
 };
 
-void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
+static void icp_pit_init(SysBusDevice *dev)
 {
     int iomemtype;
-    icp_pit_state *s;
+    icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
 
-    s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
     /* Timer 0 runs at the system clock speed (40MHz).  */
-    s->timer[0] = arm_timer_init(40000000, pic[irq]);
+    s->timer[0] = arm_timer_init(40000000);
     /* The other two timers run at 1MHz.  */
-    s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
-    s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);
+    s->timer[1] = arm_timer_init(1000000);
+    s->timer[2] = arm_timer_init(1000000);
+
+    sysbus_init_irq(dev, &s->timer[0]->irq);
+    sysbus_init_irq(dev, &s->timer[1]->irq);
+    sysbus_init_irq(dev, &s->timer[2]->irq);
 
     iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
                                        icp_pit_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+    sysbus_init_mmio(dev, 0x1000, iomemtype);
     /* This device has no state to save/restore.  The component timers will
        save themselves.  */
 }
+
+static void arm_timer_register_devices(void)
+{
+    sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
+    sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
+}
+
+device_init(arm_timer_register_devices)