X-Git-Url: http://git.maemo.org/git/?p=qemu;a=blobdiff_plain;f=hw%2Ftusb6010.c;fp=hw%2Ftusb6010.c;h=4a8e75cbafdaf69564cd09bebd79379eb4bdaec8;hp=dfd282474d6a1471f208a350eb104e65f894ab68;hb=a03c3bde4e288e790eccfb8cd45abd8ecbf467dc;hpb=e2ffa1bf065fa199f27d661d495573e9d6059bf1

diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index dfd2824..4a8e75c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -35,10 +35,10 @@
 #endif
 
 
-struct tusb_s {
+struct TUSBState {
     int iomemtype[2];
     qemu_irq irq;
-    struct musb_s *musb;
+    MUSBState *musb;
     QEMUTimer *otg_timer;
     QEMUTimer *pwr_timer;
 
@@ -244,17 +244,17 @@ struct tusb_s {
 #define TUSB_EP_CONFIG_XFR_SIZE(v)	((v) & 0x7fffffff)
 #define TUSB_PROD_TEST_RESET_VAL	0xa596
 
-int tusb6010_sync_io(struct tusb_s *s)
+int tusb6010_sync_io(TUSBState *s)
 {
     return s->iomemtype[0];
 }
 
-int tusb6010_async_io(struct tusb_s *s)
+int tusb6010_async_io(TUSBState *s)
 {
     return s->iomemtype[1];
 }
 
-static void tusb_intr_update(struct tusb_s *s)
+static void tusb_intr_update(TUSBState *s)
 {
     if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
         qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
@@ -262,7 +262,7 @@ static void tusb_intr_update(struct tusb_s *s)
         qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
 }
 
-static void tusb_usbip_intr_update(struct tusb_s *s)
+static void tusb_usbip_intr_update(TUSBState *s)
 {
     /* TX interrupt in the MUSB */
     if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
@@ -281,7 +281,7 @@ static void tusb_usbip_intr_update(struct tusb_s *s)
     tusb_intr_update(s);
 }
 
-static void tusb_dma_intr_update(struct tusb_s *s)
+static void tusb_dma_intr_update(TUSBState *s)
 {
     if (s->dma_intr & ~s->dma_mask)
         s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
@@ -291,7 +291,7 @@ static void tusb_dma_intr_update(struct tusb_s *s)
     tusb_intr_update(s);
 }
 
-static void tusb_gpio_intr_update(struct tusb_s *s)
+static void tusb_gpio_intr_update(TUSBState *s)
 {
     /* TODO: How is this signalled?  */
 }
@@ -301,7 +301,7 @@ extern CPUWriteMemoryFunc *musb_write[];
 
 static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -318,7 +318,7 @@ static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
 
 static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -335,7 +335,7 @@ static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
 
 static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
     int offset = addr & 0xfff;
     int epnum;
     uint32_t ret;
@@ -460,7 +460,7 @@ static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
 static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -481,7 +481,7 @@ static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
 static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -502,7 +502,7 @@ static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
 static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
     int offset = addr & 0xfff;
     int epnum;
 
@@ -522,8 +522,7 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
         s->dev_config = value;
         s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
         if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
-            cpu_abort(cpu_single_env, "%s: Product Test mode not allowed\n",
-                            __FUNCTION__);
+            hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
         break;
 
     case TUSB_PHY_OTG_CTRL_ENABLE:
@@ -674,7 +673,7 @@ static CPUWriteMemoryFunc *tusb_async_writefn[] = {
 
 static void tusb_otg_tick(void *opaque)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     s->otg_timer_val = 0;
     s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
@@ -683,7 +682,7 @@ static void tusb_otg_tick(void *opaque)
 
 static void tusb_power_tick(void *opaque)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     if (s->power) {
         s->intr_ok = ~0;
@@ -693,7 +692,7 @@ static void tusb_power_tick(void *opaque)
 
 static void tusb_musb_core_intr(void *opaque, int source, int level)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
     uint16_t otg_status = s->otg_status;
     TRACE("intr 0x%08x, 0x%08x, 0x%08x", source, level, musb_core_intr_get(s->musb));
 
@@ -744,9 +743,9 @@ static void tusb_musb_core_intr(void *opaque, int source, int level)
     }
 }
 
-struct tusb_s *tusb6010_init(qemu_irq intr)
+TUSBState *tusb6010_init(qemu_irq intr)
 {
-    struct tusb_s *s = qemu_mallocz(sizeof(*s));
+    TUSBState *s = qemu_mallocz(sizeof(*s));
 
     s->test_reset = TUSB_PROD_TEST_RESET_VAL;
     s->host_mode = 0;
@@ -767,7 +766,7 @@ struct tusb_s *tusb6010_init(qemu_irq intr)
     return s;
 }
 
-void tusb6010_power(struct tusb_s *s, int on)
+void tusb6010_power(TUSBState *s, int on)
 {
     if (!on)
         s->power = 0;