X-Git-Url: http://git.maemo.org/git/?p=qemu;a=blobdiff_plain;f=qemu-tech.texi;fp=qemu-tech.texi;h=ed2d35bf5e4382e515a0f00f5b720b408011edbe;hp=6c24d910c31e0533f80cf60dfeb395c6d4af211b;hb=759b334a9739814df2883aa4c41b1c0f5670e90a;hpb=7e2198fc87e878b8ce5df965477e21713ebf7834

diff --git a/qemu-tech.texi b/qemu-tech.texi
index 6c24d91..ed2d35b 100644
--- a/qemu-tech.texi
+++ b/qemu-tech.texi
@@ -363,7 +363,9 @@ look at @code{tcg/README}.
 Lazy evaluation of CPU condition codes (@code{EFLAGS} register on x86)
 is important for CPUs where every instruction sets the condition
 codes. It tends to be less important on conventional RISC systems
-where condition codes are only updated when explicitly requested.
+where condition codes are only updated when explicitly requested. On
+Sparc64, costly update of both 32 and 64 bit condition codes can be
+avoided with lazy evaluation.
 
 Instead of computing the condition codes after each x86 instruction,
 QEMU just stores one operand (called @code{CC_SRC}), the result
@@ -376,8 +378,8 @@ conditional branches.
 @code{CC_OP} is almost never explicitly set in the generated code
 because it is known at translation time.
 
-The lazy condition code evaluation is used on x86, m68k and cris. ARM
-uses a simplified variant for the N and Z flags.
+The lazy condition code evaluation is used on x86, m68k, cris and
+Sparc. ARM uses a simplified variant for the N and Z flags.
 
 @node CPU state optimisations
 @section CPU state optimisations