From 1d01299d29184c2d48af843626e0d7a5ef21aef7 Mon Sep 17 00:00:00 2001 From: blueswir1 Date: Wed, 10 Sep 2008 19:57:13 +0000 Subject: [PATCH] Convert basic 32 bit VIS ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-sparc/helper.h | 17 +------ target-sparc/op_helper.c | 81 ++++---------------------------- target-sparc/translate.c | 114 ++++++++++++++++------------------------------ 3 files changed, 48 insertions(+), 164 deletions(-) diff --git a/target-sparc/helper.h b/target-sparc/helper.h index a22c716..1c16b25 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -138,29 +138,16 @@ F_HELPER_0_0(stox); F_HELPER_0_0(dtox); F_HELPER_0_0(qtox); F_HELPER_0_0(aligndata); -DEF_HELPER(void, helper_movl_FT0_0, (void)) -DEF_HELPER(void, helper_movl_DT0_0, (void)) -DEF_HELPER(void, helper_movl_FT0_1, (void)) -DEF_HELPER(void, helper_movl_DT0_1, (void)) F_HELPER_0_0(not); -F_HELPER_0_0(nots); F_HELPER_0_0(nor); -F_HELPER_0_0(nors); F_HELPER_0_0(or); -F_HELPER_0_0(ors); F_HELPER_0_0(xor); -F_HELPER_0_0(xors); F_HELPER_0_0(and); -F_HELPER_0_0(ands); F_HELPER_0_0(ornot); -F_HELPER_0_0(ornots); F_HELPER_0_0(andnot); -F_HELPER_0_0(andnots); F_HELPER_0_0(nand); -F_HELPER_0_0(nands); F_HELPER_0_0(xnor); -F_HELPER_0_0(xnors); F_HELPER_0_0(pmerge); F_HELPER_0_0(mul8x16); F_HELPER_0_0(mul8x16al); @@ -172,9 +159,9 @@ F_HELPER_0_0(muld8ulx16); F_HELPER_0_0(expand); #define VIS_HELPER(name) \ F_HELPER_0_0(name##16); \ - F_HELPER_0_0(name##16s); \ + DEF_HELPER(uint32_t, helper_f ## name ## 16s, (uint32_t src1, uint32_t src2))\ F_HELPER_0_0(name##32); \ - F_HELPER_0_0(name##32s) + DEF_HELPER(uint32_t, helper_f ## name ## 32s, (uint32_t src1, uint32_t src2)) VIS_HELPER(padd); VIS_HELPER(psub); diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 84ed6f6..895e7ec 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -246,116 +246,51 @@ void helper_faligndata(void) *((uint64_t *)&DT0) = tmp; } -void helper_movl_FT0_0(void) -{ - *((uint32_t *)&FT0) = 0; -} - -void helper_movl_DT0_0(void) -{ - *((uint64_t *)&DT0) = 0; -} - -void helper_movl_FT0_1(void) -{ - *((uint32_t *)&FT0) = 0xffffffff; -} - -void helper_movl_DT0_1(void) -{ - *((uint64_t *)&DT0) = 0xffffffffffffffffULL; -} - void helper_fnot(void) { *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1; } -void helper_fnots(void) -{ - *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1; -} - void helper_fnor(void) { *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1); } -void helper_fnors(void) -{ - *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1); -} - void helper_for(void) { *(uint64_t *)&DT0 |= *(uint64_t *)&DT1; } -void helper_fors(void) -{ - *(uint32_t *)&FT0 |= *(uint32_t *)&FT1; -} - void helper_fxor(void) { *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1; } -void helper_fxors(void) -{ - *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1; -} - void helper_fand(void) { *(uint64_t *)&DT0 &= *(uint64_t *)&DT1; } -void helper_fands(void) -{ - *(uint32_t *)&FT0 &= *(uint32_t *)&FT1; -} - void helper_fornot(void) { *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1; } -void helper_fornots(void) -{ - *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1; -} - void helper_fandnot(void) { *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1; } -void helper_fandnots(void) -{ - *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1; -} - void helper_fnand(void) { *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1); } -void helper_fnands(void) -{ - *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1); -} - void helper_fxnor(void) { *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1; } -void helper_fxnors(void) -{ - *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1; -} - #ifdef WORDS_BIGENDIAN #define VIS_B64(n) b[7 - (n)] #define VIS_W64(n) w[3 - (n)] @@ -597,17 +532,17 @@ void helper_fexpand(void) DT0 = d.d; \ } \ \ - void name##16s(void) \ + uint32_t name##16s(uint32_t src1, uint32_t src2) \ { \ vis32 s, d; \ \ - s.f = FT0; \ - d.f = FT1; \ + s.l = src1; \ + d.l = src2; \ \ d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ \ - FT0 = d.f; \ + return d.l; \ } \ \ void name##32(void) \ @@ -623,16 +558,16 @@ void helper_fexpand(void) DT0 = d.d; \ } \ \ - void name##32s(void) \ + uint32_t name##32s(uint32_t src1, uint32_t src2) \ { \ vis32 s, d; \ \ - s.f = FT0; \ - d.f = FT1; \ + s.l = src1; \ + d.l = src2; \ \ d.l = F(d.l, s.l); \ \ - FT0 = d.f; \ + return d.l; \ } #define FADD(a, b) ((a) + (b)) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 937c708..017f4c6 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3836,10 +3836,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x051: /* VIS I fpadd16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fpadd16s); - gen_op_store_FT0_fpr(rd); + tcg_gen_helper_1_2(helper_fpadd16s, cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x052: /* VIS I fpadd32 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3850,10 +3848,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x053: /* VIS I fpadd32s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fpadd32s); - gen_op_store_FT0_fpr(rd); + tcg_gen_helper_1_2(helper_fpadd32s, cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x054: /* VIS I fpsub16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3864,10 +3860,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x055: /* VIS I fpsub16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fpsub16s); - gen_op_store_FT0_fpr(rd); + tcg_gen_helper_1_2(helper_fpsub16s, cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x056: /* VIS I fpsub32 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3878,20 +3872,17 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x057: /* VIS I fpsub32s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fpsub32s); - gen_op_store_FT0_fpr(rd); + tcg_gen_helper_1_2(helper_fpsub32s, cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_0_0(helper_movl_DT0_0); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0); + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); break; case 0x061: /* VIS I fzeros */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_0_0(helper_movl_FT0_0); - gen_op_store_FT0_fpr(rd); + tcg_gen_movi_i32(cpu_fpr[rd], 0); break; case 0x062: /* VIS I fnor */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3902,10 +3893,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x063: /* VIS I fnors */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fnors); - gen_op_store_FT0_fpr(rd); + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); + tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3916,10 +3905,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x065: /* VIS I fandnot2s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT1(rs1); - gen_op_load_fpr_FT0(rs2); - tcg_gen_helper_0_0(helper_fandnots); - gen_op_store_FT0_fpr(rd); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); + tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); break; case 0x066: /* VIS I fnot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3929,9 +3916,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x067: /* VIS I fnot2s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fnot); - gen_op_store_FT0_fpr(rd); + tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1); break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3942,10 +3927,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x069: /* VIS I fandnot1s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fandnots); - gen_op_store_FT0_fpr(rd); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); + tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); break; case 0x06a: /* VIS I fnot1 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3955,9 +3938,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06b: /* VIS I fnot1s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT1(rs1); - tcg_gen_helper_0_0(helper_fnot); - gen_op_store_FT0_fpr(rd); + tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1); break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3968,10 +3949,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06d: /* VIS I fxors */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fxors); - gen_op_store_FT0_fpr(rd); + tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3982,10 +3960,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06f: /* VIS I fnands */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fnands); - gen_op_store_FT0_fpr(rd); + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); + tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3996,10 +3972,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x071: /* VIS I fands */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fands); - gen_op_store_FT0_fpr(rd); + tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x072: /* VIS I fxnor */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4010,20 +3983,18 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x073: /* VIS I fxnors */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fxnors); - gen_op_store_FT0_fpr(rd); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); + tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); break; case 0x074: /* VIS I fsrc1 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); + tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x075: /* VIS I fsrc1s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_store_FT0_fpr(rd); + tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4034,10 +4005,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x077: /* VIS I fornot2s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT1(rs1); - gen_op_load_fpr_FT0(rs2); - tcg_gen_helper_0_0(helper_fornots); - gen_op_store_FT0_fpr(rd); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); + tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); break; case 0x078: /* VIS I fsrc2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4046,8 +4015,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x079: /* VIS I fsrc2s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs2); - gen_op_store_FT0_fpr(rd); + tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4058,10 +4026,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x07b: /* VIS I fornot1s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fornots); - gen_op_store_FT0_fpr(rd); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); + tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); break; case 0x07c: /* VIS I for */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4072,20 +4038,16 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x07d: /* VIS I fors */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_FT0(rs1); - gen_op_load_fpr_FT1(rs2); - tcg_gen_helper_0_0(helper_fors); - gen_op_store_FT0_fpr(rd); + tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x07e: /* VIS I fone */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_0_0(helper_movl_DT0_1); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1); + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); break; case 0x07f: /* VIS I fones */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_0_0(helper_movl_FT0_1); - gen_op_store_FT0_fpr(rd); + tcg_gen_movi_i32(cpu_fpr[rd], -1); break; case 0x080: /* VIS I shutdown */ case 0x081: /* VIS II siam */ -- 1.7.9.5