git.maemo.org Git - drnoksnes/blob - getset.h

   1 /*
   2  * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
   3  *
   4  * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and
   5  *                           Jerremy Koot (jkoot@snes9x.com)
   6  *
   7  * Super FX C emulator code
   8  * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and
   9  *                           Gary Henderson.
  10  * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
  11  *
  12  * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson.
  13  * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_.
  14  * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com).
  15  *
  16  * DOS port code contains the works of other authors. See headers in
  17  * individual files.
  18  *
  19  * Snes9x homepage: http://www.snes9x.com
  20  *
  21  * Permission to use, copy, modify and distribute Snes9x in both binary and
  22  * source form, for non-commercial purposes, is hereby granted without fee,
  23  * providing that this license information and copyright notice appear with
  24  * all copies and any derived work.
  25  *
  26  * This software is provided 'as-is', without any express or implied
  27  * warranty. In no event shall the authors be held liable for any damages
  28  * arising from the use of this software.
  29  *
  30  * Snes9x is freeware for PERSONAL USE only. Commercial users should
  31  * seek permission of the copyright holders first. Commercial use includes
  32  * charging money for Snes9x or software derived from Snes9x.
  33  *
  34  * The copyright holders request that bug fixes and improvements to the code
  35  * should be forwarded to them so everyone can benefit from the modifications
  36  * in future versions.
  37  *
  38  * Super NES and Super Nintendo Entertainment System are trademarks of
  39  * Nintendo Co., Limited and its subsidiary companies.
  40  */
  41 #ifndef _GETSET_H_
  42 #define _GETSET_H_
  43
  44 #include "ppu.h"
  45 #include "dsp1.h"
  46 #include "cpuexec.h"
  47 #include "sa1.h"
  48
  49 //#define __memcheck__
  50 //#define __show_io__
  51 extern int oppause;
  52 extern uint16 mem_check;
  53
  54 INLINE uint8 S9xGetByte (uint32 Address)
  55 {
  56 #ifdef __show_io__
  57         char str[64];
  58         sprintf(str,"rd @ %04X",Address);
  59         S9xMessage(0,0,str);
  60 #endif
  61 #ifdef __memcheck__
  62         mem_check+=(Address>>16)+Address;
  63 #endif
  64         const int block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK;
  65     uint8 *GetAddress = Memory.Map[block];
  66
  67         if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
  68         {
  69 #ifdef VAR_CYCLES
  70                 CPU.Cycles += Memory.MemorySpeed [block];
  71 #endif
  72 #ifdef CPU_SHUTDOWN
  73                 if (Memory.BlockIsRAM [block])
  74                         CPU.WaitAddress = CPU.PCAtOpcodeStart;
  75 #endif
  76                 return (*(GetAddress + (Address & 0xffff)));
  77         }
  78
  79     switch ((CMemory::Types)(intptr_t) GetAddress)
  80     {
  81     case CMemory::MAP_PPU:
  82 #ifdef VAR_CYCLES
  83         if (!CPU.InDMA)
  84             CPU.Cycles += ONE_CYCLE;
  85 #endif
  86         return (S9xGetPPU (Address & 0xffff));
  87     case CMemory::MAP_CPU:
  88 #ifdef VAR_CYCLES
  89         CPU.Cycles += ONE_CYCLE;
  90 #endif
  91         return (S9xGetCPU (Address & 0xffff));
  92     case CMemory::MAP_DSP:
  93 #ifdef VAR_CYCLES
  94         CPU.Cycles += SLOW_ONE_CYCLE;
  95 #endif
  96         return (S9xGetDSP (Address & 0xffff));
  97     case CMemory::MAP_SA1RAM:
  98     case CMemory::MAP_LOROM_SRAM:
  99 #ifdef VAR_CYCLES
 100         CPU.Cycles += SLOW_ONE_CYCLE;
 101 #endif
 102         return (*(Memory.SRAM + ((Address & CPU.Memory_SRAMMask))));
 103
 104     case CMemory::MAP_HIROM_SRAM:
 105 #ifdef VAR_CYCLES
 106         CPU.Cycles += SLOW_ONE_CYCLE;
 107 #endif
 108         return (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
 109                                   ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)));
 110
 111     case CMemory::MAP_DEBUG:
 112 #ifdef DEBUGGER
 113         printf ("R(B) %06x\n", Address);
 114 #endif
 115
 116     case CMemory::MAP_BWRAM:
 117 #ifdef VAR_CYCLES
 118         CPU.Cycles += SLOW_ONE_CYCLE;
 119 #endif
 120         return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)));
 121
 122     case CMemory::MAP_C4:
 123         return (S9xGetC4 (Address & 0xffff));
 124
 125     default:
 126     case CMemory::MAP_NONE:
 127 #ifdef VAR_CYCLES
 128         CPU.Cycles += SLOW_ONE_CYCLE;
 129 #endif
 130 #ifdef DEBUGGER
 131         printf ("R(B) %06x\n", Address);
 132 #endif
 133         return ((Address >> 8) & 0xff);
 134     }
 135 }
 136
 137 INLINE uint16 S9xGetWord (uint32 Address)
 138 {
 139 #ifdef __show_io__
 140         char str[64];
 141         sprintf(str,"rd @ %04X",Address);
 142         S9xMessage(0,0,str);
 143 #endif
 144 #ifdef __memcheck__
 145         mem_check+=(Address>>16)+Address;
 146 #endif
 147         if ((Address & 0x1fff) == 0x1fff)
 148         {
 149                 return (S9xGetByte (Address) | (S9xGetByte (Address + 1) << 8));
 150         }
 151
 152         const int block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK;
 153         uint8 *GetAddress = Memory.Map[block];
 154
 155     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 156     {
 157 #ifdef VAR_CYCLES
 158         CPU.Cycles += Memory.MemorySpeed [block] << 1;
 159 #endif
 160 #ifdef CPU_SHUTDOWN
 161         if (Memory.BlockIsRAM [block])
 162             CPU.WaitAddress = CPU.PCAtOpcodeStart;
 163 #endif
 164 #ifdef FAST_LSB_WORD_ACCESS
 165         return (*(uint16 *) (GetAddress + (Address & 0xffff)));
 166 #else
 167         return (*(GetAddress + (Address & 0xffff)) |
 168                 (*(GetAddress + (Address & 0xffff) + 1) << 8));
 169 #endif
 170     }
 171
 172     switch ((CMemory::Types)(intptr_t) GetAddress)
 173     {
 174     case CMemory::MAP_PPU:
 175 #ifdef VAR_CYCLES
 176         if (!CPU.InDMA)
 177             CPU.Cycles += TWO_CYCLES;
 178 #endif
 179         return (S9xGetPPU (Address & 0xffff) |
 180                 (S9xGetPPU ((Address + 1) & 0xffff) << 8));
 181     case CMemory::MAP_CPU:
 182 #ifdef VAR_CYCLES
 183         CPU.Cycles += TWO_CYCLES;
 184 #endif
 185         return (S9xGetCPU (Address & 0xffff) |
 186                 (S9xGetCPU ((Address + 1) & 0xffff) << 8));
 187     case CMemory::MAP_DSP:
 188 #ifdef VAR_CYCLES
 189         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 190 #endif
 191         return (S9xGetDSP (Address & 0xffff) |
 192                 (S9xGetDSP ((Address + 1) & 0xffff) << 8));
 193     case CMemory::MAP_SA1RAM:
 194     case CMemory::MAP_LOROM_SRAM:
 195 #ifdef VAR_CYCLES
 196         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 197 #endif
 198         return (*(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) |
 199                 (*(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) << 8));
 200
 201     case CMemory::MAP_HIROM_SRAM:
 202 #ifdef VAR_CYCLES
 203         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 204 #endif
 205         return (*(Memory.SRAM +
 206                   (((Address & 0x7fff) - 0x6000 +
 207                     ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) |
 208                 (*(Memory.SRAM +
 209                    ((((Address + 1) & 0x7fff) - 0x6000 +
 210                      (((Address + 1) & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) << 8));
 211
 212     case CMemory::MAP_BWRAM:
 213 #ifdef VAR_CYCLES
 214         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 215 #endif
 216         return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) |
 217                 (*(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) << 8));
 218
 219     case CMemory::MAP_DEBUG:
 220 #ifdef DEBUGGER
 221         printf ("R(W) %06x\n", Address);
 222 #endif
 223
 224     case CMemory::MAP_C4:
 225         return (S9xGetC4 (Address & 0xffff) |
 226                 (S9xGetC4 ((Address + 1) & 0xffff) << 8));
 227
 228     default:
 229     case CMemory::MAP_NONE:
 230 #ifdef VAR_CYCLES
 231         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 232 #endif
 233 #ifdef DEBUGGER
 234         printf ("R(W) %06x\n", Address);
 235 #endif
 236         return (((Address >> 8) | (Address & 0xff00)) & 0xffff);
 237     }
 238 }
 239
 240 INLINE void S9xSetByte (uint8 Byte, uint32 Address)
 241 {
 242 #ifdef __show_io__
 243         char str[64];
 244         sprintf(str,"wr @ %04X %02X",Address,Byte);
 245         S9xMessage(0,0,str);
 246 #endif
 247 #ifdef __memcheck__
 248         mem_check+=Byte;
 249 #endif
 250
 251 #if defined(CPU_SHUTDOWN)
 252     CPU.WaitAddress = NULL;
 253 #endif
 254         const int block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK;
 255         uint8 *SetAddress = Memory.WriteMap[block];
 256
 257     if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
 258     {
 259 #ifdef VAR_CYCLES
 260         CPU.Cycles += Memory.MemorySpeed [block];
 261 #endif
 262 #ifdef CPU_SHUTDOWN
 263         SetAddress += Address & 0xffff;
 264 #ifdef USE_SA1
 265         if (SetAddress == SA1.WaitByteAddress1 ||
 266             SetAddress == SA1.WaitByteAddress2)
 267         {
 268             SA1.Executing = SA1.S9xOpcodes != NULL;
 269             SA1.WaitCounter = 0;
 270         }
 271 #endif
 272         *SetAddress = Byte;
 273 #else
 274         *(SetAddress + (Address & 0xffff)) = Byte;
 275 #endif
 276         return;
 277     }
 278
 279     switch ((CMemory::Types)(intptr_t) SetAddress)
 280     {
 281     case CMemory::MAP_PPU:
 282 #ifdef VAR_CYCLES
 283         if (!CPU.InDMA)
 284             CPU.Cycles += ONE_CYCLE;
 285 #endif
 286         S9xSetPPU (Byte, Address & 0xffff);
 287         return;
 288
 289     case CMemory::MAP_CPU:
 290 #ifdef VAR_CYCLES
 291         CPU.Cycles += ONE_CYCLE;
 292 #endif
 293         S9xSetCPU (Byte, Address & 0xffff);
 294         return;
 295
 296     case CMemory::MAP_DSP:
 297 #ifdef VAR_CYCLES
 298         CPU.Cycles += SLOW_ONE_CYCLE;
 299 #endif
 300         S9xSetDSP (Byte, Address & 0xffff);
 301         return;
 302
 303     case CMemory::MAP_LOROM_SRAM:
 304 #ifdef VAR_CYCLES
 305         CPU.Cycles += SLOW_ONE_CYCLE;
 306 #endif
 307         if (CPU.Memory_SRAMMask)
 308         {
 309             *(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = Byte;
 310             CPU.SRAMModified = TRUE;
 311         }
 312         return;
 313
 314     case CMemory::MAP_HIROM_SRAM:
 315 #ifdef VAR_CYCLES
 316         CPU.Cycles += SLOW_ONE_CYCLE;
 317 #endif
 318         if (CPU.Memory_SRAMMask)
 319         {
 320             *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
 321                               ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) = Byte;
 322             CPU.SRAMModified = TRUE;
 323         }
 324         return;
 325
 326     case CMemory::MAP_BWRAM:
 327 #ifdef VAR_CYCLES
 328         CPU.Cycles += SLOW_ONE_CYCLE;
 329 #endif
 330         *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte;
 331         CPU.SRAMModified = TRUE;
 332         return;
 333
 334     case CMemory::MAP_DEBUG:
 335 #ifdef DEBUGGER
 336         printf ("W(B) %06x\n", Address);
 337 #endif
 338
 339     case CMemory::MAP_SA1RAM:
 340 #ifdef VAR_CYCLES
 341         CPU.Cycles += SLOW_ONE_CYCLE;
 342 #endif
 343         *(Memory.SRAM + (Address & 0xffff)) = Byte;
 344         SA1.Executing = !SA1.Waiting;
 345         break;
 346
 347     case CMemory::MAP_C4:
 348         S9xSetC4 (Byte, Address & 0xffff);
 349         return;
 350
 351     default:
 352     case CMemory::MAP_NONE:
 353 #ifdef VAR_CYCLES
 354         CPU.Cycles += SLOW_ONE_CYCLE;
 355 #endif
 356 #ifdef DEBUGGER
 357         printf ("W(B) %06x\n", Address);
 358 #endif
 359         return;
 360     }
 361 }
 362
 363 INLINE void S9xSetWord (uint16 Word, uint32 Address)
 364 {
 365 #ifdef __show_io__
 366         char str[64];
 367         sprintf(str,"wr @ %04X %04X",Address,Word);
 368         S9xMessage(0,0,str);
 369 #endif
 370 #ifdef __memcheck__
 371         mem_check+=Word;
 372 #endif
 373 #if defined(CPU_SHUTDOWN)
 374     CPU.WaitAddress = NULL;
 375 #endif
 376         const int block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK;
 377         uint8 *SetAddress = Memory.WriteMap[block];
 378
 379     if (SetAddress >= (uint8 *) CMemory::MAP_LAST)
 380     {
 381 #ifdef VAR_CYCLES
 382         CPU.Cycles += Memory.MemorySpeed [block] << 1;
 383 #endif
 384 #if defined(CPU_SHUTDOWN) && defined(USE_SA1)
 385         uint8 *SetAddressSA1 = SetAddress + (Address & 0xffff);
 386         if (SetAddressSA1 == SA1.WaitByteAddress1 ||
 387             SetAddressSA1 == SA1.WaitByteAddress2)
 388         {
 389             SA1.Executing = SA1.S9xOpcodes != NULL;
 390             SA1.WaitCounter = 0;
 391         }
 392 #endif
 393 #ifdef FAST_LSB_WORD_ACCESS
 394         *(uint16 *) (SetAddress + (Address & 0xffff)) = Word;
 395 #else
 396         *(SetAddress + (Address & 0xffff)) = (uint8) Word;
 397         *(SetAddress + ((Address + 1) & 0xffff)) = Word >> 8;
 398 #endif
 399         return;
 400     }
 401
 402     switch ((CMemory::Types)(intptr_t) SetAddress)
 403     {
 404     case CMemory::MAP_PPU:
 405 #ifdef VAR_CYCLES
 406         if (!CPU.InDMA)
 407             CPU.Cycles += TWO_CYCLES;
 408 #endif
 409         S9xSetPPU ((uint8) Word, Address & 0xffff);
 410         S9xSetPPU (Word >> 8, (Address & 0xffff) + 1);
 411         return;
 412
 413     case CMemory::MAP_CPU:
 414 #ifdef VAR_CYCLES
 415         CPU.Cycles += TWO_CYCLES;
 416 #endif
 417         S9xSetCPU ((uint8) Word, (Address & 0xffff));
 418         S9xSetCPU (Word >> 8, (Address & 0xffff) + 1);
 419         return;
 420
 421     case CMemory::MAP_DSP:
 422 #ifdef VAR_CYCLES
 423         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 424 #endif
 425         S9xSetDSP ((uint8) Word, (Address & 0xffff));
 426         S9xSetDSP (Word >> 8, (Address & 0xffff) + 1);
 427         return;
 428
 429     case CMemory::MAP_LOROM_SRAM:
 430 #ifdef VAR_CYCLES
 431         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 432 #endif
 433         if (CPU.Memory_SRAMMask)
 434         {
 435             *(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = (uint8) Word;
 436             *(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) = Word >> 8;
 437             CPU.SRAMModified = TRUE;
 438         }
 439         return;
 440
 441     case CMemory::MAP_HIROM_SRAM:
 442 #ifdef VAR_CYCLES
 443         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 444 #endif
 445         if (CPU.Memory_SRAMMask)
 446         {
 447                 *(Memory.SRAM +
 448                         ((Address & 0x7fff) - 0x6000) +
 449                         (((Address & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask)
 450                 ) =     (uint8) Word;
 451
 452                 *(Memory.SRAM +
 453                         (((Address + 1) & 0x7fff) - 0x6000) +
 454                         ((((Address + 1) & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask)
 455                 ) = (uint8) (Word >> 8);
 456
 457             CPU.SRAMModified = TRUE;
 458         }
 459         return;
 460
 461     case CMemory::MAP_BWRAM:
 462 #ifdef VAR_CYCLES
 463         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 464 #endif
 465         *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = (uint8) Word;
 466         *(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) = (uint8) (Word >> 8);
 467         CPU.SRAMModified = TRUE;
 468         return;
 469
 470     case CMemory::MAP_DEBUG:
 471 #ifdef DEBUGGER
 472         printf ("W(W) %06x\n", Address);
 473 #endif
 474
 475     case CMemory::MAP_SA1RAM:
 476 #ifdef VAR_CYCLES
 477         CPU.Cycles += SLOW_ONE_CYCLE;
 478 #endif
 479         *(Memory.SRAM + (Address & 0xffff)) = (uint8) Word;
 480         *(Memory.SRAM + ((Address + 1) & 0xffff)) = (uint8) (Word >> 8);
 481         SA1.Executing = !SA1.Waiting;
 482         break;
 483
 484     case CMemory::MAP_C4:
 485         S9xSetC4 (Word & 0xff, Address & 0xffff);
 486         S9xSetC4 ((uint8) (Word >> 8), (Address + 1) & 0xffff);
 487         return;
 488
 489     default:
 490     case CMemory::MAP_NONE:
 491 #ifdef VAR_CYCLES
 492         CPU.Cycles += SLOW_ONE_CYCLE * 2;
 493 #endif
 494 #ifdef DEBUGGER
 495         printf ("W(W) %06x\n", Address);
 496 #endif
 497         return;
 498     }
 499 }
 500
 501 INLINE uint8 *GetBasePointer (uint32 Address)
 502 {
 503     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 504     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 505         return (GetAddress);
 506
 507     switch ((CMemory::Types)(intptr_t) GetAddress)
 508     {
 509     case CMemory::MAP_PPU:
 510         return (Memory.FillRAM - 0x2000);
 511     case CMemory::MAP_CPU:
 512         return (Memory.FillRAM - 0x4000);
 513     case CMemory::MAP_DSP:
 514         return (Memory.FillRAM - 0x6000);
 515     case CMemory::MAP_SA1RAM:
 516     case CMemory::MAP_LOROM_SRAM:
 517         return (Memory.SRAM);
 518     case CMemory::MAP_BWRAM:
 519         return (Memory.BWRAM - 0x6000);
 520     case CMemory::MAP_HIROM_SRAM:
 521         return (Memory.SRAM - 0x6000);
 522     case CMemory::MAP_C4:
 523         return (Memory.C4RAM - 0x6000);
 524     case CMemory::MAP_DEBUG:
 525 #ifdef DEBUGGER
 526         printf ("GBP %06x\n", Address);
 527 #endif
 528     default:
 529     case CMemory::MAP_NONE:
 530 #ifdef DEBUGGER
 531         printf ("GBP %06x\n", Address);
 532 #endif
 533         return (0);
 534     }
 535 }
 536
 537 INLINE uint8 *S9xGetMemPointer (uint32 Address)
 538 {
 539     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 540     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 541         return (GetAddress + (Address & 0xffff));
 542
 543     switch ((CMemory::Types)(intptr_t) GetAddress)
 544     {
 545     case CMemory::MAP_PPU:
 546         return (Memory.FillRAM - 0x2000 + (Address & 0xffff));
 547     case CMemory::MAP_CPU:
 548         return (Memory.FillRAM - 0x4000 + (Address & 0xffff));
 549     case CMemory::MAP_DSP:
 550         return (Memory.FillRAM - 0x6000 + (Address & 0xffff));
 551     case CMemory::MAP_SA1RAM:
 552     case CMemory::MAP_LOROM_SRAM:
 553         return (Memory.SRAM + (Address & 0xffff));
 554     case CMemory::MAP_BWRAM:
 555         return (Memory.BWRAM - 0x6000 + (Address & 0xffff));
 556     case CMemory::MAP_HIROM_SRAM:
 557         return (Memory.SRAM - 0x6000 + (Address & 0xffff));
 558
 559     case CMemory::MAP_C4:
 560         return (Memory.C4RAM - 0x6000 + (Address & 0xffff));
 561
 562     case CMemory::MAP_DEBUG:
 563 #ifdef DEBUGGER
 564         printf ("GMP %06x\n", Address);
 565 #endif
 566     default:
 567     case CMemory::MAP_NONE:
 568 #ifdef DEBUGGER
 569         printf ("GMP %06x\n", Address);
 570 #endif
 571         return (0);
 572     }
 573 }
 574
 575 INLINE void S9xSetPCBase (uint32 Address)
 576 {
 577 #ifdef VAR_CYCLES
 578     int block;
 579     uint8 *GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 580 #else
 581     uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
 582 #endif
 583     if (GetAddress >= (uint8 *) CMemory::MAP_LAST)
 584     {
 585 #ifdef VAR_CYCLES
 586         CPU.MemSpeed = Memory.MemorySpeed [block];
 587         CPU.MemSpeedx2 = CPU.MemSpeed << 1;
 588 #endif
 589         CPU.PCBase = GetAddress;
 590         CPU.PC = GetAddress + (Address & 0xffff);
 591         return;
 592     }
 593
 594     switch ((CMemory::Types)(intptr_t) GetAddress)
 595     {
 596     case CMemory::MAP_PPU:
 597 #ifdef VAR_CYCLES
 598         CPU.MemSpeed = ONE_CYCLE;
 599         CPU.MemSpeedx2 = TWO_CYCLES;
 600 #endif
 601         CPU.PCBase = Memory.FillRAM - 0x2000;
 602         CPU.PC = CPU.PCBase + (Address & 0xffff);
 603         return;
 604
 605     case CMemory::MAP_CPU:
 606 #ifdef VAR_CYCLES
 607         CPU.MemSpeed = ONE_CYCLE;
 608         CPU.MemSpeedx2 = TWO_CYCLES;
 609 #endif
 610         CPU.PCBase = Memory.FillRAM - 0x4000;
 611         CPU.PC = CPU.PCBase + (Address & 0xffff);
 612         return;
 613
 614     case CMemory::MAP_DSP:
 615 #ifdef VAR_CYCLES
 616         CPU.MemSpeed = SLOW_ONE_CYCLE;
 617         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 618 #endif
 619         CPU.PCBase = Memory.FillRAM - 0x6000;
 620         CPU.PC = CPU.PCBase + (Address & 0xffff);
 621         return;
 622
 623     case CMemory::MAP_SA1RAM:
 624     case CMemory::MAP_LOROM_SRAM:
 625 #ifdef VAR_CYCLES
 626         CPU.MemSpeed = SLOW_ONE_CYCLE;
 627         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 628 #endif
 629         CPU.PCBase = Memory.SRAM;
 630         CPU.PC = CPU.PCBase + (Address & 0xffff);
 631         return;
 632
 633     case CMemory::MAP_BWRAM:
 634 #ifdef VAR_CYCLES
 635         CPU.MemSpeed = SLOW_ONE_CYCLE;
 636         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 637 #endif
 638         CPU.PCBase = Memory.BWRAM - 0x6000;
 639         CPU.PC = CPU.PCBase + (Address & 0xffff);
 640         return;
 641     case CMemory::MAP_HIROM_SRAM:
 642 #ifdef VAR_CYCLES
 643         CPU.MemSpeed = SLOW_ONE_CYCLE;
 644         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 645 #endif
 646         CPU.PCBase = Memory.SRAM - 0x6000;
 647         CPU.PC = CPU.PCBase + (Address & 0xffff);
 648         return;
 649
 650     case CMemory::MAP_C4:
 651 #ifdef VAR_CYCLES
 652         CPU.MemSpeed = SLOW_ONE_CYCLE;
 653         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 654 #endif
 655         CPU.PCBase = Memory.C4RAM - 0x6000;
 656         CPU.PC = CPU.PCBase + (Address & 0xffff);
 657         return;
 658
 659     case CMemory::MAP_DEBUG:
 660 #ifdef DEBUGGER
 661         printf ("SBP %06x\n", Address);
 662 #endif
 663
 664     default:
 665     case CMemory::MAP_NONE:
 666 #ifdef VAR_CYCLES
 667         CPU.MemSpeed = SLOW_ONE_CYCLE;
 668         CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
 669 #endif
 670 #ifdef DEBUGGER
 671         printf ("SBP %06x\n", Address);
 672 #endif
 673         CPU.PCBase = Memory.SRAM;
 674         CPU.PC = Memory.SRAM + (Address & 0xffff);
 675         return;
 676     }
 677 }
 678 #endif