git.maemo.org Git - drnoksnes/blob - os9x_65c816.s

   1
   2 /****************************************************************
   3 ****************************************************************/
   4 @ notaz
   5 .equiv ASM_SPC700,              1               ;@ 1 = use notaz's ASM_SPC700 core
   6
   7 /****************************************************************
   8         DEFINES
   9 ****************************************************************/
  10
  11 .equ MAP_LAST,  12
  12
  13 rstatus         .req R4  @ format : 0xff800000
  14 reg_d_bank      .req R4  @ format : 0x000000ll
  15 reg_a           .req R5  @ format : 0xhhll0000 or 0xll000000
  16 reg_d           .req R6  @ format : 0xhhll0000
  17 reg_p_bank      .req R6  @ format : 0x000000ll
  18 reg_x           .req R7  @ format : 0xhhll0000 or 0xll000000
  19 reg_s           .req R8  @ format : 0x0000hhll
  20 reg_y           .req R9  @ format : 0xhhll0000 or 0xll000000
  21
  22 rpc             .req R10 @ 32bits address
  23 reg_cycles      .req R11 @ 32bits counter
  24 regpcbase       .req R12 @ 32bits address
  25
  26 rscratch        .req R0  @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD
  27 regopcode       .req R0  @ format : 0x000000ll
  28 rscratch2       .req R1  @ format : 0xhhll for calculation and value
  29 rscratch3       .req R2  @
  30 rscratch4       .req R3  @ ??????
  31
  32 @ used for SBC opcode
  33 rscratch9       .req R10 @ ??????
  34
  35 reg_cpu_var .req R14
  36
  37
  38 @ not used
  39 @ R13   @ Pointer 32 bit on a struct.
  40
  41 @ R15 = pc (sic!)
  42
  43 .equ STATUS_SHIFTER,            24
  44 .equ MASK_EMUL,         (1<<(STATUS_SHIFTER-1))
  45 .equ MASK_SHIFTER_CARRY,        (STATUS_SHIFTER+1)
  46 .equ    MASK_CARRY,             (1<<(STATUS_SHIFTER))  @ 0
  47 .equ    MASK_ZERO,              (2<<(STATUS_SHIFTER))  @ 1
  48 .equ MASK_IRQ,          (4<<(STATUS_SHIFTER))  @ 2
  49 .equ MASK_DECIMAL,              (8<<(STATUS_SHIFTER))  @ 3
  50 .equ    MASK_INDEX,             (16<<(STATUS_SHIFTER)) @ 4  @ 1
  51 .equ    MASK_MEM,               (32<<(STATUS_SHIFTER)) @ 5  @ 2
  52 .equ    MASK_OVERFLOW,          (64<<(STATUS_SHIFTER)) @ 6  @ 4
  53 .equ    MASK_NEG,               (128<<(STATUS_SHIFTER))@ 7  @ 8
  54
  55 .equ ONE_CYCLE, 6
  56 .equ SLOW_ONE_CYCLE, 8
  57
  58 .equ    NMI_FLAG,           (1 << 7)
  59 .equ IRQ_PENDING_FLAG,    (1 << 11)
  60 .equ SCAN_KEYS_FLAG,        (1 << 4)
  61
  62
  63 .equ MEMMAP_BLOCK_SIZE, (0x1000)
  64 .equ MEMMAP_SHIFT, 12
  65 .equ MEMMAP_MASK, (0xFFF)
  66
  67 /****************************************************************
  68         MACROS
  69 ****************************************************************/
  70
  71 @ #include "os9x_65c816_mac_gen.h"
  72 /*****************************************************************/
  73 /*     Offset in SCPUState structure                             */
  74 /*****************************************************************/
  75 .equ Flags_ofs,             0
  76 .equ BranchSkip_ofs,    4
  77 .equ NMIActive_ofs,             5
  78 .equ IRQActive_ofs,             6
  79 .equ WaitingForInterrupt_ofs,   7
  80
  81 .equ    RPB_ofs,                8
  82 .equ    RDB_ofs,                9
  83 .equ    RP_ofs,             10
  84 .equ    RA_ofs,             12
  85 .equ    RAH_ofs,            13
  86 .equ    RD_ofs,             14
  87 .equ    RX_ofs,             16
  88 .equ    RS_ofs,             18
  89 .equ    RY_ofs,             20
  90 @.equ   RPC_ofs,                22
  91
  92 .equ PC_ofs,                    24
  93 .equ Cycles_ofs,                28
  94 .equ PCBase_ofs,                32
  95
  96 .equ PCAtOpcodeStart_ofs,       36
  97 .equ WaitAddress_ofs,           40
  98 .equ WaitCounter_ofs,           44
  99 .equ NextEvent_ofs,                 48
 100 .equ V_Counter_ofs,                 52
 101 .equ MemSpeed_ofs,                  56
 102 .equ MemSpeedx2_ofs,            60
 103 .equ FastROMSpeed_ofs,      64
 104 .equ AutoSaveTimer_ofs,     68
 105 .equ NMITriggerPoint_ofs,       72
 106 .equ NMICycleCount_ofs,     76
 107 .equ IRQCycleCount_ofs,     80
 108
 109 .equ InDMA_ofs,                 84
 110 .equ WhichEvent,                    85
 111 .equ SRAMModified_ofs,      86
 112 .equ BRKTriggered_ofs,      87
 113 .equ    asm_OPTABLE_ofs,                88
 114 .equ TriedInterleavedMode2_ofs, 92
 115
 116 .equ Map_ofs,               96
 117 .equ WriteMap_ofs,      100
 118 .equ MemorySpeed_ofs,   104
 119 .equ BlockIsRAM_ofs,    108
 120 .equ SRAM,                      112
 121 .equ BWRAM,             116
 122 .equ SRAMMask,          120
 123
 124 .equ    APUExecuting_ofs,   122
 125 @ notaz
 126 .equ    APU_Cycles,         124
 127
 128 /*****************************************************************/
 129
 130 /* prepare */
 131 .macro          PREPARE_C_CALL
 132         STMFD   R13!,{R12,R14}
 133 .endm
 134 .macro          PREPARE_C_CALL_R0
 135         STMFD   R13!,{R0,R12,R14}
 136 .endm
 137 .macro          PREPARE_C_CALL_R0R1
 138         STMFD   R13!,{R0,R1,R12,R14}
 139 .endm
 140 .macro          PREPARE_C_CALL_LIGHT
 141         STMFD   R13!,{R14}
 142 .endm
 143 .macro          PREPARE_C_CALL_LIGHTR12
 144         STMFD   R13!,{R12,R14}
 145 .endm
 146 /* restore */
 147 .macro          RESTORE_C_CALL
 148         LDMFD   R13!,{R12,R14}
 149 .endm
 150 .macro          RESTORE_C_CALL_R0
 151         LDMFD   R13!,{R0,R12,R14}
 152 .endm
 153 .macro          RESTORE_C_CALL_R1
 154         LDMFD   R13!,{R1,R12,R14}
 155 .endm
 156 .macro          RESTORE_C_CALL_LIGHT
 157         LDMFD   R13!,{R14}
 158 .endm
 159 .macro          RESTORE_C_CALL_LIGHTR12
 160         LDMFD   R13!,{R12,R14}
 161 .endm
 162
 163
 164 @ --------------
 165 .macro          LOAD_REGS
 166     @ notaz
 167     add     r0,reg_cpu_var,#8
 168     ldmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 169     @ rstatus (P) & reg_d_bank
 170     mov     reg_d_bank,r1,lsl #16
 171     mov     reg_d_bank,reg_d_bank,lsr #24
 172     mov     r0,r1,lsr #16
 173         orrs    rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24
 174         @ if Carry set, then EMULATION bit was set
 175         orrcs   rstatus,rstatus,#MASK_EMUL
 176     @ reg_d & reg_p_bank
 177     mov     reg_d,reg_a,lsr #16
 178     mov     reg_d,reg_d,lsl #8
 179     orr     reg_d,reg_d,r1,lsl #24
 180     mov     reg_d,reg_d,ror #24    @ 0xdddd00pb
 181     @ reg_x, reg_s
 182     mov     reg_s,reg_x,lsr #16
 183         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 184         tst             rstatus,#MASK_INDEX
 185         movne   reg_x,reg_x,lsl #24
 186         movne   reg_y,reg_y,lsl #24
 187         moveq   reg_x,reg_x,lsl #16
 188         moveq   reg_y,reg_y,lsl #16
 189         tst             rstatus,#MASK_MEM
 190         movne   reg_a,reg_a,lsl #24
 191         moveq   reg_a,reg_a,lsl #16
 192
 193 /*
 194     @ reg_d & reg_p_bank share the same register
 195         LDRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 196         LDRH            rscratch,[reg_cpu_var,#RD_ofs]
 197         ORR             reg_d,reg_d,rscratch, LSL #16
 198         @ rstatus & reg_d_bank share the same register
 199         LDRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 200         LDRH            rscratch,[reg_cpu_var,#RP_ofs]
 201         ORRS            rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24
 202         @ if Carry set, then EMULATION bit was set
 203         ORRCS           rstatus,rstatus,#MASK_EMUL
 204         @
 205         LDRH            reg_a,[reg_cpu_var,#RA_ofs]
 206         LDRH            reg_x,[reg_cpu_var,#RX_ofs]
 207         LDRH            reg_y,[reg_cpu_var,#RY_ofs]
 208         LDRH            reg_s,[reg_cpu_var,#RS_ofs]
 209         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 210         TST             rstatus,#MASK_INDEX
 211         MOVNE           reg_x,reg_x,LSL #24
 212         MOVNE           reg_y,reg_y,LSL #24
 213         MOVEQ           reg_x,reg_x,LSL #16
 214         MOVEQ           reg_y,reg_y,LSL #16
 215         TST             rstatus,#MASK_MEM
 216         MOVNE           reg_a,reg_a,LSL #24
 217         MOVEQ           reg_a,reg_a,LSL #16
 218
 219         LDR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 220         LDR             rpc,[reg_cpu_var,#PC_ofs]
 221         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 222 */
 223 .endm
 224
 225
 226 .macro          SAVE_REGS
 227     @ notaz
 228     @ reg_p_bank, reg_d_bank and rstatus
 229     mov         r1, rstatus, lsr #16
 230     orr     r1, r1, reg_p_bank, lsl #24
 231         movs    r1, r1, lsr #8
 232         orrcs   r1, r1, #0x100 @ EMULATION bit
 233     orr     r1, r1, reg_d_bank, lsl #24
 234     mov     r1, r1, ror #16
 235     @ reg_a, reg_d
 236         tst             rstatus,#MASK_MEM
 237         ldrneh  r0, [reg_cpu_var,#RA_ofs]
 238         bicne   r0, r0,#0xFF
 239         orrne   reg_a, r0, reg_a,lsr #24
 240         moveq   reg_a, reg_a, lsr #16
 241     mov     reg_d, reg_d, lsr #16
 242         orr     reg_a, reg_a, reg_d, lsl #16
 243         @ Shift X&Y according to the current mode (INDEX, MEMORY bits)
 244         tst             rstatus,#MASK_INDEX
 245         movne   reg_x,reg_x,LSR #24
 246         movne   reg_y,reg_y,LSR #24
 247         moveq   reg_x,reg_x,LSR #16
 248         moveq   reg_y,reg_y,LSR #16
 249     @ reg_x, reg_s
 250         orr     reg_x, reg_x, reg_s, lsl #16
 251     @ store
 252     add     r0,reg_cpu_var,#8
 253     stmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 254
 255 /*
 256     @ reg_d & reg_p_bank is same register
 257         STRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 258         MOV             rscratch,reg_d, LSR #16
 259         STRH            rscratch,[reg_cpu_var,#RD_ofs]
 260         @ rstatus & reg_d_bank is same register
 261         STRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 262         MOVS            rscratch, rstatus, LSR #STATUS_SHIFTER
 263         ORRCS           rscratch,rscratch,#0x100 @ EMULATION bit
 264         STRH            rscratch,[reg_cpu_var,#RP_ofs]
 265         @
 266         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 267         TST             rstatus,#MASK_INDEX
 268         MOVNE           rscratch,reg_x,LSR #24
 269         MOVNE           rscratch2,reg_y,LSR #24
 270         MOVEQ           rscratch,reg_x,LSR #16
 271         MOVEQ           rscratch2,reg_y,LSR #16
 272         STRH            rscratch,[reg_cpu_var,#RX_ofs]
 273         STRH            rscratch2,[reg_cpu_var,#RY_ofs]
 274         TST             rstatus,#MASK_MEM
 275         LDRNEH          rscratch,[reg_cpu_var,#RA_ofs]
 276         BICNE           rscratch,rscratch,#0xFF
 277         ORRNE           rscratch,rscratch,reg_a,LSR #24
 278         MOVEQ           rscratch,reg_a,LSR #16
 279         STRH            rscratch,[reg_cpu_var,#RA_ofs]
 280
 281         STRH            reg_s,[reg_cpu_var,#RS_ofs]
 282         STR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 283         STR             rpc,[reg_cpu_var,#PC_ofs]
 284
 285         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 286 */
 287 .endm
 288
 289 /*****************************************************************/
 290 .macro          ADD1CYCLE
 291                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 292 .endm
 293 .macro          ADD1CYCLENE
 294                 addne   reg_cycles,reg_cycles, #ONE_CYCLE
 295 .endm
 296 .macro          ADD1CYCLEEQ
 297                 addeq   reg_cycles,reg_cycles, #ONE_CYCLE
 298 .endm
 299
 300 .macro          ADD2CYCLE
 301                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 302 .endm
 303 .macro          ADD2CYCLENE
 304                 addne   reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 305 .endm
 306 .macro          ADD2CYCLE2MEM
 307                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 308                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 309                 add     reg_cycles, reg_cycles, rscratch, LSL #1
 310 .endm
 311 .macro          ADD2CYCLE1MEM
 312                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 313                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 314                 add     reg_cycles, reg_cycles, rscratch
 315 .endm
 316
 317 .macro          ADD3CYCLE
 318                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*3)
 319 .endm
 320
 321 .macro          ADD1CYCLE1MEM
 322                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 323                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 324                 add     reg_cycles, reg_cycles, rscratch
 325 .endm
 326
 327 .macro          ADD1CYCLE2MEM
 328                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 329                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 330                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 331 .endm
 332
 333 .macro          ADD1MEM
 334                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 335                 add     reg_cycles, reg_cycles, rscratch
 336 .endm
 337
 338 .macro          ADD2MEM
 339                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 340                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 341 .endm
 342
 343 .macro          ADD3MEM
 344                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 345                 add     reg_cycles, rscratch, reg_cycles
 346                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 347 .endm
 348
 349 /**************/
 350 .macro          ClearDecimal
 351                 BIC     rstatus,rstatus,#MASK_DECIMAL
 352 .endm
 353 .macro          SetDecimal
 354                 ORR     rstatus,rstatus,#MASK_DECIMAL
 355 .endm
 356 .macro          SetIRQ
 357                 ORR     rstatus,rstatus,#MASK_IRQ
 358 .endm
 359 .macro          ClearIRQ
 360                 BIC     rstatus,rstatus,#MASK_IRQ
 361 .endm
 362
 363 .macro          CPUShutdown
 364 @ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress)
 365                 LDR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 366                 CMP             rpc,rscratch
 367                 BNE             5431f
 368 @ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG)))
 369                 LDR             rscratch,[reg_cpu_var,#Flags_ofs]
 370                 LDR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 371                 TST             rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG)
 372                 BNE             5432f
 373                 MOVS            rscratch2,rscratch2
 374                 BNE             5432f
 375 @ CPU.WaitAddress = NULL;
 376                 MOV             rscratch,#0
 377                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 378 @ if (Settings.SA1)
 379 @               S9xSA1ExecuteDuringSleep ();            : TODO
 380
 381 @           CPU.Cycles = CPU.NextEvent;
 382                 LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
 383                 LDRB            r0,[reg_cpu_var,#APUExecuting_ofs]
 384                 MOVS            r0,r0
 385                 BEQ             5431f
 386 @           if (IAPU.APUExecuting)
 387 /*          {
 388                 ICPU.CPUExecuting = FALSE;
 389                 do
 390                 {
 391                     APU_EXECUTE1();
 392                 } while (APU.Cycles < CPU.NextEvent);
 393                 ICPU.CPUExecuting = TRUE;
 394             }
 395         */
 396                 asmAPU_EXECUTE2
 397                 B               5431f
 398 @.pool
 399 5432:
 400 /*      else
 401         if (CPU.WaitCounter >= 2)
 402             CPU.WaitCounter = 1;
 403         else
 404             CPU.WaitCounter--;
 405 */
 406                 CMP             rscratch2,#1
 407                 MOVHI           rscratch2,#1
 408                 @ SUBLS         rscratch2,rscratch2,#1
 409                 MOVLS           rscratch2,#0
 410                 STR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 411 5431:
 412
 413 .endm
 414 .macro          BranchCheck0
 415                 /*in rsctach : OpAddress
 416                 /*destroy rscratch2*/
 417                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 418                 MOVS    rscratch2,rscratch2
 419                 BEQ     1110f
 420                 MOV     rscratch2,#0
 421                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 422                 SUB     rscratch2,rpc,regpcbase
 423                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 424                 CMP     rscratch2,rscratch
 425                 BHI     1111f
 426 1110:
 427 .endm
 428 .macro          BranchCheck1
 429                 /*in rsctach : OpAddress
 430                 /*destroy rscratch2*/
 431                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 432                 MOVS    rscratch2,rscratch2
 433                 BEQ     1110f
 434                 MOV     rscratch2,#0
 435                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 436                 SUB     rscratch2,rpc,regpcbase
 437                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 438                 CMP     rscratch2,rscratch
 439                 BHI     1111f
 440 1110:
 441 .endm
 442 .macro          BranchCheck2
 443                 /*in rsctach : OpAddress
 444                 /*destroy rscratch2*/
 445                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 446                 MOVS    rscratch2,rscratch2
 447                 BEQ     1110f
 448                 MOV     rscratch2,#0
 449                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 450                 SUB     rscratch2,rpc,regpcbase
 451                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 452                 CMP     rscratch2,rscratch
 453                 BHI     1111f
 454 1110:
 455 .endm
 456
 457 .macro          S9xSetPCBase
 458                 @  in  : rscratch (0x00hhmmll)
 459                 PREPARE_C_CALL
 460                 BL      asm_S9xSetPCBase
 461                 RESTORE_C_CALL
 462                 LDR     rpc,[reg_cpu_var,#PC_ofs]
 463                 LDR     regpcbase,[reg_cpu_var,#PCBase_ofs]
 464 .endm
 465
 466 .macro          S9xFixCycles
 467                 TST             rstatus,#MASK_EMUL
 468                 LDRNE           rscratch, = jumptable1     @ Mode 0 : M=1,X=1
 469                 BNE             991111f
 470                 @ EMULATION=0
 471                 TST             rstatus,#MASK_MEM
 472                 BEQ             991112f
 473                 @ MEMORY=1
 474                 TST             rstatus,#MASK_INDEX
 475                 @ INDEX=1  @ Mode 0 : M=1,X=1
 476                 LDRNE           rscratch, = jumptable1
 477                 @ INDEX=0  @ Mode 1 : M=1,X=0
 478                 LDREQ           rscratch, = jumptable2
 479                 B               991111f
 480 991112:         @ MEMORY=0
 481                 TST             rstatus,#MASK_INDEX
 482                 @ INDEX=1   @ Mode 3 : M=0,X=1
 483                 LDRNE           rscratch, = jumptable4
 484                 @ INDEX=0   @ Mode 2 : M=0,X=0
 485                 LDREQ           rscratch, = jumptable3
 486 991111:
 487                 STR             rscratch,[reg_cpu_var,#asm_OPTABLE_ofs]
 488 .endm
 489 /*
 490 .macro          S9xOpcode_NMI
 491                 SAVE_REGS
 492                 PREPARE_C_CALL_LIGHT
 493                 BL      asm_S9xOpcode_NMI
 494                 RESTORE_C_CALL_LIGHT
 495                 LOAD_REGS
 496 .endm
 497 .macro          S9xOpcode_IRQ
 498                 SAVE_REGS
 499                 PREPARE_C_CALL_LIGHT
 500                 BL      asm_S9xOpcode_IRQ
 501                 RESTORE_C_CALL_LIGHT
 502                 LOAD_REGS
 503 .endm
 504 */
 505 .macro          S9xDoHBlankProcessing
 506                 SAVE_REGS
 507                 PREPARE_C_CALL_LIGHT
 508 @               BL      asm_S9xDoHBlankProcessing
 509                 BL      S9xDoHBlankProcessing
 510                 RESTORE_C_CALL_LIGHT
 511                 LOAD_REGS
 512 .endm
 513
 514 /********************************/
 515 .macro          EXEC_OP
 516                 LDR             R1,[reg_cpu_var,#asm_OPTABLE_ofs]
 517                 STR             rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs]
 518                 ADD1MEM
 519                 LDRB            R0, [rpc], #1
 520
 521                 LDR             PC, [R1,R0, LSL #2]
 522 .endm
 523 .macro          NEXTOPCODE
 524                 LDR                     rscratch,[reg_cpu_var,#NextEvent_ofs]
 525                 CMP                     reg_cycles,rscratch
 526                 BLT                     mainLoop
 527                 S9xDoHBlankProcessing
 528                 B                       mainLoop
 529 .endm
 530
 531 .macro          asmAPU_EXECUTE
 532                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 533                 CMP             R0,#1   @ spc700 enabled, hack mode off
 534                 BNE                 43210f
 535                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 536         SUBS        R0,reg_cycles,R0
 537         BMI         43210f
 538 .if ASM_SPC700
 539                 PREPARE_C_CALL_LIGHTR12
 540                 BL              spc700_execute
 541                 RESTORE_C_CALL_LIGHTR12
 542         SUB     R0,reg_cycles,R0 @ sub cycles left
 543                 STR             R0,[reg_cpu_var,#APU_Cycles]
 544 .else
 545         @ SAVE_REGS
 546                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 547                 PREPARE_C_CALL_LIGHTR12
 548                 BL              asm_APU_EXECUTE
 549                 RESTORE_C_CALL_LIGHTR12
 550                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 551 .endif
 552         @ LOAD_REGS
 553                 @ S9xFixCycles
 554 43210:
 555 .endm
 556
 557 .macro          asmAPU_EXECUTE2
 558 .if ASM_SPC700
 559                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 560                 CMP             R0,#1   @ spc700 enabled, hack mode off
 561                 BNE                 43211f
 562                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 563         SUBS        R0,reg_cycles,R0 @ reg_cycles == NextEvent
 564         BLE         43211f
 565                 PREPARE_C_CALL_LIGHTR12
 566                 BL              spc700_execute
 567                 RESTORE_C_CALL_LIGHTR12
 568         SUB     R0,reg_cycles,R0 @ sub cycles left
 569                 STR             R0,[reg_cpu_var,#APU_Cycles]
 570 43211:
 571 .else
 572                 @ SAVE_REGS
 573                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 574                 PREPARE_C_CALL_LIGHTR12
 575                 BL              asm_APU_EXECUTE2
 576                 RESTORE_C_CALL_LIGHTR12
 577                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 578                 @ LOAD_REGS
 579 .endif
 580 .endm
 581
 582 .macro          S9xGetWord
 583                 @  in  : rscratch (0x00hhmmll)
 584                 @  out : rscratch (0xhhll0000)
 585                 STMFD   R13!,{PC} @ Push return address
 586                 B       asmS9xGetWord
 587                 MOV     R0,R0
 588                 MOV     R0, R0, LSL #16
 589 .endm
 590 .macro          S9xGetWordLow
 591                 @  in  : rscratch (0x00hhmmll)
 592                 @  out : rscratch (0x0000hhll)
 593                 STMFD   R13!,{PC} @ Push return address
 594                 B       asmS9xGetWord
 595                 MOV     R0,R0
 596 .endm
 597 .macro          S9xGetWordRegStatus     reg
 598                 @  in  : rscratch (0x00hhmmll)
 599                 @  out : reg      (0xhhll0000)
 600                 @  flags have to be updated with read value
 601                 STMFD   R13!,{PC} @ Push return address
 602                 B       asmS9xGetWord
 603                 MOV     R0,R0
 604                 MOVS    \reg, R0, LSL #16
 605 .endm
 606 .macro          S9xGetWordRegNS reg
 607                 @  in  : rscratch (0x00hhmmll)
 608                 @  out : reg (0xhhll0000)
 609                 @  DOES NOT DESTROY rscratch (R0)
 610                 STMFD   R13!,{R0}
 611                 STMFD   R13!,{PC} @ Push return address
 612                 B       asmS9xGetWord
 613                 MOV     R0,R0
 614                 MOV     \reg, R0, LSL #16
 615                 LDMFD   R13!,{R0}
 616 .endm
 617 .macro          S9xGetWordLowRegNS      reg
 618                 @  in  : rscratch (0x00hhmmll)
 619                 @  out : reg (0xhhll0000)
 620                 @  DOES NOT DESTROY rscratch (R0)
 621                 STMFD   R13!,{R0}
 622                 STMFD   R13!,{PC} @ Push return address
 623                 B       asmS9xGetWord
 624                 MOV     R0,R0
 625                 MOV     \reg, R0
 626                 LDMFD   R13!,{R0}
 627 .endm
 628
 629 .macro          S9xGetByte
 630                 @  in  : rscratch (0x00hhmmll)
 631                 @  out : rscratch (0xll000000)
 632                 STMFD   R13!,{PC} @ Push return address
 633                 B       asmS9xGetByte
 634                 MOV     R0,R0
 635                 MOV     R0, R0, LSL #24
 636 .endm
 637 .macro          S9xGetByteLow
 638                 @  in  : rscratch (0x00hhmmll)
 639                 @  out : rscratch (0x000000ll)
 640                 STMFD   R13!,{PC}
 641                 B       asmS9xGetByte
 642                 MOV     R0,R0
 643 .endm
 644 .macro          S9xGetByteRegStatus     reg
 645                 @  in  : rscratch (0x00hhmmll)
 646                 @  out : reg      (0xll000000)
 647                 @  flags have to be updated with read value
 648                 STMFD   R13!,{PC} @ Push return address
 649                 B       asmS9xGetByte
 650                 MOV     R0,R0
 651                 MOVS    \reg, R0, LSL #24
 652 .endm
 653 .macro          S9xGetByteRegNS reg
 654                 @  in  : rscratch (0x00hhmmll)
 655                 @  out : reg      (0xll000000)
 656                 @  DOES NOT DESTROY rscratch (R0)
 657                 STMFD   R13!,{R0}
 658                 STMFD   R13!,{PC} @ Push return address
 659                 B       asmS9xGetByte
 660                 MOV     R0,R0
 661                 MOVS    \reg, R0, LSL #24
 662                 LDMFD   R13!,{R0}
 663 .endm
 664 .macro          S9xGetByteLowRegNS      reg
 665                 @  in  : rscratch (0x00hhmmll)
 666                 @  out : reg      (0x000000ll)
 667                 @  DOES NOT DESTROY rscratch (R0)
 668                 STMFD   R13!,{R0}
 669                 STMFD   R13!,{PC} @ Push return address
 670                 B       asmS9xGetByte
 671                 MOV     R0,R0
 672                 MOVS    \reg, R0
 673                 LDMFD   R13!,{R0}
 674 .endm
 675
 676 .macro          S9xSetWord      regValue
 677                 @  in  : regValue  (0xhhll0000)
 678                 @  in  : rscratch=address   (0x00hhmmll)
 679                 MOV     R1,\regValue, LSR #16
 680                 STMFD   R13!,{PC} @ Push return address
 681                 B       asmS9xSetWord
 682                 MOV     R0,R0
 683 .endm
 684 .macro          S9xSetWordZero
 685                 @  in  : rscratch=address   (0x00hhmmll)
 686                 MOV     R1,#0
 687                 STMFD   R13!,{PC} @ Push return address
 688                 B       asmS9xSetWord
 689                 MOV     R0,R0
 690 .endm
 691 .macro          S9xSetWordLow   regValue
 692                 @  in  : regValue  (0x0000hhll)
 693                 @  in  : rscratch=address   (0x00hhmmll)
 694                 MOV     R1,\regValue
 695                 STMFD   R13!,{PC} @ Push return address
 696                 B       asmS9xSetWord
 697                 MOV     R0,R0
 698 .endm
 699 .macro          S9xSetByte      regValue
 700                 @  in  : regValue  (0xll000000)
 701                 @  in  : rscratch=address   (0x00hhmmll)
 702                 MOV     R1,\regValue, LSR #24
 703                 STMFD   R13!,{PC} @ Push return address
 704                 B       asmS9xSetByte
 705                 MOV     R0,R0
 706 .endm
 707 .macro          S9xSetByteZero
 708                 @  in  : rscratch=address   (0x00hhmmll)
 709                 MOV     R1,#0
 710                 STMFD   R13!,{PC} @ Push return address
 711                 B       asmS9xSetByte
 712                 MOV     R0,R0
 713 .endm
 714 .macro          S9xSetByteLow   regValue
 715                 @  in  : regValue  (0x000000ll)
 716                 @  in  : rscratch=address   (0x00hhmmll)
 717                 MOV     R1,\regValue
 718                 STMFD   R13!,{PC} @ Push return address
 719                 B       asmS9xSetByte
 720                 MOV     R0,R0
 721 .endm
 722
 723
 724 @  ===========================================
 725 @  ===========================================
 726 @  Adressing mode
 727 @  ===========================================
 728 @  ===========================================
 729
 730
 731 .macro          Absolute
 732                 ADD2MEM
 733                 LDRB    rscratch2    , [rpc, #1]
 734                 LDRB    rscratch   , [rpc],#2
 735                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 736                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 737 .endm
 738 .macro          AbsoluteIndexedIndirectX0
 739                 ADD2MEM
 740                 LDRB    rscratch2    , [rpc, #1]
 741                 LDRB    rscratch   , [rpc], #2
 742                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 743                 ADD     rscratch    , reg_x, rscratch, LSL #16
 744                 MOV     rscratch , rscratch, LSR #16
 745                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 746                 S9xGetWordLow
 747
 748 .endm
 749 .macro          AbsoluteIndexedIndirectX1
 750                 ADD2MEM
 751                 LDRB    rscratch2    , [rpc, #1]
 752                 LDRB    rscratch   , [rpc], #2
 753                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 754                 ADD     rscratch    , rscratch, reg_x, LSR #24
 755                 BIC     rscratch , rscratch, #0x00FF0000
 756                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 757                 S9xGetWordLow
 758
 759 .endm
 760 .macro          AbsoluteIndirectLong
 761                 ADD2MEM
 762                 LDRB                    rscratch2    , [rpc, #1]
 763                 LDRB                    rscratch   , [rpc], #2
 764                 ORR                     rscratch    , rscratch, rscratch2, LSL #8
 765                 S9xGetWordLowRegNS      rscratch2
 766                 ADD                     rscratch   , rscratch,  #2
 767                 STMFD                   r13!,{rscratch2}
 768                 S9xGetByteLow
 769                 LDMFD                   r13!,{rscratch2}
 770                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 771 .endm
 772 .macro          AbsoluteIndirect
 773                 ADD2MEM
 774                 LDRB    rscratch2    , [rpc,#1]
 775                 LDRB    rscratch   , [rpc], #2
 776                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 777                 S9xGetWordLow
 778                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 779 .endm
 780 .macro          AbsoluteIndexedX0
 781                 ADD2MEM
 782                 LDRB    rscratch2    , [rpc, #1]
 783                 LDRB    rscratch   , [rpc], #2
 784                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 785                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 786                 ADD     rscratch    , rscratch, reg_x, LSR #16
 787 .endm
 788 .macro          AbsoluteIndexedX1
 789                 ADD2MEM
 790                 LDRB    rscratch2    , [rpc, #1]
 791                 LDRB    rscratch   , [rpc], #2
 792                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 793                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 794                 ADD     rscratch    , rscratch, reg_x, LSR #24
 795 .endm
 796
 797
 798 .macro          AbsoluteIndexedY0
 799                 ADD2MEM
 800                 LDRB    rscratch2    , [rpc, #1]
 801                 LDRB    rscratch   , [rpc], #2
 802                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 803                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 804                 ADD     rscratch    , rscratch, reg_y, LSR #16
 805 .endm
 806 .macro          AbsoluteIndexedY1
 807                 ADD2MEM
 808                 LDRB    rscratch2    , [rpc, #1]
 809                 LDRB    rscratch   , [rpc], #2
 810                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 811                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 812                 ADD     rscratch    , rscratch, reg_y, LSR #24
 813 .endm
 814 .macro          AbsoluteLong
 815                 ADD3MEM
 816                 LDRB    rscratch2    , [rpc, #1]
 817                 LDRB    rscratch   , [rpc], #2
 818                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 819                 LDRB    rscratch2   , [rpc], #1
 820                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 821 .endm
 822
 823
 824 .macro          AbsoluteLongIndexedX0
 825                 ADD3MEM
 826                 LDRB    rscratch2    , [rpc, #1]
 827                 LDRB    rscratch   , [rpc], #2
 828                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 829                 LDRB    rscratch2   , [rpc], #1
 830                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 831                 ADD     rscratch    , rscratch, reg_x, LSR #16
 832                 BIC     rscratch, rscratch, #0xFF000000
 833 .endm
 834 .macro          AbsoluteLongIndexedX1
 835                 ADD3MEM
 836                 LDRB    rscratch2    , [rpc, #1]
 837                 LDRB    rscratch   , [rpc], #2
 838                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 839                 LDRB    rscratch2   , [rpc], #1
 840                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 841                 ADD     rscratch    , rscratch, reg_x, LSR #24
 842                 BIC     rscratch, rscratch, #0xFF000000
 843 .endm
 844 .macro          Direct
 845                 ADD1MEM
 846                 LDRB    rscratch    , [rpc], #1
 847                 ADD     rscratch    , reg_d, rscratch, LSL #16
 848                 MOV     rscratch, rscratch, LSR #16
 849 .endm
 850 .macro          DirectIndirect
 851                 ADD1MEM
 852                 LDRB    rscratch    , [rpc], #1
 853                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 854                 MOV     rscratch, rscratch, LSR #16
 855                 S9xGetWordLow
 856                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 857 .endm
 858 .macro          DirectIndirectLong
 859                 ADD1MEM
 860                 LDRB                    rscratch    , [rpc], #1
 861                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 862                 MOV                     rscratch, rscratch, LSR #16
 863                 S9xGetWordLowRegNS      rscratch2
 864                 ADD                     rscratch    , rscratch,#2
 865                 STMFD                   r13!,{rscratch2}
 866                 S9xGetByteLow
 867                 LDMFD                   r13!,{rscratch2}
 868                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 869 .endm
 870 .macro          DirectIndirectIndexed0
 871                 ADD1MEM
 872                 LDRB    rscratch    , [rpc], #1
 873                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 874                 MOV     rscratch, rscratch, LSR #16
 875                 S9xGetWordLow
 876                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 877                 ADD     rscratch, rscratch,reg_y, LSR #16
 878 .endm
 879 .macro          DirectIndirectIndexed1
 880                 ADD1MEM
 881                 LDRB    rscratch    , [rpc], #1
 882                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 883                 MOV     rscratch, rscratch, LSR #16
 884                 S9xGetWordLow
 885                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 886                 ADD     rscratch, rscratch,reg_y, LSR #24
 887 .endm
 888 .macro          DirectIndirectIndexedLong0
 889                 ADD1MEM
 890                 LDRB                    rscratch    , [rpc], #1
 891                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 892                 MOV                     rscratch, rscratch, LSR #16
 893                 S9xGetWordLowRegNS      rscratch2
 894                 ADD                     rscratch    , rscratch,#2
 895                 STMFD                   r13!,{rscratch2}
 896                 S9xGetByteLow
 897                 LDMFD                   r13!,{rscratch2}
 898                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 899                 ADD                     rscratch, rscratch,reg_y, LSR #16
 900 .endm
 901 .macro          DirectIndirectIndexedLong1
 902                 ADD1MEM
 903                 LDRB                    rscratch    , [rpc], #1
 904                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 905                 MOV                     rscratch, rscratch, LSR #16
 906                 S9xGetWordLowRegNS      rscratch2
 907                 ADD                     rscratch    , rscratch,#2
 908                 STMFD                   r13!,{rscratch2}
 909                 S9xGetByteLow
 910                 LDMFD                   r13!,{rscratch2}
 911                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 912                 ADD                     rscratch, rscratch,reg_y, LSR #24
 913 .endm
 914 .macro          DirectIndexedIndirect0
 915                 ADD1CYCLE1MEM
 916                 LDRB    rscratch    , [rpc], #1
 917                 ADD     rscratch2   , reg_d , reg_x
 918                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 919                 MOV     rscratch, rscratch, LSR #16
 920                 S9xGetWordLow
 921                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 922 .endm
 923 .macro          DirectIndexedIndirect1
 924                 ADD1CYCLE1MEM
 925                 LDRB    rscratch    , [rpc], #1
 926                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 927                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 928                 MOV     rscratch, rscratch, LSR #16
 929                 S9xGetWordLow
 930                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 931 .endm
 932 .macro          DirectIndexedX0
 933                 ADD1CYCLE1MEM
 934                 LDRB    rscratch    , [rpc], #1
 935                 ADD     rscratch2   , reg_d , reg_x
 936                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 937                 MOV     rscratch, rscratch, LSR #16
 938 .endm
 939 .macro          DirectIndexedX1
 940                 ADD1CYCLE1MEM
 941                 LDRB    rscratch    , [rpc], #1
 942                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 943                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 944                 MOV     rscratch, rscratch, LSR #16
 945 .endm
 946 .macro          DirectIndexedY0
 947                 ADD1CYCLE1MEM
 948                 LDRB    rscratch    , [rpc], #1
 949                 ADD     rscratch2   , reg_d , reg_y
 950                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 951                 MOV     rscratch, rscratch, LSR #16
 952 .endm
 953 .macro          DirectIndexedY1
 954                 ADD1CYCLE1MEM
 955                 LDRB    rscratch    , [rpc], #1
 956                 ADD     rscratch2   , reg_d , reg_y, LSR #8
 957                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 958                 MOV     rscratch, rscratch, LSR #16
 959 .endm
 960 .macro          Immediate8
 961                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 962                 SUB     rscratch, rscratch, regpcbase
 963                 ADD     rpc, rpc, #1
 964 .endm
 965 .macro          Immediate16
 966                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 967                 SUB     rscratch, rscratch, regpcbase
 968                 ADD     rpc, rpc, #2
 969 .endm
 970 .macro          asmRelative
 971                 ADD1MEM
 972                 LDRSB   rscratch    , [rpc],#1
 973                 ADD     rscratch , rscratch , rpc
 974                 SUB     rscratch , rscratch, regpcbase
 975                 UXTH rscratch,rscratch
 976 .endm
 977 .macro          asmRelativeLong
 978                 ADD1CYCLE2MEM
 979                 LDRB    rscratch2    , [rpc, #1]
 980                 LDRB    rscratch   , [rpc], #2
 981                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 982                 SUB     rscratch2    , rpc, regpcbase
 983                 ADD     rscratch    , rscratch2, rscratch
 984                 BIC     rscratch,rscratch,#0x00FF0000
 985 .endm
 986
 987
 988 .macro          StackasmRelative
 989                 ADD1CYCLE1MEM
 990                 LDRB    rscratch    , [rpc], #1
 991                 ADD     rscratch    , rscratch, reg_s
 992                 BIC     rscratch,rscratch,#0x00FF0000
 993 .endm
 994 .macro          StackasmRelativeIndirectIndexed0
 995                 ADD2CYCLE1MEM
 996                 LDRB    rscratch    , [rpc], #1
 997                 ADD     rscratch    , rscratch, reg_s
 998                 BIC     rscratch,rscratch,#0x00FF0000
 999                 S9xGetWordLow
1000                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1001                 ADD     rscratch    , rscratch, reg_y, LSR #16
1002                 BIC     rscratch, rscratch, #0xFF000000
1003 .endm
1004 .macro          StackasmRelativeIndirectIndexed1
1005                 ADD2CYCLE1MEM
1006                 LDRB    rscratch    , [rpc], #1
1007                 ADD     rscratch    , rscratch, reg_s
1008                 BIC     rscratch,rscratch,#0x00FF0000
1009                 S9xGetWordLow
1010                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1011                 ADD     rscratch    , rscratch, reg_y, LSR #24
1012                 BIC     rscratch, rscratch, #0xFF000000
1013 .endm
1014
1015
1016 /****************************************/
1017 .macro          PushB           reg
1018                 MOV             rscratch,reg_s
1019                 S9xSetByte      \reg
1020                 SUB             reg_s,reg_s,#1
1021 .endm
1022 .macro          PushBLow        reg
1023                 MOV             rscratch,reg_s
1024                 S9xSetByteLow   \reg
1025                 SUB             reg_s,reg_s,#1
1026 .endm
1027 .macro          PushWLow        reg
1028                 SUB             rscratch,reg_s,#1
1029                 S9xSetWordLow   \reg
1030                 SUB             reg_s,reg_s,#2
1031 .endm
1032 .macro          PushWrLow
1033                 MOV             rscratch2,rscratch
1034                 SUB             rscratch,reg_s,#1
1035                 S9xSetWordLow   rscratch2
1036                 SUB             reg_s,reg_s,#2
1037 .endm
1038 .macro          PushW           reg
1039                 SUB             rscratch,reg_s,#1
1040                 S9xSetWord      \reg
1041                 SUB             reg_s,reg_s,#2
1042 .endm
1043
1044 /********/
1045
1046 .macro          PullB           reg
1047                 ADD             rscratch,reg_s,#1
1048                 S9xGetByteLow
1049                 ADD             reg_s,reg_s,#1
1050                 MOV             \reg,rscratch,LSL #24
1051 .endm
1052 .macro          PullBr
1053                 ADD             rscratch,reg_s,#1
1054                 S9xGetByte
1055                 ADD             reg_s,reg_s,#1
1056 .endm
1057 .macro          PullBLow        reg
1058                 ADD             rscratch,reg_s,#1
1059                 S9xGetByteLow
1060                 ADD             reg_s,reg_s,#1
1061                 MOV             \reg,rscratch
1062 .endm
1063 .macro          PullBrLow
1064                 ADD             rscratch,reg_s,#1
1065                 S9xGetByteLow
1066                 ADD             reg_s,reg_s,#1
1067 .endm
1068 .macro          PullW           reg
1069                 ADD             rscratch,reg_s,#1
1070                 S9xGetWordLow
1071                 ADD             reg_s,reg_s,#2
1072                 MOV             \reg,rscratch,LSL #16
1073 .endm
1074
1075 .macro          PullWLow        reg
1076                 ADD             rscratch,reg_s,#1
1077                 S9xGetWordLow
1078                 ADD             reg_s,reg_s,#2
1079                 MOV             \reg,rscratch
1080 .endm
1081
1082
1083 /*****************/
1084 .macro          PullBS          reg
1085                 ADD             rscratch,reg_s,#1
1086                 S9xGetByteLow
1087                 ADD             reg_s,reg_s,#1
1088                 MOVS            \reg,rscratch,LSL #24
1089 .endm
1090 .macro          PullBrS
1091                 ADD             rscratch,reg_s,#1
1092                 S9xGetByteLow
1093                 ADD             reg_s,reg_s,#1
1094                 MOVS            rscratch,rscratch,LSL #24
1095 .endm
1096 .macro          PullBLowS       reg
1097                 ADD             rscratch,reg_s,#1
1098                 S9xGetByteLow
1099                 ADD             reg_s,reg_s,#1
1100                 MOVS            \reg,rscratch
1101 .endm
1102 .macro          PullBrLowS
1103                 ADD             rscratch,reg_s,#1
1104                 S9xGetByteLow
1105                 ADD             reg_s,reg_s,#1
1106                 MOVS            rscratch,rscratch
1107 .endm
1108 .macro          PullWS          reg
1109                 ADD             rscratch,reg_s,#1
1110                 S9xGetWordLow
1111                 ADD             reg_s,reg_s,#2
1112                 MOVS            \reg,rscratch, LSL #16
1113 .endm
1114 .macro          PullWrS
1115                 ADD             rscratch,reg_s,#1
1116                 S9xGetWordLow
1117                 ADD             reg_s,reg_s,#2
1118                 MOVS            rscratch,rscratch, LSL #16
1119 .endm
1120 .macro          PullWLowS       reg
1121                 ADD             rscratch,reg_s,#1
1122                 S9xGetWordLow
1123                 ADD             reg_s,reg_s,#2
1124                 MOVS            \reg,rscratch
1125 .endm
1126 .macro          PullWrLowS
1127                 ADD             rscratch,reg_s,#1
1128                 S9xGetWordLow
1129                 ADD             reg_s,reg_s,#2
1130                 MOVS            rscratch,rscratch
1131 .endm
1132
1133 @ START OF PROGRAM CODE
1134
1135 .text
1136
1137 .align 4
1138
1139 .globl asmS9xGetByte
1140 .globl asmS9xGetWord
1141 .globl asmS9xSetByte
1142 .globl asmS9xSetWord
1143
1144 @ uint8 aaS9xGetByte(uint32 address);
1145 asmS9xGetByte:
1146         @  in : R0  = 0x00hhmmll
1147         @  out : R0 = 0x000000ll
1148         @  DESTROYED : R1,R2,R3
1149         @  UPDATE : reg_cycles
1150         @ R1 <= block
1151         MOV             R1,R0,LSR #MEMMAP_SHIFT
1152         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1153         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1154         @ so AND MEMMAP_MASK is BIC 0xFF000
1155         BIC             R1,R1,#0xFF000
1156         @ R2 <= Map[block] (GetAddress)
1157         LDR             R2,[reg_cpu_var,#Map_ofs]
1158         LDR             R2,[R2,R1,LSL #2]
1159         CMP             R2,#MAP_LAST
1160         BLO             GBSpecial  @ special
1161         @  Direct ROM/RAM acess
1162         @ R2 <= GetAddress + Address & 0xFFFF
1163         @ R3 <= MemorySpeed[block]
1164         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1165         MOV             R0,R0,LSL #16
1166         LDRB            R3,[R3,R1]
1167         ADD             R2,R2,R0,LSR #16
1168         @ Update CPU.Cycles
1169         ADD             reg_cycles,reg_cycles,R3
1170         @ R3 = BlockIsRAM[block]
1171         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1172         @ Get value to return
1173         LDRB            R0,[R2]
1174         LDRB            R3,[R3,R1]
1175         MOVS            R3,R3
1176         @  if BlockIsRAM => update for CPUShutdown
1177         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1178         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1179
1180         LDMFD           R13!,{PC} @ Return
1181 GBSpecial:
1182
1183         LDR             PC,[PC,R2,LSL #2]
1184         MOV             R0,R0           @ nop, for align
1185         .long GBPPU
1186         .long GBCPU
1187         .long GBDSP
1188         .long GBLSRAM
1189         .long GBHSRAM
1190         .long GBNONE
1191         .long GBDEBUG
1192         .long GBC4
1193         .long GBBWRAM
1194         .long GBNONE
1195         .long GBNONE
1196         .long GBNONE
1197         /*.long GB7ROM
1198         .long GB7RAM
1199         .long GB7SRM*/
1200 GBPPU:
1201         @ InDMA ?
1202         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1203         MOVS            R1,R1
1204         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1205         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1206         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1207         MOV             R0,R0,LSR #16
1208                 PREPARE_C_CALL
1209         BL              S9xGetPPU
1210                 RESTORE_C_CALL
1211         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1212         LDMFD           R13!,{PC} @ Return
1213 GBCPU:
1214         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1215         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1216         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1217         MOV             R0,R0,LSR #16
1218                 PREPARE_C_CALL
1219         BL              S9xGetCPU
1220                 RESTORE_C_CALL
1221         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1222         LDMFD           R13!,{PC} @ Return
1223 GBDSP:
1224         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1225         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1226         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1227         MOV             R0,R0,LSR #16
1228                 PREPARE_C_CALL
1229         BL              S9xGetDSP
1230                 RESTORE_C_CALL
1231         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1232         LDMFD           R13!,{PC} @ Return
1233 GBLSRAM:
1234         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1235         LDRH            R2,[reg_cpu_var,#SRAMMask]
1236         LDR             R1,[reg_cpu_var,#SRAM]
1237         AND             R0,R2,R0                @ Address&SRAMMask
1238         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1239         LDMFD           R13!,{PC}
1240 GB7SRM:
1241 GBHSRAM:
1242         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1243
1244         MOV             R1,R0,LSL #17
1245         AND             R2,R0,#0xF0000
1246         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1247         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1248         ADD             R0,R2,R1
1249         LDRH            R2,[reg_cpu_var,#SRAMMask]
1250         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1251         LDR             R1,[reg_cpu_var,#SRAM]
1252         AND             R0,R2,R0                @ Address&SRAMMask
1253         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1254         LDMFD           R13!,{PC}               @ return
1255 GB7ROM:
1256 GB7RAM:
1257 GBNONE:
1258         MOV             R0,R0,LSR #8
1259         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1260         AND             R0,R0,#0xFF
1261         LDMFD           R13!,{PC}
1262 @ GBDEBUG:
1263         /*ADD           reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1264         MOV             R0,#0
1265         LDMFD           R13!,{PC}*/
1266 GBC4:
1267         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1268         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1269         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1270         MOV             R0,R0,LSR #16
1271                 PREPARE_C_CALL
1272         BL              S9xGetC4
1273                 RESTORE_C_CALL
1274         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1275         LDMFD           R13!,{PC} @ Return
1276 GBDEBUG:
1277 GBBWRAM:
1278         MOV             R0,R0,LSL #17
1279         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1280         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1281         LDR             R1,[reg_cpu_var,#BWRAM]
1282         SUB             R0,R0,#0x6000   @ ((Address & 0x7fff) - 0x6000)
1283         LDRB            R0,[R0,R1]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1284         LDMFD           R13!,{PC}
1285
1286
1287 @ uint16 aaS9xGetWord(uint32 address);
1288 asmS9xGetWord:
1289         @  in : R0  = 0x00hhmmll
1290         @  out : R0 = 0x000000ll
1291         @  DESTROYED : R1,R2,R3
1292         @  UPDATE : reg_cycles
1293
1294
1295         MOV             R1,R0,LSL #19
1296         ADDS            R1,R1,#0x80000
1297         @ if = 0x1FFF => 0
1298         BNE             GW_NotBoundary
1299
1300         STMFD           R13!,{R0}
1301                 STMFD           R13!,{PC}
1302         B               asmS9xGetByte
1303                 MOV             R0,R0
1304         LDMFD           R13!,{R1}
1305         STMFD           R13!,{R0}
1306         ADD             R0,R1,#1
1307                 STMFD           R13!,{PC}
1308         B               asmS9xGetByte
1309                 MOV             R0,R0
1310         LDMFD           R13!,{R1}
1311         ORR             R0,R1,R0,LSL #8
1312         LDMFD           R13!,{PC}
1313
1314 GW_NotBoundary:
1315
1316         @ R1 <= block
1317         MOV             R1,R0,LSR #MEMMAP_SHIFT
1318         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1319         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1320         @ so AND MEMMAP_MASK is BIC 0xFF000
1321         BIC             R1,R1,#0xFF000
1322         @ R2 <= Map[block] (GetAddress)
1323         LDR             R2,[reg_cpu_var,#Map_ofs]
1324         LDR             R2,[R2,R1,LSL #2]
1325         CMP             R2,#MAP_LAST
1326         BLO             GWSpecial  @ special
1327         @  Direct ROM/RAM acess
1328
1329         TST             R0,#1
1330         BNE             GW_Not_Aligned1
1331         @ R2 <= GetAddress + Address & 0xFFFF
1332         @ R3 <= MemorySpeed[block]
1333         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1334         MOV             R0,R0,LSL #16
1335         LDRB            R3,[R3,R1]
1336         MOV             R0,R0,LSR #16
1337         @ Update CPU.Cycles
1338         ADD             reg_cycles,reg_cycles,R3, LSL #1
1339         @ R3 = BlockIsRAM[block]
1340         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1341         @ Get value to return
1342         LDRH            R0,[R2,R0]
1343         LDRB            R3,[R3,R1]
1344         MOVS            R3,R3
1345         @  if BlockIsRAM => update for CPUShutdown
1346         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1347         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1348
1349         LDMFD           R13!,{PC} @ Return
1350 GW_Not_Aligned1:
1351
1352         MOV             R0,R0,LSL #16
1353         ADD             R3,R0,#0x10000
1354         LDRB            R3,[R2,R3,LSR #16]      @ GetAddress+ (Address+1)&0xFFFF
1355         LDRB            R0,[R2,R0,LSR #16]      @ GetAddress+ Address&0xFFFF
1356         ORR             R0,R0,R3,LSL #8
1357
1358         @  if BlockIsRAM => update for CPUShutdown
1359         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1360         LDR             R2,[reg_cpu_var,#MemorySpeed_ofs]
1361         LDRB            R3,[R3,R1]   @ R3 = BlockIsRAM[block]
1362         LDRB            R2,[R2,R1]   @ R2 <= MemorySpeed[block]
1363         MOVS            R3,R3       @ IsRAM ? CPUShutdown stuff
1364         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1365         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1366         ADD             reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles
1367         LDMFD           R13!,{PC}  @ Return
1368 GWSpecial:
1369         LDR             PC,[PC,R2,LSL #2]
1370         MOV             R0,R0           @ nop, for align
1371         .long GWPPU
1372         .long GWCPU
1373         .long GWDSP
1374         .long GWLSRAM
1375         .long GWHSRAM
1376         .long GWNONE
1377         .long GWDEBUG
1378         .long GWC4
1379         .long GWBWRAM
1380         .long GWNONE
1381         .long GWNONE
1382         .long GWNONE
1383         /*.long GW7ROM
1384         .long GW7RAM
1385         .long GW7SRM*/
1386 /*      MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
1387         MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
1388         MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
1389
1390 GWPPU:
1391         @ InDMA ?
1392         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1393         MOVS            R1,R1
1394         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1395         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1396         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1397         MOV             R0,R0,LSR #16
1398                 PREPARE_C_CALL_R0
1399         BL              S9xGetPPU
1400         LDMFD           R13!,{R1}
1401         STMFD           R13!,{R0}
1402         ADD             R0,R1,#1
1403         @ BIC           R0,R0,#0x10000
1404         BL              S9xGetPPU
1405                 RESTORE_C_CALL_R1
1406         ORR             R0,R1,R0,LSL #8
1407         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1408         LDMFD           R13!,{PC} @ Return
1409 GWCPU:
1410         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1411         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1412         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1413         MOV             R0,R0,LSR #16
1414                 PREPARE_C_CALL_R0
1415         BL              S9xGetCPU
1416         LDMFD           R13!,{R1}
1417         STMFD           R13!,{R0}
1418         ADD             R0,R1,#1
1419         @ BIC           R0,R0,#0x10000
1420         BL              S9xGetCPU
1421                 RESTORE_C_CALL_R1
1422         ORR             R0,R1,R0,LSL #8
1423         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1424         LDMFD           R13!,{PC} @ Return
1425 GWDSP:
1426         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1427         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1428         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1429         MOV             R0,R0,LSR #16
1430                 PREPARE_C_CALL_R0
1431         BL              S9xGetDSP
1432         LDMFD           R13!,{R1}
1433         STMFD           R13!,{R0}
1434         ADD             R0,R1,#1
1435         @ BIC           R0,R0,#0x10000
1436         BL              S9xGetDSP
1437                 RESTORE_C_CALL_R1
1438         ORR             R0,R1,R0,LSL #8
1439         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1440         LDMFD           R13!,{PC} @ Return
1441 GWLSRAM:
1442         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1443
1444         TST             R0,#1
1445         BNE             GW_Not_Aligned2
1446         LDRH            R2,[reg_cpu_var,#SRAMMask]
1447         LDR             R1,[reg_cpu_var,#SRAM]
1448         AND             R3,R2,R0                @ Address&SRAMMask
1449         LDRH            R0,[R3,R1]              @ *Memory.SRAM + Address&SRAMMask
1450         LDMFD           R13!,{PC}       @ return
1451 GW_Not_Aligned2:
1452         LDRH            R2,[reg_cpu_var,#SRAMMask]
1453         LDR             R1,[reg_cpu_var,#SRAM]
1454         AND             R3,R2,R0                @ Address&SRAMMask
1455         ADD             R0,R0,#1
1456         AND             R2,R0,R2                @ Address&SRAMMask
1457         LDRB            R3,[R1,R3]              @ *Memory.SRAM + Address&SRAMMask
1458         LDRB            R2,[R1,R2]              @ *Memory.SRAM + Address&SRAMMask
1459         ORR             R0,R3,R2,LSL #8
1460         LDMFD           R13!,{PC}       @ return
1461 GW7SRM:
1462 GWHSRAM:
1463         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1464
1465         TST             R0,#1
1466         BNE             GW_Not_Aligned3
1467
1468         MOV             R1,R0,LSL #17
1469         AND             R2,R0,#0xF0000
1470         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1471         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1472         ADD             R0,R2,R1
1473         LDRH            R2,[reg_cpu_var,#SRAMMask]
1474         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1475         LDR             R1,[reg_cpu_var,#SRAM]
1476         AND             R0,R2,R0                @ Address&SRAMMask
1477         LDRH            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1478         LDMFD           R13!,{PC}               @ return
1479
1480 GW_Not_Aligned3:
1481         MOV             R3,R0,LSL #17
1482         AND             R2,R0,#0xF0000
1483         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1484         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1485         ADD             R2,R2,R3
1486         ADD             R0,R0,#1
1487         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1488         MOV             R3,R0,LSL #17
1489         AND             R0,R0,#0xF0000
1490         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1491         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1492         ADD             R0,R0,R3
1493         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1494         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1495         AND             R2,R3,R2                @ Address...&SRAMMask
1496         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1497
1498         LDR             R3,[reg_cpu_var,#SRAM]
1499         LDRB            R0,[R0,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1500         LDRB            R2,[R2,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1501         ORR             R0,R2,R0,LSL #8
1502
1503         LDMFD           R13!,{PC}               @ return
1504 GW7ROM:
1505 GW7RAM:
1506 GWNONE:
1507         MOV             R0,R0,LSL #16
1508         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1509         MOV             R0,R0,LSR #24
1510         ORR             R0,R0,R0,LSL #8
1511         LDMFD           R13!,{PC}
1512 GWDEBUG:
1513         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1514         MOV             R0,#0
1515         LDMFD           R13!,{PC}
1516 GWC4:
1517         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1518         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1519         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1520         MOV             R0,R0,LSR #16
1521                 PREPARE_C_CALL_R0
1522         BL              S9xGetC4
1523         LDMFD           R13!,{R1}
1524         STMFD           R13!,{R0}
1525         ADD             R0,R1,#1
1526         @ BIC           R0,R0,#0x10000
1527         BL              S9xGetC4
1528                 RESTORE_C_CALL_R1
1529         ORR             R0,R1,R0,LSL #8
1530         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1531         LDMFD           R13!,{PC} @ Return
1532 GWBWRAM:
1533         TST             R0,#1
1534         BNE             GW_Not_Aligned4
1535         MOV             R0,R0,LSL #17
1536         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1537         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1538         LDR             R1,[reg_cpu_var,#BWRAM]
1539         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1540         LDRH            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1541         LDMFD           R13!,{PC}               @ return
1542 GW_Not_Aligned4:
1543         MOV             R0,R0,LSL #17
1544         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1545         ADD             R3,R0,#0x20000
1546         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1547         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1548         LDR             R1,[reg_cpu_var,#BWRAM]
1549         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1550         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
1551         LDRB            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1552         LDRB            R3,[R1,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1553         ORR             R0,R0,R3,LSL #8
1554         LDMFD           R13!,{PC}               @ return
1555
1556
1557
1558
1559 @ void aaS9xSetByte(uint32 address,uint8 val);
1560 asmS9xSetByte:
1561         @  in : R0=0x00hhmmll  R1=0x000000ll
1562         @  DESTROYED : R0,R1,R2,R3
1563         @  UPDATE : reg_cycles
1564         @ cpu shutdown
1565         MOV             R2,#0
1566         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1567         @
1568
1569         @ R3 <= block
1570         MOV             R3,R0,LSR #MEMMAP_SHIFT
1571         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1572         @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1573         @ so AND MEMMAP_MASK is BIC 0xFF000
1574         BIC             R3,R3,#0xFF000
1575         @ R2 <= Map[block] (SetAddress)
1576         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1577         LDR             R2,[R2,R3,LSL #2]
1578         CMP             R2,#MAP_LAST
1579         BLO             SBSpecial  @ special
1580         @  Direct ROM/RAM acess
1581
1582         @ R2 <= SetAddress + Address & 0xFFFF
1583         MOV             R0,R0,LSL #16
1584         ADD             R2,R2,R0,LSR #16
1585         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1586         @ Set byte
1587         STRB            R1,[R2]
1588         @ R0 <= MemorySpeed[block]
1589         LDRB            R0,[R0,R3]
1590         @ Update CPU.Cycles
1591         ADD             reg_cycles,reg_cycles,R0
1592         @ CPUShutdown
1593         @ only SA1 here : TODO
1594         @ Return
1595         LDMFD           R13!,{PC}
1596 SBSpecial:
1597         LDR             PC,[PC,R2,LSL #2]
1598         MOV             R0,R0           @ nop, for align
1599         .long SBPPU
1600         .long SBCPU
1601         .long SBDSP
1602         .long SBLSRAM
1603         .long SBHSRAM
1604         .long SBNONE
1605         .long SBDEBUG
1606         .long SBC4
1607         .long SBBWRAM
1608         .long SBNONE
1609         .long SBNONE
1610         .long SBNONE
1611         /*.long SB7ROM
1612         .long SB7RAM
1613         .long SB7SRM*/
1614 SBPPU:
1615         @ InDMA ?
1616         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1617         MOVS            R2,R2
1618         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1619         MOV             R0,R0,LSL #16
1620         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1621         MOV             R0,R0,LSR #16
1622                 PREPARE_C_CALL
1623         MOV             R12,R0
1624         UXTB    R0,R1
1625         MOV             R1,R12
1626         BL              S9xSetPPU
1627                 RESTORE_C_CALL
1628         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1629         LDMFD           R13!,{PC} @ Return
1630 SBCPU:
1631         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1632         MOV             R0,R0,LSL #16
1633         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1634         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1635                 PREPARE_C_CALL
1636         MOV             R12,R0
1637         UXTB    R0,R1
1638         MOV             R1,R12
1639         BL              S9xSetCPU
1640                 RESTORE_C_CALL
1641         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1642         LDMFD           R13!,{PC} @ Return
1643 SBDSP:
1644         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1645         MOV             R0,R0,LSL #16
1646         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1647         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1648                 PREPARE_C_CALL
1649         MOV             R12,R0
1650         UXTB    R0,R1
1651         MOV             R1,R12
1652         BL              S9xSetDSP
1653                 RESTORE_C_CALL
1654         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1655         LDMFD           R13!,{PC} @ Return
1656 SBLSRAM:
1657         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1658         LDRH            R2,[reg_cpu_var,#SRAMMask]
1659         MOVS            R2,R2
1660         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1661         LDR             R3,[reg_cpu_var,#SRAM]
1662         AND             R0,R2,R0                @ Address&SRAMMask
1663         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1664
1665         MOV             R0,#1
1666         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1667         LDMFD           R13!,{PC}  @ return
1668 SB7SRM:
1669 SBHSRAM:
1670         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1671
1672         MOV             R3,R0,LSL #17
1673         AND             R2,R0,#0xF0000
1674         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1675         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1676         ADD             R0,R2,R3
1677
1678         LDRH            R2,[reg_cpu_var,#SRAMMask]
1679         MOVS            R2,R2
1680         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1681
1682         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1683         LDR             R3,[reg_cpu_var,#SRAM]
1684         AND             R0,R2,R0                @ Address&SRAMMask
1685         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1686
1687         MOV             R0,#1
1688         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1689         LDMFD           R13!,{PC}       @ return
1690 SB7ROM:
1691 SB7RAM:
1692 SBNONE:
1693 SBDEBUG:
1694         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1695         LDMFD           R13!,{PC}
1696 SBC4:
1697         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1698         MOV             R0,R0,LSL #16
1699         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1700         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1701                 PREPARE_C_CALL
1702         MOV             R12,R0
1703         UXTB    R0,R1
1704         MOV             R1,R12
1705         BL              S9xSetC4
1706                 RESTORE_C_CALL
1707         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1708         LDMFD           R13!,{PC} @ Return
1709 SBBWRAM:
1710         MOV             R0,R0,LSL #17
1711         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1712         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1713         LDR             R2,[reg_cpu_var,#BWRAM]
1714         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1715         STRB            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1716
1717         MOV             R0,#1
1718         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1719
1720         LDMFD           R13!,{PC}
1721
1722
1723
1724 @ void aaS9xSetWord(uint32 address,uint16 val);
1725 asmS9xSetWord:
1726         @  in : R0  = 0x00hhmmll R1=0x0000hhll
1727         @  DESTROYED : R0,R1,R2,R3
1728         @  UPDATE : reg_cycles
1729         @ R1 <= block
1730
1731         MOV             R2,R0,LSL #19
1732         ADDS            R2,R2,#0x80000
1733         @ if = 0x1FFF => 0
1734         BNE             SW_NotBoundary
1735
1736         STMFD           R13!,{R0,R1}
1737                 STMFD           R13!,{PC}
1738         B               asmS9xSetByte
1739                 MOV             R0,R0
1740         LDMFD           R13!,{R0,R1}
1741         ADD             R0,R0,#1
1742         MOV             R1,R1,LSR #8
1743                 STMFD           R13!,{PC}
1744         B               asmS9xSetByte
1745                 MOV             R0,R0
1746
1747         LDMFD           R13!,{PC}
1748
1749 SW_NotBoundary:
1750
1751         MOV             R2,#0
1752         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1753         @
1754         @ R3 <= block
1755         MOV             R3,R0,LSR #MEMMAP_SHIFT
1756         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1757         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1758         @ so AND MEMMAP_MASK is BIC 0xFF000
1759         BIC             R3,R3,#0xFF000
1760         @ R2 <= Map[block] (SetAddress)
1761         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1762         LDR             R2,[R2,R3,LSL #2]
1763         CMP             R2,#MAP_LAST
1764         BLO             SWSpecial  @ special
1765         @  Direct ROM/RAM acess
1766
1767
1768         @ check if address is 16bits aligned or not
1769         TST             R0,#1
1770         BNE             SW_not_aligned1
1771         @ aligned
1772         MOV             R0,R0,LSL #16
1773         ADD             R2,R2,R0,LSR #16        @ address & 0xFFFF + SetAddress
1774         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1775         @ Set word
1776         STRH            R1,[R2]
1777         @ R1 <= MemorySpeed[block]
1778         LDRB            R0,[R0,R3]
1779         @ Update CPU.Cycles
1780         ADD             reg_cycles,reg_cycles,R0, LSL #1
1781         @ CPUShutdown
1782         @ only SA1 here : TODO
1783         @ Return
1784         LDMFD           R13!,{PC}
1785
1786 SW_not_aligned1:
1787         @ R1 = (Address&0xFFFF)<<16
1788         MOV             R0,R0,LSL #16
1789         @ First write @address
1790         STRB            R1,[R2,R0,LSR #16]
1791         ADD             R0,R0,#0x10000
1792         MOV             R1,R1,LSR #8
1793         @ Second write @address+1
1794         STRB            R1,[R2,R0,LSR #16]
1795         @ R1 <= MemorySpeed[block]
1796         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1797         LDRB            R0,[R0,R3]
1798         @ Update CPU.Cycles
1799         ADD             reg_cycles,reg_cycles,R0,LSL #1
1800         @ CPUShutdown
1801         @ only SA1 here : TODO
1802         @ Return
1803         LDMFD           R13!,{PC}
1804 SWSpecial:
1805         LDR             PC,[PC,R2,LSL #2]
1806         MOV             R0,R0           @ nop, for align
1807         .long SWPPU
1808         .long SWCPU
1809         .long SWDSP
1810         .long SWLSRAM
1811         .long SWHSRAM
1812         .long SWNONE
1813         .long SWDEBUG
1814         .long SWC4
1815         .long SWBWRAM
1816         .long SWNONE
1817         .long SWNONE
1818         .long SWNONE
1819         /*.long SW7ROM
1820         .long SW7RAM
1821         .long SW7SRM*/
1822 SWPPU:
1823         @ InDMA ?
1824         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1825         MOVS            R2,R2
1826         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1827         MOV             R0,R0,LSL #16
1828         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1829         MOV             R0,R0,LSR #16
1830         MOV             R2,R1
1831         MOV             R1,R0
1832         MOV             R0,R2
1833                 PREPARE_C_CALL_R0R1
1834         UXTB    R0,R0
1835         BL              S9xSetPPU
1836         LDMFD           R13!,{R0,R1}
1837         ADD             R1,R1,#1
1838         UXTB    R0,R0,ROR #8
1839         BIC             R1,R1,#0x10000
1840         BL              S9xSetPPU
1841                 RESTORE_C_CALL
1842         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1843         LDMFD           R13!,{PC} @ Return
1844 SWCPU:
1845         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1846         MOV             R0,R0,LSL #16
1847         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1848         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1849         MOV             R2,R1
1850         MOV             R1,R0
1851         MOV             R0,R2
1852                 PREPARE_C_CALL_R0R1
1853         UXTB    R0,R0
1854         BL              S9xSetCPU
1855         LDMFD           R13!,{R0,R1}
1856         ADD             R1,R1,#1
1857         UXTB    R0,R0,ROR #8    @ ((R0 >> 8) & 0xFF)
1858         BIC             R1,R1,#0x10000
1859         BL              S9xSetCPU
1860                 RESTORE_C_CALL
1861         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1862         LDMFD           R13!,{PC} @ Return
1863 SWDSP:
1864         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1865         MOV             R0,R0,LSL #16
1866         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1867         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1868         MOV             R2,R1
1869         MOV             R1,R0
1870         MOV             R0,R2
1871                 PREPARE_C_CALL_R0R1
1872         UXTB    R0,R0
1873         BL              S9xSetDSP
1874         LDMFD           R13!,{R0,R1}
1875         ADD             R1,R1,#1
1876         UXTB    R0,R0,ROR #8
1877         BIC             R1,R1,#0x10000
1878         BL              S9xSetDSP
1879                 RESTORE_C_CALL
1880         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1881         LDMFD           R13!,{PC} @ Return
1882 SWLSRAM:
1883         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1884         LDRH            R2,[reg_cpu_var,#SRAMMask]
1885         MOVS            R2,R2
1886         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1887
1888         AND             R3,R2,R0                @ Address&SRAMMask
1889         TST             R0,#1
1890         BNE             SW_not_aligned2
1891         @ aligned
1892         LDR             R0,[reg_cpu_var,#SRAM]
1893         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1894         MOV             R0,#1
1895         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1896         LDMFD           R13!,{PC}  @ return
1897 SW_not_aligned2:
1898
1899         ADD             R0,R0,#1
1900         AND             R2,R2,R0                @ (Address+1)&SRAMMask
1901         LDR             R0,[reg_cpu_var,#SRAM]
1902         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1903         MOV             R1,R1,LSR #8
1904         STRB            R1,[R0,R2]              @ *Memory.SRAM + (Address+1)&SRAMMask
1905         MOV             R0,#1
1906         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1907         LDMFD           R13!,{PC}  @ return
1908 SW7SRM:
1909 SWHSRAM:
1910         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1911
1912         LDRH            R2,[reg_cpu_var,#SRAMMask]
1913         MOVS            R2,R2
1914         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1915
1916         TST             R0,#1
1917         BNE             SW_not_aligned3
1918         @ aligned
1919         MOV             R3,R0,LSL #17
1920         AND             R2,R0,#0xF0000
1921         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1922         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1923         ADD             R0,R2,R3
1924         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1925         LDRH            R2,[reg_cpu_var,#SRAMMask]
1926         LDR             R3,[reg_cpu_var,#SRAM]
1927         AND             R0,R2,R0                @ Address&SRAMMask
1928         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1929         MOV             R0,#1
1930         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1931         LDMFD           R13!,{PC}       @ return
1932 SW_not_aligned3:
1933         MOV             R3,R0,LSL #17
1934         AND             R2,R0,#0xF0000
1935         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1936         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1937         ADD             R2,R2,R3
1938         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1939
1940         ADD             R0,R0,#1
1941         MOV             R3,R0,LSL #17
1942         AND             R0,R0,#0xF0000
1943         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1944         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1945         ADD             R0,R0,R3
1946         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1947         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1948         AND             R2,R3,R2                @ Address...&SRAMMask
1949         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1950
1951         LDR             R3,[reg_cpu_var,#SRAM]
1952         STRB            R1,[R2,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1953         MOV             R1,R1,LSR #8
1954         STRB            R1,[R0,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1955
1956         MOV             R0,#1
1957         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1958         LDMFD           R13!,{PC}       @ return
1959 SW7ROM:
1960 SW7RAM:
1961 SWNONE:
1962 SWDEBUG:
1963         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1964         LDMFD           R13!,{PC}       @ return
1965 SWC4:
1966         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1967         MOV             R0,R0,LSL #16
1968         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1969         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1970         MOV             R2,R1
1971         MOV             R1,R0
1972         MOV             R0,R2
1973                 PREPARE_C_CALL_R0R1
1974         UXTB    R0,R0
1975         BL              S9xSetC4
1976         LDMFD           R13!,{R0,R1}
1977         ADD             R1,R1,#1
1978         UXTB    R0,R0,ROR #8
1979         BIC             R1,R1,#0x10000
1980         BL              S9xSetC4
1981                 RESTORE_C_CALL
1982         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1983         LDMFD           R13!,{PC} @ Return
1984 SWBWRAM:
1985         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1986         TST             R0,#1
1987         BNE             SW_not_aligned4
1988         @ aligned
1989         MOV             R0,R0,LSL #17
1990         LDR             R2,[reg_cpu_var,#BWRAM]
1991         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1992         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1993         MOV             R3,#1
1994         STRH            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1995         STRB            R3,[reg_cpu_var,#SRAMModified_ofs]
1996         LDMFD           R13!,{PC}       @ return
1997 SW_not_aligned4:
1998         MOV             R0,R0,LSL #17
1999         ADD             R3,R0,#0x20000
2000         MOV             R0,R0,LSR #17   @ Address&0x7FFF
2001         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
2002         LDR             R2,[reg_cpu_var,#BWRAM]
2003         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2004         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
2005         STRB            R1,[R2,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2006         MOV             R1,R1,LSR #8
2007         STRB            R1,[R2,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
2008         MOV             R0,#1
2009         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
2010         LDMFD           R13!,{PC}               @ return
2011
2012
2013
2014
2015
2016 /*****************************************************************
2017         FLAGS
2018 *****************************************************************/
2019
2020 .macro          UPDATE_C
2021                 @  CC : ARM Carry Clear
2022                 BICCC   rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2023                 @  CS : ARM Carry Set
2024                 ORRCS   rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2025 .endm
2026 .macro          UPDATE_Z
2027                 @  NE : ARM Zero Clear
2028                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2029                 @  EQ : ARM Zero Set
2030                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2031 .endm
2032 .macro          UPDATE_ZN
2033                 @  NE : ARM Zero Clear
2034                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2035                 @  EQ : ARM Zero Set
2036                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2037                 @  PL : ARM Neg Clear
2038                 BICPL   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2039                 @  MI : ARM Neg Set
2040                 ORRMI   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2041 .endm
2042
2043 /*****************************************************************
2044         OPCODES_MAC
2045 *****************************************************************/
2046
2047
2048
2049
2050 .macro ADC8
2051                 TST rstatus, #MASK_DECIMAL
2052                 BEQ 1111f
2053                 S9xGetByte
2054
2055
2056                 STMFD   R13!,{rscratch}
2057                 MOV     rscratch4,#0x0F000000
2058                 @ rscratch2=xxW1xxxxxxxxxxxx
2059                 AND     rscratch2, rscratch, rscratch4
2060                 @ rscratch=xxW2xxxxxxxxxxxx
2061                 AND     rscratch, rscratch4, rscratch, LSR #4
2062                 @ rscratch3=xxA2xxxxxxxxxxxx
2063                 AND     rscratch3, rscratch4, reg_a, LSR #4
2064                 @ rscratch4=xxA1xxxxxxxxxxxx
2065                 AND     rscratch4,reg_a,rscratch4
2066                 @ R1=A1+W1+CARRY
2067                 TST     rstatus, #MASK_CARRY
2068                 ADDNE   rscratch2, rscratch2, #0x01000000
2069                 ADD     rscratch2,rscratch2,rscratch4
2070                 @  if R1 > 9
2071                 CMP     rscratch2, #0x09000000
2072                 @  then R1 -= 10
2073                 SUBGT   rscratch2, rscratch2, #0x0A000000
2074                 @  then A2++
2075                 ADDGT   rscratch3, rscratch3, #0x01000000
2076                 @  R2 = A2+W2
2077                 ADD     rscratch3, rscratch3, rscratch
2078                 @  if R2 > 9
2079                 CMP     rscratch3, #0x09000000
2080                 @  then R2 -= 10@
2081                 SUBGT   rscratch3, rscratch3, #0x0A000000
2082                 @  then SetCarry()
2083                 ORRGT   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2084                 @  else ClearCarry()
2085                 BICLE   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2086                 @  gather rscratch3 and rscratch2 into ans8
2087                 @  rscratch3 : 0R2000000
2088                 @  rscratch2 : 0R1000000
2089                 @  -> 0xR2R1000000
2090                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2091                 LDMFD   R13!,{rscratch}
2092                 @ only last bit
2093                 AND     rscratch,rscratch,#0x80000000
2094                 @  (register.AL ^ Work8)
2095                 EORS    rscratch3, reg_a, rscratch
2096                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2097                 BNE     1112f
2098                 @  (Work8 ^ Ans8)
2099                 EORS    rscratch3, rscratch2, rscratch
2100                 @  & 0x80
2101                 TSTNE   rscratch3,#0x80000000
2102                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2103                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2104 1112:
2105                 MOVS reg_a, rscratch2
2106                 UPDATE_ZN
2107                 B 1113f
2108 1111:
2109                 S9xGetByteLow
2110                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2111                 SUBCS rscratch, rscratch, #0x100
2112                 ADCS reg_a, reg_a, rscratch, ROR #8
2113                 @ OverFlow
2114                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2115                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2116                 @ Carry
2117                 UPDATE_C
2118                 @ clear lower part
2119                 ANDS reg_a, reg_a, #0xFF000000
2120                 @ Update flag
2121                 UPDATE_ZN
2122 1113:
2123 .endm
2124 /* TO TEST */
2125 .macro ADC16
2126                 TST rstatus, #MASK_DECIMAL
2127                 BEQ 1111f
2128                 S9xGetWord
2129
2130                 @ rscratch = W3W2W1W0........
2131                 LDR     rscratch4, = 0x0F0F0000
2132                 @  rscratch2 = xxW2xxW0xxxxxx
2133                 @  rscratch3 = xxW3xxW1xxxxxx
2134                 AND     rscratch2, rscratch4, rscratch
2135                 AND     rscratch3, rscratch4, rscratch, LSR #4
2136                 @  rscratch2 = xxW3xxW1xxW2xxW0
2137                 ORR     rscratch2, rscratch3, rscratch2, LSR #16
2138                 @  rscratch3 = xxA2xxA0xxxxxx
2139                 @  rscratch4 = xxA3xxA1xxxxxx
2140                 @  rscratch2 = xxA3xxA1xxA2xxA0
2141                 AND     rscratch3, rscratch4, reg_a
2142                 AND     rscratch4, rscratch4, reg_a, LSR #4
2143                 ORR     rscratch3, rscratch4, rscratch3, LSR #16
2144                 ADD     rscratch2, rscratch3, rscratch2
2145                 LDR     rscratch4, = 0x0F0F0000
2146                 @  rscratch2 = A + W
2147                 TST     rstatus, #MASK_CARRY
2148                 ADDNE   rscratch2, rscratch2, #0x1
2149                 @  rscratch2 = A + W + C
2150                 @ A0
2151                 AND     rscratch3, rscratch2, #0x0000001F
2152                 CMP     rscratch3, #0x00000009
2153                 ADDHI   rscratch2, rscratch2, #0x00010000
2154                 SUBHI   rscratch2, rscratch2, #0x0000000A
2155                 @ A1
2156                 AND     rscratch3, rscratch2, #0x001F0000
2157                 CMP     rscratch3, #0x00090000
2158                 ADDHI   rscratch2, rscratch2, #0x00000100
2159                 SUBHI   rscratch2, rscratch2, #0x000A0000
2160                 @ A2
2161                 AND     rscratch3, rscratch2, #0x00001F00
2162                 CMP     rscratch3, #0x00000900
2163                 SUBHI   rscratch2, rscratch2, #0x00000A00
2164                 ADDHI   rscratch2, rscratch2, #0x01000000
2165                 @ A3
2166                 AND     rscratch3, rscratch2, #0x1F000000
2167                 CMP     rscratch3, #0x09000000
2168                 SUBHI   rscratch2, rscratch2, #0x0A000000
2169                 @ SetCarry
2170                 ORRHI   rstatus, rstatus, #MASK_CARRY
2171                 @ ClearCarry
2172                 BICLS   rstatus, rstatus, #MASK_CARRY
2173                 @ rscratch2 = xxR3xxR1xxR2xxR0
2174                 @ Pack result
2175                 @ rscratch3 = xxR3xxR1xxxxxxxx
2176                 AND     rscratch3, rscratch4, rscratch2
2177                 @ rscratch2 = xxR2xxR0xxxxxxxx
2178                 AND     rscratch2, rscratch4, rscratch2,LSL #16
2179                 @ rscratch2 = R3R2R1R0xxxxxxxx
2180                 ORR     rscratch2, rscratch2,rscratch3,LSL #4
2181 @ only last bit
2182                 AND     rscratch,rscratch,#0x80000000
2183                 @  (register.AL ^ Work8)
2184                 EORS    rscratch3, reg_a, rscratch
2185                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2186                 BNE     1112f
2187                 @  (Work8 ^ Ans8)
2188                 EORS    rscratch3, rscratch2, rscratch
2189                 TSTNE   rscratch3,#0x80000000
2190                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2191                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2192 1112:
2193                 MOVS    reg_a, rscratch2
2194                 UPDATE_ZN
2195                 B       1113f
2196 1111:
2197                 S9xGetWordLow
2198                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2199                 SUBCS rscratch, rscratch, #0x10000
2200                 ADCS reg_a, reg_a,rscratch, ROR #16
2201                 @ OverFlow
2202                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2203                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2204                 MOV reg_a, reg_a, LSR #16
2205                 @ Carry
2206                 UPDATE_C
2207                 @ clear lower parts
2208                 MOVS reg_a, reg_a, LSL #16
2209                 @ Update flag
2210                 UPDATE_ZN
2211 1113:
2212 .endm
2213
2214
2215 .macro          AND16
2216                 S9xGetWord
2217                 ANDS            reg_a, reg_a, rscratch
2218                 UPDATE_ZN
2219 .endm
2220 .macro          AND8
2221                 S9xGetByte
2222                 ANDS            reg_a, reg_a, rscratch
2223                 UPDATE_ZN
2224 .endm
2225 .macro          A_ASL8
2226                 @  7    instr
2227                 MOVS    reg_a, reg_a, LSL #1
2228                 UPDATE_C
2229                 UPDATE_ZN
2230                 ADD1CYCLE
2231 .endm
2232 .macro          A_ASL16
2233                 @  7    instr
2234                 MOVS    reg_a, reg_a, LSL #1
2235                 UPDATE_C
2236                 UPDATE_ZN
2237                 ADD1CYCLE
2238 .endm
2239 .macro          ASL16
2240                 S9xGetWordRegNS rscratch2             @         do not destroy Opadress in rscratch
2241                 MOVS            rscratch2, rscratch2, LSL #1
2242                 UPDATE_C
2243                 UPDATE_ZN
2244                 S9xSetWord      rscratch2
2245                 ADD1CYCLE
2246 .endm
2247 .macro          ASL8
2248                 S9xGetByteRegNS rscratch2             @         do not destroy Opadress in rscratch
2249                 MOVS            rscratch2, rscratch2, LSL #1
2250                 UPDATE_C
2251                 UPDATE_ZN
2252                 S9xSetByte      rscratch2
2253                 ADD1CYCLE
2254 .endm
2255 .macro          BIT8
2256                 S9xGetByte
2257                 MOVS    rscratch2, rscratch, LSL #1
2258                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2259                 @                                         ARM N = Snes V
2260                 @  If Carry Set, then Set Neg in SNES
2261                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set C to zero
2262                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set C to one
2263                 @  If Neg Set, then Set Overflow in SNES
2264                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set N to zero
2265                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set N to one
2266
2267                 @  Now do a real AND    with A register
2268                 @  Set Zero Flag, bit test
2269                 ANDS    rscratch2, reg_a, rscratch
2270                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2271                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2272 .endm
2273
2274 .macro          BIT16
2275                 S9xGetWord
2276                 MOVS    rscratch2, rscratch, LSL #1
2277                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2278                 @                                         ARM N = Snes V
2279                 @  If Carry Set, then Set Neg in SNES
2280                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2281                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2282                 @  If Neg Set, then Set Overflow in SNES
2283                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set V to zero
2284                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set V to one
2285                 @  Now do a real AND    with A register
2286                 @  Set Zero Flag, bit test
2287                 ANDS    rscratch2, reg_a, rscratch
2288                 @  Bit set  ->Z=0->xxxNE Clear flag
2289                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2290                 @  Bit clear->Z=1->xxxEQ Set flag
2291                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2292 .endm
2293 .macro          CMP8
2294                 S9xGetByte
2295                 SUBS    rscratch2,reg_a,rscratch
2296                 BICCC   rstatus, rstatus, #MASK_CARRY
2297                 ORRCS   rstatus, rstatus, #MASK_CARRY
2298                 UPDATE_ZN
2299
2300 .endm
2301 .macro          CMP16
2302                 S9xGetWord
2303                 SUBS    rscratch2,reg_a,rscratch
2304                 BICCC   rstatus, rstatus, #MASK_CARRY
2305                 ORRCS   rstatus, rstatus, #MASK_CARRY
2306                 UPDATE_ZN
2307
2308 .endm
2309 .macro          CMX16
2310                 S9xGetWord
2311                 SUBS    rscratch2,reg_x,rscratch
2312                 BICCC   rstatus, rstatus, #MASK_CARRY
2313                 ORRCS   rstatus, rstatus, #MASK_CARRY
2314                 UPDATE_ZN
2315 .endm
2316 .macro          CMX8
2317                 S9xGetByte
2318                 SUBS    rscratch2,reg_x,rscratch
2319                 BICCC   rstatus, rstatus, #MASK_CARRY
2320                 ORRCS   rstatus, rstatus, #MASK_CARRY
2321                 UPDATE_ZN
2322 .endm
2323 .macro          CMY16
2324                 S9xGetWord
2325                 SUBS    rscratch2,reg_y,rscratch
2326                 BICCC   rstatus, rstatus, #MASK_CARRY
2327                 ORRCS   rstatus, rstatus, #MASK_CARRY
2328                 UPDATE_ZN
2329 .endm
2330 .macro          CMY8
2331                 S9xGetByte
2332                 SUBS    rscratch2,reg_y,rscratch
2333                 BICCC   rstatus, rstatus, #MASK_CARRY
2334                 ORRCS   rstatus, rstatus, #MASK_CARRY
2335                 UPDATE_ZN
2336 .endm
2337 .macro          A_DEC8
2338                 MOV             rscratch,#0
2339                 SUBS            reg_a, reg_a, #0x01000000
2340                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2341                 UPDATE_ZN
2342                 ADD1CYCLE
2343 .endm
2344 .macro          A_DEC16
2345                 MOV             rscratch,#0
2346                 SUBS            reg_a, reg_a, #0x00010000
2347                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2348                 UPDATE_ZN
2349                 ADD1CYCLE
2350 .endm
2351 .macro          DEC16
2352                 S9xGetWordRegNS rscratch2              @  do not        destroy Opadress in rscratch
2353                 MOV             rscratch3,#0
2354                 SUBS            rscratch2, rscratch2, #0x00010000
2355                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2356                 UPDATE_ZN
2357                 S9xSetWord      rscratch2
2358                 ADD1CYCLE
2359 .endm
2360 .macro          DEC8
2361                 S9xGetByteRegNS rscratch2              @  do not        destroy Opadress in rscratch
2362                 MOV             rscratch3,#0
2363                 SUBS            rscratch2, rscratch2, #0x01000000
2364                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2365                 UPDATE_ZN
2366                 S9xSetByte      rscratch2
2367                 ADD1CYCLE
2368 .endm
2369 .macro          EOR16
2370                 S9xGetWord
2371                 EORS            reg_a, reg_a, rscratch
2372                 UPDATE_ZN
2373 .endm
2374 .macro          EOR8
2375                 S9xGetByte
2376                 EORS            reg_a, reg_a, rscratch
2377                 UPDATE_ZN
2378 .endm
2379 .macro          A_INC8
2380                 MOV             rscratch3,#0
2381                 ADDS            reg_a, reg_a, #0x01000000
2382                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2383                 UPDATE_ZN
2384                 ADD1CYCLE
2385 .endm
2386 .macro          A_INC16
2387                 MOV             rscratch3,#0
2388                 ADDS            reg_a, reg_a, #0x00010000
2389                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2390                 UPDATE_ZN
2391                 ADD1CYCLE
2392 .endm
2393 .macro          INC16
2394                 S9xGetWordRegNS rscratch2
2395                 MOV             rscratch3,#0
2396                 ADDS            rscratch2, rscratch2, #0x00010000
2397                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2398                 UPDATE_ZN
2399                 S9xSetWord      rscratch2
2400                 ADD1CYCLE
2401 .endm
2402 .macro          INC8
2403                 S9xGetByteRegNS rscratch2
2404                 MOV             rscratch3,#0
2405                 ADDS            rscratch2, rscratch2, #0x01000000
2406                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2407                 UPDATE_ZN
2408                 S9xSetByte      rscratch2
2409                 ADD1CYCLE
2410 .endm
2411 .macro          LDA16
2412                 S9xGetWordRegStatus reg_a
2413                 UPDATE_ZN
2414 .endm
2415 .macro          LDA8
2416                 S9xGetByteRegStatus reg_a
2417                 UPDATE_ZN
2418 .endm
2419 .macro          LDX16
2420                 S9xGetWordRegStatus reg_x
2421                 UPDATE_ZN
2422 .endm
2423 .macro          LDX8
2424                 S9xGetByteRegStatus reg_x
2425                 UPDATE_ZN
2426 .endm
2427 .macro          LDY16
2428                 S9xGetWordRegStatus reg_y
2429                 UPDATE_ZN
2430 .endm
2431 .macro          LDY8
2432                 S9xGetByteRegStatus reg_y
2433                 UPDATE_ZN
2434 .endm
2435 .macro          A_LSR16
2436                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2437                 MOVS    reg_a, reg_a, LSR #17            @  hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
2438                 @  Update Zero
2439                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2440                 MOV     reg_a, reg_a, LSL #16                   @  -> 0lllllll 00000000 00000000        00000000
2441                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2442                 @  Note : the two MOV are included between instruction, to optimize
2443                 @  the pipeline.
2444                 UPDATE_C
2445                 ADD1CYCLE
2446 .endm
2447 .macro          A_LSR8
2448                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2449                 MOVS    reg_a, reg_a, LSR #25            @  llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2450                 @  Update Zero
2451                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2452                 MOV     reg_a, reg_a, LSL #24                   @  -> 00000000 00000000 00000000        0lllllll
2453                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2454                 @  Note : the two MOV are included between instruction, to optimize
2455                 @  the pipeline.
2456                 UPDATE_C
2457                 ADD1CYCLE
2458 .endm
2459 .macro          LSR16
2460                 S9xGetWordRegNS rscratch2
2461                 @  N set to zero by >> 1 LSR
2462                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2463                 MOVS            rscratch2, rscratch2, LSR #17              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2464                 @  Update Carry
2465                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2466                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2467                 @  Update Zero
2468                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2469                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2470                 S9xSetWordLow   rscratch2
2471                 ADD1CYCLE
2472 .endm
2473 .macro          LSR8
2474                 S9xGetByteRegNS rscratch2
2475                 @  N set to zero by >> 1 LSR
2476                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2477                 MOVS            rscratch2, rscratch2, LSR #25              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2478                 @  Update Carry
2479                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2480                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2481                 @  Update Zero
2482                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2483                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2484                 S9xSetByteLow   rscratch2
2485                 ADD1CYCLE
2486 .endm
2487 .macro          ORA8
2488                 S9xGetByte
2489                 ORRS            reg_a, reg_a, rscratch
2490                 UPDATE_ZN
2491 .endm
2492 .macro          ORA16
2493                 S9xGetWord
2494                 ORRS            reg_a, reg_a, rscratch
2495                 UPDATE_ZN
2496 .endm
2497 .macro          A_ROL16
2498                 TST             rstatus, #MASK_CARRY
2499                 ORRNE           reg_a, reg_a, #0x00008000
2500                 MOVS            reg_a, reg_a, LSL #1
2501                 UPDATE_ZN
2502                 UPDATE_C
2503                 ADD1CYCLE
2504 .endm
2505 .macro          A_ROL8
2506                 TST             rstatus, #MASK_CARRY
2507                 ORRNE           reg_a, reg_a, #0x00800000
2508                 MOVS            reg_a, reg_a, LSL #1
2509                 UPDATE_ZN
2510                 UPDATE_C
2511                 ADD1CYCLE
2512 .endm
2513 .macro          ROL16
2514                 S9xGetWordRegNS rscratch2
2515                 TST             rstatus, #MASK_CARRY
2516                 ORRNE           rscratch2, rscratch2, #0x00008000
2517                 MOVS            rscratch2, rscratch2, LSL #1
2518                 UPDATE_ZN
2519                 UPDATE_C
2520                 S9xSetWord      rscratch2
2521                 ADD1CYCLE
2522 .endm
2523 .macro          ROL8
2524                 S9xGetByteRegNS rscratch2
2525                 TST             rstatus, #MASK_CARRY
2526                 ORRNE           rscratch2, rscratch2, #0x00800000
2527                 MOVS            rscratch2, rscratch2, LSL #1
2528                 UPDATE_ZN
2529                 UPDATE_C
2530                 S9xSetByte      rscratch2
2531                 ADD1CYCLE
2532 .endm
2533 .macro          A_ROR16
2534                 MOV                     reg_a,reg_a, LSR #16
2535                 TST                     rstatus, #MASK_CARRY
2536                 ORRNE                   reg_a, reg_a, #0x00010000
2537                 ORRNE                   rstatus,rstatus,#MASK_NEG
2538                 BICEQ                   rstatus,rstatus,#MASK_NEG
2539                 MOVS                    reg_a,reg_a,LSR #1
2540                 UPDATE_C
2541                 UPDATE_Z
2542                 MOV                     reg_a,reg_a, LSL #16
2543                 ADD1CYCLE
2544 .endm
2545 .macro          A_ROR8
2546                 MOV                     reg_a,reg_a, LSR #24
2547                 TST                     rstatus, #MASK_CARRY
2548                 ORRNE                   reg_a, reg_a, #0x00000100
2549                 ORRNE                   rstatus,rstatus,#MASK_NEG
2550                 BICEQ                   rstatus,rstatus,#MASK_NEG
2551                 MOVS                    reg_a,reg_a,LSR #1
2552                 UPDATE_C
2553                 UPDATE_Z
2554                 MOV                     reg_a,reg_a, LSL #24
2555                 ADD1CYCLE
2556 .endm
2557 .macro          ROR16
2558                 S9xGetWordLowRegNS      rscratch2
2559                 TST                     rstatus, #MASK_CARRY
2560                 ORRNE                   rscratch2, rscratch2, #0x00010000
2561                 ORRNE                   rstatus,rstatus,#MASK_NEG
2562                 BICEQ                   rstatus,rstatus,#MASK_NEG
2563                 MOVS                    rscratch2,rscratch2,LSR #1
2564                 UPDATE_C
2565                 UPDATE_Z
2566                 S9xSetWordLow   rscratch2
2567                 ADD1CYCLE
2568
2569 .endm
2570 .macro          ROR8
2571                 S9xGetByteLowRegNS      rscratch2
2572                 TST                     rstatus, #MASK_CARRY
2573                 ORRNE                   rscratch2, rscratch2, #0x00000100
2574                 ORRNE                   rstatus,rstatus,#MASK_NEG
2575                 BICEQ                   rstatus,rstatus,#MASK_NEG
2576                 MOVS                    rscratch2,rscratch2,LSR #1
2577                 UPDATE_C
2578                 UPDATE_Z
2579                 S9xSetByteLow   rscratch2
2580                 ADD1CYCLE
2581 .endm
2582
2583 .macro SBC16
2584         TST rstatus, #MASK_DECIMAL
2585                 BEQ 1111f
2586                 @ TODO
2587                 S9xGetWord
2588
2589                 STMFD   R13!,{rscratch9}
2590                 MOV     rscratch9,#0x000F0000
2591         @ rscratch2 - result
2592         @ rscratch3 - scratch
2593         @ rscratch4 - scratch
2594         @ rscratch9 - pattern
2595
2596                 AND     rscratch2, rscratch, #0x000F0000
2597                 TST     rstatus, #MASK_CARRY
2598                 ADDEQ   rscratch2, rscratch2, #0x00010000  @ W1=W1+!Carry
2599                 AND     rscratch4, reg_a, #0x000F0000
2600         SUB     rscratch2, rscratch4,rscratch2          @ R1=A1-W1-!Carry
2601                 CMP     rscratch2, #0x00090000  @  if R1 > 9
2602                 ADDHI   rscratch2, rscratch2, #0x000A0000 @  then R1 += 10
2603                 AND         rscratch2, rscratch2, #0x000F0000
2604
2605                 AND     rscratch3, rscratch9, rscratch, LSR #4
2606         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W2++)
2607
2608                 AND     rscratch4, rscratch9, reg_a, LSR #4
2609         SUB     rscratch3, rscratch4, rscratch3         @ R2=A2-W2
2610                 CMP     rscratch3, #0x00090000  @  if R2 > 9
2611                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R2 += 10
2612                 AND         rscratch3, rscratch3, #0x000F0000
2613                 ORR         rscratch2, rscratch2, rscratch3,LSL #4
2614
2615                 AND     rscratch3, rscratch9, rscratch, LSR #8
2616         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2617
2618                 AND     rscratch4, rscratch9, reg_a, LSR #8
2619         SUB     rscratch3, rscratch4, rscratch3         @ R3=A3-W3
2620                 CMP     rscratch3, #0x00090000  @  if R3 > 9
2621                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R3 += 10
2622                 AND         rscratch3, rscratch3, #0x000F0000
2623                 ORR         rscratch2, rscratch2, rscratch3,LSL #8
2624
2625                 AND     rscratch3, rscratch9, rscratch, LSR #12
2626         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2627
2628                 AND     rscratch4, rscratch9, reg_a, LSR #12
2629         SUB     rscratch3, rscratch4, rscratch3         @ R4=A4-W4
2630                 CMP     rscratch3, #0x00090000  @  if R4 > 9
2631                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R4 += 10
2632                 BICHI   rstatus, rstatus, #MASK_CARRY   @  then ClearCarry
2633                 ORRLS   rstatus, rstatus, #MASK_CARRY   @  else SetCarry
2634
2635                 AND         rscratch3,rscratch3,#0x000F0000
2636                 ORR         rscratch2,rscratch2,rscratch3,LSL #12
2637
2638                 LDMFD   R13!,{rscratch9}
2639                 @ only last bit
2640                 AND     reg_a,reg_a,#0x80000000
2641                 @  (register.A.W ^ Work8)
2642                 EORS    rscratch3, reg_a, rscratch
2643                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2644                 BEQ     1112f
2645                 @  (register.A.W ^ Ans8)
2646                 EORS    rscratch3, reg_a, rscratch2
2647                 @  & 0x80
2648                 TSTNE   rscratch3,#0x80000000
2649                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2650                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2651 1112:
2652                 MOVS    reg_a, rscratch2
2653                 UPDATE_ZN
2654                 B 1113f
2655 1111:
2656                 S9xGetWordLow
2657                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2658                 SBCS reg_a, reg_a, rscratch, LSL #16
2659                 @ OverFlow
2660                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2661                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2662                 MOV reg_a, reg_a, LSR #16
2663                 @ Carry
2664                 UPDATE_C
2665                 MOVS reg_a, reg_a, LSL #16
2666                 @ Update flag
2667                 UPDATE_ZN
2668 1113:
2669 .endm
2670
2671 .macro SBC8
2672                 TST rstatus, #MASK_DECIMAL
2673                 BEQ 1111f
2674                 S9xGetByte
2675                 STMFD   R13!,{rscratch}
2676                 MOV     rscratch4,#0x0F000000
2677                 @ rscratch2=xxW1xxxxxxxxxxxx
2678                 AND     rscratch2, rscratch, rscratch4
2679                 @ rscratch=xxW2xxxxxxxxxxxx
2680                 AND     rscratch, rscratch4, rscratch, LSR #4
2681                 @ rscratch3=xxA2xxxxxxxxxxxx
2682                 AND     rscratch3, rscratch4, reg_a, LSR #4
2683                 @ rscratch4=xxA1xxxxxxxxxxxx
2684                 AND     rscratch4,reg_a,rscratch4
2685                 @ R1=A1-W1-!CARRY
2686                 TST     rstatus, #MASK_CARRY
2687                 ADDEQ   rscratch2, rscratch2, #0x01000000
2688                 SUB     rscratch2,rscratch4,rscratch2
2689                 @  if R1 > 9
2690                 CMP     rscratch2, #0x09000000
2691                 @  then R1 += 10
2692                 ADDHI   rscratch2, rscratch2, #0x0A000000
2693                 @  then A2-- (W2++)
2694                 ADDHI   rscratch, rscratch, #0x01000000
2695                 @  R2=A2-W2
2696                 SUB     rscratch3, rscratch3, rscratch
2697                 @  if R2 > 9
2698                 CMP     rscratch3, #0x09000000
2699                 @  then R2 -= 10@
2700                 ADDHI   rscratch3, rscratch3, #0x0A000000
2701                 @  then SetCarry()
2702                 BICHI   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2703                 @  else ClearCarry()
2704                 ORRLS   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2705                 @  gather rscratch3 and rscratch2 into ans8
2706                 AND     rscratch3,rscratch3,#0x0F000000
2707                 AND     rscratch2,rscratch2,#0x0F000000
2708                 @  rscratch3 : 0R2000000
2709                 @  rscratch2 : 0R1000000
2710                 @  -> 0xR2R1000000
2711                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2712                 LDMFD   R13!,{rscratch}
2713                 @ only last bit
2714                 AND     reg_a,reg_a,#0x80000000
2715                 @  (register.AL ^ Work8)
2716                 EORS    rscratch3, reg_a, rscratch
2717                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2718                 BEQ     1112f
2719                 @  (register.AL ^ Ans8)
2720                 EORS    rscratch3, reg_a, rscratch2
2721                 @  & 0x80
2722                 TSTNE   rscratch3,#0x80000000
2723                 BICEQ rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2724                 ORRNE rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2725 1112:
2726                 MOVS reg_a, rscratch2
2727                 UPDATE_ZN
2728                 B 1113f
2729 1111:
2730                 S9xGetByteLow
2731                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2732                 SBCS reg_a, reg_a, rscratch, LSL #24
2733                 @ OverFlow
2734                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2735                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2736                 @ Carry
2737                 UPDATE_C
2738                 @ Update flag
2739                 ANDS reg_a, reg_a, #0xFF000000
2740                 UPDATE_ZN
2741 1113:
2742 .endm
2743
2744 .macro          STA16
2745                 S9xSetWord      reg_a
2746 .endm
2747 .macro          STA8
2748                 S9xSetByte      reg_a
2749 .endm
2750 .macro          STX16
2751                 S9xSetWord      reg_x
2752 .endm
2753 .macro          STX8
2754                 S9xSetByte      reg_x
2755 .endm
2756 .macro          STY16
2757                 S9xSetWord      reg_y
2758 .endm
2759 .macro          STY8
2760                 S9xSetByte      reg_y
2761 .endm
2762 .macro          STZ16
2763                 S9xSetWordZero
2764 .endm
2765 .macro          STZ8
2766                 S9xSetByteZero
2767 .endm
2768 .macro          TSB16
2769                 S9xGetWordRegNS rscratch2
2770                 TST             reg_a, rscratch2
2771                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2772                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2773                 ORR             rscratch2, reg_a, rscratch2
2774                 S9xSetWord      rscratch2
2775                 ADD1CYCLE
2776 .endm
2777 .macro          TSB8
2778                 S9xGetByteRegNS rscratch2
2779                 TST             reg_a, rscratch2
2780                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2781                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2782                 ORR             rscratch2, reg_a, rscratch2
2783                 S9xSetByte      rscratch2
2784                 ADD1CYCLE
2785 .endm
2786 .macro          TRB16
2787                 S9xGetWordRegNS rscratch2
2788                 TST             reg_a, rscratch2
2789                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2790                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2791                 MVN             rscratch3, reg_a
2792                 AND             rscratch2, rscratch3, rscratch2
2793                 S9xSetWord      rscratch2
2794                 ADD1CYCLE
2795 .endm
2796 .macro          TRB8
2797                 S9xGetByteRegNS rscratch2
2798                 TST             reg_a, rscratch2
2799                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2800                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2801                 MVN             rscratch3, reg_a
2802                 AND             rscratch2, rscratch3, rscratch2
2803                 S9xSetByte      rscratch2
2804                 ADD1CYCLE
2805 .endm
2806 /**************************************************************************/
2807
2808
2809 /**************************************************************************/
2810
2811 .macro          Op09M0          /*ORA*/
2812                 LDRB            rscratch2, [rpc,#1]
2813                 LDRB            rscratch, [rpc], #2
2814                 ORR             rscratch2,rscratch,rscratch2,LSL #8
2815                 ORRS            reg_a,reg_a,rscratch2,LSL #16
2816                 UPDATE_ZN
2817                 ADD2MEM
2818 .endm
2819 .macro          Op09M1          /*ORA*/
2820                 LDRB            rscratch, [rpc], #1
2821                 ORRS            reg_a,reg_a,rscratch,LSL #24
2822                 UPDATE_ZN
2823                 ADD1MEM
2824 .endm
2825 /***********************************************************************/
2826 .macro          Op90    /*BCC*/
2827                 asmRelative
2828                 BranchCheck0
2829                 TST             rstatus, #MASK_CARRY
2830                 BNE             1111f
2831                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2832                 ADD1CYCLE
2833                 CPUShutdown
2834 1111:
2835 .endm
2836 .macro          OpB0    /*BCS*/
2837                 asmRelative
2838                 BranchCheck0
2839                 TST             rstatus, #MASK_CARRY
2840                 BEQ             1111f
2841                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2842                 ADD1CYCLE
2843                 CPUShutdown
2844 1111:
2845 .endm
2846 .macro          OpF0    /*BEQ*/
2847                 asmRelative
2848                 BranchCheck2
2849                 TST             rstatus, #MASK_ZERO
2850                 BEQ             1111f
2851                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2852                 ADD1CYCLE
2853                 CPUShutdown
2854 1111:
2855 .endm
2856 .macro          OpD0    /*BNE*/
2857                 asmRelative
2858                 BranchCheck1
2859                 TST             rstatus, #MASK_ZERO
2860                 BNE             1111f
2861                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2862                 ADD1CYCLE
2863                 CPUShutdown
2864 1111:
2865 .endm
2866 .macro          Op30    /*BMI*/
2867                 asmRelative
2868                 BranchCheck0
2869                 TST             rstatus, #MASK_NEG
2870                 BEQ             1111f
2871                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2872                 ADD1CYCLE
2873                 CPUShutdown
2874 1111:
2875 .endm
2876 .macro          Op10   /*BPL*/
2877                 asmRelative
2878                 BranchCheck1
2879                 TST             rstatus, #MASK_NEG @  neg, z!=0, NE
2880                 BNE             1111f
2881                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2882                 ADD1CYCLE
2883                 CPUShutdown
2884 1111:
2885 .endm
2886 .macro          Op50   /*BVC*/
2887                 asmRelative
2888                 BranchCheck0
2889                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2890                 BNE             1111f
2891                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2892                 ADD1CYCLE
2893                 CPUShutdown
2894 1111:
2895 .endm
2896 .macro          Op70   /*BVS*/
2897                 asmRelative
2898                 BranchCheck0
2899                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2900                 BEQ             1111f
2901                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2902                 ADD1CYCLE
2903                 CPUShutdown
2904 1111:
2905 .endm
2906 .macro          Op80   /*BRA*/
2907                 asmRelative
2908                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2909                 ADD1CYCLE
2910                 CPUShutdown
2911 1111:
2912 .endm
2913 /*******************************************************************************************/
2914 /************************************************************/
2915 /* SetFlag Instructions ********************************************************************** */
2916 .macro          Op38 /*SEC*/
2917                 ORR             rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2918                 ADD1CYCLE
2919 .endm
2920 .macro          OpF8 /*SED*/
2921                 SetDecimal
2922                 ADD1CYCLE
2923 .endm
2924 .macro          Op78 /*SEI*/
2925                 SetIRQ
2926                 ADD1CYCLE
2927 .endm
2928
2929
2930 /****************************************************************************************/
2931 /* ClearFlag Instructions ******************************************************************** */
2932 .macro          Op18  /*CLC*/
2933                 BIC             rstatus, rstatus, #MASK_CARRY
2934                 ADD1CYCLE
2935 .endm
2936 .macro          OpD8 /*CLD*/
2937                 ClearDecimal
2938                 ADD1CYCLE
2939 .endm
2940 .macro          Op58  /*CLI*/
2941                 ClearIRQ
2942                 ADD1CYCLE
2943                 @ CHECK_FOR_IRQ
2944 .endm
2945 .macro          OpB8 /*CLV*/
2946                 BIC             rstatus, rstatus, #MASK_OVERFLOW
2947                 ADD1CYCLE
2948 .endm
2949
2950 /******************************************************************************************/
2951 /* DEX/DEY *********************************************************************************** */
2952
2953 .macro          OpCAX1  /*DEX*/
2954                 MOV             rscratch3,#0
2955                 SUBS            reg_x, reg_x, #0x01000000
2956                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2957                 UPDATE_ZN
2958                 ADD1CYCLE
2959 .endm
2960 .macro          OpCAX0  /*DEX*/
2961                 MOV             rscratch3,#0
2962                 SUBS            reg_x, reg_x, #0x00010000
2963                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2964                 UPDATE_ZN
2965                 ADD1CYCLE
2966 .endm
2967 .macro          Op88X1 /*DEY*/
2968                 MOV             rscratch3,#0
2969                 SUBS            reg_y, reg_y, #0x01000000
2970                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2971                 UPDATE_ZN
2972                 ADD1CYCLE
2973 .endm
2974 .macro          Op88X0 /*DEY*/
2975                 MOV             rscratch3,#0
2976                 SUBS            reg_y, reg_y, #0x00010000
2977                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2978                 UPDATE_ZN
2979                 ADD1CYCLE
2980 .endm
2981
2982 /******************************************************************************************/
2983 /* INX/INY *********************************************************************************** */
2984 .macro          OpE8X1
2985                 MOV             rscratch3,#0
2986                 ADDS            reg_x, reg_x, #0x01000000
2987                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2988                 UPDATE_ZN
2989                 ADD1CYCLE
2990 .endm
2991 .macro          OpE8X0
2992                 MOV             rscratch3,#0
2993                 ADDS            reg_x, reg_x, #0x00010000
2994                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2995                 UPDATE_ZN
2996                 ADD1CYCLE
2997 .endm
2998 .macro          OpC8X1
2999                 MOV             rscratch3,#0
3000                 ADDS            reg_y, reg_y, #0x01000000
3001                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3002                 UPDATE_ZN
3003                 ADD1CYCLE
3004 .endm
3005 .macro          OpC8X0
3006                 MOV             rscratch3,#0
3007                 ADDS            reg_y, reg_y, #0x00010000
3008                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3009                 UPDATE_ZN
3010                 ADD1CYCLE
3011 .endm
3012
3013 /**********************************************************************************************/
3014
3015 /* NOP *************************************************************************************** */
3016 .macro          OpEA
3017                 ADD1CYCLE
3018 .endm
3019
3020 /**************************************************************************/
3021 /* PUSH Instructions **************************************************** */
3022 .macro          OpF4
3023                 Absolute
3024                 PushWrLow
3025 .endm
3026 .macro          OpD4
3027                 DirectIndirect
3028                 PushWrLow
3029 .endm
3030 .macro          Op62
3031                 asmRelativeLong
3032                 PushWrLow
3033 .endm
3034 .macro          Op48M0
3035                 PushW           reg_a
3036                 ADD1CYCLE
3037 .endm
3038 .macro          Op48M1
3039                 PushB           reg_a
3040                 ADD1CYCLE
3041 .endm
3042 .macro          Op8B
3043                 AND             rscratch2, reg_d_bank, #0xFF
3044                 PushBLow        rscratch2
3045                 ADD1CYCLE
3046 .endm
3047 .macro          Op0B
3048                 PushW           reg_d
3049                 ADD1CYCLE
3050 .endm
3051 .macro          Op4B
3052                 PushBlow        reg_p_bank
3053                 ADD1CYCLE
3054 .endm
3055 .macro          Op08
3056                 PushB           rstatus
3057                 ADD1CYCLE
3058 .endm
3059 .macro          OpDAX1
3060                 PushB           reg_x
3061                 ADD1CYCLE
3062 .endm
3063 .macro          OpDAX0
3064                 PushW           reg_x
3065                 ADD1CYCLE
3066 .endm
3067 .macro          Op5AX1
3068                 PushB           reg_y
3069                 ADD1CYCLE
3070 .endm
3071 .macro          Op5AX0
3072                 PushW           reg_y
3073                 ADD1CYCLE
3074 .endm
3075 /**************************************************************************/
3076 /* PULL Instructions **************************************************** */
3077 .macro          Op68M1
3078                 PullBS          reg_a
3079                 UPDATE_ZN
3080                 ADD2CYCLE
3081 .endm
3082 .macro          Op68M0
3083                 PullWS          reg_a
3084                 UPDATE_ZN
3085                 ADD2CYCLE
3086 .endm
3087 .macro          OpAB
3088                 BIC             reg_d_bank,reg_d_bank, #0xFF
3089                 PullBrS
3090                 ORR             reg_d_bank,reg_d_bank,rscratch, LSR #24
3091                 UPDATE_ZN
3092                 ADD2CYCLE
3093 .endm
3094 .macro          Op2B
3095                 UXTH    reg_d,reg_d
3096                 PullWrS
3097                 ORR             reg_d,rscratch,reg_d
3098                 UPDATE_ZN
3099                 ADD2CYCLE
3100 .endm
3101 .macro          Op28X1M1        /*PLP*/
3102                 @ INDEX set, MEMORY set
3103                 BIC             rstatus,rstatus,#0xFF000000
3104                 PullBr
3105                 ORR             rstatus,rscratch,rstatus
3106                 TST             rstatus, #MASK_INDEX
3107                 @ INDEX clear & was set : 8->16
3108                 MOVEQ           reg_x,reg_x,LSR #8
3109                 MOVEQ           reg_y,reg_y,LSR #8
3110                 TST             rstatus, #MASK_MEM
3111                 @ MEMORY cleared & was set : 8->16
3112                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3113                 MOVEQ           reg_a,reg_a,LSR #8
3114                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3115                 S9xFixCycles
3116                 ADD2CYCLE
3117 .endm
3118 .macro          Op28X0M1        /*PLP*/
3119                 @ INDEX cleared, MEMORY set
3120                 BIC             rstatus,rstatus,#0xFF000000
3121                 PullBr
3122                 ORR             rstatus,rscratch,rstatus
3123                 TST             rstatus, #MASK_INDEX
3124                 @ INDEX set & was cleared : 16->8
3125                 MOVNE           reg_x,reg_x,LSL #8
3126                 MOVNE           reg_y,reg_y,LSL #8
3127                 TST             rstatus, #MASK_MEM
3128                 @ MEMORY cleared & was set : 8->16
3129                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3130                 MOVEQ           reg_a,reg_a,LSR #8
3131                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3132                 S9xFixCycles
3133                 ADD2CYCLE
3134 .endm
3135 .macro          Op28X1M0        /*PLP*/
3136                 @ INDEX set, MEMORY set
3137                 BIC             rstatus,rstatus,#0xFF000000
3138                 PullBr
3139                 ORR             rstatus,rscratch,rstatus
3140                 TST             rstatus, #MASK_INDEX
3141                 @ INDEX clear & was set : 8->16
3142                 MOVEQ           reg_x,reg_x,LSR #8
3143                 MOVEQ           reg_y,reg_y,LSR #8
3144                 TST             rstatus, #MASK_MEM
3145                 @ MEMORY set & was cleared : 16->8
3146                 MOVNE           rscratch,reg_a,LSR #24
3147                 MOVNE           reg_a,reg_a,LSL #8
3148                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3149                 S9xFixCycles
3150                 ADD2CYCLE
3151 .endm
3152 .macro          Op28X0M0        /*PLP*/
3153                 @ INDEX set, MEMORY set
3154                 BIC             rstatus,rstatus,#0xFF000000
3155                 PullBr
3156                 ORR             rstatus,rscratch,rstatus
3157                 TST             rstatus, #MASK_INDEX
3158                 @ INDEX set & was cleared : 16->8
3159                 MOVNE           reg_x,reg_x,LSL #8
3160                 MOVNE           reg_y,reg_y,LSL #8
3161                 TST             rstatus, #MASK_MEM
3162                 @ MEMORY set & was cleared : 16->8
3163                 MOVNE           rscratch,reg_a,LSR #24
3164                 MOVNE           reg_a,reg_a,LSL #8
3165                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3166                 S9xFixCycles
3167                 ADD2CYCLE
3168 .endm
3169 .macro          OpFAX1
3170                 PullBS          reg_x
3171                 UPDATE_ZN
3172                 ADD2CYCLE
3173 .endm
3174 .macro          OpFAX0
3175                 PullWS          reg_x
3176                 UPDATE_ZN
3177                 ADD2CYCLE
3178 .endm
3179 .macro          Op7AX1
3180                 PullBS          reg_y
3181                 UPDATE_ZN
3182                 ADD2CYCLE
3183 .endm
3184 .macro          Op7AX0
3185                 PullWS          reg_y
3186                 UPDATE_ZN
3187                 ADD2CYCLE
3188 .endm
3189
3190 /**********************************************************************************************/
3191 /* Transfer Instructions ********************************************************************* */
3192 .macro          OpAAX1M1 /*TAX8*/
3193                 MOVS            reg_x, reg_a
3194                 UPDATE_ZN
3195                 ADD1CYCLE
3196 .endm
3197 .macro          OpAAX0M1 /*TAX16*/
3198                 LDRB            reg_x, [reg_cpu_var,#RAH_ofs]
3199                 MOV             reg_x, reg_x,LSL #24
3200                 ORRS            reg_x, reg_x,reg_a, LSR #8
3201                 UPDATE_ZN
3202                 ADD1CYCLE
3203 .endm
3204 .macro          OpAAX1M0 /*TAX8*/
3205                 MOVS            reg_x, reg_a, LSL #8
3206                 UPDATE_ZN
3207                 ADD1CYCLE
3208 .endm
3209 .macro          OpAAX0M0 /*TAX16*/
3210                 MOVS            reg_x, reg_a
3211                 UPDATE_ZN
3212                 ADD1CYCLE
3213 .endm
3214 .macro          OpA8X1M1 /*TAY8*/
3215                 MOVS            reg_y, reg_a
3216                 UPDATE_ZN
3217                 ADD1CYCLE
3218 .endm
3219 .macro          OpA8X0M1 /*TAY16*/
3220                 LDRB            reg_y, [reg_cpu_var,#RAH_ofs]
3221                 MOV             reg_y, reg_y,LSL #24
3222                 ORRS            reg_y, reg_y,reg_a, LSR #8
3223                 UPDATE_ZN
3224                 ADD1CYCLE
3225 .endm
3226 .macro          OpA8X1M0 /*TAY8*/
3227                 MOVS            reg_y, reg_a, LSL #8
3228                 UPDATE_ZN
3229                 ADD1CYCLE
3230 .endm
3231 .macro          OpA8X0M0 /*TAY16*/
3232                 MOVS            reg_y, reg_a
3233                 UPDATE_ZN
3234                 ADD1CYCLE
3235 .endm
3236 .macro          Op5BM1
3237                 LDRB            rscratch, [reg_cpu_var,#RAH_ofs]
3238                 MOV             reg_d,reg_d,LSL #16
3239                 MOV             rscratch,rscratch,LSL #24
3240                 ORRS            rscratch,rscratch,reg_a, LSR #8
3241                 UPDATE_ZN
3242                 ORR             reg_d,rscratch,reg_d,LSR #16
3243                 ADD1CYCLE
3244 .endm
3245 .macro          Op5BM0
3246                 MOV             reg_d,reg_d,LSL #16
3247                 MOVS            reg_a,reg_a
3248                 UPDATE_ZN
3249                 ORR             reg_d,reg_a,reg_d,LSR #16
3250                 ADD1CYCLE
3251 .endm
3252 .macro          Op1BM1
3253                 TST             rstatus, #MASK_EMUL
3254                 MOVNE           reg_s, reg_a, LSR #24
3255                 ORRNE           reg_s, reg_s, #0x100
3256                 LDREQB          reg_s, [reg_cpu_var,#RAH_ofs]
3257                 ORREQ           reg_s, reg_s, reg_a
3258                 MOVEQ           reg_s, reg_s, ROR #24
3259                 ADD1CYCLE
3260 .endm
3261 .macro          Op1BM0
3262                 MOV             reg_s, reg_a, LSR #16
3263                 ADD1CYCLE
3264 .endm
3265 .macro          Op7BM1
3266                 MOVS            reg_a, reg_d, ASR #16
3267                 UPDATE_ZN
3268                 MOV             rscratch,reg_a,LSR #8
3269                 MOV             reg_a,reg_a, LSL #24
3270                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3271                 ADD1CYCLE
3272 .endm
3273 .macro          Op7BM0
3274                 MOVS            reg_a, reg_d, ASR #16
3275                 UPDATE_ZN
3276                 MOV             reg_a,reg_a, LSL #16
3277                 ADD1CYCLE
3278 .endm
3279 .macro          Op3BM1
3280                 MOV             rscratch,reg_s, LSR #8
3281                 MOVS            reg_a, reg_s, LSL #16
3282                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3283                 UPDATE_ZN
3284                 MOV             reg_a,reg_a, LSL #8
3285                 ADD1CYCLE
3286 .endm
3287 .macro          Op3BM0
3288                 MOVS            reg_a, reg_s, LSL #16
3289                 UPDATE_ZN
3290                 ADD1CYCLE
3291 .endm
3292 .macro          OpBAX1
3293                 MOVS            reg_x, reg_s, LSL #24
3294                 UPDATE_ZN
3295                 ADD1CYCLE
3296 .endm
3297 .macro          OpBAX0
3298                 MOVS            reg_x, reg_s, LSL #16
3299                 UPDATE_ZN
3300                 ADD1CYCLE
3301 .endm
3302 .macro          Op8AM1X1
3303                 MOVS            reg_a, reg_x
3304                 UPDATE_ZN
3305                 ADD1CYCLE
3306 .endm
3307 .macro          Op8AM1X0
3308                 MOVS            reg_a, reg_x, LSL #8
3309                 UPDATE_ZN
3310                 ADD1CYCLE
3311 .endm
3312 .macro          Op8AM0X1
3313                 MOVS            reg_a, reg_x, LSR #8
3314                 UPDATE_ZN
3315                 ADD1CYCLE
3316 .endm
3317 .macro          Op8AM0X0
3318                 MOVS            reg_a, reg_x
3319                 UPDATE_ZN
3320                 ADD1CYCLE
3321 .endm
3322 .macro          Op9AX1
3323                 MOV             reg_s, reg_x, LSR #24
3324                 TST             rstatus, #MASK_EMUL
3325                 ORRNE           reg_s, reg_s, #0x100
3326                 ADD1CYCLE
3327 .endm
3328 .macro          Op9AX0
3329                 MOV             reg_s, reg_x, LSR #16
3330                 ADD1CYCLE
3331 .endm
3332 .macro          Op9BX1
3333                 MOVS            reg_y, reg_x
3334                 UPDATE_ZN
3335                 ADD1CYCLE
3336 .endm
3337 .macro          Op9BX0
3338                 MOVS            reg_y, reg_x
3339                 UPDATE_ZN
3340                 ADD1CYCLE
3341 .endm
3342 .macro          Op98M1X1
3343                 MOVS            reg_a, reg_y
3344                 UPDATE_ZN
3345                 ADD1CYCLE
3346 .endm
3347 .macro          Op98M1X0
3348                 MOVS            reg_a, reg_y, LSL #8
3349                 UPDATE_ZN
3350                 ADD1CYCLE
3351 .endm
3352 .macro          Op98M0X1
3353                 MOVS            reg_a, reg_y, LSR #8
3354                 UPDATE_ZN
3355                 ADD1CYCLE
3356 .endm
3357 .macro          Op98M0X0
3358                 MOVS            reg_a, reg_y
3359                 UPDATE_ZN
3360                 ADD1CYCLE
3361 .endm
3362 .macro          OpBBX1
3363                 MOVS            reg_x, reg_y
3364                 UPDATE_ZN
3365                 ADD1CYCLE
3366 .endm
3367 .macro          OpBBX0
3368                 MOVS            reg_x, reg_y
3369                 UPDATE_ZN
3370                 ADD1CYCLE
3371 .endm
3372
3373 /**********************************************************************************************/
3374 /* XCE *************************************************************************************** */
3375
3376 .macro          OpFB
3377     TST         rstatus,#MASK_CARRY
3378     BEQ         1111f
3379     @ CARRY is set
3380     TST         rstatus,#MASK_EMUL
3381     BNE         1112f
3382     @ EMUL is cleared
3383     BIC         rstatus,rstatus,#(MASK_CARRY)
3384     TST         rstatus,#MASK_INDEX
3385     @ X & Y were 16bits before
3386     MOVEQ       reg_x,reg_x,LSL #8
3387     MOVEQ       reg_y,reg_y,LSL #8
3388     TST         rstatus,#MASK_MEM
3389     @ A was 16bits before
3390     @ save AH
3391     MOVEQ       rscratch,reg_a,LSR #24
3392     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3393     MOVEQ       reg_a,reg_a,LSL #8
3394     ORR         rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
3395     AND         reg_s,reg_s,#0xFF
3396     ORR         reg_s,reg_s,#0x100
3397     B           1113f
3398 1112:
3399     @ EMUL is set
3400     TST         rstatus,#MASK_INDEX
3401     @ X & Y were 16bits before
3402     MOVEQ       reg_x,reg_x,LSL #8
3403     MOVEQ       reg_y,reg_y,LSL #8
3404     TST         rstatus,#MASK_MEM
3405     @ A was 16bits before
3406     @ save AH
3407     MOVEQ       rscratch,reg_a,LSR #24
3408     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3409     MOVEQ       reg_a,reg_a,LSL #8
3410     ORR         rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
3411     AND         reg_s,reg_s,#0xFF
3412     ORR         reg_s,reg_s,#0x100
3413     B           1113f
3414 1111:
3415     @ CARRY is cleared
3416     TST         rstatus,#MASK_EMUL
3417     BEQ         1115f
3418     @ EMUL was set : X,Y & A were 8bits
3419     @ Now have to check MEMORY & INDEX for potential conversions to 16bits
3420     TST         rstatus,#MASK_INDEX
3421     @  X & Y are now 16bits
3422     MOVEQ       reg_x,reg_x,LSR #8
3423     MOVEQ       reg_y,reg_y,LSR #8
3424     TST         rstatus,#MASK_MEM
3425     @  A is now 16bits
3426     MOVEQ       reg_a,reg_a,LSR #8
3427     @ restore AH
3428     LDREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3429     ORREQ       reg_a,reg_a,rscratch,LSL #24
3430 1115:
3431     BIC         rstatus,rstatus,#(MASK_EMUL)
3432     ORR         rstatus,rstatus,#(MASK_CARRY)
3433 1113:
3434     ADD1CYCLE
3435     S9xFixCycles
3436 .endm
3437
3438 /*******************************************************************************/
3439 /* BRK *************************************************************************/
3440 .macro          Op00            /*BRK*/
3441                 MOV             rscratch,#1
3442                 STRB            rscratch,[reg_cpu_var,#BRKTriggered_ofs]
3443
3444                 TST             rstatus, #MASK_EMUL
3445                 @  EQ is flag to zero (!CheckEmu)
3446                 BNE             2001f@ elseOp00
3447                 PushBLow        reg_p_bank
3448                 SUB             rscratch, rpc, regpcbase
3449                 ADD             rscratch2, rscratch, #1
3450                 PushWLow        rscratch2
3451                 @  PackStatus
3452                 PushB           rstatus
3453                 ClearDecimal
3454                 SetIRQ
3455                 BIC             reg_p_bank, reg_p_bank, #0xFF
3456                 MOV             rscratch, #0xE6
3457                 ORR             rscratch, rscratch, #0xFF00
3458                 S9xGetWordLow
3459                 S9xSetPCBase
3460                 ADD2CYCLE
3461                 B               2002f@ endOp00
3462 2001:@ elseOp00
3463                 SUB             rscratch2, rpc, regpcbase
3464                 PushWLow        rscratch2
3465                 @  PackStatus
3466                 PushB           rstatus
3467                 ClearDecimal
3468                 SetIRQ
3469                 BIC             reg_p_bank,reg_p_bank, #0xFF
3470                 MOV             rscratch, #0xFE
3471                 ORR             rscratch, rscratch, #0xFF00
3472                 S9xGetWordLow
3473                 S9xSetPCBase
3474                 ADD1CYCLE
3475 2002:@ endOp00
3476 .endm
3477
3478
3479 /**********************************************************************************************/
3480 /* BRL ************************************************************************************** */
3481 .macro          Op82    /*BRL*/
3482                 asmRelativeLong
3483                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3484                 S9xSetPCBase
3485 .endm
3486 /**********************************************************************************************/
3487 /* IRQ *************************************************************************************** */
3488 @ void S9xOpcode_IRQ (void)
3489 .macro          S9xOpcode_IRQ   @ IRQ
3490                 TST             rstatus, #MASK_EMUL
3491                 @  EQ is flag to zero (!CheckEmu)
3492                 BNE             2121f@ elseOp02
3493                 PushBLow        reg_p_bank
3494                 SUB             rscratch2, rpc, regpcbase
3495                 PushWLow        rscratch2
3496                 @  PackStatus
3497                 PushB           rstatus
3498                 ClearDecimal
3499                 SetIRQ
3500                 BIC             reg_p_bank, reg_p_bank,#0xFF
3501                 MOV             rscratch, #0xEE
3502                 ORR             rscratch, rscratch, #0xFF00
3503                 S9xGetWordLow
3504                 S9xSetPCBase
3505                 ADD2CYCLE
3506                 B 2122f
3507 2121:@ else
3508                 SUB             rscratch2, rpc, regpcbase
3509                 PushWLow        rscratch2
3510                 @  PackStatus
3511                 PushB           rstatus
3512                 ClearDecimal
3513                 SetIRQ
3514                 BIC             reg_p_bank,reg_p_bank, #0xFF
3515                 MOV             rscratch, #0xFE
3516                 ORR             rscratch, rscratch, #0xFF00
3517                 S9xGetWordLow
3518                 S9xSetPCBase
3519                 ADD1CYCLE
3520 2122:
3521 .endm
3522
3523 /*
3524 void asm_S9xOpcode_IRQ(void)
3525 {
3526     if (!CheckEmulation())
3527     {
3528         PushB (Registers.PB);
3529         PushW (CPU.PC - CPU.PCBase);
3530         PushB (Registers.PL);
3531         ClearDecimal ();
3532         SetIRQ ();
3533
3534         Registers.PB = 0;
3535                 S9xSetPCBase (S9xGetWord (0xFFEE));
3536         CPU.Cycles += TWO_CYCLES;
3537     }
3538     else
3539     {
3540         PushW (CPU.PC - CPU.PCBase);
3541         PushB (Registers.PL);
3542         ClearDecimal ();
3543         SetIRQ ();
3544
3545         Registers.PB = 0;
3546         S9xSetPCBase (S9xGetWord (0xFFFE));
3547         CPU.Cycles += ONE_CYCLE;
3548     }
3549 }
3550 */
3551
3552 /**********************************************************************************************/
3553 /* NMI *************************************************************************************** */
3554 @ void S9xOpcode_NMI (void)
3555 .macro          S9xOpcode_NMI   @ NMI
3556                 TST             rstatus, #MASK_EMUL
3557                 @  EQ is flag to zero (!CheckEmu)
3558                 BNE             2123f@ elseOp02
3559                 PushBLow        reg_p_bank
3560                 SUB             rscratch2, rpc, regpcbase
3561                 PushWLow        rscratch2
3562                 @  PackStatus
3563                 PushB           rstatus
3564                 ClearDecimal
3565                 SetIRQ
3566                 BIC             reg_p_bank, reg_p_bank,#0xFF
3567                 MOV             rscratch, #0xEA
3568                 ORR             rscratch, rscratch, #0xFF00
3569                 S9xGetWordLow
3570                 S9xSetPCBase
3571                 ADD2CYCLE
3572                 B 2124f
3573 2123:@ else
3574                 SUB             rscratch2, rpc, regpcbase
3575                 PushWLow        rscratch2
3576                 @  PackStatus
3577                 PushB           rstatus
3578                 ClearDecimal
3579                 SetIRQ
3580                 BIC             reg_p_bank,reg_p_bank, #0xFF
3581                 MOV             rscratch, #0xFA
3582                 ORR             rscratch, rscratch, #0xFF00
3583                 S9xGetWordLow
3584                 S9xSetPCBase
3585                 ADD1CYCLE
3586 2124:
3587 .endm
3588 /*
3589 void asm_S9xOpcode_NMI(void)
3590 {
3591         if (!CheckEmulation())
3592     {
3593         PushB (Registers.PB);
3594         PushW (CPU.PC - CPU.PCBase);
3595         PushB (Registers.PL);
3596         ClearDecimal ();
3597         SetIRQ ();
3598
3599         Registers.PB = 0;
3600         S9xSetPCBase (S9xGetWord (0xFFEA));
3601         CPU.Cycles += TWO_CYCLES;
3602     }
3603     else
3604     {
3605         PushW (CPU.PC - CPU.PCBase);
3606         PushB (Registers.PL);
3607         ClearDecimal ();
3608         SetIRQ ();
3609
3610         Registers.PB = 0;
3611         S9xSetPCBase (S9xGetWord (0xFFFA));
3612         CPU.Cycles += ONE_CYCLE;
3613     }
3614 }
3615 */
3616
3617 /**********************************************************************************************/
3618 /* COP *************************************************************************************** */
3619 .macro          Op02            /*COP*/
3620                 TST             rstatus, #MASK_EMUL
3621                 @  EQ is flag to zero (!CheckEmu)
3622                 BNE             2021f@ elseOp02
3623                 PushBLow        reg_p_bank
3624                 SUB             rscratch, rpc, regpcbase
3625                 ADD             rscratch2, rscratch, #1
3626                 PushWLow        rscratch2
3627                 @  PackStatus
3628                 PushB           rstatus
3629                 ClearDecimal
3630                 SetIRQ
3631                 BIC             reg_p_bank, reg_p_bank,#0xFF
3632                 MOV             rscratch, #0xE4
3633                 ORR             rscratch, rscratch, #0xFF00
3634                 S9xGetWordLow
3635                 S9xSetPCBase
3636                 ADD2CYCLE
3637                 B 2022f@ endOp02
3638 2021:@ elseOp02
3639                 SUB             rscratch2, rpc, regpcbase
3640                 PushWLow        rscratch2
3641                 @  PackStatus
3642                 PushB           rstatus
3643                 ClearDecimal
3644                 SetIRQ
3645                 BIC             reg_p_bank,reg_p_bank, #0xFF
3646                 MOV             rscratch, #0xF4
3647                 ORR             rscratch, rscratch, #0xFF00
3648                 S9xGetWordLow
3649                 S9xSetPCBase
3650                 ADD1CYCLE
3651 2022:@ endOp02
3652 .endm
3653
3654 /**********************************************************************************************/
3655 /* JML *************************************************************************************** */
3656 .macro          OpDC
3657                 AbsoluteIndirectLong
3658                 BIC             reg_p_bank,reg_p_bank,#0xFF
3659                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3660                 S9xSetPCBase
3661                 ADD2CYCLE
3662 .endm
3663 .macro          Op5C
3664                 AbsoluteLong
3665                 BIC             reg_p_bank,reg_p_bank,#0xFF
3666                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3667                 S9xSetPCBase
3668 .endm
3669
3670 /**********************************************************************************************/
3671 /* JMP *************************************************************************************** */
3672 .macro          Op4C
3673                 Absolute
3674                 BIC             rscratch, rscratch, #0xFF0000
3675                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3676                 S9xSetPCBase
3677                 CPUShutdown
3678 .endm
3679 .macro          Op6C
3680                 AbsoluteIndirect
3681                 BIC             rscratch, rscratch, #0xFF0000
3682                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3683                 S9xSetPCBase
3684 .endm
3685 .macro          Op7C
3686                 ADD             rscratch, rscratch, reg_p_bank, LSL #16
3687                 S9xSetPCBase
3688                 ADD1CYCLE
3689 .endm
3690
3691 /**********************************************************************************************/
3692 /* JSL/RTL *********************************************************************************** */
3693 .macro          Op22
3694                 PushBlow        reg_p_bank
3695                 SUB             rscratch, rpc, regpcbase
3696                 @ SUB           rscratch2, rscratch2, #1
3697                 ADD             rscratch2, rscratch, #2
3698                 PushWlow        rscratch2
3699                 AbsoluteLong
3700                 BIC             reg_p_bank,reg_p_bank,#0xFF
3701                 ORR             reg_p_bank, reg_p_bank, rscratch, LSR #16
3702                 S9xSetPCBase
3703 .endm
3704 .macro          Op6B
3705                 PullWLow        rpc
3706                 BIC             reg_p_bank,reg_p_bank,#0xFF
3707                 PullBrLow
3708                 ORR             reg_p_bank, reg_p_bank, rscratch
3709                 ADD             rscratch, rpc, #1
3710                 BIC             rscratch, rscratch,#0xFF0000
3711                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3712                 S9xSetPCBase
3713                 ADD2CYCLE
3714 .endm
3715 /**********************************************************************************************/
3716 /* JSR/RTS *********************************************************************************** */
3717 .macro          Op20
3718                 SUB             rscratch, rpc, regpcbase
3719                 @ SUB           rscratch2, rscratch2, #1
3720                 ADD             rscratch2, rscratch, #1
3721                 PushWlow        rscratch2
3722                 Absolute
3723                 BIC             rscratch, rscratch, #0xFF0000
3724                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3725                 S9xSetPCBase
3726                 ADD1CYCLE
3727 .endm
3728 .macro          OpFCX0
3729                 SUB             rscratch, rpc, regpcbase
3730                 @ SUB           rscratch2, rscratch2, #1
3731                 ADD             rscratch2, rscratch, #1
3732                 PushWlow        rscratch2
3733                 AbsoluteIndexedIndirectX0
3734                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3735                 S9xSetPCBase
3736                 ADD1CYCLE
3737 .endm
3738 .macro          OpFCX1
3739                 SUB             rscratch, rpc, regpcbase
3740                 @ SUB           rscratch2, rscratch2, #1
3741                 ADD             rscratch2, rscratch, #1
3742                 PushWlow        rscratch2
3743                 AbsoluteIndexedIndirectX1
3744                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3745                 S9xSetPCBase
3746                 ADD1CYCLE
3747 .endm
3748 .macro          Op60
3749                 PullWLow        rpc
3750                 ADD             rscratch, rpc, #1
3751                 BIC             rscratch, rscratch,#0x10000
3752                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3753                 S9xSetPCBase
3754                 ADD3CYCLE
3755 .endm
3756
3757 /**********************************************************************************************/
3758 /* MVN/MVP *********************************************************************************** */
3759 .macro          Op54X1M1
3760                 @ Save RegStatus = reg_d_bank >> 24
3761                 MOV             rscratch, reg_d_bank, LSR #16
3762                 LDRB            reg_d_bank    , [rpc], #1
3763                 LDRB            rscratch2    , [rpc], #1
3764                 @ Restore RegStatus = reg_d_bank >> 24
3765                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3766                 MOV             rscratch    , reg_x, LSR #24
3767                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3768                 S9xGetByteLow
3769                 MOV             rscratch2, rscratch
3770                 MOV             rscratch   , reg_y, LSR #24
3771                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3772                 S9xSetByteLow   rscratch2
3773                 @ load 16bits A
3774                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3775                 MOV             reg_a,reg_a,LSR #8
3776                 ORR             reg_a,reg_a,rscratch, LSL #24
3777                 ADD             reg_x, reg_x, #0x01000000
3778                 SUB             reg_a, reg_a, #0x00010000
3779                 ADD             reg_y, reg_y, #0x01000000
3780                 CMP             reg_a, #0xFFFF0000
3781                 SUBNE           rpc, rpc, #3
3782                 @ update AH
3783                 MOV             rscratch, reg_a, LSR #24
3784                 MOV             reg_a,reg_a,LSL #8
3785                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3786                 ADD2CYCLE2MEM
3787 .endm
3788 .macro          Op54X1M0
3789                 @ Save RegStatus = reg_d_bank >> 24
3790                 MOV             rscratch, reg_d_bank, LSR #16
3791                 LDRB            reg_d_bank    , [rpc], #1
3792                 LDRB            rscratch2    , [rpc], #1
3793                 @ Restore RegStatus = reg_d_bank >> 24
3794                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3795                 MOV             rscratch    , reg_x, LSR #24
3796                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3797                 S9xGetByteLow
3798                 MOV             rscratch2, rscratch
3799                 MOV             rscratch   , reg_y, LSR #24
3800                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3801                 S9xSetByteLow   rscratch2
3802                 ADD             reg_x, reg_x, #0x01000000
3803                 SUB             reg_a, reg_a, #0x00010000
3804                 ADD             reg_y, reg_y, #0x01000000
3805                 CMP             reg_a, #0xFFFF0000
3806                 SUBNE           rpc, rpc, #3
3807                 ADD2CYCLE2MEM
3808 .endm
3809 .macro          Op54X0M1
3810                 @ Save RegStatus = reg_d_bank >> 24
3811                 MOV             rscratch, reg_d_bank, LSR #16
3812                 LDRB            reg_d_bank    , [rpc], #1
3813                 LDRB            rscratch2    , [rpc], #1
3814                 @ Restore RegStatus = reg_d_bank >> 24
3815                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3816                 MOV             rscratch    , reg_x, LSR #16
3817                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3818                 S9xGetByteLow
3819                 MOV             rscratch2, rscratch
3820                 MOV             rscratch   , reg_y, LSR #16
3821                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3822                 S9xSetByteLow   rscratch2
3823                 @ load 16bits A
3824                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3825                 MOV             reg_a,reg_a,LSR #8
3826                 ORR             reg_a,reg_a,rscratch, LSL #24
3827                 ADD             reg_x, reg_x, #0x00010000
3828                 SUB             reg_a, reg_a, #0x00010000
3829                 ADD             reg_y, reg_y, #0x00010000
3830                 CMP             reg_a, #0xFFFF0000
3831                 SUBNE           rpc, rpc, #3
3832                 @ update AH
3833                 MOV             rscratch, reg_a, LSR #24
3834                 MOV             reg_a,reg_a,LSL #8
3835                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3836                 ADD2CYCLE2MEM
3837 .endm
3838 .macro          Op54X0M0
3839                 @ Save RegStatus = reg_d_bank >> 24
3840                 MOV             rscratch, reg_d_bank, LSR #16
3841                 LDRB            reg_d_bank    , [rpc], #1
3842                 LDRB            rscratch2    , [rpc], #1
3843                 @ Restore RegStatus = reg_d_bank >> 24
3844                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3845                 MOV             rscratch    , reg_x, LSR #16
3846                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3847                 S9xGetByteLow
3848                 MOV             rscratch2, rscratch
3849                 MOV             rscratch   , reg_y, LSR #16
3850                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3851                 S9xSetByteLow   rscratch2
3852                 ADD             reg_x, reg_x, #0x00010000
3853                 SUB             reg_a, reg_a, #0x00010000
3854                 ADD             reg_y, reg_y, #0x00010000
3855                 CMP             reg_a, #0xFFFF0000
3856                 SUBNE           rpc, rpc, #3
3857                 ADD2CYCLE2MEM
3858 .endm
3859
3860 .macro          Op44X1M1
3861                 @ Save RegStatus = reg_d_bank >> 24
3862                 MOV             rscratch, reg_d_bank, LSR #16
3863                 LDRB            reg_d_bank    , [rpc], #1
3864                 LDRB            rscratch2    , [rpc], #1
3865                 @ Restore RegStatus = reg_d_bank >> 24
3866                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3867                 MOV             rscratch    , reg_x, LSR #24
3868                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3869                 S9xGetByteLow
3870                 MOV             rscratch2, rscratch
3871                 MOV             rscratch   , reg_y, LSR #24
3872                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3873                 S9xSetByteLow   rscratch2
3874                 @ load 16bits A
3875                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3876                 MOV             reg_a,reg_a,LSR #8
3877                 ORR             reg_a,reg_a,rscratch, LSL #24
3878                 SUB             reg_x, reg_x, #0x01000000
3879                 SUB             reg_a, reg_a, #0x00010000
3880                 SUB             reg_y, reg_y, #0x01000000
3881                 CMP             reg_a, #0xFFFF0000
3882                 SUBNE           rpc, rpc, #3
3883                 @ update AH
3884                 MOV             rscratch, reg_a, LSR #24
3885                 MOV             reg_a,reg_a,LSL #8
3886                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3887                 ADD2CYCLE2MEM
3888 .endm
3889 .macro          Op44X1M0
3890                 @ Save RegStatus = reg_d_bank >> 24
3891                 MOV             rscratch, reg_d_bank, LSR #16
3892                 LDRB            reg_d_bank    , [rpc], #1
3893                 LDRB            rscratch2    , [rpc], #1
3894                 @ Restore RegStatus = reg_d_bank >> 24
3895                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3896                 MOV             rscratch    , reg_x, LSR #24
3897                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3898                 S9xGetByteLow
3899                 MOV             rscratch2, rscratch
3900                 MOV             rscratch   , reg_y, LSR #24
3901                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3902                 S9xSetByteLow   rscratch2
3903                 SUB             reg_x, reg_x, #0x01000000
3904                 SUB             reg_a, reg_a, #0x00010000
3905                 SUB             reg_y, reg_y, #0x01000000
3906                 CMP             reg_a, #0xFFFF0000
3907                 SUBNE           rpc, rpc, #3
3908                 ADD2CYCLE2MEM
3909 .endm
3910 .macro          Op44X0M1
3911                 @ Save RegStatus = reg_d_bank >> 24
3912                 MOV             rscratch, reg_d_bank, LSR #16
3913                 LDRB            reg_d_bank    , [rpc], #1
3914                 LDRB            rscratch2    , [rpc], #1
3915                 @ Restore RegStatus = reg_d_bank >> 24
3916                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3917                 MOV             rscratch    , reg_x, LSR #16
3918                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3919                 S9xGetByteLow
3920                 MOV             rscratch2, rscratch
3921                 MOV             rscratch   , reg_y, LSR #16
3922                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3923                 S9xSetByteLow   rscratch2
3924                 @ load 16bits A
3925                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3926                 MOV             reg_a,reg_a,LSR #8
3927                 ORR             reg_a,reg_a,rscratch, LSL #24
3928                 SUB             reg_x, reg_x, #0x00010000
3929                 SUB             reg_a, reg_a, #0x00010000
3930                 SUB             reg_y, reg_y, #0x00010000
3931                 CMP             reg_a, #0xFFFF0000
3932                 SUBNE           rpc, rpc, #3
3933                 @ update AH
3934                 MOV             rscratch, reg_a, LSR #24
3935                 MOV             reg_a,reg_a,LSL #8
3936                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3937                 ADD2CYCLE2MEM
3938 .endm
3939 .macro          Op44X0M0
3940                 @ Save RegStatus = reg_d_bank >> 24
3941                 MOV             rscratch, reg_d_bank, LSR #16
3942                 LDRB            reg_d_bank    , [rpc], #1
3943                 LDRB            rscratch2    , [rpc], #1
3944                 @ Restore RegStatus = reg_d_bank >> 24
3945                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3946                 MOV             rscratch    , reg_x, LSR #16
3947                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3948                 S9xGetByteLow
3949                 MOV             rscratch2, rscratch
3950                 MOV             rscratch   , reg_y, LSR #16
3951                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3952                 S9xSetByteLow   rscratch2
3953                 SUB             reg_x, reg_x, #0x00010000
3954                 SUB             reg_a, reg_a, #0x00010000
3955                 SUB             reg_y, reg_y, #0x00010000
3956                 CMP             reg_a, #0xFFFF0000
3957                 SUBNE           rpc, rpc, #3
3958                 ADD2CYCLE2MEM
3959 .endm
3960
3961 /**********************************************************************************************/
3962 /* REP/SEP *********************************************************************************** */
3963 .macro          OpC2
3964                 @  status&=~(*rpc++);
3965                 @  so possible changes are :
3966                 @  INDEX = 1 -> 0  : X,Y 8bits -> 16bits
3967                 @  MEM = 1 -> 0 : A 8bits -> 16bits
3968                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
3969                 MOV             rscratch3, rstatus
3970                 LDRB            rscratch, [rpc], #1
3971                 MVN             rscratch, rscratch
3972                 AND             rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
3973                 TST             rstatus,#MASK_EMUL
3974                 BEQ             1111f
3975                 @ emulation mode on : no changes since it was on before opcode
3976                 @ just be sure to reset MEM & INDEX accordingly
3977                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
3978                 B               1112f
3979 1111:
3980                 @ NOT in Emulation mode, check INDEX & MEMORY bits
3981                 @ Now check INDEX
3982                 TST             rscratch3,#MASK_INDEX
3983                 BEQ             1113f
3984                 @  X & Y were 8bit before
3985                 TST             rstatus,#MASK_INDEX
3986                 BNE             1113f
3987                 @  X & Y are now 16bits
3988                 MOV             reg_x,reg_x,LSR #8
3989                 MOV             reg_y,reg_y,LSR #8
3990 1113:           @ X & Y still in 16bits
3991                 @ Now check MEMORY
3992                 TST             rscratch3,#MASK_MEM
3993                 BEQ             1112f
3994                 @  A was 8bit before
3995                 TST             rstatus,#MASK_MEM
3996                 BNE             1112f
3997                 @  A is now 16bits
3998                 MOV             reg_a,reg_a,LSR #8
3999                 @ restore AH
4000                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4001                 ORREQ           reg_a,reg_a,rscratch,LSL #24
4002 1112:
4003                 S9xFixCycles
4004                 ADD1CYCLE1MEM
4005 .endm
4006 .macro          OpE2
4007                 @  status|=*rpc++;
4008                 @  so possible changes are :
4009                 @  INDEX = 0 -> 1  : X,Y 16bits -> 8bits
4010                 @  MEM = 0 -> 1 : A 16bits -> 8bits
4011                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
4012                 MOV             rscratch3, rstatus
4013                 LDRB            rscratch, [rpc], #1
4014                 ORR             rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
4015                 TST             rstatus,#MASK_EMUL
4016                 BEQ             10111f
4017                 @ emulation mode on : no changes sinc eit was on before opcode
4018                 @ just be sure to have mem & index set accordingly
4019                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
4020                 B               10112f
4021 10111:
4022                 @ NOT in Emulation mode, check INDEX & MEMORY bits
4023                 @ Now check INDEX
4024                 TST             rscratch3,#MASK_INDEX
4025                 BNE             10113f
4026                 @  X & Y were 16bit before
4027                 TST             rstatus,#MASK_INDEX
4028                 BEQ             10113f
4029                 @  X & Y are now 8bits
4030                 MOV             reg_x,reg_x,LSL #8
4031                 MOV             reg_y,reg_y,LSL #8
4032 10113:          @ X & Y still in 16bits
4033                 @ Now check MEMORY
4034                 TST             rscratch3,#MASK_MEM
4035                 BNE             10112f
4036                 @  A was 16bit before
4037                 TST             rstatus,#MASK_MEM
4038                 BEQ             10112f
4039                 @  A is now 8bits
4040                 @  save AH
4041                 MOV             rscratch,reg_a,LSR #24
4042                 MOV             reg_a,reg_a,LSL #8
4043                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
4044 10112:
4045                 S9xFixCycles
4046                 ADD1CYCLE1MEM
4047 .endm
4048
4049 /**********************************************************************************************/
4050 /* XBA *************************************************************************************** */
4051 .macro          OpEBM1
4052                 @ A is 8bits
4053                 ADD             rscratch,reg_cpu_var,#RAH_ofs
4054                 MOV             reg_a,reg_a, LSR #24
4055                 SWPB            reg_a,reg_a,[rscratch]
4056                 MOVS            reg_a,reg_a, LSL #24
4057                 UPDATE_ZN
4058                 ADD2CYCLE
4059 .endm
4060 .macro          OpEBM0
4061                 @ A is 16bits
4062                 MOV             rscratch, reg_a, ROR #24 @  ll0000hh
4063                 ORR             rscratch, rscratch, reg_a, LSR #8@  ll0000hh + 00hhll00 -> llhhllhh
4064                 MOV             reg_a, rscratch, LSL #16@  llhhllhh -> llhh0000
4065                 MOVS            rscratch,rscratch,LSL #24 @ to set Z & N flags with AL
4066                 UPDATE_ZN
4067                 ADD2CYCLE
4068 .endm
4069
4070
4071 /**********************************************************************************************/
4072 /* RTI *************************************************************************************** */
4073 .macro          Op40X1M1
4074                 @ INDEX set, MEMORY set
4075                 BIC             rstatus,rstatus,#0xFF000000
4076                 PullBr
4077                 ORR             rstatus,rscratch,rstatus
4078                 PullWlow        rpc
4079                 TST             rstatus, #MASK_EMUL
4080                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4081                 BNE             2401f
4082                 PullBrLow
4083                 BIC             reg_p_bank,reg_p_bank,#0xFF
4084                 ORR             reg_p_bank,reg_p_bank,rscratch
4085 2401:
4086                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4087                 S9xSetPCBase
4088                 TST             rstatus, #MASK_INDEX
4089                 @ INDEX cleared & was set : 8->16
4090                 MOVEQ           reg_x,reg_x,LSR #8
4091                 MOVEQ           reg_y,reg_y,LSR #8
4092                 TST             rstatus, #MASK_MEM
4093                 @ MEMORY cleared & was set : 8->16
4094                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4095                 MOVEQ           reg_a,reg_a,LSR #8
4096                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4097                 ADD2CYCLE
4098                 S9xFixCycles
4099 .endm
4100 .macro          Op40X0M1
4101                 @ INDEX cleared, MEMORY set
4102                 BIC             rstatus,rstatus,#0xFF000000
4103                 PullBr
4104                 ORR             rstatus,rscratch,rstatus
4105                 PullWlow        rpc
4106                 TST             rstatus, #MASK_EMUL
4107                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4108                 BNE             2401f
4109                 PullBrLow
4110                 BIC             reg_p_bank,reg_p_bank,#0xFF
4111                 ORR             reg_p_bank,reg_p_bank,rscratch
4112 2401:
4113                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4114                 S9xSetPCBase
4115                 TST             rstatus, #MASK_INDEX
4116                 @ INDEX set & was cleared : 16->8
4117                 MOVNE           reg_x,reg_x,LSL #8
4118                 MOVNE           reg_y,reg_y,LSL #8
4119                 TST             rstatus, #MASK_MEM
4120                 @ MEMORY cleared & was set : 8->16
4121                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4122                 MOVEQ           reg_a,reg_a,LSR #8
4123                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4124                 ADD2CYCLE
4125                 S9xFixCycles
4126 .endm
4127 .macro          Op40X1M0
4128                 @ INDEX set, MEMORY cleared
4129                 BIC             rstatus,rstatus,#0xFF000000
4130                 PullBr
4131                 ORR             rstatus,rscratch,rstatus
4132                 PullWlow        rpc
4133                 TST             rstatus, #MASK_EMUL
4134                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4135                 BNE             2401f
4136                 PullBrLow
4137                 BIC             reg_p_bank,reg_p_bank,#0xFF
4138                 ORR             reg_p_bank,reg_p_bank,rscratch
4139 2401:
4140                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4141                 S9xSetPCBase
4142                 TST             rstatus, #MASK_INDEX
4143                 @ INDEX cleared & was set : 8->16
4144                 MOVEQ           reg_x,reg_x,LSR #8
4145                 MOVEQ           reg_y,reg_y,LSR #8
4146                 TST             rstatus, #MASK_MEM
4147                 @ MEMORY set & was cleared : 16->8
4148                 MOVNE           rscratch,reg_a,LSR #24
4149                 MOVNE           reg_a,reg_a,LSL #8
4150                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4151                 ADD2CYCLE
4152                 S9xFixCycles
4153 .endm
4154 .macro          Op40X0M0
4155                 @ INDEX cleared, MEMORY cleared
4156                 BIC             rstatus,rstatus,#0xFF000000
4157                 PullBr
4158                 ORR             rstatus,rscratch,rstatus
4159                 PullWlow        rpc
4160                 TST             rstatus, #MASK_EMUL
4161                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4162                 BNE             2401f
4163                 PullBrLow
4164                 BIC             reg_p_bank,reg_p_bank,#0xFF
4165                 ORR             reg_p_bank,reg_p_bank,rscratch
4166 2401:
4167                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4168                 S9xSetPCBase
4169                 TST             rstatus, #MASK_INDEX
4170                 @ INDEX set & was cleared : 16->8
4171                 MOVNE           reg_x,reg_x,LSL #8
4172                 MOVNE           reg_y,reg_y,LSL #8
4173                 TST             rstatus, #MASK_MEM
4174                 @ MEMORY set & was cleared : 16->8
4175                 @ MEMORY set & was cleared : 16->8
4176                 MOVNE           rscratch,reg_a,LSR #24
4177                 MOVNE           reg_a,reg_a,LSL #8
4178                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4179                 ADD2CYCLE
4180                 S9xFixCycles
4181 .endm
4182
4183
4184 /**********************************************************************************************/
4185 /* STP/WAI/DB ******************************************************************************** */
4186 @  WAI
4187 .macro          OpCB    /*WAI*/
4188         LDRB            rscratch,[reg_cpu_var,#IRQActive_ofs]
4189         MOVS            rscratch,rscratch
4190         @ (CPU.IRQActive)
4191         ADD2CYCLENE
4192         BNE             1234f
4193 /*
4194         CPU.WaitingForInterrupt = TRUE;
4195         CPU.PC--;
4196 */
4197         MOV             rscratch,#1
4198         SUB             rpc,rpc,#1
4199 /*
4200             CPU.Cycles = CPU.NextEvent;
4201 */
4202         STRB            rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs]
4203         LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
4204 /*
4205         if (IAPU.APUExecuting)
4206             {
4207                 ICPU.CPUExecuting = FALSE;
4208                 do
4209                 {
4210                     APU_EXECUTE1 ();
4211                 } while (APU.Cycles < CPU.NextEvent);
4212                 ICPU.CPUExecuting = TRUE;
4213             }
4214 */
4215         LDRB            rscratch,[reg_cpu_var,#APUExecuting_ofs]
4216         MOVS            rscratch,rscratch
4217         BEQ             1234f
4218         asmAPU_EXECUTE2
4219
4220 1234:
4221 .endm
4222 .macro          OpDB    /*STP*/
4223                 SUB     rpc,rpc,#1
4224                 @ CPU.Flags |= DEBUG_MODE_FLAG;
4225 .endm
4226 .macro          Op42   /*Reserved Snes9X: SNESAdvance SpeedHack */
4227 @ Explanation: this is a reserved opcode turned into special "idle"/hlt opcode.
4228 @ This means we should do an hblank now.
4229 /*-
4230         CPU.Cycles = CPU.NextEvent;
4231 */      ldr reg_cycles, [reg_cpu_var,#NextEvent_ofs]
4232 @ Now execute the shadowed branch
4233 @ Equivalent to "asmRelative":
4234         ADD1MEM
4235         ldrb rscratch, [rpc], #1
4236         and rscratch2, rscratch, #0xf0  @branch type
4237         orr rscratch, rscratch, #0xf0   @branch dest (always negative, so sign ext)
4238         sxtb rscratch, rscratch
4239         add rscratch, rscratch, rpc
4240         sub rscratch, rscratch, regpcbase
4241         uxth rscratch, rscratch
4242 @ TODO: Do something with rscratch2 before BranchCheck clobbers it.
4243 @ Currently hardcoded to BEQ
4244         BranchCheck2
4245                 TST             rstatus, #MASK_ZERO
4246                 BEQ             1111f
4247                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
4248                 ADD1CYCLE
4249                 CPUShutdown
4250 .endm
4251
4252 /**********************************************************************************************/
4253 /* AND ******************************************************************************** */
4254 .macro          Op29M1
4255                 LDRB    rscratch    , [rpc], #1
4256                 ANDS    reg_a    , reg_a,       rscratch, LSL #24
4257                 UPDATE_ZN
4258                 ADD1MEM
4259 .endm
4260 .macro          Op29M0
4261                 LDRB    rscratch2  , [rpc,#1]
4262                 LDRB    rscratch   , [rpc], #2
4263                 ORR     rscratch, rscratch, rscratch2, LSL #8
4264                 ANDS    reg_a    , reg_a,       rscratch, LSL #16
4265                 UPDATE_ZN
4266                 ADD2MEM
4267 .endm
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283 /**********************************************************************************************/
4284 /* EOR ******************************************************************************** */
4285 .macro          Op49M0
4286                 LDRB    rscratch2 , [rpc, #1]
4287                 LDRB    rscratch , [rpc], #2
4288                 ORR     rscratch, rscratch, rscratch2,LSL #8
4289                 EORS    reg_a, reg_a, rscratch,LSL #16
4290                 UPDATE_ZN
4291                 ADD2MEM
4292 .endm
4293
4294
4295 .macro          Op49M1
4296                 LDRB    rscratch , [rpc], #1
4297                 EORS    reg_a, reg_a, rscratch,LSL #24
4298                 UPDATE_ZN
4299                 ADD1MEM
4300 .endm
4301
4302
4303 /**********************************************************************************************/
4304 /* STA *************************************************************************************** */
4305 .macro          Op81M1
4306                 STA8
4307                 @ TST           rstatus, #MASK_INDEX
4308                 @ ADD1CYCLENE
4309 .endm
4310 .macro          Op81M0
4311                 STA16
4312                 @ TST rstatus, #MASK_INDEX
4313                 @ ADD1CYCLENE
4314 .endm
4315
4316
4317 /**********************************************************************************************/
4318 /* BIT *************************************************************************************** */
4319 .macro          Op89M1
4320                 LDRB    rscratch , [rpc], #1
4321                 TST     reg_a, rscratch, LSL #24
4322                 UPDATE_Z
4323                 ADD1MEM
4324 .endm
4325 .macro          Op89M0
4326                 LDRB    rscratch2 , [rpc, #1]
4327                 LDRB    rscratch , [rpc], #2
4328                 ORR     rscratch, rscratch, rscratch2, LSL #8
4329                 TST     reg_a, rscratch, LSL #16
4330                 UPDATE_Z
4331                 ADD2MEM
4332 .endm
4333
4334
4335
4336
4337
4338
4339 /**********************************************************************************************/
4340 /* LDY *************************************************************************************** */
4341 .macro          OpA0X1
4342                 LDRB    rscratch , [rpc], #1
4343                 MOVS    reg_y, rscratch, LSL #24
4344                 UPDATE_ZN
4345                 ADD1MEM
4346 .endm
4347 .macro          OpA0X0
4348                 LDRB    rscratch2 , [rpc, #1]
4349                 LDRB    rscratch , [rpc], #2
4350                 ORR     rscratch, rscratch, rscratch2, LSL #8
4351                 MOVS    reg_y, rscratch, LSL #16
4352                 UPDATE_ZN
4353                 ADD2MEM
4354 .endm
4355
4356 /**********************************************************************************************/
4357 /* LDX *************************************************************************************** */
4358 .macro          OpA2X1
4359                 LDRB    rscratch , [rpc], #1
4360                 MOVS    reg_x, rscratch, LSL #24
4361                 UPDATE_ZN
4362                 ADD1MEM
4363 .endm
4364 .macro          OpA2X0
4365                 LDRB    rscratch2 , [rpc, #1]
4366                 LDRB    rscratch , [rpc], #2
4367                 ORR     rscratch, rscratch, rscratch2, LSL #8
4368                 MOVS    reg_x, rscratch, LSL #16
4369                 UPDATE_ZN
4370                 ADD2MEM
4371 .endm
4372
4373 /**********************************************************************************************/
4374 /* LDA *************************************************************************************** */
4375 .macro          OpA9M1
4376                 LDRB    rscratch , [rpc], #1
4377                 MOVS    reg_a, rscratch, LSL #24
4378                 UPDATE_ZN
4379                 ADD1MEM
4380 .endm
4381 .macro          OpA9M0
4382                 LDRB    rscratch2 , [rpc, #1]
4383                 LDRB    rscratch , [rpc], #2
4384                 ORR     rscratch, rscratch, rscratch2, LSL #8
4385                 MOVS    reg_a, rscratch, LSL #16
4386                 UPDATE_ZN
4387                 ADD2MEM
4388 .endm
4389
4390 /**********************************************************************************************/
4391 /* CMY *************************************************************************************** */
4392 .macro          OpC0X1
4393                 LDRB    rscratch    , [rpc], #1
4394                 SUBS    rscratch2   , reg_y , rscratch, LSL #24
4395                 BICCC   rstatus, rstatus, #MASK_CARRY
4396                 ORRCS   rstatus, rstatus, #MASK_CARRY
4397                 UPDATE_ZN
4398                 ADD1MEM
4399 .endm
4400 .macro          OpC0X0
4401                 LDRB    rscratch2   , [rpc, #1]
4402                 LDRB    rscratch   , [rpc], #2
4403                 ORR     rscratch, rscratch, rscratch2, LSL #8
4404                 SUBS    rscratch2   , reg_y, rscratch, LSL #16
4405                 BICCC   rstatus, rstatus, #MASK_CARRY
4406                 ORRCS   rstatus, rstatus, #MASK_CARRY
4407                 UPDATE_ZN
4408                 ADD2MEM
4409 .endm
4410
4411
4412
4413
4414
4415 /**********************************************************************************************/
4416 /* CMP *************************************************************************************** */
4417 .macro          OpC9M1
4418                 LDRB    rscratch    , [rpc], #1
4419                 SUBS    rscratch2   , reg_a , rscratch, LSL #24
4420                 BICCC   rstatus, rstatus, #MASK_CARRY
4421                 ORRCS   rstatus, rstatus, #MASK_CARRY
4422                 UPDATE_ZN
4423                 ADD1MEM
4424 .endm
4425 .macro          OpC9M0
4426                 LDRB    rscratch2   , [rpc,#1]
4427                 LDRB    rscratch   , [rpc], #2
4428                 ORR     rscratch, rscratch, rscratch2, LSL #8
4429                 SUBS    rscratch2   , reg_a, rscratch, LSL #16
4430                 BICCC   rstatus, rstatus, #MASK_CARRY
4431                 ORRCS   rstatus, rstatus, #MASK_CARRY
4432                 UPDATE_ZN
4433                 ADD2MEM
4434 .endm
4435
4436 /**********************************************************************************************/
4437 /* CMX *************************************************************************************** */
4438 .macro          OpE0X1
4439                 LDRB    rscratch    , [rpc], #1
4440                 SUBS    rscratch2   , reg_x , rscratch, LSL #24
4441                 BICCC   rstatus, rstatus, #MASK_CARRY
4442                 ORRCS   rstatus, rstatus, #MASK_CARRY
4443                 UPDATE_ZN
4444                 ADD1MEM
4445 .endm
4446 .macro          OpE0X0
4447                 LDRB    rscratch2   , [rpc,#1]
4448                 LDRB    rscratch   , [rpc], #2
4449                 ORR     rscratch, rscratch, rscratch2, LSL #8
4450                 SUBS    rscratch2   , reg_x, rscratch, LSL #16
4451                 BICCC   rstatus, rstatus, #MASK_CARRY
4452                 ORRCS   rstatus, rstatus, #MASK_CARRY
4453                 UPDATE_ZN
4454                 ADD2MEM
4455 .endm
4456
4457
4458 /****************************************************************
4459         GLOBAL
4460 ****************************************************************/
4461 .global asmMainLoop
4462 .type   asmMainLoop, function
4463
4464 @ void asmMainLoop(asm_cpu_var_t *asmcpuPtr);
4465 asmMainLoop:
4466         @ save registers
4467         STMFD           R13!,{R4-R11, LR}
4468         @ init pointer to CPUvar structure
4469         MOV             reg_cpu_var,R0
4470         @ init registers
4471         LOAD_REGS
4472         @ get cpu mode from flag and init jump table
4473         S9xFixCycles
4474
4475 mainLoop:
4476         @ APU Execute
4477         asmAPU_EXECUTE
4478
4479         @ Test Flags
4480         LDR             rscratch,[reg_cpu_var,#Flags_ofs]
4481         MOVS            rscratch,rscratch
4482         BNE             CPUFlags_set    @ If flags => check for irq/nmi/scan_keys...
4483
4484         EXEC_OP                                         @ Execute next opcode
4485
4486 CPUFlags_set:   @ Check flags (!=0)
4487                 TST     rscratch,#NMI_FLAG              @ Check NMI
4488                 BEQ     CPUFlagsNMI_FLAG_cleared
4489                 LDR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4490                 SUBS    rscratch2,rscratch2,#1
4491                 STR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4492                 BNE     CPUFlagsNMI_FLAG_cleared
4493                 BIC     rscratch,rscratch,#NMI_FLAG
4494                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4495                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4496                 MOVS    rscratch2,rscratch2
4497                 BEQ     NotCPUaitingForInterruptNMI
4498                 MOV     rscratch2,#0
4499                 ADD     rpc,rpc,#1
4500                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4501 NotCPUaitingForInterruptNMI:
4502                 S9xOpcode_NMI
4503                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4504 CPUFlagsNMI_FLAG_cleared:
4505                 TST     rscratch,#IRQ_PENDING_FLAG   @ Check IRQ_PENDING_FLAG
4506                 BEQ     CPUFlagsIRQ_PENDING_FLAG_cleared
4507                 LDR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4508                 MOVS    rscratch2,rscratch2
4509                 BNE     CPUIRQCycleCount_NotZero
4510                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4511                 MOVS    rscratch2,rscratch2
4512                 BEQ     NotCPUaitingForInterruptIRQ
4513                 MOV     rscratch2,#0
4514                 ADD     rpc,rpc,#1
4515                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4516 NotCPUaitingForInterruptIRQ:
4517                 LDRB    rscratch2,[reg_cpu_var,#IRQActive_ofs]
4518                 MOVS    rscratch2,rscratch2
4519                 BEQ     CPUIRQActive_cleared
4520                 TST     rstatus,#MASK_IRQ
4521                 BNE     CPUFlagsIRQ_PENDING_FLAG_cleared
4522                 S9xOpcode_IRQ
4523                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4524                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4525 CPUIRQActive_cleared:
4526                 BIC     rscratch,rscratch,#IRQ_PENDING_FLAG
4527                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4528                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4529 CPUIRQCycleCount_NotZero:
4530                 SUB     rscratch2,rscratch2,#1
4531                 STR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4532 CPUFlagsIRQ_PENDING_FLAG_cleared:
4533
4534                 TST     rscratch,#SCAN_KEYS_FLAG   @ Check SCAN_KEYS_FLAG
4535                 BNE     endmainLoop
4536
4537         EXEC_OP @ Execute next opcode
4538
4539 endmainLoop:
4540     /*Registers.PC = CPU.PC - CPU.PCBase;
4541     S9xPackStatus ();
4542     APURegisters.PC = IAPU.PC - IAPU.RAM;
4543     S9xAPUPackStatus ();
4544
4545     if (CPU.Flags & SCAN_KEYS_FLAG)
4546     {
4547             S9xSyncSpeed ();
4548         CPU.Flags &= ~SCAN_KEYS_FLAG;
4549     }   */
4550 /********end*/
4551         SAVE_REGS
4552         LDMFD           R13!,{R4-R11, LR}
4553         BX LR
4554 .pool
4555 .size asmMainLoop, asmMainLoop-.
4556
4557 @ void test_opcode(struct asm_cpu_var *asm_var);
4558 test_opcode:
4559         @ save registers
4560         STMFD           R13!,{R4-R11,LR}
4561         @ init pointer to CPUvar structure
4562         MOV             reg_cpu_var,R0
4563         @ init registers
4564         LOAD_REGS
4565         @ get cpu mode from flag and init jump table
4566         S9xFixCycles
4567
4568         EXEC_OP
4569 .pool
4570
4571 /*****************************************************************
4572        ASM CODE
4573 *****************************************************************/
4574
4575
4576 jumptable1:             .long   Op00mod1
4577                         .long   Op01M1mod1
4578                         .long   Op02mod1
4579                         .long   Op03M1mod1
4580                         .long   Op04M1mod1
4581                         .long   Op05M1mod1
4582                         .long   Op06M1mod1
4583                         .long   Op07M1mod1
4584                         .long   Op08mod1
4585                         .long   Op09M1mod1
4586                         .long   Op0AM1mod1
4587                         .long   Op0Bmod1
4588                         .long   Op0CM1mod1
4589                         .long   Op0DM1mod1
4590                         .long   Op0EM1mod1
4591                         .long   Op0FM1mod1
4592                         .long   Op10mod1
4593                         .long   Op11M1mod1
4594                         .long   Op12M1mod1
4595                         .long   Op13M1mod1
4596                         .long   Op14M1mod1
4597                         .long   Op15M1mod1
4598                         .long   Op16M1mod1
4599                         .long   Op17M1mod1
4600                         .long   Op18mod1
4601                         .long   Op19M1mod1
4602                         .long   Op1AM1mod1
4603                         .long   Op1Bmod1
4604                         .long   Op1CM1mod1
4605                         .long   Op1DM1mod1
4606                         .long   Op1EM1mod1
4607                         .long   Op1FM1mod1
4608                         .long   Op20mod1
4609                         .long   Op21M1mod1
4610                         .long   Op22mod1
4611                         .long   Op23M1mod1
4612                         .long   Op24M1mod1
4613                         .long   Op25M1mod1
4614                         .long   Op26M1mod1
4615                         .long   Op27M1mod1
4616                         .long   Op28mod1
4617                         .long   Op29M1mod1
4618                         .long   Op2AM1mod1
4619                         .long   Op2Bmod1
4620                         .long   Op2CM1mod1
4621                         .long   Op2DM1mod1
4622                         .long   Op2EM1mod1
4623                         .long   Op2FM1mod1
4624                         .long   Op30mod1
4625                         .long   Op31M1mod1
4626                         .long   Op32M1mod1
4627                         .long   Op33M1mod1
4628                         .long   Op34M1mod1
4629                         .long   Op35M1mod1
4630                         .long   Op36M1mod1
4631                         .long   Op37M1mod1
4632                         .long   Op38mod1
4633                         .long   Op39M1mod1
4634                         .long   Op3AM1mod1
4635                         .long   Op3Bmod1
4636                         .long   Op3CM1mod1
4637                         .long   Op3DM1mod1
4638                         .long   Op3EM1mod1
4639                         .long   Op3FM1mod1
4640                         .long   Op40mod1
4641                         .long   Op41M1mod1
4642                         .long   Op42mod1
4643                         .long   Op43M1mod1
4644                         .long   Op44X1mod1
4645                         .long   Op45M1mod1
4646                         .long   Op46M1mod1
4647                         .long   Op47M1mod1
4648                         .long   Op48M1mod1
4649                         .long   Op49M1mod1
4650                         .long   Op4AM1mod1
4651                         .long   Op4Bmod1
4652                         .long   Op4Cmod1
4653                         .long   Op4DM1mod1
4654                         .long   Op4EM1mod1
4655                         .long   Op4FM1mod1
4656                         .long   Op50mod1
4657                         .long   Op51M1mod1
4658                         .long   Op52M1mod1
4659                         .long   Op53M1mod1
4660                         .long   Op54X1mod1
4661                         .long   Op55M1mod1
4662                         .long   Op56M1mod1
4663                         .long   Op57M1mod1
4664                         .long   Op58mod1
4665                         .long   Op59M1mod1
4666                         .long   Op5AX1mod1
4667                         .long   Op5Bmod1
4668                         .long   Op5Cmod1
4669                         .long   Op5DM1mod1
4670                         .long   Op5EM1mod1
4671                         .long   Op5FM1mod1
4672                         .long   Op60mod1
4673                         .long   Op61M1mod1
4674                         .long   Op62mod1
4675                         .long   Op63M1mod1
4676                         .long   Op64M1mod1
4677                         .long   Op65M1mod1
4678                         .long   Op66M1mod1
4679                         .long   Op67M1mod1
4680                         .long   Op68M1mod1
4681                         .long   Op69M1mod1
4682                         .long   Op6AM1mod1
4683                         .long   Op6Bmod1
4684                         .long   Op6Cmod1
4685                         .long   Op6DM1mod1
4686                         .long   Op6EM1mod1
4687                         .long   Op6FM1mod1
4688                         .long   Op70mod1
4689                         .long   Op71M1mod1
4690                         .long   Op72M1mod1
4691                         .long   Op73M1mod1
4692                         .long   Op74M1mod1
4693                         .long   Op75M1mod1
4694                         .long   Op76M1mod1
4695                         .long   Op77M1mod1
4696                         .long   Op78mod1
4697                         .long   Op79M1mod1
4698                         .long   Op7AX1mod1
4699                         .long   Op7Bmod1
4700                         .long   Op7Cmod1
4701                         .long   Op7DM1mod1
4702                         .long   Op7EM1mod1
4703                         .long   Op7FM1mod1
4704                         .long   Op80mod1
4705                         .long   Op81M1mod1
4706                         .long   Op82mod1
4707                         .long   Op83M1mod1
4708                         .long   Op84X1mod1
4709                         .long   Op85M1mod1
4710                         .long   Op86X1mod1
4711                         .long   Op87M1mod1
4712                         .long   Op88X1mod1
4713                         .long   Op89M1mod1
4714                         .long   Op8AM1mod1
4715                         .long   Op8Bmod1
4716                         .long   Op8CX1mod1
4717                         .long   Op8DM1mod1
4718                         .long   Op8EX1mod1
4719                         .long   Op8FM1mod1
4720                         .long   Op90mod1
4721                         .long   Op91M1mod1
4722                         .long   Op92M1mod1
4723                         .long   Op93M1mod1
4724                         .long   Op94X1mod1
4725                         .long   Op95M1mod1
4726                         .long   Op96X1mod1
4727                         .long   Op97M1mod1
4728                         .long   Op98M1mod1
4729                         .long   Op99M1mod1
4730                         .long   Op9Amod1
4731                         .long   Op9BX1mod1
4732                         .long   Op9CM1mod1
4733                         .long   Op9DM1mod1
4734                         .long   Op9EM1mod1
4735                         .long   Op9FM1mod1
4736                         .long   OpA0X1mod1
4737                         .long   OpA1M1mod1
4738                         .long   OpA2X1mod1
4739                         .long   OpA3M1mod1
4740                         .long   OpA4X1mod1
4741                         .long   OpA5M1mod1
4742                         .long   OpA6X1mod1
4743                         .long   OpA7M1mod1
4744                         .long   OpA8X1mod1
4745                         .long   OpA9M1mod1
4746                         .long   OpAAX1mod1
4747                         .long   OpABmod1
4748                         .long   OpACX1mod1
4749                         .long   OpADM1mod1
4750                         .long   OpAEX1mod1
4751                         .long   OpAFM1mod1
4752                         .long   OpB0mod1
4753                         .long   OpB1M1mod1
4754                         .long   OpB2M1mod1
4755                         .long   OpB3M1mod1
4756                         .long   OpB4X1mod1
4757                         .long   OpB5M1mod1
4758                         .long   OpB6X1mod1
4759                         .long   OpB7M1mod1
4760                         .long   OpB8mod1
4761                         .long   OpB9M1mod1
4762                         .long   OpBAX1mod1
4763                         .long   OpBBX1mod1
4764                         .long   OpBCX1mod1
4765                         .long   OpBDM1mod1
4766                         .long   OpBEX1mod1
4767                         .long   OpBFM1mod1
4768                         .long   OpC0X1mod1
4769                         .long   OpC1M1mod1
4770                         .long   OpC2mod1
4771                         .long   OpC3M1mod1
4772                         .long   OpC4X1mod1
4773                         .long   OpC5M1mod1
4774                         .long   OpC6M1mod1
4775                         .long   OpC7M1mod1
4776                         .long   OpC8X1mod1
4777                         .long   OpC9M1mod1
4778                         .long   OpCAX1mod1
4779                         .long   OpCBmod1
4780                         .long   OpCCX1mod1
4781                         .long   OpCDM1mod1
4782                         .long   OpCEM1mod1
4783                         .long   OpCFM1mod1
4784                         .long   OpD0mod1
4785                         .long   OpD1M1mod1
4786                         .long   OpD2M1mod1
4787                         .long   OpD3M1mod1
4788                         .long   OpD4mod1
4789                         .long   OpD5M1mod1
4790                         .long   OpD6M1mod1
4791                         .long   OpD7M1mod1
4792                         .long   OpD8mod1
4793                         .long   OpD9M1mod1
4794                         .long   OpDAX1mod1
4795                         .long   OpDBmod1
4796                         .long   OpDCmod1
4797                         .long   OpDDM1mod1
4798                         .long   OpDEM1mod1
4799                         .long   OpDFM1mod1
4800                         .long   OpE0X1mod1
4801                         .long   OpE1M1mod1
4802                         .long   OpE2mod1
4803                         .long   OpE3M1mod1
4804                         .long   OpE4X1mod1
4805                         .long   OpE5M1mod1
4806                         .long   OpE6M1mod1
4807                         .long   OpE7M1mod1
4808                         .long   OpE8X1mod1
4809                         .long   OpE9M1mod1
4810                         .long   OpEAmod1
4811                         .long   OpEBmod1
4812                         .long   OpECX1mod1
4813                         .long   OpEDM1mod1
4814                         .long   OpEEM1mod1
4815                         .long   OpEFM1mod1
4816                         .long   OpF0mod1
4817                         .long   OpF1M1mod1
4818                         .long   OpF2M1mod1
4819                         .long   OpF3M1mod1
4820                         .long   OpF4mod1
4821                         .long   OpF5M1mod1
4822                         .long   OpF6M1mod1
4823                         .long   OpF7M1mod1
4824                         .long   OpF8mod1
4825                         .long   OpF9M1mod1
4826                         .long   OpFAX1mod1
4827                         .long   OpFBmod1
4828                         .long   OpFCmod1
4829                         .long   OpFDM1mod1
4830                         .long   OpFEM1mod1
4831                         .long   OpFFM1mod1
4832
4833 Op00mod1:
4834 lbl00mod1:      Op00
4835                         NEXTOPCODE
4836 Op01M1mod1:
4837 lbl01mod1a:     DirectIndexedIndirect1
4838 lbl01mod1b:     ORA8
4839                         NEXTOPCODE
4840 Op02mod1:
4841 lbl02mod1:      Op02
4842                         NEXTOPCODE
4843 Op03M1mod1:
4844 lbl03mod1a:     StackasmRelative
4845 lbl03mod1b:     ORA8
4846                         NEXTOPCODE
4847 Op04M1mod1:
4848 lbl04mod1a:     Direct
4849 lbl04mod1b:     TSB8
4850                         NEXTOPCODE
4851 Op05M1mod1:
4852 lbl05mod1a:     Direct
4853 lbl05mod1b:     ORA8
4854                         NEXTOPCODE
4855 Op06M1mod1:
4856 lbl06mod1a:     Direct
4857 lbl06mod1b:     ASL8
4858                         NEXTOPCODE
4859 Op07M1mod1:
4860 lbl07mod1a:     DirectIndirectLong
4861 lbl07mod1b:     ORA8
4862                         NEXTOPCODE
4863 Op08mod1:
4864 lbl08mod1:      Op08
4865                         NEXTOPCODE
4866 Op09M1mod1:
4867 lbl09mod1:      Op09M1
4868                         NEXTOPCODE
4869 Op0AM1mod1:
4870 lbl0Amod1a:     A_ASL8
4871                         NEXTOPCODE
4872 Op0Bmod1:
4873 lbl0Bmod1:      Op0B
4874                         NEXTOPCODE
4875 Op0CM1mod1:
4876 lbl0Cmod1a:     Absolute
4877 lbl0Cmod1b:     TSB8
4878                         NEXTOPCODE
4879 Op0DM1mod1:
4880 lbl0Dmod1a:     Absolute
4881 lbl0Dmod1b:     ORA8
4882                         NEXTOPCODE
4883 Op0EM1mod1:
4884 lbl0Emod1a:     Absolute
4885 lbl0Emod1b:     ASL8
4886                         NEXTOPCODE
4887 Op0FM1mod1:
4888 lbl0Fmod1a:     AbsoluteLong
4889 lbl0Fmod1b:     ORA8
4890                         NEXTOPCODE
4891 Op10mod1:
4892 lbl10mod1:      Op10
4893                         NEXTOPCODE
4894 Op11M1mod1:
4895 lbl11mod1a:     DirectIndirectIndexed1
4896 lbl11mod1b:     ORA8
4897                         NEXTOPCODE
4898 Op12M1mod1:
4899 lbl12mod1a:     DirectIndirect
4900 lbl12mod1b:     ORA8
4901                         NEXTOPCODE
4902 Op13M1mod1:
4903 lbl13mod1a:     StackasmRelativeIndirectIndexed1
4904 lbl13mod1b:     ORA8
4905                         NEXTOPCODE
4906 Op14M1mod1:
4907 lbl14mod1a:     Direct
4908 lbl14mod1b:     TRB8
4909                         NEXTOPCODE
4910 Op15M1mod1:
4911 lbl15mod1a:     DirectIndexedX1
4912 lbl15mod1b:     ORA8
4913                         NEXTOPCODE
4914 Op16M1mod1:
4915 lbl16mod1a:     DirectIndexedX1
4916 lbl16mod1b:     ASL8
4917                         NEXTOPCODE
4918 Op17M1mod1:
4919 lbl17mod1a:     DirectIndirectIndexedLong1
4920 lbl17mod1b:     ORA8
4921                         NEXTOPCODE
4922 Op18mod1:
4923 lbl18mod1:      Op18
4924                         NEXTOPCODE
4925 Op19M1mod1:
4926 lbl19mod1a:     AbsoluteIndexedY1
4927 lbl19mod1b:     ORA8
4928                         NEXTOPCODE
4929 Op1AM1mod1:
4930 lbl1Amod1a:     A_INC8
4931                         NEXTOPCODE
4932 Op1Bmod1:
4933 lbl1Bmod1:      Op1BM1
4934                         NEXTOPCODE
4935 Op1CM1mod1:
4936 lbl1Cmod1a:     Absolute
4937 lbl1Cmod1b:     TRB8
4938                         NEXTOPCODE
4939 Op1DM1mod1:
4940 lbl1Dmod1a:     AbsoluteIndexedX1
4941 lbl1Dmod1b:     ORA8
4942                         NEXTOPCODE
4943 Op1EM1mod1:
4944 lbl1Emod1a:     AbsoluteIndexedX1
4945 lbl1Emod1b:     ASL8
4946                         NEXTOPCODE
4947 Op1FM1mod1:
4948 lbl1Fmod1a:     AbsoluteLongIndexedX1
4949 lbl1Fmod1b:     ORA8
4950                         NEXTOPCODE
4951 Op20mod1:
4952 lbl20mod1:      Op20
4953                         NEXTOPCODE
4954 Op21M1mod1:
4955 lbl21mod1a:     DirectIndexedIndirect1
4956 lbl21mod1b:     AND8
4957                         NEXTOPCODE
4958 Op22mod1:
4959 lbl22mod1:      Op22
4960                         NEXTOPCODE
4961 Op23M1mod1:
4962 lbl23mod1a:     StackasmRelative
4963 lbl23mod1b:     AND8
4964                         NEXTOPCODE
4965 Op24M1mod1:
4966 lbl24mod1a:     Direct
4967 lbl24mod1b:     BIT8
4968                         NEXTOPCODE
4969 Op25M1mod1:
4970 lbl25mod1a:     Direct
4971 lbl25mod1b:     AND8
4972                         NEXTOPCODE
4973 Op26M1mod1:
4974 lbl26mod1a:     Direct
4975 lbl26mod1b:     ROL8
4976                         NEXTOPCODE
4977 Op27M1mod1:
4978 lbl27mod1a:     DirectIndirectLong
4979 lbl27mod1b:     AND8
4980                         NEXTOPCODE
4981 Op28mod1:
4982 lbl28mod1:      Op28X1M1
4983                         NEXTOPCODE
4984 .pool
4985 Op29M1mod1:
4986 lbl29mod1:      Op29M1
4987                         NEXTOPCODE
4988 Op2AM1mod1:
4989 lbl2Amod1a:     A_ROL8
4990                         NEXTOPCODE
4991 Op2Bmod1:
4992 lbl2Bmod1:      Op2B
4993                         NEXTOPCODE
4994 Op2CM1mod1:
4995 lbl2Cmod1a:     Absolute
4996 lbl2Cmod1b:     BIT8
4997                         NEXTOPCODE
4998 Op2DM1mod1:
4999 lbl2Dmod1a:     Absolute
5000 lbl2Dmod1b:     AND8
5001                         NEXTOPCODE
5002 Op2EM1mod1:
5003 lbl2Emod1a:     Absolute
5004 lbl2Emod1b:     ROL8
5005                         NEXTOPCODE
5006 Op2FM1mod1:
5007 lbl2Fmod1a:     AbsoluteLong
5008 lbl2Fmod1b:     AND8
5009                         NEXTOPCODE
5010 Op30mod1:
5011 lbl30mod1:      Op30
5012                         NEXTOPCODE
5013 Op31M1mod1:
5014 lbl31mod1a:     DirectIndirectIndexed1
5015 lbl31mod1b:     AND8
5016                         NEXTOPCODE
5017 Op32M1mod1:
5018 lbl32mod1a:     DirectIndirect
5019 lbl32mod1b:     AND8
5020                         NEXTOPCODE
5021 Op33M1mod1:
5022 lbl33mod1a:     StackasmRelativeIndirectIndexed1
5023 lbl33mod1b:     AND8
5024                         NEXTOPCODE
5025 Op34M1mod1:
5026 lbl34mod1a:     DirectIndexedX1
5027 lbl34mod1b:     BIT8
5028                         NEXTOPCODE
5029 Op35M1mod1:
5030 lbl35mod1a:     DirectIndexedX1
5031 lbl35mod1b:     AND8
5032                         NEXTOPCODE
5033 Op36M1mod1:
5034 lbl36mod1a:     DirectIndexedX1
5035 lbl36mod1b:     ROL8
5036                         NEXTOPCODE
5037 Op37M1mod1:
5038 lbl37mod1a:     DirectIndirectIndexedLong1
5039 lbl37mod1b:     AND8
5040                         NEXTOPCODE
5041 Op38mod1:
5042 lbl38mod1:      Op38
5043                         NEXTOPCODE
5044 Op39M1mod1:
5045 lbl39mod1a:     AbsoluteIndexedY1
5046 lbl39mod1b:     AND8
5047                         NEXTOPCODE
5048 Op3AM1mod1:
5049 lbl3Amod1a:     A_DEC8
5050                         NEXTOPCODE
5051 Op3Bmod1:
5052 lbl3Bmod1:      Op3BM1
5053                         NEXTOPCODE
5054 Op3CM1mod1:
5055 lbl3Cmod1a:     AbsoluteIndexedX1
5056 lbl3Cmod1b:     BIT8
5057                         NEXTOPCODE
5058 Op3DM1mod1:
5059 lbl3Dmod1a:     AbsoluteIndexedX1
5060 lbl3Dmod1b:     AND8
5061                         NEXTOPCODE
5062 Op3EM1mod1:
5063 lbl3Emod1a:     AbsoluteIndexedX1
5064 lbl3Emod1b:     ROL8
5065                         NEXTOPCODE
5066 Op3FM1mod1:
5067 lbl3Fmod1a:     AbsoluteLongIndexedX1
5068 lbl3Fmod1b:     AND8
5069                         NEXTOPCODE
5070 Op40mod1:
5071 lbl40mod1:      Op40X1M1
5072                         NEXTOPCODE
5073 .pool
5074 Op41M1mod1:
5075 lbl41mod1a:     DirectIndexedIndirect1
5076 lbl41mod1b:     EOR8
5077                         NEXTOPCODE
5078 Op42mod1:
5079 lbl42mod1:      Op42
5080                         NEXTOPCODE
5081 Op43M1mod1:
5082 lbl43mod1a:     StackasmRelative
5083 lbl43mod1b:     EOR8
5084                         NEXTOPCODE
5085 Op44X1mod1:
5086 lbl44mod1:      Op44X1M1
5087                         NEXTOPCODE
5088 Op45M1mod1:
5089 lbl45mod1a:     Direct
5090 lbl45mod1b:     EOR8
5091                         NEXTOPCODE
5092 Op46M1mod1:
5093 lbl46mod1a:     Direct
5094 lbl46mod1b:     LSR8
5095                         NEXTOPCODE
5096 Op47M1mod1:
5097 lbl47mod1a:     DirectIndirectLong
5098 lbl47mod1b:     EOR8
5099                         NEXTOPCODE
5100 Op48M1mod1:
5101 lbl48mod1:      Op48M1
5102                         NEXTOPCODE
5103 Op49M1mod1:
5104 lbl49mod1:      Op49M1
5105                         NEXTOPCODE
5106 Op4AM1mod1:
5107 lbl4Amod1a:     A_LSR8
5108                         NEXTOPCODE
5109 Op4Bmod1:
5110 lbl4Bmod1:      Op4B
5111                         NEXTOPCODE
5112 Op4Cmod1:
5113 lbl4Cmod1:      Op4C
5114                         NEXTOPCODE
5115 Op4DM1mod1:
5116 lbl4Dmod1a:     Absolute
5117 lbl4Dmod1b:     EOR8
5118                         NEXTOPCODE
5119 Op4EM1mod1:
5120 lbl4Emod1a:     Absolute
5121 lbl4Emod1b:     LSR8
5122                         NEXTOPCODE
5123 Op4FM1mod1:
5124 lbl4Fmod1a:     AbsoluteLong
5125 lbl4Fmod1b:     EOR8
5126                         NEXTOPCODE
5127 Op50mod1:
5128 lbl50mod1:      Op50
5129                         NEXTOPCODE
5130 Op51M1mod1:
5131 lbl51mod1a:     DirectIndirectIndexed1
5132 lbl51mod1b:     EOR8
5133                         NEXTOPCODE
5134 Op52M1mod1:
5135 lbl52mod1a:     DirectIndirect
5136 lbl52mod1b:     EOR8
5137                         NEXTOPCODE
5138 Op53M1mod1:
5139 lbl53mod1a:     StackasmRelativeIndirectIndexed1
5140 lbl53mod1b:     EOR8
5141                         NEXTOPCODE
5142 Op54X1mod1:
5143 lbl54mod1:      Op54X1M1
5144                         NEXTOPCODE
5145 Op55M1mod1:
5146 lbl55mod1a:     DirectIndexedX1
5147 lbl55mod1b:     EOR8
5148                         NEXTOPCODE
5149 Op56M1mod1:
5150 lbl56mod1a:     DirectIndexedX1
5151 lbl56mod1b:     LSR8
5152                         NEXTOPCODE
5153 Op57M1mod1:
5154 lbl57mod1a:     DirectIndirectIndexedLong1
5155 lbl57mod1b:     EOR8
5156                         NEXTOPCODE
5157 Op58mod1:
5158 lbl58mod1:      Op58
5159                         NEXTOPCODE
5160 Op59M1mod1:
5161 lbl59mod1a:     AbsoluteIndexedY1
5162 lbl59mod1b:     EOR8
5163                         NEXTOPCODE
5164 Op5AX1mod1:
5165 lbl5Amod1:      Op5AX1
5166                         NEXTOPCODE
5167 Op5Bmod1:
5168 lbl5Bmod1:      Op5BM1
5169                         NEXTOPCODE
5170 Op5Cmod1:
5171 lbl5Cmod1:      Op5C
5172                         NEXTOPCODE
5173 Op5DM1mod1:
5174 lbl5Dmod1a:     AbsoluteIndexedX1
5175 lbl5Dmod1b:     EOR8
5176                         NEXTOPCODE
5177 Op5EM1mod1:
5178 lbl5Emod1a:     AbsoluteIndexedX1
5179 lbl5Emod1b:     LSR8
5180                         NEXTOPCODE
5181 Op5FM1mod1:
5182 lbl5Fmod1a:     AbsoluteLongIndexedX1
5183 lbl5Fmod1b:     EOR8
5184                         NEXTOPCODE
5185 Op60mod1:
5186 lbl60mod1:      Op60
5187                         NEXTOPCODE
5188 Op61M1mod1:
5189 lbl61mod1a:     DirectIndexedIndirect1
5190 lbl61mod1b:     ADC8
5191                         NEXTOPCODE
5192 Op62mod1:
5193 lbl62mod1:      Op62
5194                         NEXTOPCODE
5195 Op63M1mod1:
5196 lbl63mod1a:     StackasmRelative
5197 lbl63mod1b:     ADC8
5198                         NEXTOPCODE
5199 Op64M1mod1:
5200 lbl64mod1a:     Direct
5201 lbl64mod1b:     STZ8
5202                         NEXTOPCODE
5203 Op65M1mod1:
5204 lbl65mod1a:     Direct
5205 lbl65mod1b:     ADC8
5206                         NEXTOPCODE
5207 Op66M1mod1:
5208 lbl66mod1a:     Direct
5209 lbl66mod1b:     ROR8
5210                         NEXTOPCODE
5211 Op67M1mod1:
5212 lbl67mod1a:     DirectIndirectLong
5213 lbl67mod1b:     ADC8
5214                         NEXTOPCODE
5215 Op68M1mod1:
5216 lbl68mod1:      Op68M1
5217                         NEXTOPCODE
5218 Op69M1mod1:
5219 lbl69mod1a:     Immediate8
5220 lbl69mod1b:     ADC8
5221                         NEXTOPCODE
5222 Op6AM1mod1:
5223 lbl6Amod1a:     A_ROR8
5224                         NEXTOPCODE
5225 Op6Bmod1:
5226 lbl6Bmod1:      Op6B
5227                         NEXTOPCODE
5228 Op6Cmod1:
5229 lbl6Cmod1:      Op6C
5230                         NEXTOPCODE
5231 Op6DM1mod1:
5232 lbl6Dmod1a:     Absolute
5233 lbl6Dmod1b:     ADC8
5234                         NEXTOPCODE
5235 Op6EM1mod1:
5236 lbl6Emod1a:     Absolute
5237 lbl6Emod1b:     ROR8
5238                         NEXTOPCODE
5239 Op6FM1mod1:
5240 lbl6Fmod1a:     AbsoluteLong
5241 lbl6Fmod1b:     ADC8
5242                         NEXTOPCODE
5243 Op70mod1:
5244 lbl70mod1:      Op70
5245                         NEXTOPCODE
5246 Op71M1mod1:
5247 lbl71mod1a:     DirectIndirectIndexed1
5248 lbl71mod1b:     ADC8
5249                         NEXTOPCODE
5250 Op72M1mod1:
5251 lbl72mod1a:     DirectIndirect
5252 lbl72mod1b:     ADC8
5253                         NEXTOPCODE
5254 Op73M1mod1:
5255 lbl73mod1a:     StackasmRelativeIndirectIndexed1
5256 lbl73mod1b:     ADC8
5257                         NEXTOPCODE
5258
5259 Op74M1mod1:
5260 lbl74mod1a:     DirectIndexedX1
5261 lbl74mod1b:     STZ8
5262                         NEXTOPCODE
5263 Op75M1mod1:
5264 lbl75mod1a:     DirectIndexedX1
5265 lbl75mod1b:     ADC8
5266                         NEXTOPCODE
5267 Op76M1mod1:
5268 lbl76mod1a:     DirectIndexedX1
5269 lbl76mod1b:     ROR8
5270                         NEXTOPCODE
5271 Op77M1mod1:
5272 lbl77mod1a:     DirectIndirectIndexedLong1
5273 lbl77mod1b:     ADC8
5274                         NEXTOPCODE
5275 Op78mod1:
5276 lbl78mod1:      Op78
5277                         NEXTOPCODE
5278 Op79M1mod1:
5279 lbl79mod1a:     AbsoluteIndexedY1
5280 lbl79mod1b:     ADC8
5281                         NEXTOPCODE
5282 Op7AX1mod1:
5283 lbl7Amod1:      Op7AX1
5284                         NEXTOPCODE
5285 Op7Bmod1:
5286 lbl7Bmod1:      Op7BM1
5287                         NEXTOPCODE
5288 Op7Cmod1:
5289 lbl7Cmod1:      AbsoluteIndexedIndirectX1
5290                 Op7C
5291                         NEXTOPCODE
5292 Op7DM1mod1:
5293 lbl7Dmod1a:     AbsoluteIndexedX1
5294 lbl7Dmod1b:     ADC8
5295                         NEXTOPCODE
5296 Op7EM1mod1:
5297 lbl7Emod1a:     AbsoluteIndexedX1
5298 lbl7Emod1b:     ROR8
5299                         NEXTOPCODE
5300 Op7FM1mod1:
5301 lbl7Fmod1a:     AbsoluteLongIndexedX1
5302 lbl7Fmod1b:     ADC8
5303                         NEXTOPCODE
5304
5305
5306 Op80mod1:
5307 lbl80mod1:      Op80
5308                         NEXTOPCODE
5309 Op81M1mod1:
5310 lbl81mod1a:     DirectIndexedIndirect1
5311 lbl81mod1b:     Op81M1
5312                         NEXTOPCODE
5313 Op82mod1:
5314 lbl82mod1:      Op82
5315                         NEXTOPCODE
5316 Op83M1mod1:
5317 lbl83mod1a:     StackasmRelative
5318 lbl83mod1b:     STA8
5319                         NEXTOPCODE
5320 Op84X1mod1:
5321 lbl84mod1a:     Direct
5322 lbl84mod1b:     STY8
5323                         NEXTOPCODE
5324 Op85M1mod1:
5325 lbl85mod1a:     Direct
5326 lbl85mod1b:     STA8
5327                         NEXTOPCODE
5328 Op86X1mod1:
5329 lbl86mod1a:     Direct
5330 lbl86mod1b:     STX8
5331                         NEXTOPCODE
5332 Op87M1mod1:
5333 lbl87mod1a:     DirectIndirectLong
5334 lbl87mod1b:     STA8
5335                         NEXTOPCODE
5336 Op88X1mod1:
5337 lbl88mod1:      Op88X1
5338                         NEXTOPCODE
5339 Op89M1mod1:
5340 lbl89mod1:      Op89M1
5341                         NEXTOPCODE
5342 Op8AM1mod1:
5343 lbl8Amod1:      Op8AM1X1
5344                         NEXTOPCODE
5345 Op8Bmod1:
5346 lbl8Bmod1:      Op8B
5347                         NEXTOPCODE
5348 Op8CX1mod1:
5349 lbl8Cmod1a:     Absolute
5350 lbl8Cmod1b:     STY8
5351                         NEXTOPCODE
5352 Op8DM1mod1:
5353 lbl8Dmod1a:     Absolute
5354 lbl8Dmod1b:     STA8
5355                         NEXTOPCODE
5356 Op8EX1mod1:
5357 lbl8Emod1a:     Absolute
5358 lbl8Emod1b:     STX8
5359                         NEXTOPCODE
5360 Op8FM1mod1:
5361 lbl8Fmod1a:     AbsoluteLong
5362 lbl8Fmod1b:     STA8
5363                         NEXTOPCODE
5364 Op90mod1:
5365 lbl90mod1:      Op90
5366                         NEXTOPCODE
5367 Op91M1mod1:
5368 lbl91mod1a:     DirectIndirectIndexed1
5369 lbl91mod1b:     STA8
5370                         NEXTOPCODE
5371 Op92M1mod1:
5372 lbl92mod1a:     DirectIndirect
5373 lbl92mod1b:     STA8
5374                         NEXTOPCODE
5375 Op93M1mod1:
5376 lbl93mod1a:     StackasmRelativeIndirectIndexed1
5377 lbl93mod1b:     STA8
5378                         NEXTOPCODE
5379 Op94X1mod1:
5380 lbl94mod1a:     DirectIndexedX1
5381 lbl94mod1b:     STY8
5382                         NEXTOPCODE
5383 Op95M1mod1:
5384 lbl95mod1a:     DirectIndexedX1
5385 lbl95mod1b:     STA8
5386                         NEXTOPCODE
5387 Op96X1mod1:
5388 lbl96mod1a:     DirectIndexedY1
5389 lbl96mod1b:     STX8
5390                         NEXTOPCODE
5391 Op97M1mod1:
5392 lbl97mod1a:     DirectIndirectIndexedLong1
5393 lbl97mod1b:     STA8
5394                         NEXTOPCODE
5395 Op98M1mod1:
5396 lbl98mod1:      Op98M1X1
5397                         NEXTOPCODE
5398 Op99M1mod1:
5399 lbl99mod1a:     AbsoluteIndexedY1
5400 lbl99mod1b:     STA8
5401                         NEXTOPCODE
5402 Op9Amod1:
5403 lbl9Amod1:      Op9AX1
5404                         NEXTOPCODE
5405 Op9BX1mod1:
5406 lbl9Bmod1:      Op9BX1
5407                         NEXTOPCODE
5408 Op9CM1mod1:
5409 lbl9Cmod1a:     Absolute
5410 lbl9Cmod1b:     STZ8
5411                         NEXTOPCODE
5412 Op9DM1mod1:
5413 lbl9Dmod1a:     AbsoluteIndexedX1
5414 lbl9Dmod1b:     STA8
5415                         NEXTOPCODE
5416 Op9EM1mod1:
5417 lbl9Emod1:      AbsoluteIndexedX1
5418                 STZ8
5419                         NEXTOPCODE
5420 Op9FM1mod1:
5421 lbl9Fmod1a:     AbsoluteLongIndexedX1
5422 lbl9Fmod1b:     STA8
5423                         NEXTOPCODE
5424 OpA0X1mod1:
5425 lblA0mod1:      OpA0X1
5426                         NEXTOPCODE
5427 OpA1M1mod1:
5428 lblA1mod1a:     DirectIndexedIndirect1
5429 lblA1mod1b:     LDA8
5430                         NEXTOPCODE
5431 OpA2X1mod1:
5432 lblA2mod1:      OpA2X1
5433                         NEXTOPCODE
5434 OpA3M1mod1:
5435 lblA3mod1a:     StackasmRelative
5436 lblA3mod1b:     LDA8
5437                         NEXTOPCODE
5438 OpA4X1mod1:
5439 lblA4mod1a:     Direct
5440 lblA4mod1b:     LDY8
5441                         NEXTOPCODE
5442 OpA5M1mod1:
5443 lblA5mod1a:     Direct
5444 lblA5mod1b:     LDA8
5445                         NEXTOPCODE
5446 OpA6X1mod1:
5447 lblA6mod1a:     Direct
5448 lblA6mod1b:     LDX8
5449                         NEXTOPCODE
5450 OpA7M1mod1:
5451 lblA7mod1a:     DirectIndirectLong
5452 lblA7mod1b:     LDA8
5453                         NEXTOPCODE
5454 OpA8X1mod1:
5455 lblA8mod1:      OpA8X1M1
5456                         NEXTOPCODE
5457 OpA9M1mod1:
5458 lblA9mod1:      OpA9M1
5459                         NEXTOPCODE
5460 OpAAX1mod1:
5461 lblAAmod1:      OpAAX1M1
5462                         NEXTOPCODE
5463 OpABmod1:
5464 lblABmod1:      OpAB
5465                         NEXTOPCODE
5466 OpACX1mod1:
5467 lblACmod1a:     Absolute
5468 lblACmod1b:     LDY8
5469                         NEXTOPCODE
5470 OpADM1mod1:
5471 lblADmod1a:     Absolute
5472 lblADmod1b:     LDA8
5473                         NEXTOPCODE
5474 OpAEX1mod1:
5475 lblAEmod1a:     Absolute
5476 lblAEmod1b:     LDX8
5477                         NEXTOPCODE
5478 OpAFM1mod1:
5479 lblAFmod1a:     AbsoluteLong
5480 lblAFmod1b:     LDA8
5481                         NEXTOPCODE
5482 OpB0mod1:
5483 lblB0mod1:      OpB0
5484                         NEXTOPCODE
5485 OpB1M1mod1:
5486 lblB1mod1a:     DirectIndirectIndexed1
5487 lblB1mod1b:     LDA8
5488                         NEXTOPCODE
5489 OpB2M1mod1:
5490 lblB2mod1a:     DirectIndirect
5491 lblB2mod1b:     LDA8
5492                         NEXTOPCODE
5493 OpB3M1mod1:
5494 lblB3mod1a:     StackasmRelativeIndirectIndexed1
5495 lblB3mod1b:     LDA8
5496                         NEXTOPCODE
5497 OpB4X1mod1:
5498 lblB4mod1a:     DirectIndexedX1
5499 lblB4mod1b:     LDY8
5500                         NEXTOPCODE
5501 OpB5M1mod1:
5502 lblB5mod1a:     DirectIndexedX1
5503 lblB5mod1b:     LDA8
5504                         NEXTOPCODE
5505 OpB6X1mod1:
5506 lblB6mod1a:     DirectIndexedY1
5507 lblB6mod1b:     LDX8
5508                         NEXTOPCODE
5509 OpB7M1mod1:
5510 lblB7mod1a:     DirectIndirectIndexedLong1
5511 lblB7mod1b:     LDA8
5512                         NEXTOPCODE
5513 OpB8mod1:
5514 lblB8mod1:      OpB8
5515                         NEXTOPCODE
5516 OpB9M1mod1:
5517 lblB9mod1a:     AbsoluteIndexedY1
5518 lblB9mod1b:     LDA8
5519                         NEXTOPCODE
5520 OpBAX1mod1:
5521 lblBAmod1:      OpBAX1
5522                         NEXTOPCODE
5523 OpBBX1mod1:
5524 lblBBmod1:      OpBBX1
5525                         NEXTOPCODE
5526 OpBCX1mod1:
5527 lblBCmod1a:     AbsoluteIndexedX1
5528 lblBCmod1b:     LDY8
5529                         NEXTOPCODE
5530 OpBDM1mod1:
5531 lblBDmod1a:     AbsoluteIndexedX1
5532 lblBDmod1b:     LDA8
5533                         NEXTOPCODE
5534 OpBEX1mod1:
5535 lblBEmod1a:     AbsoluteIndexedY1
5536 lblBEmod1b:     LDX8
5537                         NEXTOPCODE
5538 OpBFM1mod1:
5539 lblBFmod1a:     AbsoluteLongIndexedX1
5540 lblBFmod1b:     LDA8
5541                         NEXTOPCODE
5542 OpC0X1mod1:
5543 lblC0mod1:      OpC0X1
5544                         NEXTOPCODE
5545 OpC1M1mod1:
5546 lblC1mod1a:     DirectIndexedIndirect1
5547 lblC1mod1b:     CMP8
5548                         NEXTOPCODE
5549 OpC2mod1:
5550 lblC2mod1:      OpC2
5551                         NEXTOPCODE
5552 .pool
5553 OpC3M1mod1:
5554 lblC3mod1a:     StackasmRelative
5555 lblC3mod1b:     CMP8
5556                         NEXTOPCODE
5557 OpC4X1mod1:
5558 lblC4mod1a:     Direct
5559 lblC4mod1b:     CMY8
5560                         NEXTOPCODE
5561 OpC5M1mod1:
5562 lblC5mod1a:     Direct
5563 lblC5mod1b:     CMP8
5564                         NEXTOPCODE
5565 OpC6M1mod1:
5566 lblC6mod1a:     Direct
5567 lblC6mod1b:     DEC8
5568                         NEXTOPCODE
5569 OpC7M1mod1:
5570 lblC7mod1a:     DirectIndirectLong
5571 lblC7mod1b:     CMP8
5572                         NEXTOPCODE
5573 OpC8X1mod1:
5574 lblC8mod1:      OpC8X1
5575                         NEXTOPCODE
5576 OpC9M1mod1:
5577 lblC9mod1:      OpC9M1
5578                         NEXTOPCODE
5579 OpCAX1mod1:
5580 lblCAmod1:      OpCAX1
5581                         NEXTOPCODE
5582 OpCBmod1:
5583 lblCBmod1:      OpCB
5584                         NEXTOPCODE
5585 OpCCX1mod1:
5586 lblCCmod1a:     Absolute
5587 lblCCmod1b:     CMY8
5588                         NEXTOPCODE
5589 OpCDM1mod1:
5590 lblCDmod1a:     Absolute
5591 lblCDmod1b:     CMP8
5592                         NEXTOPCODE
5593 OpCEM1mod1:
5594 lblCEmod1a:     Absolute
5595 lblCEmod1b:     DEC8
5596                         NEXTOPCODE
5597 OpCFM1mod1:
5598 lblCFmod1a:     AbsoluteLong
5599 lblCFmod1b:     CMP8
5600                         NEXTOPCODE
5601 OpD0mod1:
5602 lblD0mod1:      OpD0
5603                         NEXTOPCODE
5604 OpD1M1mod1:
5605 lblD1mod1a:     DirectIndirectIndexed1
5606 lblD1mod1b:     CMP8
5607                         NEXTOPCODE
5608 OpD2M1mod1:
5609 lblD2mod1a:     DirectIndirect
5610 lblD2mod1b:     CMP8
5611                         NEXTOPCODE
5612 OpD3M1mod1:
5613 lblD3mod1a:     StackasmRelativeIndirectIndexed1
5614 lblD3mod1b:     CMP8
5615                         NEXTOPCODE
5616 OpD4mod1:
5617 lblD4mod1:      OpD4
5618                         NEXTOPCODE
5619 OpD5M1mod1:
5620 lblD5mod1a:     DirectIndexedX1
5621 lblD5mod1b:     CMP8
5622                         NEXTOPCODE
5623 OpD6M1mod1:
5624 lblD6mod1a:     DirectIndexedX1
5625 lblD6mod1b:     DEC8
5626                         NEXTOPCODE
5627 OpD7M1mod1:
5628 lblD7mod1a:     DirectIndirectIndexedLong1
5629 lblD7mod1b:     CMP8
5630                         NEXTOPCODE
5631 OpD8mod1:
5632 lblD8mod1:      OpD8
5633                         NEXTOPCODE
5634 OpD9M1mod1:
5635 lblD9mod1a:     AbsoluteIndexedY1
5636 lblD9mod1b:     CMP8
5637                         NEXTOPCODE
5638 OpDAX1mod1:
5639 lblDAmod1:      OpDAX1
5640                         NEXTOPCODE
5641 OpDBmod1:
5642 lblDBmod1:      OpDB
5643                         NEXTOPCODE
5644 OpDCmod1:
5645 lblDCmod1:      OpDC
5646                         NEXTOPCODE
5647 OpDDM1mod1:
5648 lblDDmod1a:     AbsoluteIndexedX1
5649 lblDDmod1b:     CMP8
5650                         NEXTOPCODE
5651 OpDEM1mod1:
5652 lblDEmod1a:     AbsoluteIndexedX1
5653 lblDEmod1b:     DEC8
5654                         NEXTOPCODE
5655 OpDFM1mod1:
5656 lblDFmod1a:     AbsoluteLongIndexedX1
5657 lblDFmod1b:     CMP8
5658                         NEXTOPCODE
5659 OpE0X1mod1:
5660 lblE0mod1:      OpE0X1
5661                         NEXTOPCODE
5662 OpE1M1mod1:
5663 lblE1mod1a:     DirectIndexedIndirect1
5664 lblE1mod1b:     SBC8
5665                         NEXTOPCODE
5666 OpE2mod1:
5667 lblE2mod1:      OpE2
5668                         NEXTOPCODE
5669 .pool
5670 OpE3M1mod1:
5671 lblE3mod1a:     StackasmRelative
5672 lblE3mod1b:     SBC8
5673                         NEXTOPCODE
5674 OpE4X1mod1:
5675 lblE4mod1a:     Direct
5676 lblE4mod1b:     CMX8
5677                         NEXTOPCODE
5678 OpE5M1mod1:
5679 lblE5mod1a:     Direct
5680 lblE5mod1b:     SBC8
5681                         NEXTOPCODE
5682 OpE6M1mod1:
5683 lblE6mod1a:     Direct
5684 lblE6mod1b:     INC8
5685                         NEXTOPCODE
5686 OpE7M1mod1:
5687 lblE7mod1a:     DirectIndirectLong
5688 lblE7mod1b:     SBC8
5689                         NEXTOPCODE
5690 OpE8X1mod1:
5691 lblE8mod1:      OpE8X1
5692                         NEXTOPCODE
5693 OpE9M1mod1:
5694 lblE9mod1a:     Immediate8
5695 lblE9mod1b:     SBC8
5696                         NEXTOPCODE
5697 OpEAmod1:
5698 lblEAmod1:      OpEA
5699                         NEXTOPCODE
5700 OpEBmod1:
5701 lblEBmod1:      OpEBM1
5702                         NEXTOPCODE
5703 OpECX1mod1:
5704 lblECmod1a:     Absolute
5705 lblECmod1b:     CMX8
5706                         NEXTOPCODE
5707 OpEDM1mod1:
5708 lblEDmod1a:     Absolute
5709 lblEDmod1b:     SBC8
5710                         NEXTOPCODE
5711 OpEEM1mod1:
5712 lblEEmod1a:     Absolute
5713 lblEEmod1b:     INC8
5714                         NEXTOPCODE
5715 OpEFM1mod1:
5716 lblEFmod1a:     AbsoluteLong
5717 lblEFmod1b:     SBC8
5718                         NEXTOPCODE
5719 OpF0mod1:
5720 lblF0mod1:      OpF0
5721                         NEXTOPCODE
5722 OpF1M1mod1:
5723 lblF1mod1a:     DirectIndirectIndexed1
5724 lblF1mod1b:     SBC8
5725                         NEXTOPCODE
5726 OpF2M1mod1:
5727 lblF2mod1a:     DirectIndirect
5728 lblF2mod1b:     SBC8
5729                         NEXTOPCODE
5730 OpF3M1mod1:
5731 lblF3mod1a:     StackasmRelativeIndirectIndexed1
5732 lblF3mod1b:     SBC8
5733                         NEXTOPCODE
5734 OpF4mod1:
5735 lblF4mod1:      OpF4
5736                         NEXTOPCODE
5737 OpF5M1mod1:
5738 lblF5mod1a:     DirectIndexedX1
5739 lblF5mod1b:     SBC8
5740                         NEXTOPCODE
5741 OpF6M1mod1:
5742 lblF6mod1a:     DirectIndexedX1
5743 lblF6mod1b:     INC8
5744                         NEXTOPCODE
5745 OpF7M1mod1:
5746 lblF7mod1a:     DirectIndirectIndexedLong1
5747 lblF7mod1b:     SBC8
5748                         NEXTOPCODE
5749 OpF8mod1:
5750 lblF8mod1:      OpF8
5751                         NEXTOPCODE
5752 OpF9M1mod1:
5753 lblF9mod1a:     AbsoluteIndexedY1
5754 lblF9mod1b:     SBC8
5755                         NEXTOPCODE
5756 OpFAX1mod1:
5757 lblFAmod1:      OpFAX1
5758                         NEXTOPCODE
5759 OpFBmod1:
5760 lblFBmod1:      OpFB
5761                         NEXTOPCODE
5762 OpFCmod1:
5763 lblFCmod1:      OpFCX1
5764                         NEXTOPCODE
5765 OpFDM1mod1:
5766 lblFDmod1a:     AbsoluteIndexedX1
5767 lblFDmod1b:     SBC8
5768                         NEXTOPCODE
5769 OpFEM1mod1:
5770 lblFEmod1a:     AbsoluteIndexedX1
5771 lblFEmod1b:     INC8
5772                         NEXTOPCODE
5773 OpFFM1mod1:
5774 lblFFmod1a:     AbsoluteLongIndexedX1
5775 lblFFmod1b:     SBC8
5776                         NEXTOPCODE
5777 .pool
5778
5779
5780 jumptable2:             .long   Op00mod2
5781                         .long   Op01M1mod2
5782                         .long   Op02mod2
5783                         .long   Op03M1mod2
5784                         .long   Op04M1mod2
5785                         .long   Op05M1mod2
5786                         .long   Op06M1mod2
5787                         .long   Op07M1mod2
5788                         .long   Op08mod2
5789                         .long   Op09M1mod2
5790                         .long   Op0AM1mod2
5791                         .long   Op0Bmod2
5792                         .long   Op0CM1mod2
5793                         .long   Op0DM1mod2
5794                         .long   Op0EM1mod2
5795                         .long   Op0FM1mod2
5796                         .long   Op10mod2
5797                         .long   Op11M1mod2
5798                         .long   Op12M1mod2
5799                         .long   Op13M1mod2
5800                         .long   Op14M1mod2
5801                         .long   Op15M1mod2
5802                         .long   Op16M1mod2
5803                         .long   Op17M1mod2
5804                         .long   Op18mod2
5805                         .long   Op19M1mod2
5806                         .long   Op1AM1mod2
5807                         .long   Op1Bmod2
5808                         .long   Op1CM1mod2
5809                         .long   Op1DM1mod2
5810                         .long   Op1EM1mod2
5811                         .long   Op1FM1mod2
5812                         .long   Op20mod2
5813                         .long   Op21M1mod2
5814                         .long   Op22mod2
5815                         .long   Op23M1mod2
5816                         .long   Op24M1mod2
5817                         .long   Op25M1mod2
5818                         .long   Op26M1mod2
5819                         .long   Op27M1mod2
5820                         .long   Op28mod2
5821                         .long   Op29M1mod2
5822                         .long   Op2AM1mod2
5823                         .long   Op2Bmod2
5824                         .long   Op2CM1mod2
5825                         .long   Op2DM1mod2
5826                         .long   Op2EM1mod2
5827                         .long   Op2FM1mod2
5828                         .long   Op30mod2
5829                         .long   Op31M1mod2
5830                         .long   Op32M1mod2
5831                         .long   Op33M1mod2
5832                         .long   Op34M1mod2
5833                         .long   Op35M1mod2
5834                         .long   Op36M1mod2
5835                         .long   Op37M1mod2
5836                         .long   Op38mod2
5837                         .long   Op39M1mod2
5838                         .long   Op3AM1mod2
5839                         .long   Op3Bmod2
5840                         .long   Op3CM1mod2
5841                         .long   Op3DM1mod2
5842                         .long   Op3EM1mod2
5843                         .long   Op3FM1mod2
5844                         .long   Op40mod2
5845                         .long   Op41M1mod2
5846                         .long   Op42mod2
5847                         .long   Op43M1mod2
5848                         .long   Op44X0mod2
5849                         .long   Op45M1mod2
5850                         .long   Op46M1mod2
5851                         .long   Op47M1mod2
5852                         .long   Op48M1mod2
5853                         .long   Op49M1mod2
5854                         .long   Op4AM1mod2
5855                         .long   Op4Bmod2
5856                         .long   Op4Cmod2
5857                         .long   Op4DM1mod2
5858                         .long   Op4EM1mod2
5859                         .long   Op4FM1mod2
5860                         .long   Op50mod2
5861                         .long   Op51M1mod2
5862                         .long   Op52M1mod2
5863                         .long   Op53M1mod2
5864                         .long   Op54X0mod2
5865                         .long   Op55M1mod2
5866                         .long   Op56M1mod2
5867                         .long   Op57M1mod2
5868                         .long   Op58mod2
5869                         .long   Op59M1mod2
5870                         .long   Op5AX0mod2
5871                         .long   Op5Bmod2
5872                         .long   Op5Cmod2
5873                         .long   Op5DM1mod2
5874                         .long   Op5EM1mod2
5875                         .long   Op5FM1mod2
5876                         .long   Op60mod2
5877                         .long   Op61M1mod2
5878                         .long   Op62mod2
5879                         .long   Op63M1mod2
5880                         .long   Op64M1mod2
5881                         .long   Op65M1mod2
5882                         .long   Op66M1mod2
5883                         .long   Op67M1mod2
5884                         .long   Op68M1mod2
5885                         .long   Op69M1mod2
5886                         .long   Op6AM1mod2
5887                         .long   Op6Bmod2
5888                         .long   Op6Cmod2
5889                         .long   Op6DM1mod2
5890                         .long   Op6EM1mod2
5891                         .long   Op6FM1mod2
5892                         .long   Op70mod2
5893                         .long   Op71M1mod2
5894                         .long   Op72M1mod2
5895                         .long   Op73M1mod2
5896                         .long   Op74M1mod2
5897                         .long   Op75M1mod2
5898                         .long   Op76M1mod2
5899                         .long   Op77M1mod2
5900                         .long   Op78mod2
5901                         .long   Op79M1mod2
5902                         .long   Op7AX0mod2
5903                         .long   Op7Bmod2
5904                         .long   Op7Cmod2
5905                         .long   Op7DM1mod2
5906                         .long   Op7EM1mod2
5907                         .long   Op7FM1mod2
5908                         .long   Op80mod2
5909                         .long   Op81M1mod2
5910                         .long   Op82mod2
5911                         .long   Op83M1mod2
5912                         .long   Op84X0mod2
5913                         .long   Op85M1mod2
5914                         .long   Op86X0mod2
5915                         .long   Op87M1mod2
5916                         .long   Op88X0mod2
5917                         .long   Op89M1mod2
5918                         .long   Op8AM1mod2
5919                         .long   Op8Bmod2
5920                         .long   Op8CX0mod2
5921                         .long   Op8DM1mod2
5922                         .long   Op8EX0mod2
5923                         .long   Op8FM1mod2
5924                         .long   Op90mod2
5925                         .long   Op91M1mod2
5926                         .long   Op92M1mod2
5927                         .long   Op93M1mod2
5928                         .long   Op94X0mod2
5929                         .long   Op95M1mod2
5930                         .long   Op96X0mod2
5931                         .long   Op97M1mod2
5932                         .long   Op98M1mod2
5933                         .long   Op99M1mod2
5934                         .long   Op9Amod2
5935                         .long   Op9BX0mod2
5936                         .long   Op9CM1mod2
5937                         .long   Op9DM1mod2
5938                         .long   Op9EM1mod2
5939                         .long   Op9FM1mod2
5940                         .long   OpA0X0mod2
5941                         .long   OpA1M1mod2
5942                         .long   OpA2X0mod2
5943                         .long   OpA3M1mod2
5944                         .long   OpA4X0mod2
5945                         .long   OpA5M1mod2
5946                         .long   OpA6X0mod2
5947                         .long   OpA7M1mod2
5948                         .long   OpA8X0mod2
5949                         .long   OpA9M1mod2
5950                         .long   OpAAX0mod2
5951                         .long   OpABmod2
5952                         .long   OpACX0mod2
5953                         .long   OpADM1mod2
5954                         .long   OpAEX0mod2
5955                         .long   OpAFM1mod2
5956                         .long   OpB0mod2
5957                         .long   OpB1M1mod2
5958                         .long   OpB2M1mod2
5959                         .long   OpB3M1mod2
5960                         .long   OpB4X0mod2
5961                         .long   OpB5M1mod2
5962                         .long   OpB6X0mod2
5963                         .long   OpB7M1mod2
5964                         .long   OpB8mod2
5965                         .long   OpB9M1mod2
5966                         .long   OpBAX0mod2
5967                         .long   OpBBX0mod2
5968                         .long   OpBCX0mod2
5969                         .long   OpBDM1mod2
5970                         .long   OpBEX0mod2
5971                         .long   OpBFM1mod2
5972                         .long   OpC0X0mod2
5973                         .long   OpC1M1mod2
5974                         .long   OpC2mod2
5975                         .long   OpC3M1mod2
5976                         .long   OpC4X0mod2
5977                         .long   OpC5M1mod2
5978                         .long   OpC6M1mod2
5979                         .long   OpC7M1mod2
5980                         .long   OpC8X0mod2
5981                         .long   OpC9M1mod2
5982                         .long   OpCAX0mod2
5983                         .long   OpCBmod2
5984                         .long   OpCCX0mod2
5985                         .long   OpCDM1mod2
5986                         .long   OpCEM1mod2
5987                         .long   OpCFM1mod2
5988                         .long   OpD0mod2
5989                         .long   OpD1M1mod2
5990                         .long   OpD2M1mod2
5991                         .long   OpD3M1mod2
5992                         .long   OpD4mod2
5993                         .long   OpD5M1mod2
5994                         .long   OpD6M1mod2
5995                         .long   OpD7M1mod2
5996                         .long   OpD8mod2
5997                         .long   OpD9M1mod2
5998                         .long   OpDAX0mod2
5999                         .long   OpDBmod2
6000                         .long   OpDCmod2
6001                         .long   OpDDM1mod2
6002                         .long   OpDEM1mod2
6003                         .long   OpDFM1mod2
6004                         .long   OpE0X0mod2
6005                         .long   OpE1M1mod2
6006                         .long   OpE2mod2
6007                         .long   OpE3M1mod2
6008                         .long   OpE4X0mod2
6009                         .long   OpE5M1mod2
6010                         .long   OpE6M1mod2
6011                         .long   OpE7M1mod2
6012                         .long   OpE8X0mod2
6013                         .long   OpE9M1mod2
6014                         .long   OpEAmod2
6015                         .long   OpEBmod2
6016                         .long   OpECX0mod2
6017                         .long   OpEDM1mod2
6018                         .long   OpEEM1mod2
6019                         .long   OpEFM1mod2
6020                         .long   OpF0mod2
6021                         .long   OpF1M1mod2
6022                         .long   OpF2M1mod2
6023                         .long   OpF3M1mod2
6024                         .long   OpF4mod2
6025                         .long   OpF5M1mod2
6026                         .long   OpF6M1mod2
6027                         .long   OpF7M1mod2
6028                         .long   OpF8mod2
6029                         .long   OpF9M1mod2
6030                         .long   OpFAX0mod2
6031                         .long   OpFBmod2
6032                         .long   OpFCmod2
6033                         .long   OpFDM1mod2
6034                         .long   OpFEM1mod2
6035                         .long   OpFFM1mod2
6036 Op00mod2:
6037 lbl00mod2:      Op00
6038                         NEXTOPCODE
6039 Op01M1mod2:
6040 lbl01mod2a:     DirectIndexedIndirect0
6041 lbl01mod2b:     ORA8
6042                         NEXTOPCODE
6043 Op02mod2:
6044 lbl02mod2:      Op02
6045                         NEXTOPCODE
6046 Op03M1mod2:
6047 lbl03mod2a:     StackasmRelative
6048 lbl03mod2b:     ORA8
6049                         NEXTOPCODE
6050 Op04M1mod2:
6051 lbl04mod2a:     Direct
6052 lbl04mod2b:     TSB8
6053                         NEXTOPCODE
6054 Op05M1mod2:
6055 lbl05mod2a:     Direct
6056 lbl05mod2b:     ORA8
6057                         NEXTOPCODE
6058 Op06M1mod2:
6059 lbl06mod2a:     Direct
6060 lbl06mod2b:     ASL8
6061                         NEXTOPCODE
6062 Op07M1mod2:
6063 lbl07mod2a:     DirectIndirectLong
6064 lbl07mod2b:     ORA8
6065                         NEXTOPCODE
6066 Op08mod2:
6067 lbl08mod2:      Op08
6068                         NEXTOPCODE
6069 Op09M1mod2:
6070 lbl09mod2:      Op09M1
6071                         NEXTOPCODE
6072 Op0AM1mod2:
6073 lbl0Amod2a:     A_ASL8
6074                         NEXTOPCODE
6075 Op0Bmod2:
6076 lbl0Bmod2:      Op0B
6077                         NEXTOPCODE
6078 Op0CM1mod2:
6079 lbl0Cmod2a:     Absolute
6080 lbl0Cmod2b:     TSB8
6081                         NEXTOPCODE
6082 Op0DM1mod2:
6083 lbl0Dmod2a:     Absolute
6084 lbl0Dmod2b:     ORA8
6085                         NEXTOPCODE
6086 Op0EM1mod2:
6087 lbl0Emod2a:     Absolute
6088 lbl0Emod2b:     ASL8
6089                         NEXTOPCODE
6090 Op0FM1mod2:
6091 lbl0Fmod2a:     AbsoluteLong
6092 lbl0Fmod2b:     ORA8
6093                         NEXTOPCODE
6094 Op10mod2:
6095 lbl10mod2:      Op10
6096                         NEXTOPCODE
6097 Op11M1mod2:
6098 lbl11mod2a:     DirectIndirectIndexed0
6099 lbl11mod2b:     ORA8
6100                         NEXTOPCODE
6101 Op12M1mod2:
6102 lbl12mod2a:     DirectIndirect
6103 lbl12mod2b:     ORA8
6104                         NEXTOPCODE
6105 Op13M1mod2:
6106 lbl13mod2a:     StackasmRelativeIndirectIndexed0
6107 lbl13mod2b:     ORA8
6108                         NEXTOPCODE
6109 Op14M1mod2:
6110 lbl14mod2a:     Direct
6111 lbl14mod2b:     TRB8
6112                         NEXTOPCODE
6113 Op15M1mod2:
6114 lbl15mod2a:     DirectIndexedX0
6115 lbl15mod2b:     ORA8
6116                         NEXTOPCODE
6117 Op16M1mod2:
6118 lbl16mod2a:     DirectIndexedX0
6119 lbl16mod2b:     ASL8
6120                         NEXTOPCODE
6121 Op17M1mod2:
6122 lbl17mod2a:     DirectIndirectIndexedLong0
6123 lbl17mod2b:     ORA8
6124                         NEXTOPCODE
6125 Op18mod2:
6126 lbl18mod2:      Op18
6127                         NEXTOPCODE
6128 Op19M1mod2:
6129 lbl19mod2a:     AbsoluteIndexedY0
6130 lbl19mod2b:     ORA8
6131                         NEXTOPCODE
6132 Op1AM1mod2:
6133 lbl1Amod2a:     A_INC8
6134                         NEXTOPCODE
6135 Op1Bmod2:
6136 lbl1Bmod2:      Op1BM1
6137                         NEXTOPCODE
6138 Op1CM1mod2:
6139 lbl1Cmod2a:     Absolute
6140 lbl1Cmod2b:     TRB8
6141                         NEXTOPCODE
6142 Op1DM1mod2:
6143 lbl1Dmod2a:     AbsoluteIndexedX0
6144 lbl1Dmod2b:     ORA8
6145                         NEXTOPCODE
6146 Op1EM1mod2:
6147 lbl1Emod2a:     AbsoluteIndexedX0
6148 lbl1Emod2b:     ASL8
6149                         NEXTOPCODE
6150 Op1FM1mod2:
6151 lbl1Fmod2a:     AbsoluteLongIndexedX0
6152 lbl1Fmod2b:     ORA8
6153                         NEXTOPCODE
6154 Op20mod2:
6155 lbl20mod2:      Op20
6156                         NEXTOPCODE
6157 Op21M1mod2:
6158 lbl21mod2a:     DirectIndexedIndirect0
6159 lbl21mod2b:     AND8
6160                         NEXTOPCODE
6161 Op22mod2:
6162 lbl22mod2:      Op22
6163                         NEXTOPCODE
6164 Op23M1mod2:
6165 lbl23mod2a:     StackasmRelative
6166 lbl23mod2b:     AND8
6167                         NEXTOPCODE
6168 Op24M1mod2:
6169 lbl24mod2a:     Direct
6170 lbl24mod2b:     BIT8
6171                         NEXTOPCODE
6172 Op25M1mod2:
6173 lbl25mod2a:     Direct
6174 lbl25mod2b:     AND8
6175                         NEXTOPCODE
6176 Op26M1mod2:
6177 lbl26mod2a:     Direct
6178 lbl26mod2b:     ROL8
6179                         NEXTOPCODE
6180 Op27M1mod2:
6181 lbl27mod2a:     DirectIndirectLong
6182 lbl27mod2b:     AND8
6183                         NEXTOPCODE
6184 Op28mod2:
6185 lbl28mod2:      Op28X0M1
6186                         NEXTOPCODE
6187 .pool
6188 Op29M1mod2:
6189 lbl29mod2:      Op29M1
6190                         NEXTOPCODE
6191 Op2AM1mod2:
6192 lbl2Amod2a:     A_ROL8
6193                         NEXTOPCODE
6194 Op2Bmod2:
6195 lbl2Bmod2:      Op2B
6196                         NEXTOPCODE
6197 Op2CM1mod2:
6198 lbl2Cmod2a:     Absolute
6199 lbl2Cmod2b:     BIT8
6200                         NEXTOPCODE
6201 Op2DM1mod2:
6202 lbl2Dmod2a:     Absolute
6203 lbl2Dmod2b:     AND8
6204                         NEXTOPCODE
6205 Op2EM1mod2:
6206 lbl2Emod2a:     Absolute
6207 lbl2Emod2b:     ROL8
6208                         NEXTOPCODE
6209 Op2FM1mod2:
6210 lbl2Fmod2a:     AbsoluteLong
6211 lbl2Fmod2b:     AND8
6212                         NEXTOPCODE
6213 Op30mod2:
6214 lbl30mod2:      Op30
6215                         NEXTOPCODE
6216 Op31M1mod2:
6217 lbl31mod2a:     DirectIndirectIndexed0
6218 lbl31mod2b:     AND8
6219                         NEXTOPCODE
6220 Op32M1mod2:
6221 lbl32mod2a:     DirectIndirect
6222 lbl32mod2b:     AND8
6223                         NEXTOPCODE
6224 Op33M1mod2:
6225 lbl33mod2a:     StackasmRelativeIndirectIndexed0
6226 lbl33mod2b:     AND8
6227                         NEXTOPCODE
6228 Op34M1mod2:
6229 lbl34mod2a:     DirectIndexedX0
6230 lbl34mod2b:     BIT8
6231                         NEXTOPCODE
6232 Op35M1mod2:
6233 lbl35mod2a:     DirectIndexedX0
6234 lbl35mod2b:     AND8
6235                         NEXTOPCODE
6236 Op36M1mod2:
6237 lbl36mod2a:     DirectIndexedX0
6238 lbl36mod2b:     ROL8
6239                         NEXTOPCODE
6240 Op37M1mod2:
6241 lbl37mod2a:     DirectIndirectIndexedLong0
6242 lbl37mod2b:     AND8
6243                         NEXTOPCODE
6244 Op38mod2:
6245 lbl38mod2:      Op38
6246                         NEXTOPCODE
6247 Op39M1mod2:
6248 lbl39mod2a:     AbsoluteIndexedY0
6249 lbl39mod2b:     AND8
6250                         NEXTOPCODE
6251 Op3AM1mod2:
6252 lbl3Amod2a:     A_DEC8
6253                         NEXTOPCODE
6254 Op3Bmod2:
6255 lbl3Bmod2:      Op3BM1
6256                         NEXTOPCODE
6257 Op3CM1mod2:
6258 lbl3Cmod2a:     AbsoluteIndexedX0
6259 lbl3Cmod2b:     BIT8
6260                         NEXTOPCODE
6261 Op3DM1mod2:
6262 lbl3Dmod2a:     AbsoluteIndexedX0
6263 lbl3Dmod2b:     AND8
6264                         NEXTOPCODE
6265 Op3EM1mod2:
6266 lbl3Emod2a:     AbsoluteIndexedX0
6267 lbl3Emod2b:     ROL8
6268                         NEXTOPCODE
6269 Op3FM1mod2:
6270 lbl3Fmod2a:     AbsoluteLongIndexedX0
6271 lbl3Fmod2b:     AND8
6272                         NEXTOPCODE
6273 Op40mod2:
6274 lbl40mod2:      Op40X0M1
6275                         NEXTOPCODE
6276 .pool
6277 Op41M1mod2:
6278 lbl41mod2a:     DirectIndexedIndirect0
6279 lbl41mod2b:     EOR8
6280                         NEXTOPCODE
6281 Op42mod2:
6282 lbl42mod2:      Op42
6283                         NEXTOPCODE
6284 Op43M1mod2:
6285 lbl43mod2a:     StackasmRelative
6286 lbl43mod2b:     EOR8
6287                         NEXTOPCODE
6288 Op44X0mod2:
6289 lbl44mod2:      Op44X0M1
6290                         NEXTOPCODE
6291 Op45M1mod2:
6292 lbl45mod2a:     Direct
6293 lbl45mod2b:     EOR8
6294                         NEXTOPCODE
6295 Op46M1mod2:
6296 lbl46mod2a:     Direct
6297 lbl46mod2b:     LSR8
6298                         NEXTOPCODE
6299 Op47M1mod2:
6300 lbl47mod2a:     DirectIndirectLong
6301 lbl47mod2b:     EOR8
6302                         NEXTOPCODE
6303 Op48M1mod2:
6304 lbl48mod2:      Op48M1
6305                         NEXTOPCODE
6306 Op49M1mod2:
6307 lbl49mod2:      Op49M1
6308                         NEXTOPCODE
6309 Op4AM1mod2:
6310 lbl4Amod2a:     A_LSR8
6311                         NEXTOPCODE
6312 Op4Bmod2:
6313 lbl4Bmod2:      Op4B
6314                         NEXTOPCODE
6315 Op4Cmod2:
6316 lbl4Cmod2:      Op4C
6317                         NEXTOPCODE
6318 Op4DM1mod2:
6319 lbl4Dmod2a:     Absolute
6320 lbl4Dmod2b:     EOR8
6321                         NEXTOPCODE
6322 Op4EM1mod2:
6323 lbl4Emod2a:     Absolute
6324 lbl4Emod2b:     LSR8
6325                         NEXTOPCODE
6326 Op4FM1mod2:
6327 lbl4Fmod2a:     AbsoluteLong
6328 lbl4Fmod2b:     EOR8
6329                         NEXTOPCODE
6330 Op50mod2:
6331 lbl50mod2:      Op50
6332                         NEXTOPCODE
6333 Op51M1mod2:
6334 lbl51mod2a:     DirectIndirectIndexed0
6335 lbl51mod2b:     EOR8
6336                         NEXTOPCODE
6337 Op52M1mod2:
6338 lbl52mod2a:     DirectIndirect
6339 lbl52mod2b:     EOR8
6340                         NEXTOPCODE
6341 Op53M1mod2:
6342 lbl53mod2a:     StackasmRelativeIndirectIndexed0
6343 lbl53mod2b:     EOR8
6344                         NEXTOPCODE
6345 Op54X0mod2:
6346 lbl54mod2:      Op54X0M1
6347                         NEXTOPCODE
6348 Op55M1mod2:
6349 lbl55mod2a:     DirectIndexedX0
6350 lbl55mod2b:     EOR8
6351                         NEXTOPCODE
6352 Op56M1mod2:
6353 lbl56mod2a:     DirectIndexedX0
6354 lbl56mod2b:     LSR8
6355                         NEXTOPCODE
6356 Op57M1mod2:
6357 lbl57mod2a:     DirectIndirectIndexedLong0
6358 lbl57mod2b:     EOR8
6359                         NEXTOPCODE
6360 Op58mod2:
6361 lbl58mod2:      Op58
6362                         NEXTOPCODE
6363 Op59M1mod2:
6364 lbl59mod2a:     AbsoluteIndexedY0
6365 lbl59mod2b:     EOR8
6366                         NEXTOPCODE
6367 Op5AX0mod2:
6368 lbl5Amod2:      Op5AX0
6369                         NEXTOPCODE
6370 Op5Bmod2:
6371 lbl5Bmod2:      Op5BM1
6372                         NEXTOPCODE
6373 Op5Cmod2:
6374 lbl5Cmod2:      Op5C
6375                         NEXTOPCODE
6376 Op5DM1mod2:
6377 lbl5Dmod2a:     AbsoluteIndexedX0
6378 lbl5Dmod2b:     EOR8
6379                         NEXTOPCODE
6380 Op5EM1mod2:
6381 lbl5Emod2a:     AbsoluteIndexedX0
6382 lbl5Emod2b:     LSR8
6383                         NEXTOPCODE
6384 Op5FM1mod2:
6385 lbl5Fmod2a:     AbsoluteLongIndexedX0
6386 lbl5Fmod2b:     EOR8
6387                         NEXTOPCODE
6388 Op60mod2:
6389 lbl60mod2:      Op60
6390                         NEXTOPCODE
6391 Op61M1mod2:
6392 lbl61mod2a:     DirectIndexedIndirect0
6393 lbl61mod2b:     ADC8
6394                         NEXTOPCODE
6395 Op62mod2:
6396 lbl62mod2:      Op62
6397                         NEXTOPCODE
6398 Op63M1mod2:
6399 lbl63mod2a:     StackasmRelative
6400 lbl63mod2b:     ADC8
6401                         NEXTOPCODE
6402 Op64M1mod2:
6403 lbl64mod2a:     Direct
6404 lbl64mod2b:     STZ8
6405                         NEXTOPCODE
6406 Op65M1mod2:
6407 lbl65mod2a:     Direct
6408 lbl65mod2b:     ADC8
6409                         NEXTOPCODE
6410 Op66M1mod2:
6411 lbl66mod2a:     Direct
6412 lbl66mod2b:     ROR8
6413                         NEXTOPCODE
6414 Op67M1mod2:
6415 lbl67mod2a:     DirectIndirectLong
6416 lbl67mod2b:     ADC8
6417                         NEXTOPCODE
6418 Op68M1mod2:
6419 lbl68mod2:      Op68M1
6420                         NEXTOPCODE
6421 Op69M1mod2:
6422 lbl69mod2a:     Immediate8
6423 lbl69mod2b:     ADC8
6424                         NEXTOPCODE
6425 Op6AM1mod2:
6426 lbl6Amod2a:     A_ROR8
6427                         NEXTOPCODE
6428 Op6Bmod2:
6429 lbl6Bmod2:      Op6B
6430                         NEXTOPCODE
6431 Op6Cmod2:
6432 lbl6Cmod2:      Op6C
6433                         NEXTOPCODE
6434 Op6DM1mod2:
6435 lbl6Dmod2a:     Absolute
6436 lbl6Dmod2b:     ADC8
6437                         NEXTOPCODE
6438 Op6EM1mod2:
6439 lbl6Emod2a:     Absolute
6440 lbl6Emod2b:     ROR8
6441                         NEXTOPCODE
6442 Op6FM1mod2:
6443 lbl6Fmod2a:     AbsoluteLong
6444 lbl6Fmod2b:     ADC8
6445                         NEXTOPCODE
6446 Op70mod2:
6447 lbl70mod2:      Op70
6448                         NEXTOPCODE
6449 Op71M1mod2:
6450 lbl71mod2a:     DirectIndirectIndexed0
6451 lbl71mod2b:     ADC8
6452                         NEXTOPCODE
6453 Op72M1mod2:
6454 lbl72mod2a:     DirectIndirect
6455 lbl72mod2b:     ADC8
6456                         NEXTOPCODE
6457 Op73M1mod2:
6458 lbl73mod2a:     StackasmRelativeIndirectIndexed0
6459 lbl73mod2b:     ADC8
6460                         NEXTOPCODE
6461 Op74M1mod2:
6462 lbl74mod2a:     DirectIndexedX0
6463 lbl74mod2b:     STZ8
6464                         NEXTOPCODE
6465 Op75M1mod2:
6466 lbl75mod2a:     DirectIndexedX0
6467 lbl75mod2b:     ADC8
6468                         NEXTOPCODE
6469 Op76M1mod2:
6470 lbl76mod2a:     DirectIndexedX0
6471 lbl76mod2b:     ROR8
6472                         NEXTOPCODE
6473 Op77M1mod2:
6474 lbl77mod2a:     DirectIndirectIndexedLong0
6475 lbl77mod2b:     ADC8
6476                         NEXTOPCODE
6477 Op78mod2:
6478 lbl78mod2:      Op78
6479                         NEXTOPCODE
6480 Op79M1mod2:
6481 lbl79mod2a:     AbsoluteIndexedY0
6482 lbl79mod2b:     ADC8
6483                         NEXTOPCODE
6484 Op7AX0mod2:
6485 lbl7Amod2:      Op7AX0
6486                         NEXTOPCODE
6487 Op7Bmod2:
6488 lbl7Bmod2:      Op7BM1
6489                         NEXTOPCODE
6490 Op7Cmod2:
6491 lbl7Cmod2:      AbsoluteIndexedIndirectX0
6492                 Op7C
6493                         NEXTOPCODE
6494 Op7DM1mod2:
6495 lbl7Dmod2a:     AbsoluteIndexedX0
6496 lbl7Dmod2b:     ADC8
6497                         NEXTOPCODE
6498 Op7EM1mod2:
6499 lbl7Emod2a:     AbsoluteIndexedX0
6500 lbl7Emod2b:     ROR8
6501                         NEXTOPCODE
6502 Op7FM1mod2:
6503 lbl7Fmod2a:     AbsoluteLongIndexedX0
6504 lbl7Fmod2b:     ADC8
6505                         NEXTOPCODE
6506
6507
6508 Op80mod2:
6509 lbl80mod2:      Op80
6510                         NEXTOPCODE
6511 Op81M1mod2:
6512 lbl81mod2a:     DirectIndexedIndirect0
6513 lbl81mod2b:     Op81M1
6514                         NEXTOPCODE
6515 Op82mod2:
6516 lbl82mod2:      Op82
6517                         NEXTOPCODE
6518 Op83M1mod2:
6519 lbl83mod2a:     StackasmRelative
6520 lbl83mod2b:     STA8
6521                         NEXTOPCODE
6522 Op84X0mod2:
6523 lbl84mod2a:     Direct
6524 lbl84mod2b:     STY16
6525                         NEXTOPCODE
6526 Op85M1mod2:
6527 lbl85mod2a:     Direct
6528 lbl85mod2b:     STA8
6529                         NEXTOPCODE
6530 Op86X0mod2:
6531 lbl86mod2a:     Direct
6532 lbl86mod2b:     STX16
6533                         NEXTOPCODE
6534 Op87M1mod2:
6535 lbl87mod2a:     DirectIndirectLong
6536 lbl87mod2b:     STA8
6537                         NEXTOPCODE
6538 Op88X0mod2:
6539 lbl88mod2:      Op88X0
6540                         NEXTOPCODE
6541 Op89M1mod2:
6542 lbl89mod2:      Op89M1
6543                         NEXTOPCODE
6544 Op8AM1mod2:
6545 lbl8Amod2:      Op8AM1X0
6546                         NEXTOPCODE
6547 Op8Bmod2:
6548 lbl8Bmod2:      Op8B
6549                         NEXTOPCODE
6550 Op8CX0mod2:
6551 lbl8Cmod2a:     Absolute
6552 lbl8Cmod2b:     STY16
6553                         NEXTOPCODE
6554 Op8DM1mod2:
6555 lbl8Dmod2a:     Absolute
6556 lbl8Dmod2b:     STA8
6557                         NEXTOPCODE
6558 Op8EX0mod2:
6559 lbl8Emod2a:     Absolute
6560 lbl8Emod2b:     STX16
6561                         NEXTOPCODE
6562 Op8FM1mod2:
6563 lbl8Fmod2a:     AbsoluteLong
6564 lbl8Fmod2b:     STA8
6565                         NEXTOPCODE
6566 Op90mod2:
6567 lbl90mod2:      Op90
6568                         NEXTOPCODE
6569 Op91M1mod2:
6570 lbl91mod2a:     DirectIndirectIndexed0
6571 lbl91mod2b:     STA8
6572                         NEXTOPCODE
6573 Op92M1mod2:
6574 lbl92mod2a:     DirectIndirect
6575 lbl92mod2b:     STA8
6576                         NEXTOPCODE
6577 Op93M1mod2:
6578 lbl93mod2a:     StackasmRelativeIndirectIndexed0
6579 lbl93mod2b:     STA8
6580                         NEXTOPCODE
6581 Op94X0mod2:
6582 lbl94mod2a:     DirectIndexedX0
6583 lbl94mod2b:     STY16
6584                         NEXTOPCODE
6585 Op95M1mod2:
6586 lbl95mod2a:     DirectIndexedX0
6587 lbl95mod2b:     STA8
6588                         NEXTOPCODE
6589 Op96X0mod2:
6590 lbl96mod2a:     DirectIndexedY0
6591 lbl96mod2b:     STX16
6592                         NEXTOPCODE
6593 Op97M1mod2:
6594 lbl97mod2a:     DirectIndirectIndexedLong0
6595 lbl97mod2b:     STA8
6596                         NEXTOPCODE
6597 Op98M1mod2:
6598 lbl98mod2:      Op98M1X0
6599                         NEXTOPCODE
6600 Op99M1mod2:
6601 lbl99mod2a:     AbsoluteIndexedY0
6602 lbl99mod2b:     STA8
6603                         NEXTOPCODE
6604 Op9Amod2:
6605 lbl9Amod2:      Op9AX0
6606                         NEXTOPCODE
6607 Op9BX0mod2:
6608 lbl9Bmod2:      Op9BX0
6609                         NEXTOPCODE
6610 Op9CM1mod2:
6611 lbl9Cmod2a:     Absolute
6612 lbl9Cmod2b:     STZ8
6613                         NEXTOPCODE
6614 Op9DM1mod2:
6615 lbl9Dmod2a:     AbsoluteIndexedX0
6616 lbl9Dmod2b:     STA8
6617                         NEXTOPCODE
6618 Op9EM1mod2:
6619 lbl9Emod2:      AbsoluteIndexedX0
6620                 STZ8
6621                         NEXTOPCODE
6622 Op9FM1mod2:
6623 lbl9Fmod2a:     AbsoluteLongIndexedX0
6624 lbl9Fmod2b:     STA8
6625                         NEXTOPCODE
6626 OpA0X0mod2:
6627 lblA0mod2:      OpA0X0
6628                         NEXTOPCODE
6629 OpA1M1mod2:
6630 lblA1mod2a:     DirectIndexedIndirect0
6631 lblA1mod2b:     LDA8
6632                         NEXTOPCODE
6633 OpA2X0mod2:
6634 lblA2mod2:      OpA2X0
6635                         NEXTOPCODE
6636 OpA3M1mod2:
6637 lblA3mod2a:     StackasmRelative
6638 lblA3mod2b:     LDA8
6639                         NEXTOPCODE
6640 OpA4X0mod2:
6641 lblA4mod2a:     Direct
6642 lblA4mod2b:     LDY16
6643                         NEXTOPCODE
6644 OpA5M1mod2:
6645 lblA5mod2a:     Direct
6646 lblA5mod2b:     LDA8
6647                         NEXTOPCODE
6648 OpA6X0mod2:
6649 lblA6mod2a:     Direct
6650 lblA6mod2b:     LDX16
6651                         NEXTOPCODE
6652 OpA7M1mod2:
6653 lblA7mod2a:     DirectIndirectLong
6654 lblA7mod2b:     LDA8
6655                         NEXTOPCODE
6656 OpA8X0mod2:
6657 lblA8mod2:      OpA8X0M1
6658                         NEXTOPCODE
6659 OpA9M1mod2:
6660 lblA9mod2:      OpA9M1
6661                         NEXTOPCODE
6662 OpAAX0mod2:
6663 lblAAmod2:      OpAAX0M1
6664                         NEXTOPCODE
6665 OpABmod2:
6666 lblABmod2:      OpAB
6667                         NEXTOPCODE
6668 OpACX0mod2:
6669 lblACmod2a:     Absolute
6670 lblACmod2b:     LDY16
6671                         NEXTOPCODE
6672 OpADM1mod2:
6673 lblADmod2a:     Absolute
6674 lblADmod2b:     LDA8
6675                         NEXTOPCODE
6676 OpAEX0mod2:
6677 lblAEmod2a:     Absolute
6678 lblAEmod2b:     LDX16
6679                         NEXTOPCODE
6680 OpAFM1mod2:
6681 lblAFmod2a:     AbsoluteLong
6682 lblAFmod2b:     LDA8
6683                         NEXTOPCODE
6684 OpB0mod2:
6685 lblB0mod2:      OpB0
6686                         NEXTOPCODE
6687 OpB1M1mod2:
6688 lblB1mod2a:     DirectIndirectIndexed0
6689 lblB1mod2b:     LDA8
6690                         NEXTOPCODE
6691 OpB2M1mod2:
6692 lblB2mod2a:     DirectIndirect
6693 lblB2mod2b:     LDA8
6694                         NEXTOPCODE
6695 OpB3M1mod2:
6696 lblB3mod2a:     StackasmRelativeIndirectIndexed0
6697 lblB3mod2b:     LDA8
6698                         NEXTOPCODE
6699 OpB4X0mod2:
6700 lblB4mod2a:     DirectIndexedX0
6701 lblB4mod2b:     LDY16
6702                         NEXTOPCODE
6703 OpB5M1mod2:
6704 lblB5mod2a:     DirectIndexedX0
6705 lblB5mod2b:     LDA8
6706                         NEXTOPCODE
6707 OpB6X0mod2:
6708 lblB6mod2a:     DirectIndexedY0
6709 lblB6mod2b:     LDX16
6710                         NEXTOPCODE
6711 OpB7M1mod2:
6712 lblB7mod2a:     DirectIndirectIndexedLong0
6713 lblB7mod2b:     LDA8
6714                         NEXTOPCODE
6715 OpB8mod2:
6716 lblB8mod2:      OpB8
6717                         NEXTOPCODE
6718 OpB9M1mod2:
6719 lblB9mod2a:     AbsoluteIndexedY0
6720 lblB9mod2b:     LDA8
6721                         NEXTOPCODE
6722 OpBAX0mod2:
6723 lblBAmod2:      OpBAX0
6724                         NEXTOPCODE
6725 OpBBX0mod2:
6726 lblBBmod2:      OpBBX0
6727                         NEXTOPCODE
6728 OpBCX0mod2:
6729 lblBCmod2a:     AbsoluteIndexedX0
6730 lblBCmod2b:     LDY16
6731                         NEXTOPCODE
6732 OpBDM1mod2:
6733 lblBDmod2a:     AbsoluteIndexedX0
6734 lblBDmod2b:     LDA8
6735                         NEXTOPCODE
6736 OpBEX0mod2:
6737 lblBEmod2a:     AbsoluteIndexedY0
6738 lblBEmod2b:     LDX16
6739                         NEXTOPCODE
6740 OpBFM1mod2:
6741 lblBFmod2a:     AbsoluteLongIndexedX0
6742 lblBFmod2b:     LDA8
6743                         NEXTOPCODE
6744 OpC0X0mod2:
6745 lblC0mod2:      OpC0X0
6746                         NEXTOPCODE
6747 OpC1M1mod2:
6748 lblC1mod2a:     DirectIndexedIndirect0
6749 lblC1mod2b:     CMP8
6750                         NEXTOPCODE
6751 OpC2mod2:
6752 lblC2mod2:      OpC2
6753                         NEXTOPCODE
6754 .pool
6755 OpC3M1mod2:
6756 lblC3mod2a:     StackasmRelative
6757 lblC3mod2b:     CMP8
6758                         NEXTOPCODE
6759 OpC4X0mod2:
6760 lblC4mod2a:     Direct
6761 lblC4mod2b:     CMY16
6762                         NEXTOPCODE
6763 OpC5M1mod2:
6764 lblC5mod2a:     Direct
6765 lblC5mod2b:     CMP8
6766                         NEXTOPCODE
6767 OpC6M1mod2:
6768 lblC6mod2a:     Direct
6769 lblC6mod2b:     DEC8
6770                         NEXTOPCODE
6771 OpC7M1mod2:
6772 lblC7mod2a:     DirectIndirectLong
6773 lblC7mod2b:     CMP8
6774                         NEXTOPCODE
6775 OpC8X0mod2:
6776 lblC8mod2:      OpC8X0
6777                         NEXTOPCODE
6778 OpC9M1mod2:
6779 lblC9mod2:      OpC9M1
6780                         NEXTOPCODE
6781 OpCAX0mod2:
6782 lblCAmod2:      OpCAX0
6783                         NEXTOPCODE
6784 OpCBmod2:
6785 lblCBmod2:      OpCB
6786                         NEXTOPCODE
6787 OpCCX0mod2:
6788 lblCCmod2a:     Absolute
6789 lblCCmod2b:     CMY16
6790                         NEXTOPCODE
6791 OpCDM1mod2:
6792 lblCDmod2a:     Absolute
6793 lblCDmod2b:     CMP8
6794                         NEXTOPCODE
6795 OpCEM1mod2:
6796 lblCEmod2a:     Absolute
6797 lblCEmod2b:     DEC8
6798                         NEXTOPCODE
6799 OpCFM1mod2:
6800 lblCFmod2a:     AbsoluteLong
6801 lblCFmod2b:     CMP8
6802                         NEXTOPCODE
6803 OpD0mod2:
6804 lblD0mod2:      OpD0
6805                         NEXTOPCODE
6806 OpD1M1mod2:
6807 lblD1mod2a:     DirectIndirectIndexed0
6808 lblD1mod2b:     CMP8
6809                         NEXTOPCODE
6810 OpD2M1mod2:
6811 lblD2mod2a:     DirectIndirect
6812 lblD2mod2b:     CMP8
6813                         NEXTOPCODE
6814 OpD3M1mod2:
6815 lblD3mod2a:     StackasmRelativeIndirectIndexed0
6816 lblD3mod2b:     CMP8
6817                         NEXTOPCODE
6818 OpD4mod2:
6819 lblD4mod2:      OpD4
6820                         NEXTOPCODE
6821 OpD5M1mod2:
6822 lblD5mod2a:     DirectIndexedX0
6823 lblD5mod2b:     CMP8
6824                         NEXTOPCODE
6825 OpD6M1mod2:
6826 lblD6mod2a:     DirectIndexedX0
6827 lblD6mod2b:     DEC8
6828                         NEXTOPCODE
6829 OpD7M1mod2:
6830 lblD7mod2a:     DirectIndirectIndexedLong0
6831 lblD7mod2b:     CMP8
6832                         NEXTOPCODE
6833 OpD8mod2:
6834 lblD8mod2:      OpD8
6835                         NEXTOPCODE
6836 OpD9M1mod2:
6837 lblD9mod2a:     AbsoluteIndexedY0
6838 lblD9mod2b:     CMP8
6839                         NEXTOPCODE
6840 OpDAX0mod2:
6841 lblDAmod2:      OpDAX0
6842                         NEXTOPCODE
6843 OpDBmod2:
6844 lblDBmod2:      OpDB
6845                         NEXTOPCODE
6846 OpDCmod2:
6847 lblDCmod2:      OpDC
6848                         NEXTOPCODE
6849 OpDDM1mod2:
6850 lblDDmod2a:     AbsoluteIndexedX0
6851 lblDDmod2b:     CMP8
6852                         NEXTOPCODE
6853 OpDEM1mod2:
6854 lblDEmod2a:     AbsoluteIndexedX0
6855 lblDEmod2b:     DEC8
6856                         NEXTOPCODE
6857 OpDFM1mod2:
6858 lblDFmod2a:     AbsoluteLongIndexedX0
6859 lblDFmod2b:     CMP8
6860                         NEXTOPCODE
6861 OpE0X0mod2:
6862 lblE0mod2:      OpE0X0
6863                         NEXTOPCODE
6864 OpE1M1mod2:
6865 lblE1mod2a:     DirectIndexedIndirect0
6866 lblE1mod2b:     SBC8
6867                         NEXTOPCODE
6868 OpE2mod2:
6869 lblE2mod2:      OpE2
6870                         NEXTOPCODE
6871 .pool
6872 OpE3M1mod2:
6873 lblE3mod2a:     StackasmRelative
6874 lblE3mod2b:     SBC8
6875                         NEXTOPCODE
6876 OpE4X0mod2:
6877 lblE4mod2a:     Direct
6878 lblE4mod2b:     CMX16
6879                         NEXTOPCODE
6880 OpE5M1mod2:
6881 lblE5mod2a:     Direct
6882 lblE5mod2b:     SBC8
6883                         NEXTOPCODE
6884 OpE6M1mod2:
6885 lblE6mod2a:     Direct
6886 lblE6mod2b:     INC8
6887                         NEXTOPCODE
6888 OpE7M1mod2:
6889 lblE7mod2a:     DirectIndirectLong
6890 lblE7mod2b:     SBC8
6891                         NEXTOPCODE
6892 OpE8X0mod2:
6893 lblE8mod2:      OpE8X0
6894                         NEXTOPCODE
6895 OpE9M1mod2:
6896 lblE9mod2a:     Immediate8
6897 lblE9mod2b:     SBC8
6898                         NEXTOPCODE
6899 OpEAmod2:
6900 lblEAmod2:      OpEA
6901                         NEXTOPCODE
6902 OpEBmod2:
6903 lblEBmod2:      OpEBM1
6904                         NEXTOPCODE
6905 OpECX0mod2:
6906 lblECmod2a:     Absolute
6907 lblECmod2b:     CMX16
6908                         NEXTOPCODE
6909 OpEDM1mod2:
6910 lblEDmod2a:     Absolute
6911 lblEDmod2b:     SBC8
6912                         NEXTOPCODE
6913 OpEEM1mod2:
6914 lblEEmod2a:     Absolute
6915 lblEEmod2b:     INC8
6916                         NEXTOPCODE
6917 OpEFM1mod2:
6918 lblEFmod2a:     AbsoluteLong
6919 lblEFmod2b:     SBC8
6920                         NEXTOPCODE
6921 OpF0mod2:
6922 lblF0mod2:      OpF0
6923                         NEXTOPCODE
6924 OpF1M1mod2:
6925 lblF1mod2a:     DirectIndirectIndexed0
6926 lblF1mod2b:     SBC8
6927                         NEXTOPCODE
6928 OpF2M1mod2:
6929 lblF2mod2a:     DirectIndirect
6930 lblF2mod2b:     SBC8
6931                         NEXTOPCODE
6932 OpF3M1mod2:
6933 lblF3mod2a:     StackasmRelativeIndirectIndexed0
6934 lblF3mod2b:     SBC8
6935                         NEXTOPCODE
6936 OpF4mod2:
6937 lblF4mod2:      OpF4
6938                         NEXTOPCODE
6939 OpF5M1mod2:
6940 lblF5mod2a:     DirectIndexedX0
6941 lblF5mod2b:     SBC8
6942                         NEXTOPCODE
6943 OpF6M1mod2:
6944 lblF6mod2a:     DirectIndexedX0
6945 lblF6mod2b:     INC8
6946                         NEXTOPCODE
6947 OpF7M1mod2:
6948 lblF7mod2a:     DirectIndirectIndexedLong0
6949 lblF7mod2b:     SBC8
6950                         NEXTOPCODE
6951 OpF8mod2:
6952 lblF8mod2:      OpF8
6953                         NEXTOPCODE
6954 OpF9M1mod2:
6955 lblF9mod2a:     AbsoluteIndexedY0
6956 lblF9mod2b:     SBC8
6957                         NEXTOPCODE
6958 OpFAX0mod2:
6959 lblFAmod2:      OpFAX0
6960                         NEXTOPCODE
6961 OpFBmod2:
6962 lblFBmod2:      OpFB
6963                         NEXTOPCODE
6964 OpFCmod2:
6965 lblFCmod2:      OpFCX0
6966                         NEXTOPCODE
6967 OpFDM1mod2:
6968 lblFDmod2a:     AbsoluteIndexedX0
6969 lblFDmod2b:     SBC8
6970                         NEXTOPCODE
6971 OpFEM1mod2:
6972 lblFEmod2a:     AbsoluteIndexedX0
6973 lblFEmod2b:     INC8
6974                         NEXTOPCODE
6975 OpFFM1mod2:
6976 lblFFmod2a:     AbsoluteLongIndexedX0
6977 lblFFmod2b:     SBC8
6978                         NEXTOPCODE
6979
6980 .pool
6981
6982
6983 jumptable3:             .long   Op00mod3
6984                         .long   Op01M0mod3
6985                         .long   Op02mod3
6986                         .long   Op03M0mod3
6987                         .long   Op04M0mod3
6988                         .long   Op05M0mod3
6989                         .long   Op06M0mod3
6990                         .long   Op07M0mod3
6991                         .long   Op08mod3
6992                         .long   Op09M0mod3
6993                         .long   Op0AM0mod3
6994                         .long   Op0Bmod3
6995                         .long   Op0CM0mod3
6996                         .long   Op0DM0mod3
6997                         .long   Op0EM0mod3
6998                         .long   Op0FM0mod3
6999                         .long   Op10mod3
7000                         .long   Op11M0mod3
7001                         .long   Op12M0mod3
7002                         .long   Op13M0mod3
7003                         .long   Op14M0mod3
7004                         .long   Op15M0mod3
7005                         .long   Op16M0mod3
7006                         .long   Op17M0mod3
7007                         .long   Op18mod3
7008                         .long   Op19M0mod3
7009                         .long   Op1AM0mod3
7010                         .long   Op1Bmod3
7011                         .long   Op1CM0mod3
7012                         .long   Op1DM0mod3
7013                         .long   Op1EM0mod3
7014                         .long   Op1FM0mod3
7015                         .long   Op20mod3
7016                         .long   Op21M0mod3
7017                         .long   Op22mod3
7018                         .long   Op23M0mod3
7019                         .long   Op24M0mod3
7020                         .long   Op25M0mod3
7021                         .long   Op26M0mod3
7022                         .long   Op27M0mod3
7023                         .long   Op28mod3
7024                         .long   Op29M0mod3
7025                         .long   Op2AM0mod3
7026                         .long   Op2Bmod3
7027                         .long   Op2CM0mod3
7028                         .long   Op2DM0mod3
7029                         .long   Op2EM0mod3
7030                         .long   Op2FM0mod3
7031                         .long   Op30mod3
7032                         .long   Op31M0mod3
7033                         .long   Op32M0mod3
7034                         .long   Op33M0mod3
7035                         .long   Op34M0mod3
7036                         .long   Op35M0mod3
7037                         .long   Op36M0mod3
7038                         .long   Op37M0mod3
7039                         .long   Op38mod3
7040                         .long   Op39M0mod3
7041                         .long   Op3AM0mod3
7042                         .long   Op3Bmod3
7043                         .long   Op3CM0mod3
7044                         .long   Op3DM0mod3
7045                         .long   Op3EM0mod3
7046                         .long   Op3FM0mod3
7047                         .long   Op40mod3
7048                         .long   Op41M0mod3
7049                         .long   Op42mod3
7050                         .long   Op43M0mod3
7051                         .long   Op44X0mod3
7052                         .long   Op45M0mod3
7053                         .long   Op46M0mod3
7054                         .long   Op47M0mod3
7055                         .long   Op48M0mod3
7056                         .long   Op49M0mod3
7057                         .long   Op4AM0mod3
7058                         .long   Op4Bmod3
7059                         .long   Op4Cmod3
7060                         .long   Op4DM0mod3
7061                         .long   Op4EM0mod3
7062                         .long   Op4FM0mod3
7063                         .long   Op50mod3
7064                         .long   Op51M0mod3
7065                         .long   Op52M0mod3
7066                         .long   Op53M0mod3
7067                         .long   Op54X0mod3
7068                         .long   Op55M0mod3
7069                         .long   Op56M0mod3
7070                         .long   Op57M0mod3
7071                         .long   Op58mod3
7072                         .long   Op59M0mod3
7073                         .long   Op5AX0mod3
7074                         .long   Op5Bmod3
7075                         .long   Op5Cmod3
7076                         .long   Op5DM0mod3
7077                         .long   Op5EM0mod3
7078                         .long   Op5FM0mod3
7079                         .long   Op60mod3
7080                         .long   Op61M0mod3
7081                         .long   Op62mod3
7082                         .long   Op63M0mod3
7083                         .long   Op64M0mod3
7084                         .long   Op65M0mod3
7085                         .long   Op66M0mod3
7086                         .long   Op67M0mod3
7087                         .long   Op68M0mod3
7088                         .long   Op69M0mod3
7089                         .long   Op6AM0mod3
7090                         .long   Op6Bmod3
7091                         .long   Op6Cmod3
7092                         .long   Op6DM0mod3
7093                         .long   Op6EM0mod3
7094                         .long   Op6FM0mod3
7095                         .long   Op70mod3
7096                         .long   Op71M0mod3
7097                         .long   Op72M0mod3
7098                         .long   Op73M0mod3
7099                         .long   Op74M0mod3
7100                         .long   Op75M0mod3
7101                         .long   Op76M0mod3
7102                         .long   Op77M0mod3
7103                         .long   Op78mod3
7104                         .long   Op79M0mod3
7105                         .long   Op7AX0mod3
7106                         .long   Op7Bmod3
7107                         .long   Op7Cmod3
7108                         .long   Op7DM0mod3
7109                         .long   Op7EM0mod3
7110                         .long   Op7FM0mod3
7111                         .long   Op80mod3
7112                         .long   Op81M0mod3
7113                         .long   Op82mod3
7114                         .long   Op83M0mod3
7115                         .long   Op84X0mod3
7116                         .long   Op85M0mod3
7117                         .long   Op86X0mod3
7118                         .long   Op87M0mod3
7119                         .long   Op88X0mod3
7120                         .long   Op89M0mod3
7121                         .long   Op8AM0mod3
7122                         .long   Op8Bmod3
7123                         .long   Op8CX0mod3
7124                         .long   Op8DM0mod3
7125                         .long   Op8EX0mod3
7126                         .long   Op8FM0mod3
7127                         .long   Op90mod3
7128                         .long   Op91M0mod3
7129                         .long   Op92M0mod3
7130                         .long   Op93M0mod3
7131                         .long   Op94X0mod3
7132                         .long   Op95M0mod3
7133                         .long   Op96X0mod3
7134                         .long   Op97M0mod3
7135                         .long   Op98M0mod3
7136                         .long   Op99M0mod3
7137                         .long   Op9Amod3
7138                         .long   Op9BX0mod3
7139                         .long   Op9CM0mod3
7140                         .long   Op9DM0mod3
7141                         .long   Op9EM0mod3
7142                         .long   Op9FM0mod3
7143                         .long   OpA0X0mod3
7144                         .long   OpA1M0mod3
7145                         .long   OpA2X0mod3
7146                         .long   OpA3M0mod3
7147                         .long   OpA4X0mod3
7148                         .long   OpA5M0mod3
7149                         .long   OpA6X0mod3
7150                         .long   OpA7M0mod3
7151                         .long   OpA8X0mod3
7152                         .long   OpA9M0mod3
7153                         .long   OpAAX0mod3
7154                         .long   OpABmod3
7155                         .long   OpACX0mod3
7156                         .long   OpADM0mod3
7157                         .long   OpAEX0mod3
7158                         .long   OpAFM0mod3
7159                         .long   OpB0mod3
7160                         .long   OpB1M0mod3
7161                         .long   OpB2M0mod3
7162                         .long   OpB3M0mod3
7163                         .long   OpB4X0mod3
7164                         .long   OpB5M0mod3
7165                         .long   OpB6X0mod3
7166                         .long   OpB7M0mod3
7167                         .long   OpB8mod3
7168                         .long   OpB9M0mod3
7169                         .long   OpBAX0mod3
7170                         .long   OpBBX0mod3
7171                         .long   OpBCX0mod3
7172                         .long   OpBDM0mod3
7173                         .long   OpBEX0mod3
7174                         .long   OpBFM0mod3
7175                         .long   OpC0X0mod3
7176                         .long   OpC1M0mod3
7177                         .long   OpC2mod3
7178                         .long   OpC3M0mod3
7179                         .long   OpC4X0mod3
7180                         .long   OpC5M0mod3
7181                         .long   OpC6M0mod3
7182                         .long   OpC7M0mod3
7183                         .long   OpC8X0mod3
7184                         .long   OpC9M0mod3
7185                         .long   OpCAX0mod3
7186                         .long   OpCBmod3
7187                         .long   OpCCX0mod3
7188                         .long   OpCDM0mod3
7189                         .long   OpCEM0mod3
7190                         .long   OpCFM0mod3
7191                         .long   OpD0mod3
7192                         .long   OpD1M0mod3
7193                         .long   OpD2M0mod3
7194                         .long   OpD3M0mod3
7195                         .long   OpD4mod3
7196                         .long   OpD5M0mod3
7197                         .long   OpD6M0mod3
7198                         .long   OpD7M0mod3
7199                         .long   OpD8mod3
7200                         .long   OpD9M0mod3
7201                         .long   OpDAX0mod3
7202                         .long   OpDBmod3
7203                         .long   OpDCmod3
7204                         .long   OpDDM0mod3
7205                         .long   OpDEM0mod3
7206                         .long   OpDFM0mod3
7207                         .long   OpE0X0mod3
7208                         .long   OpE1M0mod3
7209                         .long   OpE2mod3
7210                         .long   OpE3M0mod3
7211                         .long   OpE4X0mod3
7212                         .long   OpE5M0mod3
7213                         .long   OpE6M0mod3
7214                         .long   OpE7M0mod3
7215                         .long   OpE8X0mod3
7216                         .long   OpE9M0mod3
7217                         .long   OpEAmod3
7218                         .long   OpEBmod3
7219                         .long   OpECX0mod3
7220                         .long   OpEDM0mod3
7221                         .long   OpEEM0mod3
7222                         .long   OpEFM0mod3
7223                         .long   OpF0mod3
7224                         .long   OpF1M0mod3
7225                         .long   OpF2M0mod3
7226                         .long   OpF3M0mod3
7227                         .long   OpF4mod3
7228                         .long   OpF5M0mod3
7229                         .long   OpF6M0mod3
7230                         .long   OpF7M0mod3
7231                         .long   OpF8mod3
7232                         .long   OpF9M0mod3
7233                         .long   OpFAX0mod3
7234                         .long   OpFBmod3
7235                         .long   OpFCmod3
7236                         .long   OpFDM0mod3
7237                         .long   OpFEM0mod3
7238                         .long   OpFFM0mod3
7239 Op00mod3:
7240 lbl00mod3:      Op00
7241                         NEXTOPCODE
7242 Op01M0mod3:
7243 lbl01mod3a:     DirectIndexedIndirect0
7244 lbl01mod3b:     ORA16
7245                         NEXTOPCODE
7246 Op02mod3:
7247 lbl02mod3:      Op02
7248                         NEXTOPCODE
7249 Op03M0mod3:
7250 lbl03mod3a:     StackasmRelative
7251 lbl03mod3b:     ORA16
7252                         NEXTOPCODE
7253 Op04M0mod3:
7254 lbl04mod3a:     Direct
7255 lbl04mod3b:     TSB16
7256                         NEXTOPCODE
7257 Op05M0mod3:
7258 lbl05mod3a:     Direct
7259 lbl05mod3b:     ORA16
7260                         NEXTOPCODE
7261 Op06M0mod3:
7262 lbl06mod3a:     Direct
7263 lbl06mod3b:     ASL16
7264                         NEXTOPCODE
7265 Op07M0mod3:
7266 lbl07mod3a:     DirectIndirectLong
7267 lbl07mod3b:     ORA16
7268                         NEXTOPCODE
7269 Op08mod3:
7270 lbl08mod3:      Op08
7271                         NEXTOPCODE
7272 Op09M0mod3:
7273 lbl09mod3:      Op09M0
7274                         NEXTOPCODE
7275 Op0AM0mod3:
7276 lbl0Amod3a:     A_ASL16
7277                         NEXTOPCODE
7278 Op0Bmod3:
7279 lbl0Bmod3:      Op0B
7280                         NEXTOPCODE
7281 Op0CM0mod3:
7282 lbl0Cmod3a:     Absolute
7283 lbl0Cmod3b:     TSB16
7284                         NEXTOPCODE
7285 Op0DM0mod3:
7286 lbl0Dmod3a:     Absolute
7287 lbl0Dmod3b:     ORA16
7288                         NEXTOPCODE
7289 Op0EM0mod3:
7290 lbl0Emod3a:     Absolute
7291 lbl0Emod3b:     ASL16
7292                         NEXTOPCODE
7293 Op0FM0mod3:
7294 lbl0Fmod3a:     AbsoluteLong
7295 lbl0Fmod3b:     ORA16
7296                         NEXTOPCODE
7297 Op10mod3:
7298 lbl10mod3:      Op10
7299                         NEXTOPCODE
7300 Op11M0mod3:
7301 lbl11mod3a:     DirectIndirectIndexed0
7302 lbl11mod3b:     ORA16
7303                         NEXTOPCODE
7304 Op12M0mod3:
7305 lbl12mod3a:     DirectIndirect
7306 lbl12mod3b:     ORA16
7307                         NEXTOPCODE
7308 Op13M0mod3:
7309 lbl13mod3a:     StackasmRelativeIndirectIndexed0
7310 lbl13mod3b:     ORA16
7311                         NEXTOPCODE
7312 Op14M0mod3:
7313 lbl14mod3a:     Direct
7314 lbl14mod3b:     TRB16
7315                         NEXTOPCODE
7316 Op15M0mod3:
7317 lbl15mod3a:     DirectIndexedX0
7318 lbl15mod3b:     ORA16
7319                         NEXTOPCODE
7320 Op16M0mod3:
7321 lbl16mod3a:     DirectIndexedX0
7322 lbl16mod3b:     ASL16
7323                         NEXTOPCODE
7324 Op17M0mod3:
7325 lbl17mod3a:     DirectIndirectIndexedLong0
7326 lbl17mod3b:     ORA16
7327                         NEXTOPCODE
7328 Op18mod3:
7329 lbl18mod3:      Op18
7330                         NEXTOPCODE
7331 Op19M0mod3:
7332 lbl19mod3a:     AbsoluteIndexedY0
7333 lbl19mod3b:     ORA16
7334                         NEXTOPCODE
7335 Op1AM0mod3:
7336 lbl1Amod3a:     A_INC16
7337                         NEXTOPCODE
7338 Op1Bmod3:
7339 lbl1Bmod3:      Op1BM0
7340                         NEXTOPCODE
7341 Op1CM0mod3:
7342 lbl1Cmod3a:     Absolute
7343 lbl1Cmod3b:     TRB16
7344                         NEXTOPCODE
7345 Op1DM0mod3:
7346 lbl1Dmod3a:     AbsoluteIndexedX0
7347 lbl1Dmod3b:     ORA16
7348                         NEXTOPCODE
7349 Op1EM0mod3:
7350 lbl1Emod3a:     AbsoluteIndexedX0
7351 lbl1Emod3b:     ASL16
7352                         NEXTOPCODE
7353 Op1FM0mod3:
7354 lbl1Fmod3a:     AbsoluteLongIndexedX0
7355 lbl1Fmod3b:     ORA16
7356                         NEXTOPCODE
7357 Op20mod3:
7358 lbl20mod3:      Op20
7359                         NEXTOPCODE
7360 Op21M0mod3:
7361 lbl21mod3a:     DirectIndexedIndirect0
7362 lbl21mod3b:     AND16
7363                         NEXTOPCODE
7364 Op22mod3:
7365 lbl22mod3:      Op22
7366                         NEXTOPCODE
7367 Op23M0mod3:
7368 lbl23mod3a:     StackasmRelative
7369 lbl23mod3b:     AND16
7370                         NEXTOPCODE
7371 Op24M0mod3:
7372 lbl24mod3a:     Direct
7373 lbl24mod3b:     BIT16
7374                         NEXTOPCODE
7375 Op25M0mod3:
7376 lbl25mod3a:     Direct
7377 lbl25mod3b:     AND16
7378                         NEXTOPCODE
7379 Op26M0mod3:
7380 lbl26mod3a:     Direct
7381 lbl26mod3b:     ROL16
7382                         NEXTOPCODE
7383 Op27M0mod3:
7384 lbl27mod3a:     DirectIndirectLong
7385 lbl27mod3b:     AND16
7386                         NEXTOPCODE
7387 Op28mod3:
7388 lbl28mod3:      Op28X0M0
7389                         NEXTOPCODE
7390 .pool
7391 Op29M0mod3:
7392 lbl29mod3:      Op29M0
7393                         NEXTOPCODE
7394 Op2AM0mod3:
7395 lbl2Amod3a:     A_ROL16
7396                         NEXTOPCODE
7397 Op2Bmod3:
7398 lbl2Bmod3:      Op2B
7399                         NEXTOPCODE
7400 Op2CM0mod3:
7401 lbl2Cmod3a:     Absolute
7402 lbl2Cmod3b:     BIT16
7403                         NEXTOPCODE
7404 Op2DM0mod3:
7405 lbl2Dmod3a:     Absolute
7406 lbl2Dmod3b:     AND16
7407                         NEXTOPCODE
7408 Op2EM0mod3:
7409 lbl2Emod3a:     Absolute
7410 lbl2Emod3b:     ROL16
7411                         NEXTOPCODE
7412 Op2FM0mod3:
7413 lbl2Fmod3a:     AbsoluteLong
7414 lbl2Fmod3b:     AND16
7415                         NEXTOPCODE
7416 Op30mod3:
7417 lbl30mod3:      Op30
7418                         NEXTOPCODE
7419 Op31M0mod3:
7420 lbl31mod3a:     DirectIndirectIndexed0
7421 lbl31mod3b:     AND16
7422                         NEXTOPCODE
7423 Op32M0mod3:
7424 lbl32mod3a:     DirectIndirect
7425 lbl32mod3b:     AND16
7426                         NEXTOPCODE
7427 Op33M0mod3:
7428 lbl33mod3a:     StackasmRelativeIndirectIndexed0
7429 lbl33mod3b:     AND16
7430                         NEXTOPCODE
7431 Op34M0mod3:
7432 lbl34mod3a:     DirectIndexedX0
7433 lbl34mod3b:     BIT16
7434                         NEXTOPCODE
7435 Op35M0mod3:
7436 lbl35mod3a:     DirectIndexedX0
7437 lbl35mod3b:     AND16
7438                         NEXTOPCODE
7439 Op36M0mod3:
7440 lbl36mod3a:     DirectIndexedX0
7441 lbl36mod3b:     ROL16
7442                         NEXTOPCODE
7443 Op37M0mod3:
7444 lbl37mod3a:     DirectIndirectIndexedLong0
7445 lbl37mod3b:     AND16
7446                         NEXTOPCODE
7447 Op38mod3:
7448 lbl38mod3:      Op38
7449                         NEXTOPCODE
7450 Op39M0mod3:
7451 lbl39mod3a:     AbsoluteIndexedY0
7452 lbl39mod3b:     AND16
7453                         NEXTOPCODE
7454 Op3AM0mod3:
7455 lbl3Amod3a:     A_DEC16
7456                         NEXTOPCODE
7457 Op3Bmod3:
7458 lbl3Bmod3:      Op3BM0
7459                         NEXTOPCODE
7460 Op3CM0mod3:
7461 lbl3Cmod3a:     AbsoluteIndexedX0
7462 lbl3Cmod3b:     BIT16
7463                         NEXTOPCODE
7464 Op3DM0mod3:
7465 lbl3Dmod3a:     AbsoluteIndexedX0
7466 lbl3Dmod3b:     AND16
7467                         NEXTOPCODE
7468 Op3EM0mod3:
7469 lbl3Emod3a:     AbsoluteIndexedX0
7470 lbl3Emod3b:     ROL16
7471                         NEXTOPCODE
7472 Op3FM0mod3:
7473 lbl3Fmod3a:     AbsoluteLongIndexedX0
7474 lbl3Fmod3b:     AND16
7475                         NEXTOPCODE
7476 Op40mod3:
7477 lbl40mod3:      Op40X0M0
7478                         NEXTOPCODE
7479 .pool
7480 Op41M0mod3:
7481 lbl41mod3a:     DirectIndexedIndirect0
7482 lbl41mod3b:     EOR16
7483                         NEXTOPCODE
7484 Op42mod3:
7485 lbl42mod3:      Op42
7486                         NEXTOPCODE
7487 Op43M0mod3:
7488 lbl43mod3a:     StackasmRelative
7489 lbl43mod3b:     EOR16
7490                         NEXTOPCODE
7491 Op44X0mod3:
7492 lbl44mod3:      Op44X0M0
7493                         NEXTOPCODE
7494 Op45M0mod3:
7495 lbl45mod3a:     Direct
7496 lbl45mod3b:     EOR16
7497                         NEXTOPCODE
7498 Op46M0mod3:
7499 lbl46mod3a:     Direct
7500 lbl46mod3b:     LSR16
7501                         NEXTOPCODE
7502 Op47M0mod3:
7503 lbl47mod3a:     DirectIndirectLong
7504 lbl47mod3b:     EOR16
7505                         NEXTOPCODE
7506 Op48M0mod3:
7507 lbl48mod3:      Op48M0
7508                         NEXTOPCODE
7509 Op49M0mod3:
7510 lbl49mod3:      Op49M0
7511                         NEXTOPCODE
7512 Op4AM0mod3:
7513 lbl4Amod3a:     A_LSR16
7514                         NEXTOPCODE
7515 Op4Bmod3:
7516 lbl4Bmod3:      Op4B
7517                         NEXTOPCODE
7518 Op4Cmod3:
7519 lbl4Cmod3:      Op4C
7520                         NEXTOPCODE
7521 Op4DM0mod3:
7522 lbl4Dmod3a:     Absolute
7523 lbl4Dmod3b:     EOR16
7524                         NEXTOPCODE
7525 Op4EM0mod3:
7526 lbl4Emod3a:     Absolute
7527 lbl4Emod3b:     LSR16
7528                         NEXTOPCODE
7529 Op4FM0mod3:
7530 lbl4Fmod3a:     AbsoluteLong
7531 lbl4Fmod3b:     EOR16
7532                         NEXTOPCODE
7533 Op50mod3:
7534 lbl50mod3:      Op50
7535                         NEXTOPCODE
7536 Op51M0mod3:
7537 lbl51mod3a:     DirectIndirectIndexed0
7538 lbl51mod3b:     EOR16
7539                         NEXTOPCODE
7540 Op52M0mod3:
7541 lbl52mod3a:     DirectIndirect
7542 lbl52mod3b:     EOR16
7543                         NEXTOPCODE
7544 Op53M0mod3:
7545 lbl53mod3a:     StackasmRelativeIndirectIndexed0
7546 lbl53mod3b:     EOR16
7547                         NEXTOPCODE
7548 Op54X0mod3:
7549 lbl54mod3:      Op54X0M0
7550                         NEXTOPCODE
7551 Op55M0mod3:
7552 lbl55mod3a:     DirectIndexedX0
7553 lbl55mod3b:     EOR16
7554                         NEXTOPCODE
7555 Op56M0mod3:
7556 lbl56mod3a:     DirectIndexedX0
7557 lbl56mod3b:     LSR16
7558                         NEXTOPCODE
7559 Op57M0mod3:
7560 lbl57mod3a:     DirectIndirectIndexedLong0
7561 lbl57mod3b:     EOR16
7562                         NEXTOPCODE
7563 Op58mod3:
7564 lbl58mod3:      Op58
7565                         NEXTOPCODE
7566 Op59M0mod3:
7567 lbl59mod3a:     AbsoluteIndexedY0
7568 lbl59mod3b:     EOR16
7569                         NEXTOPCODE
7570 Op5AX0mod3:
7571 lbl5Amod3:      Op5AX0
7572                         NEXTOPCODE
7573 Op5Bmod3:
7574 lbl5Bmod3:      Op5BM0
7575                         NEXTOPCODE
7576 Op5Cmod3:
7577 lbl5Cmod3:      Op5C
7578                         NEXTOPCODE
7579 Op5DM0mod3:
7580 lbl5Dmod3a:     AbsoluteIndexedX0
7581 lbl5Dmod3b:     EOR16
7582                         NEXTOPCODE
7583 Op5EM0mod3:
7584 lbl5Emod3a:     AbsoluteIndexedX0
7585 lbl5Emod3b:     LSR16
7586                         NEXTOPCODE
7587 Op5FM0mod3:
7588 lbl5Fmod3a:     AbsoluteLongIndexedX0
7589 lbl5Fmod3b:     EOR16
7590                         NEXTOPCODE
7591 Op60mod3:
7592 lbl60mod3:      Op60
7593                         NEXTOPCODE
7594 Op61M0mod3:
7595 lbl61mod3a:     DirectIndexedIndirect0
7596 lbl61mod3b:     ADC16
7597                         NEXTOPCODE
7598 Op62mod3:
7599 lbl62mod3:      Op62
7600                         NEXTOPCODE
7601 Op63M0mod3:
7602 lbl63mod3a:     StackasmRelative
7603 lbl63mod3b:     ADC16
7604                         NEXTOPCODE
7605 .pool
7606 Op64M0mod3:
7607 lbl64mod3a:     Direct
7608 lbl64mod3b:     STZ16
7609                         NEXTOPCODE
7610 Op65M0mod3:
7611 lbl65mod3a:     Direct
7612 lbl65mod3b:     ADC16
7613                         NEXTOPCODE
7614 .pool
7615 Op66M0mod3:
7616 lbl66mod3a:     Direct
7617 lbl66mod3b:     ROR16
7618                         NEXTOPCODE
7619 Op67M0mod3:
7620 lbl67mod3a:     DirectIndirectLong
7621 lbl67mod3b:     ADC16
7622                         NEXTOPCODE
7623 .pool
7624 Op68M0mod3:
7625 lbl68mod3:      Op68M0
7626                         NEXTOPCODE
7627 Op69M0mod3:
7628 lbl69mod3a:     Immediate16
7629 lbl69mod3b:     ADC16
7630                         NEXTOPCODE
7631 .pool
7632 Op6AM0mod3:
7633 lbl6Amod3a:     A_ROR16
7634                         NEXTOPCODE
7635 Op6Bmod3:
7636 lbl6Bmod3:      Op6B
7637                         NEXTOPCODE
7638 Op6Cmod3:
7639 lbl6Cmod3:      Op6C
7640                         NEXTOPCODE
7641 Op6DM0mod3:
7642 lbl6Dmod3a:     Absolute
7643 lbl6Dmod3b:     ADC16
7644                         NEXTOPCODE
7645 Op6EM0mod3:
7646 lbl6Emod3a:     Absolute
7647 lbl6Emod3b:     ROR16
7648                         NEXTOPCODE
7649 Op6FM0mod3:
7650 lbl6Fmod3a:     AbsoluteLong
7651 lbl6Fmod3b:     ADC16
7652                         NEXTOPCODE
7653 Op70mod3:
7654 lbl70mod3:      Op70
7655                         NEXTOPCODE
7656 Op71M0mod3:
7657 lbl71mod3a:     DirectIndirectIndexed0
7658 lbl71mod3b:     ADC16
7659                         NEXTOPCODE
7660 Op72M0mod3:
7661 lbl72mod3a:     DirectIndirect
7662 lbl72mod3b:     ADC16
7663                         NEXTOPCODE
7664 Op73M0mod3:
7665 lbl73mod3a:     StackasmRelativeIndirectIndexed0
7666 lbl73mod3b:     ADC16
7667                         NEXTOPCODE
7668 .pool
7669 Op74M0mod3:
7670 lbl74mod3a:     DirectIndexedX0
7671 lbl74mod3b:     STZ16
7672                         NEXTOPCODE
7673 Op75M0mod3:
7674 lbl75mod3a:     DirectIndexedX0
7675 lbl75mod3b:     ADC16
7676                         NEXTOPCODE
7677 .pool
7678 Op76M0mod3:
7679 lbl76mod3a:     DirectIndexedX0
7680 lbl76mod3b:     ROR16
7681                         NEXTOPCODE
7682 Op77M0mod3:
7683 lbl77mod3a:     DirectIndirectIndexedLong0
7684 lbl77mod3b:     ADC16
7685                         NEXTOPCODE
7686 Op78mod3:
7687 lbl78mod3:      Op78
7688                         NEXTOPCODE
7689 Op79M0mod3:
7690 lbl79mod3a:     AbsoluteIndexedY0
7691 lbl79mod3b:     ADC16
7692                         NEXTOPCODE
7693 Op7AX0mod3:
7694 lbl7Amod3:      Op7AX0
7695                         NEXTOPCODE
7696 Op7Bmod3:
7697 lbl7Bmod3:      Op7BM0
7698                         NEXTOPCODE
7699 Op7Cmod3:
7700 lbl7Cmod3:      AbsoluteIndexedIndirectX0
7701                 Op7C
7702                         NEXTOPCODE
7703 Op7DM0mod3:
7704 lbl7Dmod3a:     AbsoluteIndexedX0
7705 lbl7Dmod3b:     ADC16
7706                         NEXTOPCODE
7707 Op7EM0mod3:
7708 lbl7Emod3a:     AbsoluteIndexedX0
7709 lbl7Emod3b:     ROR16
7710                         NEXTOPCODE
7711 Op7FM0mod3:
7712 lbl7Fmod3a:     AbsoluteLongIndexedX0
7713 lbl7Fmod3b:     ADC16
7714                         NEXTOPCODE
7715 .pool
7716 Op80mod3:
7717 lbl80mod3:      Op80
7718                         NEXTOPCODE
7719 Op81M0mod3:
7720 lbl81mod3a:     DirectIndexedIndirect0
7721 lbl81mod3b:     Op81M0
7722                         NEXTOPCODE
7723 Op82mod3:
7724 lbl82mod3:      Op82
7725                         NEXTOPCODE
7726 Op83M0mod3:
7727 lbl83mod3a:     StackasmRelative
7728 lbl83mod3b:     STA16
7729                         NEXTOPCODE
7730 Op84X0mod3:
7731 lbl84mod3a:     Direct
7732 lbl84mod3b:     STY16
7733                         NEXTOPCODE
7734 Op85M0mod3:
7735 lbl85mod3a:     Direct
7736 lbl85mod3b:     STA16
7737                         NEXTOPCODE
7738 Op86X0mod3:
7739 lbl86mod3a:     Direct
7740 lbl86mod3b:     STX16
7741                         NEXTOPCODE
7742 Op87M0mod3:
7743 lbl87mod3a:     DirectIndirectLong
7744 lbl87mod3b:     STA16
7745                         NEXTOPCODE
7746 Op88X0mod3:
7747 lbl88mod3:      Op88X0
7748                         NEXTOPCODE
7749 Op89M0mod3:
7750 lbl89mod3:      Op89M0
7751                         NEXTOPCODE
7752 Op8AM0mod3:
7753 lbl8Amod3:      Op8AM0X0
7754                         NEXTOPCODE
7755 Op8Bmod3:
7756 lbl8Bmod3:      Op8B
7757                         NEXTOPCODE
7758 Op8CX0mod3:
7759 lbl8Cmod3a:     Absolute
7760 lbl8Cmod3b:     STY16
7761                         NEXTOPCODE
7762 Op8DM0mod3:
7763 lbl8Dmod3a:     Absolute
7764 lbl8Dmod3b:     STA16
7765                         NEXTOPCODE
7766 Op8EX0mod3:
7767 lbl8Emod3a:     Absolute
7768 lbl8Emod3b:     STX16
7769                         NEXTOPCODE
7770 Op8FM0mod3:
7771 lbl8Fmod3a:     AbsoluteLong
7772 lbl8Fmod3b:     STA16
7773                         NEXTOPCODE
7774 Op90mod3:
7775 lbl90mod3:      Op90
7776                         NEXTOPCODE
7777 Op91M0mod3:
7778 lbl91mod3a:     DirectIndirectIndexed0
7779 lbl91mod3b:     STA16
7780                         NEXTOPCODE
7781 Op92M0mod3:
7782 lbl92mod3a:     DirectIndirect
7783 lbl92mod3b:     STA16
7784                         NEXTOPCODE
7785 Op93M0mod3:
7786 lbl93mod3a:     StackasmRelativeIndirectIndexed0
7787 lbl93mod3b:     STA16
7788                         NEXTOPCODE
7789 Op94X0mod3:
7790 lbl94mod3a:     DirectIndexedX0
7791 lbl94mod3b:     STY16
7792                         NEXTOPCODE
7793 Op95M0mod3:
7794 lbl95mod3a:     DirectIndexedX0
7795 lbl95mod3b:     STA16
7796                         NEXTOPCODE
7797 Op96X0mod3:
7798 lbl96mod3a:     DirectIndexedY0
7799 lbl96mod3b:     STX16
7800                         NEXTOPCODE
7801 Op97M0mod3:
7802 lbl97mod3a:     DirectIndirectIndexedLong0
7803 lbl97mod3b:     STA16
7804                         NEXTOPCODE
7805 Op98M0mod3:
7806 lbl98mod3:      Op98M0X0
7807                         NEXTOPCODE
7808 Op99M0mod3:
7809 lbl99mod3a:     AbsoluteIndexedY0
7810 lbl99mod3b:     STA16
7811                         NEXTOPCODE
7812 Op9Amod3:
7813 lbl9Amod3:      Op9AX0
7814                         NEXTOPCODE
7815 Op9BX0mod3:
7816 lbl9Bmod3:      Op9BX0
7817                         NEXTOPCODE
7818 Op9CM0mod3:
7819 lbl9Cmod3a:     Absolute
7820 lbl9Cmod3b:     STZ16
7821                         NEXTOPCODE
7822 Op9DM0mod3:
7823 lbl9Dmod3a:     AbsoluteIndexedX0
7824 lbl9Dmod3b:     STA16
7825                         NEXTOPCODE
7826 Op9EM0mod3:
7827 lbl9Emod3:      AbsoluteIndexedX0
7828                 STZ16
7829                         NEXTOPCODE
7830 Op9FM0mod3:
7831 lbl9Fmod3a:     AbsoluteLongIndexedX0
7832 lbl9Fmod3b:     STA16
7833                         NEXTOPCODE
7834 OpA0X0mod3:
7835 lblA0mod3:      OpA0X0
7836                         NEXTOPCODE
7837 OpA1M0mod3:
7838 lblA1mod3a:     DirectIndexedIndirect0
7839 lblA1mod3b:     LDA16
7840                         NEXTOPCODE
7841 OpA2X0mod3:
7842 lblA2mod3:      OpA2X0
7843                         NEXTOPCODE
7844 OpA3M0mod3:
7845 lblA3mod3a:     StackasmRelative
7846 lblA3mod3b:     LDA16
7847                         NEXTOPCODE
7848 OpA4X0mod3:
7849 lblA4mod3a:     Direct
7850 lblA4mod3b:     LDY16
7851                         NEXTOPCODE
7852 OpA5M0mod3:
7853 lblA5mod3a:     Direct
7854 lblA5mod3b:     LDA16
7855                         NEXTOPCODE
7856 OpA6X0mod3:
7857 lblA6mod3a:     Direct
7858 lblA6mod3b:     LDX16
7859                         NEXTOPCODE
7860 OpA7M0mod3:
7861 lblA7mod3a:     DirectIndirectLong
7862 lblA7mod3b:     LDA16
7863                         NEXTOPCODE
7864 OpA8X0mod3:
7865 lblA8mod3:      OpA8X0M0
7866                         NEXTOPCODE
7867 OpA9M0mod3:
7868 lblA9mod3:      OpA9M0
7869                         NEXTOPCODE
7870 OpAAX0mod3:
7871 lblAAmod3:      OpAAX0M0
7872                         NEXTOPCODE
7873 OpABmod3:
7874 lblABmod3:      OpAB
7875                         NEXTOPCODE
7876 OpACX0mod3:
7877 lblACmod3a:     Absolute
7878 lblACmod3b:     LDY16
7879                         NEXTOPCODE
7880 OpADM0mod3:
7881 lblADmod3a:     Absolute
7882 lblADmod3b:     LDA16
7883                         NEXTOPCODE
7884 OpAEX0mod3:
7885 lblAEmod3a:     Absolute
7886 lblAEmod3b:     LDX16
7887                         NEXTOPCODE
7888 OpAFM0mod3:
7889 lblAFmod3a:     AbsoluteLong
7890 lblAFmod3b:     LDA16
7891                         NEXTOPCODE
7892 OpB0mod3:
7893 lblB0mod3:      OpB0
7894                         NEXTOPCODE
7895 OpB1M0mod3:
7896 lblB1mod3a:     DirectIndirectIndexed0
7897 lblB1mod3b:     LDA16
7898                         NEXTOPCODE
7899 OpB2M0mod3:
7900 lblB2mod3a:     DirectIndirect
7901 lblB2mod3b:     LDA16
7902                         NEXTOPCODE
7903 OpB3M0mod3:
7904 lblB3mod3a:     StackasmRelativeIndirectIndexed0
7905 lblB3mod3b:     LDA16
7906                         NEXTOPCODE
7907 OpB4X0mod3:
7908 lblB4mod3a:     DirectIndexedX0
7909 lblB4mod3b:     LDY16
7910                         NEXTOPCODE
7911 OpB5M0mod3:
7912 lblB5mod3a:     DirectIndexedX0
7913 lblB5mod3b:     LDA16
7914                         NEXTOPCODE
7915 OpB6X0mod3:
7916 lblB6mod3a:     DirectIndexedY0
7917 lblB6mod3b:     LDX16
7918                         NEXTOPCODE
7919 OpB7M0mod3:
7920 lblB7mod3a:     DirectIndirectIndexedLong0
7921 lblB7mod3b:     LDA16
7922                         NEXTOPCODE
7923 OpB8mod3:
7924 lblB8mod3:      OpB8
7925                         NEXTOPCODE
7926 OpB9M0mod3:
7927 lblB9mod3a:     AbsoluteIndexedY0
7928 lblB9mod3b:     LDA16
7929                         NEXTOPCODE
7930 OpBAX0mod3:
7931 lblBAmod3:      OpBAX0
7932                         NEXTOPCODE
7933 OpBBX0mod3:
7934 lblBBmod3:      OpBBX0
7935                         NEXTOPCODE
7936 OpBCX0mod3:
7937 lblBCmod3a:     AbsoluteIndexedX0
7938 lblBCmod3b:     LDY16
7939                         NEXTOPCODE
7940 OpBDM0mod3:
7941 lblBDmod3a:     AbsoluteIndexedX0
7942 lblBDmod3b:     LDA16
7943                         NEXTOPCODE
7944 OpBEX0mod3:
7945 lblBEmod3a:     AbsoluteIndexedY0
7946 lblBEmod3b:     LDX16
7947                         NEXTOPCODE
7948 OpBFM0mod3:
7949 lblBFmod3a:     AbsoluteLongIndexedX0
7950 lblBFmod3b:     LDA16
7951                         NEXTOPCODE
7952 OpC0X0mod3:
7953 lblC0mod3:      OpC0X0
7954                         NEXTOPCODE
7955 OpC1M0mod3:
7956 lblC1mod3a:     DirectIndexedIndirect0
7957 lblC1mod3b:     CMP16
7958                         NEXTOPCODE
7959 OpC2mod3:
7960 lblC2mod3:      OpC2
7961                         NEXTOPCODE
7962 .pool
7963 OpC3M0mod3:
7964 lblC3mod3a:     StackasmRelative
7965 lblC3mod3b:     CMP16
7966                         NEXTOPCODE
7967 OpC4X0mod3:
7968 lblC4mod3a:     Direct
7969 lblC4mod3b:     CMY16
7970                         NEXTOPCODE
7971 OpC5M0mod3:
7972 lblC5mod3a:     Direct
7973 lblC5mod3b:     CMP16
7974                         NEXTOPCODE
7975 OpC6M0mod3:
7976 lblC6mod3a:     Direct
7977 lblC6mod3b:     DEC16
7978                         NEXTOPCODE
7979 OpC7M0mod3:
7980 lblC7mod3a:     DirectIndirectLong
7981 lblC7mod3b:     CMP16
7982                         NEXTOPCODE
7983 OpC8X0mod3:
7984 lblC8mod3:      OpC8X0
7985                         NEXTOPCODE
7986 OpC9M0mod3:
7987 lblC9mod3:      OpC9M0
7988                         NEXTOPCODE
7989 OpCAX0mod3:
7990 lblCAmod3:      OpCAX0
7991                         NEXTOPCODE
7992 OpCBmod3:
7993 lblCBmod3:      OpCB
7994                         NEXTOPCODE
7995 OpCCX0mod3:
7996 lblCCmod3a:     Absolute
7997 lblCCmod3b:     CMY16
7998                         NEXTOPCODE
7999 OpCDM0mod3:
8000 lblCDmod3a:     Absolute
8001 lblCDmod3b:     CMP16
8002                         NEXTOPCODE
8003 OpCEM0mod3:
8004 lblCEmod3a:     Absolute
8005 lblCEmod3b:     DEC16
8006                         NEXTOPCODE
8007 OpCFM0mod3:
8008 lblCFmod3a:     AbsoluteLong
8009 lblCFmod3b:     CMP16
8010                         NEXTOPCODE
8011 OpD0mod3:
8012 lblD0mod3:      OpD0
8013                         NEXTOPCODE
8014 OpD1M0mod3:
8015 lblD1mod3a:     DirectIndirectIndexed0
8016 lblD1mod3b:     CMP16
8017                         NEXTOPCODE
8018 OpD2M0mod3:
8019 lblD2mod3a:     DirectIndirect
8020 lblD2mod3b:     CMP16
8021                         NEXTOPCODE
8022 OpD3M0mod3:
8023 lblD3mod3a:     StackasmRelativeIndirectIndexed0
8024 lblD3mod3b:     CMP16
8025                         NEXTOPCODE
8026 OpD4mod3:
8027 lblD4mod3:      OpD4
8028                         NEXTOPCODE
8029 OpD5M0mod3:
8030 lblD5mod3a:     DirectIndexedX0
8031 lblD5mod3b:     CMP16
8032                         NEXTOPCODE
8033 OpD6M0mod3:
8034 lblD6mod3a:     DirectIndexedX0
8035 lblD6mod3b:     DEC16
8036                         NEXTOPCODE
8037 OpD7M0mod3:
8038 lblD7mod3a:     DirectIndirectIndexedLong0
8039 lblD7mod3b:     CMP16
8040                         NEXTOPCODE
8041 OpD8mod3:
8042 lblD8mod3:      OpD8
8043                         NEXTOPCODE
8044 OpD9M0mod3:
8045 lblD9mod3a:     AbsoluteIndexedY0
8046 lblD9mod3b:     CMP16
8047                         NEXTOPCODE
8048 OpDAX0mod3:
8049 lblDAmod3:      OpDAX0
8050                         NEXTOPCODE
8051 OpDBmod3:
8052 lblDBmod3:      OpDB
8053                         NEXTOPCODE
8054 OpDCmod3:
8055 lblDCmod3:      OpDC
8056                         NEXTOPCODE
8057 OpDDM0mod3:
8058 lblDDmod3a:     AbsoluteIndexedX0
8059 lblDDmod3b:     CMP16
8060                         NEXTOPCODE
8061 OpDEM0mod3:
8062 lblDEmod3a:     AbsoluteIndexedX0
8063 lblDEmod3b:     DEC16
8064                         NEXTOPCODE
8065 OpDFM0mod3:
8066 lblDFmod3a:     AbsoluteLongIndexedX0
8067 lblDFmod3b:     CMP16
8068                         NEXTOPCODE
8069 OpE0X0mod3:
8070 lblE0mod3:      OpE0X0
8071                         NEXTOPCODE
8072 OpE1M0mod3:
8073 lblE1mod3a:     DirectIndexedIndirect0
8074 lblE1mod3b:     SBC16
8075                         NEXTOPCODE
8076 OpE2mod3:
8077 lblE2mod3:      OpE2
8078                         NEXTOPCODE
8079 .pool
8080 OpE3M0mod3:
8081 lblE3mod3a:     StackasmRelative
8082 lblE3mod3b:     SBC16
8083                         NEXTOPCODE
8084 OpE4X0mod3:
8085 lblE4mod3a:     Direct
8086 lblE4mod3b:     CMX16
8087                         NEXTOPCODE
8088 OpE5M0mod3:
8089 lblE5mod3a:     Direct
8090 lblE5mod3b:     SBC16
8091                         NEXTOPCODE
8092 OpE6M0mod3:
8093 lblE6mod3a:     Direct
8094 lblE6mod3b:     INC16
8095                         NEXTOPCODE
8096 OpE7M0mod3:
8097 lblE7mod3a:     DirectIndirectLong
8098 lblE7mod3b:     SBC16
8099                         NEXTOPCODE
8100 OpE8X0mod3:
8101 lblE8mod3:      OpE8X0
8102                         NEXTOPCODE
8103 OpE9M0mod3:
8104 lblE9mod3a:     Immediate16
8105 lblE9mod3b:     SBC16
8106                         NEXTOPCODE
8107 OpEAmod3:
8108 lblEAmod3:      OpEA
8109                         NEXTOPCODE
8110 OpEBmod3:
8111 lblEBmod3:      OpEBM0
8112                         NEXTOPCODE
8113 OpECX0mod3:
8114 lblECmod3a:     Absolute
8115 lblECmod3b:     CMX16
8116                         NEXTOPCODE
8117 OpEDM0mod3:
8118 lblEDmod3a:     Absolute
8119 lblEDmod3b:     SBC16
8120                         NEXTOPCODE
8121 OpEEM0mod3:
8122 lblEEmod3a:     Absolute
8123 lblEEmod3b:     INC16
8124                         NEXTOPCODE
8125 OpEFM0mod3:
8126 lblEFmod3a:     AbsoluteLong
8127 lblEFmod3b:     SBC16
8128                         NEXTOPCODE
8129 OpF0mod3:
8130 lblF0mod3:      OpF0
8131                         NEXTOPCODE
8132 OpF1M0mod3:
8133 lblF1mod3a:     DirectIndirectIndexed0
8134 lblF1mod3b:     SBC16
8135                         NEXTOPCODE
8136 OpF2M0mod3:
8137 lblF2mod3a:     DirectIndirect
8138 lblF2mod3b:     SBC16
8139                         NEXTOPCODE
8140 OpF3M0mod3:
8141 lblF3mod3a:     StackasmRelativeIndirectIndexed0
8142 lblF3mod3b:     SBC16
8143                         NEXTOPCODE
8144 OpF4mod3:
8145 lblF4mod3:      OpF4
8146                         NEXTOPCODE
8147 OpF5M0mod3:
8148 lblF5mod3a:     DirectIndexedX0
8149 lblF5mod3b:     SBC16
8150                         NEXTOPCODE
8151 OpF6M0mod3:
8152 lblF6mod3a:     DirectIndexedX0
8153 lblF6mod3b:     INC16
8154                         NEXTOPCODE
8155 OpF7M0mod3:
8156 lblF7mod3a:     DirectIndirectIndexedLong0
8157 lblF7mod3b:     SBC16
8158                         NEXTOPCODE
8159 OpF8mod3:
8160 lblF8mod3:      OpF8
8161                         NEXTOPCODE
8162 OpF9M0mod3:
8163 lblF9mod3a:     AbsoluteIndexedY0
8164 lblF9mod3b:     SBC16
8165                         NEXTOPCODE
8166 OpFAX0mod3:
8167 lblFAmod3:      OpFAX0
8168                         NEXTOPCODE
8169 OpFBmod3:
8170 lblFBmod3:      OpFB
8171                         NEXTOPCODE
8172 OpFCmod3:
8173 lblFCmod3:      OpFCX0
8174                         NEXTOPCODE
8175 OpFDM0mod3:
8176 lblFDmod3a:     AbsoluteIndexedX0
8177 lblFDmod3b:     SBC16
8178                         NEXTOPCODE
8179 OpFEM0mod3:
8180 lblFEmod3a:     AbsoluteIndexedX0
8181 lblFEmod3b:     INC16
8182                         NEXTOPCODE
8183 OpFFM0mod3:
8184 lblFFmod3a:     AbsoluteLongIndexedX0
8185 lblFFmod3b:     SBC16
8186                         NEXTOPCODE
8187 .pool
8188
8189 jumptable4:             .long   Op00mod4
8190                         .long   Op01M0mod4
8191                         .long   Op02mod4
8192                         .long   Op03M0mod4
8193                         .long   Op04M0mod4
8194                         .long   Op05M0mod4
8195                         .long   Op06M0mod4
8196                         .long   Op07M0mod4
8197                         .long   Op08mod4
8198                         .long   Op09M0mod4
8199                         .long   Op0AM0mod4
8200                         .long   Op0Bmod4
8201                         .long   Op0CM0mod4
8202                         .long   Op0DM0mod4
8203                         .long   Op0EM0mod4
8204                         .long   Op0FM0mod4
8205                         .long   Op10mod4
8206                         .long   Op11M0mod4
8207                         .long   Op12M0mod4
8208                         .long   Op13M0mod4
8209                         .long   Op14M0mod4
8210                         .long   Op15M0mod4
8211                         .long   Op16M0mod4
8212                         .long   Op17M0mod4
8213                         .long   Op18mod4
8214                         .long   Op19M0mod4
8215                         .long   Op1AM0mod4
8216                         .long   Op1Bmod4
8217                         .long   Op1CM0mod4
8218                         .long   Op1DM0mod4
8219                         .long   Op1EM0mod4
8220                         .long   Op1FM0mod4
8221                         .long   Op20mod4
8222                         .long   Op21M0mod4
8223                         .long   Op22mod4
8224                         .long   Op23M0mod4
8225                         .long   Op24M0mod4
8226                         .long   Op25M0mod4
8227                         .long   Op26M0mod4
8228                         .long   Op27M0mod4
8229                         .long   Op28mod4
8230                         .long   Op29M0mod4
8231                         .long   Op2AM0mod4
8232                         .long   Op2Bmod4
8233                         .long   Op2CM0mod4
8234                         .long   Op2DM0mod4
8235                         .long   Op2EM0mod4
8236                         .long   Op2FM0mod4
8237                         .long   Op30mod4
8238                         .long   Op31M0mod4
8239                         .long   Op32M0mod4
8240                         .long   Op33M0mod4
8241                         .long   Op34M0mod4
8242                         .long   Op35M0mod4
8243                         .long   Op36M0mod4
8244                         .long   Op37M0mod4
8245                         .long   Op38mod4
8246                         .long   Op39M0mod4
8247                         .long   Op3AM0mod4
8248                         .long   Op3Bmod4
8249                         .long   Op3CM0mod4
8250                         .long   Op3DM0mod4
8251                         .long   Op3EM0mod4
8252                         .long   Op3FM0mod4
8253                         .long   Op40mod4
8254                         .long   Op41M0mod4
8255                         .long   Op42mod4
8256                         .long   Op43M0mod4
8257                         .long   Op44X1mod4
8258                         .long   Op45M0mod4
8259                         .long   Op46M0mod4
8260                         .long   Op47M0mod4
8261                         .long   Op48M0mod4
8262                         .long   Op49M0mod4
8263                         .long   Op4AM0mod4
8264                         .long   Op4Bmod4
8265                         .long   Op4Cmod4
8266                         .long   Op4DM0mod4
8267                         .long   Op4EM0mod4
8268                         .long   Op4FM0mod4
8269                         .long   Op50mod4
8270                         .long   Op51M0mod4
8271                         .long   Op52M0mod4
8272                         .long   Op53M0mod4
8273                         .long   Op54X1mod4
8274                         .long   Op55M0mod4
8275                         .long   Op56M0mod4
8276                         .long   Op57M0mod4
8277                         .long   Op58mod4
8278                         .long   Op59M0mod4
8279                         .long   Op5AX1mod4
8280                         .long   Op5Bmod4
8281                         .long   Op5Cmod4
8282                         .long   Op5DM0mod4
8283                         .long   Op5EM0mod4
8284                         .long   Op5FM0mod4
8285                         .long   Op60mod4
8286                         .long   Op61M0mod4
8287                         .long   Op62mod4
8288                         .long   Op63M0mod4
8289                         .long   Op64M0mod4
8290                         .long   Op65M0mod4
8291                         .long   Op66M0mod4
8292                         .long   Op67M0mod4
8293                         .long   Op68M0mod4
8294                         .long   Op69M0mod4
8295                         .long   Op6AM0mod4
8296                         .long   Op6Bmod4
8297                         .long   Op6Cmod4
8298                         .long   Op6DM0mod4
8299                         .long   Op6EM0mod4
8300                         .long   Op6FM0mod4
8301                         .long   Op70mod4
8302                         .long   Op71M0mod4
8303                         .long   Op72M0mod4
8304                         .long   Op73M0mod4
8305                         .long   Op74M0mod4
8306                         .long   Op75M0mod4
8307                         .long   Op76M0mod4
8308                         .long   Op77M0mod4
8309                         .long   Op78mod4
8310                         .long   Op79M0mod4
8311                         .long   Op7AX1mod4
8312                         .long   Op7Bmod4
8313                         .long   Op7Cmod4
8314                         .long   Op7DM0mod4
8315                         .long   Op7EM0mod4
8316                         .long   Op7FM0mod4
8317                         .long   Op80mod4
8318                         .long   Op81M0mod4
8319                         .long   Op82mod4
8320                         .long   Op83M0mod4
8321                         .long   Op84X1mod4
8322                         .long   Op85M0mod4
8323                         .long   Op86X1mod4
8324                         .long   Op87M0mod4
8325                         .long   Op88X1mod4
8326                         .long   Op89M0mod4
8327                         .long   Op8AM0mod4
8328                         .long   Op8Bmod4
8329                         .long   Op8CX1mod4
8330                         .long   Op8DM0mod4
8331                         .long   Op8EX1mod4
8332                         .long   Op8FM0mod4
8333                         .long   Op90mod4
8334                         .long   Op91M0mod4
8335                         .long   Op92M0mod4
8336                         .long   Op93M0mod4
8337                         .long   Op94X1mod4
8338                         .long   Op95M0mod4
8339                         .long   Op96X1mod4
8340                         .long   Op97M0mod4
8341                         .long   Op98M0mod4
8342                         .long   Op99M0mod4
8343                         .long   Op9Amod4
8344                         .long   Op9BX1mod4
8345                         .long   Op9CM0mod4
8346                         .long   Op9DM0mod4
8347                         .long   Op9EM0mod4
8348                         .long   Op9FM0mod4
8349                         .long   OpA0X1mod4
8350                         .long   OpA1M0mod4
8351                         .long   OpA2X1mod4
8352                         .long   OpA3M0mod4
8353                         .long   OpA4X1mod4
8354                         .long   OpA5M0mod4
8355                         .long   OpA6X1mod4
8356                         .long   OpA7M0mod4
8357                         .long   OpA8X1mod4
8358                         .long   OpA9M0mod4
8359                         .long   OpAAX1mod4
8360                         .long   OpABmod4
8361                         .long   OpACX1mod4
8362                         .long   OpADM0mod4
8363                         .long   OpAEX1mod4
8364                         .long   OpAFM0mod4
8365                         .long   OpB0mod4
8366                         .long   OpB1M0mod4
8367                         .long   OpB2M0mod4
8368                         .long   OpB3M0mod4
8369                         .long   OpB4X1mod4
8370                         .long   OpB5M0mod4
8371                         .long   OpB6X1mod4
8372                         .long   OpB7M0mod4
8373                         .long   OpB8mod4
8374                         .long   OpB9M0mod4
8375                         .long   OpBAX1mod4
8376                         .long   OpBBX1mod4
8377                         .long   OpBCX1mod4
8378                         .long   OpBDM0mod4
8379                         .long   OpBEX1mod4
8380                         .long   OpBFM0mod4
8381                         .long   OpC0X1mod4
8382                         .long   OpC1M0mod4
8383                         .long   OpC2mod4
8384                         .long   OpC3M0mod4
8385                         .long   OpC4X1mod4
8386                         .long   OpC5M0mod4
8387                         .long   OpC6M0mod4
8388                         .long   OpC7M0mod4
8389                         .long   OpC8X1mod4
8390                         .long   OpC9M0mod4
8391                         .long   OpCAX1mod4
8392                         .long   OpCBmod4
8393                         .long   OpCCX1mod4
8394                         .long   OpCDM0mod4
8395                         .long   OpCEM0mod4
8396                         .long   OpCFM0mod4
8397                         .long   OpD0mod4
8398                         .long   OpD1M0mod4
8399                         .long   OpD2M0mod4
8400                         .long   OpD3M0mod4
8401                         .long   OpD4mod4
8402                         .long   OpD5M0mod4
8403                         .long   OpD6M0mod4
8404                         .long   OpD7M0mod4
8405                         .long   OpD8mod4
8406                         .long   OpD9M0mod4
8407                         .long   OpDAX1mod4
8408                         .long   OpDBmod4
8409                         .long   OpDCmod4
8410                         .long   OpDDM0mod4
8411                         .long   OpDEM0mod4
8412                         .long   OpDFM0mod4
8413                         .long   OpE0X1mod4
8414                         .long   OpE1M0mod4
8415                         .long   OpE2mod4
8416                         .long   OpE3M0mod4
8417                         .long   OpE4X1mod4
8418                         .long   OpE5M0mod4
8419                         .long   OpE6M0mod4
8420                         .long   OpE7M0mod4
8421                         .long   OpE8X1mod4
8422                         .long   OpE9M0mod4
8423                         .long   OpEAmod4
8424                         .long   OpEBmod4
8425                         .long   OpECX1mod4
8426                         .long   OpEDM0mod4
8427                         .long   OpEEM0mod4
8428                         .long   OpEFM0mod4
8429                         .long   OpF0mod4
8430                         .long   OpF1M0mod4
8431                         .long   OpF2M0mod4
8432                         .long   OpF3M0mod4
8433                         .long   OpF4mod4
8434                         .long   OpF5M0mod4
8435                         .long   OpF6M0mod4
8436                         .long   OpF7M0mod4
8437                         .long   OpF8mod4
8438                         .long   OpF9M0mod4
8439                         .long   OpFAX1mod4
8440                         .long   OpFBmod4
8441                         .long   OpFCmod4
8442                         .long   OpFDM0mod4
8443                         .long   OpFEM0mod4
8444                         .long   OpFFM0mod4
8445 Op00mod4:
8446 lbl00mod4:      Op00
8447                         NEXTOPCODE
8448 Op01M0mod4:
8449 lbl01mod4a:     DirectIndexedIndirect1
8450 lbl01mod4b:     ORA16
8451                         NEXTOPCODE
8452 Op02mod4:
8453 lbl02mod4:      Op02
8454                         NEXTOPCODE
8455 Op03M0mod4:
8456 lbl03mod4a:     StackasmRelative
8457 lbl03mod4b:     ORA16
8458                         NEXTOPCODE
8459 Op04M0mod4:
8460 lbl04mod4a:     Direct
8461 lbl04mod4b:     TSB16
8462                         NEXTOPCODE
8463 Op05M0mod4:
8464 lbl05mod4a:     Direct
8465 lbl05mod4b:     ORA16
8466                         NEXTOPCODE
8467 Op06M0mod4:
8468 lbl06mod4a:     Direct
8469 lbl06mod4b:     ASL16
8470                         NEXTOPCODE
8471 Op07M0mod4:
8472 lbl07mod4a:     DirectIndirectLong
8473 lbl07mod4b:     ORA16
8474                         NEXTOPCODE
8475 Op08mod4:
8476 lbl08mod4:      Op08
8477                         NEXTOPCODE
8478 Op09M0mod4:
8479 lbl09mod4:      Op09M0
8480                         NEXTOPCODE
8481 Op0AM0mod4:
8482 lbl0Amod4a:     A_ASL16
8483                         NEXTOPCODE
8484 Op0Bmod4:
8485 lbl0Bmod4:      Op0B
8486                         NEXTOPCODE
8487 Op0CM0mod4:
8488 lbl0Cmod4a:     Absolute
8489 lbl0Cmod4b:     TSB16
8490                         NEXTOPCODE
8491 Op0DM0mod4:
8492 lbl0Dmod4a:     Absolute
8493 lbl0Dmod4b:     ORA16
8494                         NEXTOPCODE
8495 Op0EM0mod4:
8496 lbl0Emod4a:     Absolute
8497 lbl0Emod4b:     ASL16
8498                         NEXTOPCODE
8499 Op0FM0mod4:
8500 lbl0Fmod4a:     AbsoluteLong
8501 lbl0Fmod4b:     ORA16
8502                         NEXTOPCODE
8503 Op10mod4:
8504 lbl10mod4:      Op10
8505                         NEXTOPCODE
8506 Op11M0mod4:
8507 lbl11mod4a:     DirectIndirectIndexed1
8508 lbl11mod4b:     ORA16
8509                         NEXTOPCODE
8510 Op12M0mod4:
8511 lbl12mod4a:     DirectIndirect
8512 lbl12mod4b:     ORA16
8513                         NEXTOPCODE
8514 Op13M0mod4:
8515 lbl13mod4a:     StackasmRelativeIndirectIndexed1
8516 lbl13mod4b:     ORA16
8517                         NEXTOPCODE
8518 Op14M0mod4:
8519 lbl14mod4a:     Direct
8520 lbl14mod4b:     TRB16
8521                         NEXTOPCODE
8522 Op15M0mod4:
8523 lbl15mod4a:     DirectIndexedX1
8524 lbl15mod4b:     ORA16
8525                         NEXTOPCODE
8526 Op16M0mod4:
8527 lbl16mod4a:     DirectIndexedX1
8528 lbl16mod4b:     ASL16
8529                         NEXTOPCODE
8530 Op17M0mod4:
8531 lbl17mod4a:     DirectIndirectIndexedLong1
8532 lbl17mod4b:     ORA16
8533                         NEXTOPCODE
8534 Op18mod4:
8535 lbl18mod4:      Op18
8536                         NEXTOPCODE
8537 Op19M0mod4:
8538 lbl19mod4a:     AbsoluteIndexedY1
8539 lbl19mod4b:     ORA16
8540                         NEXTOPCODE
8541 Op1AM0mod4:
8542 lbl1Amod4a:     A_INC16
8543                         NEXTOPCODE
8544 Op1Bmod4:
8545 lbl1Bmod4:      Op1BM0
8546                         NEXTOPCODE
8547 Op1CM0mod4:
8548 lbl1Cmod4a:     Absolute
8549 lbl1Cmod4b:     TRB16
8550                         NEXTOPCODE
8551 Op1DM0mod4:
8552 lbl1Dmod4a:     AbsoluteIndexedX1
8553 lbl1Dmod4b:     ORA16
8554                         NEXTOPCODE
8555 Op1EM0mod4:
8556 lbl1Emod4a:     AbsoluteIndexedX1
8557 lbl1Emod4b:     ASL16
8558                         NEXTOPCODE
8559 Op1FM0mod4:
8560 lbl1Fmod4a:     AbsoluteLongIndexedX1
8561 lbl1Fmod4b:     ORA16
8562                         NEXTOPCODE
8563 Op20mod4:
8564 lbl20mod4:      Op20
8565                         NEXTOPCODE
8566 Op21M0mod4:
8567 lbl21mod4a:     DirectIndexedIndirect1
8568 lbl21mod4b:     AND16
8569                         NEXTOPCODE
8570 Op22mod4:
8571 lbl22mod4:      Op22
8572                         NEXTOPCODE
8573 Op23M0mod4:
8574 lbl23mod4a:     StackasmRelative
8575 lbl23mod4b:     AND16
8576                         NEXTOPCODE
8577 Op24M0mod4:
8578 lbl24mod4a:     Direct
8579 lbl24mod4b:     BIT16
8580                         NEXTOPCODE
8581 Op25M0mod4:
8582 lbl25mod4a:     Direct
8583 lbl25mod4b:     AND16
8584                         NEXTOPCODE
8585 Op26M0mod4:
8586 lbl26mod4a:     Direct
8587 lbl26mod4b:     ROL16
8588                         NEXTOPCODE
8589 Op27M0mod4:
8590 lbl27mod4a:     DirectIndirectLong
8591 lbl27mod4b:     AND16
8592                         NEXTOPCODE
8593 Op28mod4:
8594 lbl28mod4:      Op28X1M0
8595                         NEXTOPCODE
8596 .pool
8597 Op29M0mod4:
8598 lbl29mod4:      Op29M0
8599                         NEXTOPCODE
8600 Op2AM0mod4:
8601 lbl2Amod4a:     A_ROL16
8602                         NEXTOPCODE
8603 Op2Bmod4:
8604 lbl2Bmod4:      Op2B
8605                         NEXTOPCODE
8606 Op2CM0mod4:
8607 lbl2Cmod4a:     Absolute
8608 lbl2Cmod4b:     BIT16
8609                         NEXTOPCODE
8610 Op2DM0mod4:
8611 lbl2Dmod4a:     Absolute
8612 lbl2Dmod4b:     AND16
8613                         NEXTOPCODE
8614 Op2EM0mod4:
8615 lbl2Emod4a:     Absolute
8616 lbl2Emod4b:     ROL16
8617                         NEXTOPCODE
8618 Op2FM0mod4:
8619 lbl2Fmod4a:     AbsoluteLong
8620 lbl2Fmod4b:     AND16
8621                         NEXTOPCODE
8622 Op30mod4:
8623 lbl30mod4:      Op30
8624                         NEXTOPCODE
8625 Op31M0mod4:
8626 lbl31mod4a:     DirectIndirectIndexed1
8627 lbl31mod4b:     AND16
8628                         NEXTOPCODE
8629 Op32M0mod4:
8630 lbl32mod4a:     DirectIndirect
8631 lbl32mod4b:     AND16
8632                         NEXTOPCODE
8633 Op33M0mod4:
8634 lbl33mod4a:     StackasmRelativeIndirectIndexed1
8635 lbl33mod4b:     AND16
8636                         NEXTOPCODE
8637 Op34M0mod4:
8638 lbl34mod4a:     DirectIndexedX1
8639 lbl34mod4b:     BIT16
8640                         NEXTOPCODE
8641 Op35M0mod4:
8642 lbl35mod4a:     DirectIndexedX1
8643 lbl35mod4b:     AND16
8644                         NEXTOPCODE
8645 Op36M0mod4:
8646 lbl36mod4a:     DirectIndexedX1
8647 lbl36mod4b:     ROL16
8648                         NEXTOPCODE
8649 Op37M0mod4:
8650 lbl37mod4a:     DirectIndirectIndexedLong1
8651 lbl37mod4b:     AND16
8652                         NEXTOPCODE
8653 Op38mod4:
8654 lbl38mod4:      Op38
8655                         NEXTOPCODE
8656 Op39M0mod4:
8657 lbl39mod4a:     AbsoluteIndexedY1
8658 lbl39mod4b:     AND16
8659                         NEXTOPCODE
8660 Op3AM0mod4:
8661 lbl3Amod4a:     A_DEC16
8662                         NEXTOPCODE
8663 Op3Bmod4:
8664 lbl3Bmod4:      Op3BM0
8665                         NEXTOPCODE
8666 Op3CM0mod4:
8667 lbl3Cmod4a:     AbsoluteIndexedX1
8668 lbl3Cmod4b:     BIT16
8669                         NEXTOPCODE
8670 Op3DM0mod4:
8671 lbl3Dmod4a:     AbsoluteIndexedX1
8672 lbl3Dmod4b:     AND16
8673                         NEXTOPCODE
8674 Op3EM0mod4:
8675 lbl3Emod4a:     AbsoluteIndexedX1
8676 lbl3Emod4b:     ROL16
8677                         NEXTOPCODE
8678 Op3FM0mod4:
8679 lbl3Fmod4a:     AbsoluteLongIndexedX1
8680 lbl3Fmod4b:     AND16
8681                         NEXTOPCODE
8682 Op40mod4:
8683 lbl40mod4:      Op40X1M0
8684                         NEXTOPCODE
8685 .pool
8686 Op41M0mod4:
8687 lbl41mod4a:     DirectIndexedIndirect1
8688 lbl41mod4b:     EOR16
8689                         NEXTOPCODE
8690 Op42mod4:
8691 lbl42mod4:      Op42
8692                         NEXTOPCODE
8693 Op43M0mod4:
8694 lbl43mod4a:     StackasmRelative
8695 lbl43mod4b:     EOR16
8696                         NEXTOPCODE
8697 Op44X1mod4:
8698 lbl44mod4:      Op44X1M0
8699                         NEXTOPCODE
8700 Op45M0mod4:
8701 lbl45mod4a:     Direct
8702 lbl45mod4b:     EOR16
8703                         NEXTOPCODE
8704 Op46M0mod4:
8705 lbl46mod4a:     Direct
8706 lbl46mod4b:     LSR16
8707                         NEXTOPCODE
8708 Op47M0mod4:
8709 lbl47mod4a:     DirectIndirectLong
8710 lbl47mod4b:     EOR16
8711                         NEXTOPCODE
8712 Op48M0mod4:
8713 lbl48mod4:      Op48M0
8714                         NEXTOPCODE
8715 Op49M0mod4:
8716 lbl49mod4:      Op49M0
8717                         NEXTOPCODE
8718 Op4AM0mod4:
8719 lbl4Amod4a:     A_LSR16
8720                         NEXTOPCODE
8721 Op4Bmod4:
8722 lbl4Bmod4:      Op4B
8723                         NEXTOPCODE
8724 Op4Cmod4:
8725 lbl4Cmod4:      Op4C
8726                         NEXTOPCODE
8727 Op4DM0mod4:
8728 lbl4Dmod4a:     Absolute
8729 lbl4Dmod4b:     EOR16
8730                         NEXTOPCODE
8731 Op4EM0mod4:
8732 lbl4Emod4a:     Absolute
8733 lbl4Emod4b:     LSR16
8734                         NEXTOPCODE
8735 Op4FM0mod4:
8736 lbl4Fmod4a:     AbsoluteLong
8737 lbl4Fmod4b:     EOR16
8738                         NEXTOPCODE
8739 Op50mod4:
8740 lbl50mod4:      Op50
8741                         NEXTOPCODE
8742 Op51M0mod4:
8743 lbl51mod4a:     DirectIndirectIndexed1
8744 lbl51mod4b:     EOR16
8745                         NEXTOPCODE
8746 Op52M0mod4:
8747 lbl52mod4a:     DirectIndirect
8748 lbl52mod4b:     EOR16
8749                         NEXTOPCODE
8750 Op53M0mod4:
8751 lbl53mod4a:     StackasmRelativeIndirectIndexed1
8752 lbl53mod4b:     EOR16
8753                         NEXTOPCODE
8754 Op54X1mod4:
8755 lbl54mod4:      Op54X1M0
8756                         NEXTOPCODE
8757 Op55M0mod4:
8758 lbl55mod4a:     DirectIndexedX1
8759 lbl55mod4b:     EOR16
8760                         NEXTOPCODE
8761 Op56M0mod4:
8762 lbl56mod4a:     DirectIndexedX1
8763 lbl56mod4b:     LSR16
8764                         NEXTOPCODE
8765 Op57M0mod4:
8766 lbl57mod4a:     DirectIndirectIndexedLong1
8767 lbl57mod4b:     EOR16
8768                         NEXTOPCODE
8769 Op58mod4:
8770 lbl58mod4:      Op58
8771                         NEXTOPCODE
8772 Op59M0mod4:
8773 lbl59mod4a:     AbsoluteIndexedY1
8774 lbl59mod4b:     EOR16
8775                         NEXTOPCODE
8776 Op5AX1mod4:
8777 lbl5Amod4:      Op5AX1
8778                         NEXTOPCODE
8779 Op5Bmod4:
8780 lbl5Bmod4:      Op5BM0
8781                         NEXTOPCODE
8782 Op5Cmod4:
8783 lbl5Cmod4:      Op5C
8784                         NEXTOPCODE
8785 Op5DM0mod4:
8786 lbl5Dmod4a:     AbsoluteIndexedX1
8787 lbl5Dmod4b:     EOR16
8788                         NEXTOPCODE
8789 Op5EM0mod4:
8790 lbl5Emod4a:     AbsoluteIndexedX1
8791 lbl5Emod4b:     LSR16
8792                         NEXTOPCODE
8793 Op5FM0mod4:
8794 lbl5Fmod4a:     AbsoluteLongIndexedX1
8795 lbl5Fmod4b:     EOR16
8796                         NEXTOPCODE
8797 Op60mod4:
8798 lbl60mod4:      Op60
8799                         NEXTOPCODE
8800 Op61M0mod4:
8801 lbl61mod4a:     DirectIndexedIndirect1
8802 lbl61mod4b:     ADC16
8803                         NEXTOPCODE
8804 Op62mod4:
8805 lbl62mod4:      Op62
8806                         NEXTOPCODE
8807 Op63M0mod4:
8808 lbl63mod4a:     StackasmRelative
8809 lbl63mod4b:     ADC16
8810                         NEXTOPCODE
8811 .pool
8812 Op64M0mod4:
8813 lbl64mod4a:     Direct
8814 lbl64mod4b:     STZ16
8815                         NEXTOPCODE
8816 Op65M0mod4:
8817 lbl65mod4a:     Direct
8818 lbl65mod4b:     ADC16
8819                         NEXTOPCODE
8820 .pool
8821 Op66M0mod4:
8822 lbl66mod4a:     Direct
8823 lbl66mod4b:     ROR16
8824                         NEXTOPCODE
8825 Op67M0mod4:
8826 lbl67mod4a:     DirectIndirectLong
8827 lbl67mod4b:     ADC16
8828                         NEXTOPCODE
8829 .pool
8830 Op68M0mod4:
8831 lbl68mod4:      Op68M0
8832                         NEXTOPCODE
8833 Op69M0mod4:
8834 lbl69mod4a:     Immediate16
8835 lbl69mod4b:     ADC16
8836                         NEXTOPCODE
8837 .pool
8838 Op6AM0mod4:
8839 lbl6Amod4a:     A_ROR16
8840                         NEXTOPCODE
8841 Op6Bmod4:
8842 lbl6Bmod4:      Op6B
8843                         NEXTOPCODE
8844 Op6Cmod4:
8845 lbl6Cmod4:      Op6C
8846                         NEXTOPCODE
8847 Op6DM0mod4:
8848 lbl6Dmod4a:     Absolute
8849 lbl6Dmod4b:     ADC16
8850                         NEXTOPCODE
8851 Op6EM0mod4:
8852 lbl6Emod4a:     Absolute
8853 lbl6Emod4b:     ROR16
8854                         NEXTOPCODE
8855 Op6FM0mod4:
8856 lbl6Fmod4a:     AbsoluteLong
8857 lbl6Fmod4b:     ADC16
8858                         NEXTOPCODE
8859 Op70mod4:
8860 lbl70mod4:      Op70
8861                         NEXTOPCODE
8862 Op71M0mod4:
8863 lbl71mod4a:     DirectIndirectIndexed1
8864 lbl71mod4b:     ADC16
8865                         NEXTOPCODE
8866 Op72M0mod4:
8867 lbl72mod4a:     DirectIndirect
8868 lbl72mod4b:     ADC16
8869                         NEXTOPCODE
8870 Op73M0mod4:
8871 lbl73mod4a:     StackasmRelativeIndirectIndexed1
8872 lbl73mod4b:     ADC16
8873                         NEXTOPCODE
8874 .pool
8875 Op74M0mod4:
8876 lbl74mod4a:     DirectIndexedX1
8877 lbl74mod4b:     STZ16
8878                         NEXTOPCODE
8879 Op75M0mod4:
8880 lbl75mod4a:     DirectIndexedX1
8881 lbl75mod4b:     ADC16
8882                         NEXTOPCODE
8883 .pool
8884 Op76M0mod4:
8885 lbl76mod4a:     DirectIndexedX1
8886 lbl76mod4b:     ROR16
8887                         NEXTOPCODE
8888 Op77M0mod4:
8889 lbl77mod4a:     DirectIndirectIndexedLong1
8890 lbl77mod4b:     ADC16
8891                         NEXTOPCODE
8892 Op78mod4:
8893 lbl78mod4:      Op78
8894                         NEXTOPCODE
8895 Op79M0mod4:
8896 lbl79mod4a:     AbsoluteIndexedY1
8897 lbl79mod4b:     ADC16
8898                         NEXTOPCODE
8899 Op7AX1mod4:
8900 lbl7Amod4:      Op7AX1
8901                         NEXTOPCODE
8902 Op7Bmod4:
8903 lbl7Bmod4:      Op7BM0
8904                         NEXTOPCODE
8905 Op7Cmod4:
8906 lbl7Cmod4:      AbsoluteIndexedIndirectX1
8907                 Op7C
8908                         NEXTOPCODE
8909 Op7DM0mod4:
8910 lbl7Dmod4a:     AbsoluteIndexedX1
8911 lbl7Dmod4b:     ADC16
8912                         NEXTOPCODE
8913 Op7EM0mod4:
8914 lbl7Emod4a:     AbsoluteIndexedX1
8915 lbl7Emod4b:     ROR16
8916                         NEXTOPCODE
8917 Op7FM0mod4:
8918 lbl7Fmod4a:     AbsoluteLongIndexedX1
8919 lbl7Fmod4b:     ADC16
8920                         NEXTOPCODE
8921 .pool
8922 Op80mod4:
8923 lbl80mod4:      Op80
8924                         NEXTOPCODE
8925 Op81M0mod4:
8926 lbl81mod4a:     DirectIndexedIndirect1
8927 lbl81mod4b:     Op81M0
8928                         NEXTOPCODE
8929 Op82mod4:
8930 lbl82mod4:      Op82
8931                         NEXTOPCODE
8932 Op83M0mod4:
8933 lbl83mod4a:     StackasmRelative
8934 lbl83mod4b:     STA16
8935                         NEXTOPCODE
8936 Op84X1mod4:
8937 lbl84mod4a:     Direct
8938 lbl84mod4b:     STY8
8939                         NEXTOPCODE
8940 Op85M0mod4:
8941 lbl85mod4a:     Direct
8942 lbl85mod4b:     STA16
8943                         NEXTOPCODE
8944 Op86X1mod4:
8945 lbl86mod4a:     Direct
8946 lbl86mod4b:     STX8
8947                         NEXTOPCODE
8948 Op87M0mod4:
8949 lbl87mod4a:     DirectIndirectLong
8950 lbl87mod4b:     STA16
8951                         NEXTOPCODE
8952 Op88X1mod4:
8953 lbl88mod4:      Op88X1
8954                         NEXTOPCODE
8955 Op89M0mod4:
8956 lbl89mod4:      Op89M0
8957                         NEXTOPCODE
8958 Op8AM0mod4:
8959 lbl8Amod4:      Op8AM0X1
8960                         NEXTOPCODE
8961 Op8Bmod4:
8962 lbl8Bmod4:      Op8B
8963                         NEXTOPCODE
8964 Op8CX1mod4:
8965 lbl8Cmod4a:     Absolute
8966 lbl8Cmod4b:     STY8
8967                         NEXTOPCODE
8968 Op8DM0mod4:
8969 lbl8Dmod4a:     Absolute
8970 lbl8Dmod4b:     STA16
8971                         NEXTOPCODE
8972 Op8EX1mod4:
8973 lbl8Emod4a:     Absolute
8974 lbl8Emod4b:     STX8
8975                         NEXTOPCODE
8976 Op8FM0mod4:
8977 lbl8Fmod4a:     AbsoluteLong
8978 lbl8Fmod4b:     STA16
8979                         NEXTOPCODE
8980 Op90mod4:
8981 lbl90mod4:      Op90
8982                         NEXTOPCODE
8983 Op91M0mod4:
8984 lbl91mod4a:     DirectIndirectIndexed1
8985 lbl91mod4b:     STA16
8986                         NEXTOPCODE
8987 Op92M0mod4:
8988 lbl92mod4a:     DirectIndirect
8989 lbl92mod4b:     STA16
8990                         NEXTOPCODE
8991 Op93M0mod4:
8992 lbl93mod4a:     StackasmRelativeIndirectIndexed1
8993 lbl93mod4b:     STA16
8994                         NEXTOPCODE
8995 Op94X1mod4:
8996 lbl94mod4a:     DirectIndexedX1
8997 lbl94mod4b:     STY8
8998                         NEXTOPCODE
8999 Op95M0mod4:
9000 lbl95mod4a:     DirectIndexedX1
9001 lbl95mod4b:     STA16
9002                         NEXTOPCODE
9003 Op96X1mod4:
9004 lbl96mod4a:     DirectIndexedY1
9005 lbl96mod4b:     STX8
9006                         NEXTOPCODE
9007 Op97M0mod4:
9008 lbl97mod4a:     DirectIndirectIndexedLong1
9009 lbl97mod4b:     STA16
9010                         NEXTOPCODE
9011 Op98M0mod4:
9012 lbl98mod4:      Op98M0X1
9013                         NEXTOPCODE
9014 Op99M0mod4:
9015 lbl99mod4a:     AbsoluteIndexedY1
9016 lbl99mod4b:     STA16
9017                         NEXTOPCODE
9018 Op9Amod4:
9019 lbl9Amod4:      Op9AX1
9020                         NEXTOPCODE
9021 Op9BX1mod4:
9022 lbl9Bmod4:      Op9BX1
9023                         NEXTOPCODE
9024 Op9CM0mod4:
9025 lbl9Cmod4a:     Absolute
9026 lbl9Cmod4b:     STZ16
9027                         NEXTOPCODE
9028 Op9DM0mod4:
9029 lbl9Dmod4a:     AbsoluteIndexedX1
9030 lbl9Dmod4b:     STA16
9031                         NEXTOPCODE
9032 Op9EM0mod4:
9033 lbl9Emod4:      AbsoluteIndexedX1
9034                 STZ16
9035                         NEXTOPCODE
9036 Op9FM0mod4:
9037 lbl9Fmod4a:     AbsoluteLongIndexedX1
9038 lbl9Fmod4b:     STA16
9039                         NEXTOPCODE
9040 OpA0X1mod4:
9041 lblA0mod4:      OpA0X1
9042                         NEXTOPCODE
9043 OpA1M0mod4:
9044 lblA1mod4a:     DirectIndexedIndirect1
9045 lblA1mod4b:     LDA16
9046                         NEXTOPCODE
9047 OpA2X1mod4:
9048 lblA2mod4:      OpA2X1
9049                         NEXTOPCODE
9050 OpA3M0mod4:
9051 lblA3mod4a:     StackasmRelative
9052 lblA3mod4b:     LDA16
9053                         NEXTOPCODE
9054 OpA4X1mod4:
9055 lblA4mod4a:     Direct
9056 lblA4mod4b:     LDY8
9057                         NEXTOPCODE
9058 OpA5M0mod4:
9059 lblA5mod4a:     Direct
9060 lblA5mod4b:     LDA16
9061                         NEXTOPCODE
9062 OpA6X1mod4:
9063 lblA6mod4a:     Direct
9064 lblA6mod4b:     LDX8
9065                         NEXTOPCODE
9066 OpA7M0mod4:
9067 lblA7mod4a:     DirectIndirectLong
9068 lblA7mod4b:     LDA16
9069                         NEXTOPCODE
9070 OpA8X1mod4:
9071 lblA8mod4:      OpA8X1M0
9072                         NEXTOPCODE
9073 OpA9M0mod4:
9074 lblA9mod4:      OpA9M0
9075                         NEXTOPCODE
9076 OpAAX1mod4:
9077 lblAAmod4:      OpAAX1M0
9078                         NEXTOPCODE
9079 OpABmod4:
9080 lblABmod4:      OpAB
9081                         NEXTOPCODE
9082 OpACX1mod4:
9083 lblACmod4a:     Absolute
9084 lblACmod4b:     LDY8
9085                         NEXTOPCODE
9086 OpADM0mod4:
9087 lblADmod4a:     Absolute
9088 lblADmod4b:     LDA16
9089                         NEXTOPCODE
9090 OpAEX1mod4:
9091 lblAEmod4a:     Absolute
9092 lblAEmod4b:     LDX8
9093                         NEXTOPCODE
9094 OpAFM0mod4:
9095 lblAFmod4a:     AbsoluteLong
9096 lblAFmod4b:     LDA16
9097                         NEXTOPCODE
9098 OpB0mod4:
9099 lblB0mod4:      OpB0
9100                         NEXTOPCODE
9101 OpB1M0mod4:
9102 lblB1mod4a:     DirectIndirectIndexed1
9103 lblB1mod4b:     LDA16
9104                         NEXTOPCODE
9105 OpB2M0mod4:
9106 lblB2mod4a:     DirectIndirect
9107 lblB2mod4b:     LDA16
9108                         NEXTOPCODE
9109 OpB3M0mod4:
9110 lblB3mod4a:     StackasmRelativeIndirectIndexed1
9111 lblB3mod4b:     LDA16
9112                         NEXTOPCODE
9113 OpB4X1mod4:
9114 lblB4mod4a:     DirectIndexedX1
9115 lblB4mod4b:     LDY8
9116                         NEXTOPCODE
9117 OpB5M0mod4:
9118 lblB5mod4a:     DirectIndexedX1
9119 lblB5mod4b:     LDA16
9120                         NEXTOPCODE
9121 OpB6X1mod4:
9122 lblB6mod4a:     DirectIndexedY1
9123 lblB6mod4b:     LDX8
9124                         NEXTOPCODE
9125 OpB7M0mod4:
9126 lblB7mod4a:     DirectIndirectIndexedLong1
9127 lblB7mod4b:     LDA16
9128                         NEXTOPCODE
9129 OpB8mod4:
9130 lblB8mod4:      OpB8
9131                         NEXTOPCODE
9132 OpB9M0mod4:
9133 lblB9mod4a:     AbsoluteIndexedY1
9134 lblB9mod4b:     LDA16
9135                         NEXTOPCODE
9136 OpBAX1mod4:
9137 lblBAmod4:      OpBAX1
9138                         NEXTOPCODE
9139 OpBBX1mod4:
9140 lblBBmod4:      OpBBX1
9141                         NEXTOPCODE
9142 OpBCX1mod4:
9143 lblBCmod4a:     AbsoluteIndexedX1
9144 lblBCmod4b:     LDY8
9145                         NEXTOPCODE
9146 OpBDM0mod4:
9147 lblBDmod4a:     AbsoluteIndexedX1
9148 lblBDmod4b:     LDA16
9149                         NEXTOPCODE
9150 OpBEX1mod4:
9151 lblBEmod4a:     AbsoluteIndexedY1
9152 lblBEmod4b:     LDX8
9153                         NEXTOPCODE
9154 OpBFM0mod4:
9155 lblBFmod4a:     AbsoluteLongIndexedX1
9156 lblBFmod4b:     LDA16
9157                         NEXTOPCODE
9158 OpC0X1mod4:
9159 lblC0mod4:      OpC0X1
9160                         NEXTOPCODE
9161 OpC1M0mod4:
9162 lblC1mod4a:     DirectIndexedIndirect1
9163 lblC1mod4b:     CMP16
9164                         NEXTOPCODE
9165 OpC2mod4:
9166 lblC2mod4:      OpC2
9167                         NEXTOPCODE
9168 .pool
9169 OpC3M0mod4:
9170 lblC3mod4a:     StackasmRelative
9171 lblC3mod4b:     CMP16
9172                         NEXTOPCODE
9173 OpC4X1mod4:
9174 lblC4mod4a:     Direct
9175 lblC4mod4b:     CMY8
9176                         NEXTOPCODE
9177 OpC5M0mod4:
9178 lblC5mod4a:     Direct
9179 lblC5mod4b:     CMP16
9180                         NEXTOPCODE
9181 OpC6M0mod4:
9182 lblC6mod4a:     Direct
9183 lblC6mod4b:     DEC16
9184                         NEXTOPCODE
9185 OpC7M0mod4:
9186 lblC7mod4a:     DirectIndirectLong
9187 lblC7mod4b:     CMP16
9188                         NEXTOPCODE
9189 OpC8X1mod4:
9190 lblC8mod4:      OpC8X1
9191                         NEXTOPCODE
9192 OpC9M0mod4:
9193 lblC9mod4:      OpC9M0
9194                         NEXTOPCODE
9195 OpCAX1mod4:
9196 lblCAmod4:      OpCAX1
9197                         NEXTOPCODE
9198 OpCBmod4:
9199 lblCBmod4:      OpCB
9200                         NEXTOPCODE
9201 OpCCX1mod4:
9202 lblCCmod4a:     Absolute
9203 lblCCmod4b:     CMY8
9204                         NEXTOPCODE
9205 OpCDM0mod4:
9206 lblCDmod4a:     Absolute
9207 lblCDmod4b:     CMP16
9208                         NEXTOPCODE
9209 OpCEM0mod4:
9210 lblCEmod4a:     Absolute
9211 lblCEmod4b:     DEC16
9212                         NEXTOPCODE
9213 OpCFM0mod4:
9214 lblCFmod4a:     AbsoluteLong
9215 lblCFmod4b:     CMP16
9216                         NEXTOPCODE
9217 OpD0mod4:
9218 lblD0mod4:      OpD0
9219                         NEXTOPCODE
9220 OpD1M0mod4:
9221 lblD1mod4a:     DirectIndirectIndexed1
9222 lblD1mod4b:     CMP16
9223                         NEXTOPCODE
9224 OpD2M0mod4:
9225 lblD2mod4a:     DirectIndirect
9226 lblD2mod4b:     CMP16
9227                         NEXTOPCODE
9228 OpD3M0mod4:
9229 lblD3mod4a:     StackasmRelativeIndirectIndexed1
9230 lblD3mod4b:     CMP16
9231                         NEXTOPCODE
9232 OpD4mod4:
9233 lblD4mod4:      OpD4
9234                         NEXTOPCODE
9235 OpD5M0mod4:
9236 lblD5mod4a:     DirectIndexedX1
9237 lblD5mod4b:     CMP16
9238                         NEXTOPCODE
9239 OpD6M0mod4:
9240 lblD6mod4a:     DirectIndexedX1
9241 lblD6mod4b:     DEC16
9242                         NEXTOPCODE
9243 OpD7M0mod4:
9244 lblD7mod4a:     DirectIndirectIndexedLong1
9245 lblD7mod4b:     CMP16
9246                         NEXTOPCODE
9247 OpD8mod4:
9248 lblD8mod4:      OpD8
9249                         NEXTOPCODE
9250 OpD9M0mod4:
9251 lblD9mod4a:     AbsoluteIndexedY1
9252 lblD9mod4b:     CMP16
9253                         NEXTOPCODE
9254 OpDAX1mod4:
9255 lblDAmod4:      OpDAX1
9256                         NEXTOPCODE
9257 OpDBmod4:
9258 lblDBmod4:      OpDB
9259                         NEXTOPCODE
9260 OpDCmod4:
9261 lblDCmod4:      OpDC
9262                         NEXTOPCODE
9263 OpDDM0mod4:
9264 lblDDmod4a:     AbsoluteIndexedX1
9265 lblDDmod4b:     CMP16
9266                         NEXTOPCODE
9267 OpDEM0mod4:
9268 lblDEmod4a:     AbsoluteIndexedX1
9269 lblDEmod4b:     DEC16
9270                         NEXTOPCODE
9271 OpDFM0mod4:
9272 lblDFmod4a:     AbsoluteLongIndexedX1
9273 lblDFmod4b:     CMP16
9274                         NEXTOPCODE
9275 OpE0X1mod4:
9276 lblE0mod4:      OpE0X1
9277                         NEXTOPCODE
9278 OpE1M0mod4:
9279 lblE1mod4a:     DirectIndexedIndirect1
9280 lblE1mod4b:     SBC16
9281                         NEXTOPCODE
9282 OpE2mod4:
9283 lblE2mod4:      OpE2
9284                         NEXTOPCODE
9285 .pool
9286 OpE3M0mod4:
9287 lblE3mod4a:     StackasmRelative
9288 lblE3mod4b:     SBC16
9289                         NEXTOPCODE
9290 OpE4X1mod4:
9291 lblE4mod4a:     Direct
9292 lblE4mod4b:     CMX8
9293                         NEXTOPCODE
9294 OpE5M0mod4:
9295 lblE5mod4a:     Direct
9296 lblE5mod4b:     SBC16
9297                         NEXTOPCODE
9298 OpE6M0mod4:
9299 lblE6mod4a:     Direct
9300 lblE6mod4b:     INC16
9301                         NEXTOPCODE
9302 OpE7M0mod4:
9303 lblE7mod4a:     DirectIndirectLong
9304 lblE7mod4b:     SBC16
9305                         NEXTOPCODE
9306 OpE8X1mod4:
9307 lblE8mod4:      OpE8X1
9308                         NEXTOPCODE
9309 OpE9M0mod4:
9310 lblE9mod4a:     Immediate16
9311 lblE9mod4b:     SBC16
9312                         NEXTOPCODE
9313 OpEAmod4:
9314 lblEAmod4:      OpEA
9315                         NEXTOPCODE
9316 OpEBmod4:
9317 lblEBmod4:      OpEBM0
9318                         NEXTOPCODE
9319 OpECX1mod4:
9320 lblECmod4a:     Absolute
9321 lblECmod4b:     CMX8
9322                         NEXTOPCODE
9323 OpEDM0mod4:
9324 lblEDmod4a:     Absolute
9325 lblEDmod4b:     SBC16
9326                         NEXTOPCODE
9327 OpEEM0mod4:
9328 lblEEmod4a:     Absolute
9329 lblEEmod4b:     INC16
9330                         NEXTOPCODE
9331 OpEFM0mod4:
9332 lblEFmod4a:     AbsoluteLong
9333 lblEFmod4b:     SBC16
9334                         NEXTOPCODE
9335 OpF0mod4:
9336 lblF0mod4:      OpF0
9337                         NEXTOPCODE
9338 OpF1M0mod4:
9339 lblF1mod4a:     DirectIndirectIndexed1
9340 lblF1mod4b:     SBC16
9341                         NEXTOPCODE
9342 OpF2M0mod4:
9343 lblF2mod4a:     DirectIndirect
9344 lblF2mod4b:     SBC16
9345                         NEXTOPCODE
9346 OpF3M0mod4:
9347 lblF3mod4a:     StackasmRelativeIndirectIndexed1
9348 lblF3mod4b:     SBC16
9349                         NEXTOPCODE
9350 OpF4mod4:
9351 lblF4mod4:      OpF4
9352                         NEXTOPCODE
9353 OpF5M0mod4:
9354 lblF5mod4a:     DirectIndexedX1
9355 lblF5mod4b:     SBC16
9356                         NEXTOPCODE
9357 OpF6M0mod4:
9358 lblF6mod4a:     DirectIndexedX1
9359 lblF6mod4b:     INC16
9360                         NEXTOPCODE
9361 OpF7M0mod4:
9362 lblF7mod4a:     DirectIndirectIndexedLong1
9363 lblF7mod4b:     SBC16
9364                         NEXTOPCODE
9365 OpF8mod4:
9366 lblF8mod4:      OpF8
9367                         NEXTOPCODE
9368 OpF9M0mod4:
9369 lblF9mod4a:     AbsoluteIndexedY1
9370 lblF9mod4b:     SBC16
9371                         NEXTOPCODE
9372 OpFAX1mod4:
9373 lblFAmod4:      OpFAX1
9374                         NEXTOPCODE
9375 OpFBmod4:
9376 lblFBmod4:      OpFB
9377                         NEXTOPCODE
9378 OpFCmod4:
9379 lblFCmod4:      OpFCX1
9380                         NEXTOPCODE
9381 OpFDM0mod4:
9382 lblFDmod4a:     AbsoluteIndexedX1
9383 lblFDmod4b:     SBC16
9384                         NEXTOPCODE
9385 OpFEM0mod4:
9386 lblFEmod4a:     AbsoluteIndexedX1
9387 lblFEmod4b:     INC16
9388                         NEXTOPCODE
9389 OpFFM0mod4:
9390 lblFFmod4a:     AbsoluteLongIndexedX1
9391 lblFFmod4b:     SBC16
9392                         NEXTOPCODE
9393
9394
9395                         .pool
9396