git.maemo.org Git - drnoksnes/blob - os9x_65c816_mac_op.h

   1 /*****************************************************************
   2         FLAGS
   3 *****************************************************************/
   4
   5 .macro          UPDATE_C
   6                 // CC : ARM Carry Clear
   7                 BICCC   rstatus, rstatus, #MASK_CARRY  //       0 : AND mask 11111011111 : set C to zero
   8                 // CS : ARM Carry Set
   9                 ORRCS   rstatus, rstatus, #MASK_CARRY      //   1 : OR  mask 00000100000 : set C to one
  10 .endm
  11 .macro          UPDATE_Z
  12                 // NE : ARM Zero Clear
  13                 BICNE   rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
  14                 // EQ : ARM Zero Set
  15                 ORREQ   rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
  16 .endm
  17 .macro          UPDATE_ZN
  18                 // NE : ARM Zero Clear
  19                 BICNE   rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
  20                 // EQ : ARM Zero Set
  21                 ORREQ   rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
  22                 // PL : ARM Neg Clear
  23                 BICPL   rstatus, rstatus, #MASK_NEG     // 0 : AND mask 11111011111 : set N to zero
  24                 // MI : ARM Neg Set
  25                 ORRMI   rstatus, rstatus, #MASK_NEG     // 1 : OR  mask 00000100000 : set N to one
  26 .endm
  27
  28 /*****************************************************************
  29         OPCODES_MAC
  30 *****************************************************************/
  31
  32
  33
  34
  35 .macro ADC8
  36                 TST rstatus, #MASK_DECIMAL
  37                 BEQ 1111f
  38                 S9xGetByte
  39
  40
  41                 STMFD   R13!,{rscratch}
  42                 MOV     rscratch4,#0x0F000000
  43                 //rscratch2=xxW1xxxxxxxxxxxx
  44                 AND     rscratch2, rscratch, rscratch4
  45                 //rscratch=xxW2xxxxxxxxxxxx
  46                 AND     rscratch, rscratch4, rscratch, LSR #4
  47                 //rscratch3=xxA2xxxxxxxxxxxx
  48                 AND     rscratch3, rscratch4, regA, LSR #4
  49                 //rscratch4=xxA1xxxxxxxxxxxx
  50                 AND     rscratch4,regA,rscratch4
  51                 //R1=A1+W1+CARRY
  52                 TST     rstatus, #MASK_CARRY
  53                 ADDNE   rscratch2, rscratch2, #0x01000000
  54                 ADD     rscratch2,rscratch2,rscratch4
  55                 // if R1 > 9
  56                 CMP     rscratch2, #0x09000000
  57                 // then R1 -= 10
  58                 SUBGT   rscratch2, rscratch2, #0x0A000000
  59                 // then A2++
  60                 ADDGT   rscratch3, rscratch3, #0x01000000
  61                 // R2 = A2+W2
  62                 ADD     rscratch3, rscratch3, rscratch
  63                 // if R2 > 9
  64                 CMP     rscratch3, #0x09000000
  65                 // then R2 -= 10//
  66                 SUBGT   rscratch3, rscratch3, #0x0A000000
  67                 // then SetCarry()
  68                 ORRGT   rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
  69                 // else ClearCarry()
  70                 BICLE   rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
  71                 // gather rscratch3 and rscratch2 into ans8
  72                 // rscratch3 : 0R2000000
  73                 // rscratch2 : 0R1000000
  74                 // -> 0xR2R1000000
  75                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
  76                 LDMFD   R13!,{rscratch}
  77                 //only last bit
  78                 AND     rscratch,rscratch,#0x80000000
  79                 // (register.AL ^ Work8)
  80                 EORS    rscratch3, regA, rscratch
  81                 BICNE   rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
  82                 BNE     1112f
  83                 // (Work8 ^ Ans8)
  84                 EORS    rscratch3, rscratch2, rscratch
  85                 // & 0x80
  86                 TSTNE   rscratch3,#0x80000000
  87                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
  88                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
  89 1112:
  90                 MOVS regA, rscratch2
  91                 UPDATE_ZN
  92                 B 1113f
  93 1111:
  94                 S9xGetByteLow
  95                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
  96                 SUBCS rscratch, rscratch, #0x100
  97                 ADCS regA, regA, rscratch, ROR #8
  98                 //OverFlow
  99                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
 100                 BICVC rstatus, rstatus, #MASK_OVERFLOW
 101                 //Carry
 102                 UPDATE_C
 103                 //clear lower part
 104                 ANDS regA, regA, #0xFF000000
 105                 //Update flag
 106                 UPDATE_ZN
 107 1113:
 108 .endm
 109 /* TO TEST */
 110 .macro ADC16
 111                 TST rstatus, #MASK_DECIMAL
 112                 BEQ 1111f
 113                 S9xGetWord
 114
 115                 //rscratch = W3W2W1W0........
 116                 LDR     rscratch4, = 0x0F0F0000
 117                 // rscratch2 = xxW2xxW0xxxxxx
 118                 // rscratch3 = xxW3xxW1xxxxxx
 119                 AND     rscratch2, rscratch4, rscratch
 120                 AND     rscratch3, rscratch4, rscratch, LSR #4
 121                 // rscratch2 = xxW3xxW1xxW2xxW0
 122                 ORR     rscratch2, rscratch3, rscratch2, LSR #16
 123                 // rscratch3 = xxA2xxA0xxxxxx
 124                 // rscratch4 = xxA3xxA1xxxxxx
 125                 // rscratch2 = xxA3xxA1xxA2xxA0
 126                 AND     rscratch3, rscratch4, regA
 127                 AND     rscratch4, rscratch4, regA, LSR #4
 128                 ORR     rscratch3, rscratch4, rscratch3, LSR #16
 129                 ADD     rscratch2, rscratch3, rscratch2
 130                 LDR     rscratch4, = 0x0F0F0000
 131                 // rscratch2 = A + W
 132                 TST     rstatus, #MASK_CARRY
 133                 ADDNE   rscratch2, rscratch2, #0x1
 134                 // rscratch2 = A + W + C
 135                 //A0
 136                 AND     rscratch3, rscratch2, #0x0000001F
 137                 CMP     rscratch3, #0x00000009
 138                 ADDHI   rscratch2, rscratch2, #0x00010000
 139                 SUBHI   rscratch2, rscratch2, #0x0000000A
 140                 //A1
 141                 AND     rscratch3, rscratch2, #0x001F0000
 142                 CMP     rscratch3, #0x00090000
 143                 ADDHI   rscratch2, rscratch2, #0x00000100
 144                 SUBHI   rscratch2, rscratch2, #0x000A0000
 145                 //A2
 146                 AND     rscratch3, rscratch2, #0x00001F00
 147                 CMP     rscratch3, #0x00000900
 148                 SUBHI   rscratch2, rscratch2, #0x00000A00
 149                 ADDHI   rscratch2, rscratch2, #0x01000000
 150                 //A3
 151                 AND     rscratch3, rscratch2, #0x1F000000
 152                 CMP     rscratch3, #0x09000000
 153                 SUBHI   rscratch2, rscratch2, #0x0A000000
 154                 //SetCarry
 155                 ORRHI   rstatus, rstatus, #MASK_CARRY
 156                 //ClearCarry
 157                 BICLS   rstatus, rstatus, #MASK_CARRY
 158                 //rscratch2 = xxR3xxR1xxR2xxR0
 159                 //Pack result
 160                 //rscratch3 = xxR3xxR1xxxxxxxx
 161                 AND     rscratch3, rscratch4, rscratch2
 162                 //rscratch2 = xxR2xxR0xxxxxxxx
 163                 AND     rscratch2, rscratch4, rscratch2,LSL #16
 164                 //rscratch2 = R3R2R1R0xxxxxxxx
 165                 ORR     rscratch2, rscratch2,rscratch3,LSL #4
 166 //only last bit
 167                 AND     rscratch,rscratch,#0x80000000
 168                 // (register.AL ^ Work8)
 169                 EORS    rscratch3, regA, rscratch
 170                 BICNE   rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
 171                 BNE     1112f
 172                 // (Work8 ^ Ans8)
 173                 EORS    rscratch3, rscratch2, rscratch
 174                 TSTNE   rscratch3,#0x80000000
 175                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
 176                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
 177 1112:
 178                 MOVS    regA, rscratch2
 179                 UPDATE_ZN
 180                 B       1113f
 181 1111:
 182                 S9xGetWordLow
 183                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
 184                 SUBCS rscratch, rscratch, #0x10000
 185                 ADCS regA, regA,rscratch, ROR #16
 186                 //OverFlow
 187                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
 188                 BICVC rstatus, rstatus, #MASK_OVERFLOW
 189                 MOV regA, regA, LSR #16
 190                 //Carry
 191                 UPDATE_C
 192                 //clear lower parts
 193                 MOVS regA, regA, LSL #16
 194                 //Update flag
 195                 UPDATE_ZN
 196 1113:
 197 .endm
 198
 199
 200 .macro          AND16
 201                 S9xGetWord
 202                 ANDS            regA, regA, rscratch
 203                 UPDATE_ZN
 204 .endm
 205 .macro          AND8
 206                 S9xGetByte
 207                 ANDS            regA, regA, rscratch
 208                 UPDATE_ZN
 209 .endm
 210 .macro          A_ASL8
 211                 // 7    instr
 212                 MOVS    regA, regA, LSL #1
 213                 UPDATE_C
 214                 UPDATE_ZN
 215                 ADD1CYCLE
 216 .endm
 217 .macro          A_ASL16
 218                 // 7    instr
 219                 MOVS    regA, regA, LSL #1
 220                 UPDATE_C
 221                 UPDATE_ZN
 222                 ADD1CYCLE
 223 .endm
 224 .macro          ASL16
 225                 S9xGetWordRegNS rscratch2             //        do not destroy Opadress in rscratch
 226                 MOVS            rscratch2, rscratch2, LSL #1
 227                 UPDATE_C
 228                 UPDATE_ZN
 229                 S9xSetWord      rscratch2
 230                 ADD1CYCLE
 231 .endm
 232 .macro          ASL8
 233                 S9xGetByteRegNS rscratch2             //        do not destroy Opadress in rscratch
 234                 MOVS            rscratch2, rscratch2, LSL #1
 235                 UPDATE_C
 236                 UPDATE_ZN
 237                 S9xSetByte      rscratch2
 238                 ADD1CYCLE
 239 .endm
 240 .macro          BIT8
 241                 S9xGetByte
 242                 MOVS    rscratch2, rscratch, LSL #1
 243                 // Trick in ASM : shift one more bit    : ARM C = Snes N
 244                 //                                        ARM N = Snes V
 245                 // If Carry Set, then Set Neg in SNES
 246                 BICCC   rstatus, rstatus, #MASK_NEG     // 0 : AND mask 11111011111 : set C to zero
 247                 ORRCS   rstatus, rstatus, #MASK_NEG     // 1 : OR  mask 00000100000 : set C to one
 248                 // If Neg Set, then Set Overflow in SNES
 249                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  // 0 : AND mask 11111011111   : set N to zero
 250                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             // 1 : OR  mask 00000100000        : set N to one
 251
 252                 // Now do a real AND    with A register
 253                 // Set Zero Flag, bit test
 254                 ANDS    rscratch2, regA, rscratch
 255                 BICNE   rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 256                 ORREQ   rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 257 .endm
 258
 259 .macro          BIT16
 260                 S9xGetWord
 261                 MOVS    rscratch2, rscratch, LSL #1
 262                 // Trick in ASM : shift one more bit    : ARM C = Snes N
 263                 //                                        ARM N = Snes V
 264                 // If Carry Set, then Set Neg in SNES
 265                 BICCC   rstatus, rstatus, #MASK_NEG     // 0 : AND mask 11111011111 : set N to zero
 266                 ORRCS   rstatus, rstatus, #MASK_NEG     // 1 : OR  mask 00000100000 : set N to one
 267                 // If Neg Set, then Set Overflow in SNES
 268                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  // 0 : AND mask 11111011111   : set V to zero
 269                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             // 1 : OR  mask 00000100000        : set V to one
 270                 // Now do a real AND    with A register
 271                 // Set Zero Flag, bit test
 272                 ANDS    rscratch2, regA, rscratch
 273                 // Bit set  ->Z=0->xxxNE Clear flag
 274                 BICNE   rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 275                 // Bit clear->Z=1->xxxEQ Set flag
 276                 ORREQ   rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 277 .endm
 278 .macro          CMP8
 279                 S9xGetByte
 280                 SUBS    rscratch2,regA,rscratch
 281                 BICCC   rstatus, rstatus, #MASK_CARRY
 282                 ORRCS   rstatus, rstatus, #MASK_CARRY
 283                 UPDATE_ZN
 284
 285 .endm
 286 .macro          CMP16
 287                 S9xGetWord
 288                 SUBS    rscratch2,regA,rscratch
 289                 BICCC   rstatus, rstatus, #MASK_CARRY
 290                 ORRCS   rstatus, rstatus, #MASK_CARRY
 291                 UPDATE_ZN
 292
 293 .endm
 294 .macro          CMX16
 295                 S9xGetWord
 296                 SUBS    rscratch2,regX,rscratch
 297                 BICCC   rstatus, rstatus, #MASK_CARRY
 298                 ORRCS   rstatus, rstatus, #MASK_CARRY
 299                 UPDATE_ZN
 300 .endm
 301 .macro          CMX8
 302                 S9xGetByte
 303                 SUBS    rscratch2,regX,rscratch
 304                 BICCC   rstatus, rstatus, #MASK_CARRY
 305                 ORRCS   rstatus, rstatus, #MASK_CARRY
 306                 UPDATE_ZN
 307 .endm
 308 .macro          CMY16
 309                 S9xGetWord
 310                 SUBS    rscratch2,regY,rscratch
 311                 BICCC   rstatus, rstatus, #MASK_CARRY
 312                 ORRCS   rstatus, rstatus, #MASK_CARRY
 313                 UPDATE_ZN
 314 .endm
 315 .macro          CMY8
 316                 S9xGetByte
 317                 SUBS    rscratch2,regY,rscratch
 318                 BICCC   rstatus, rstatus, #MASK_CARRY
 319                 ORRCS   rstatus, rstatus, #MASK_CARRY
 320                 UPDATE_ZN
 321 .endm
 322 .macro          A_DEC8
 323                 MOV             rscratch,#0
 324                 SUBS            regA, regA, #0x01000000
 325                 STR             rscratch,[regCPUvar,#WaitAddress_ofs]
 326                 UPDATE_ZN
 327                 ADD1CYCLE
 328 .endm
 329 .macro          A_DEC16
 330                 MOV             rscratch,#0
 331                 SUBS            regA, regA, #0x00010000
 332                 STR             rscratch,[regCPUvar,#WaitAddress_ofs]
 333                 UPDATE_ZN
 334                 ADD1CYCLE
 335 .endm
 336 .macro          DEC16
 337                 S9xGetWordRegNS rscratch2              // do not        destroy Opadress in rscratch
 338                 MOV             rscratch3,#0
 339                 SUBS            rscratch2, rscratch2, #0x00010000
 340                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 341                 UPDATE_ZN
 342                 S9xSetWord      rscratch2
 343                 ADD1CYCLE
 344 .endm
 345 .macro          DEC8
 346                 S9xGetByteRegNS rscratch2              // do not        destroy Opadress in rscratch
 347                 MOV             rscratch3,#0
 348                 SUBS            rscratch2, rscratch2, #0x01000000
 349                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 350                 UPDATE_ZN
 351                 S9xSetByte      rscratch2
 352                 ADD1CYCLE
 353 .endm
 354 .macro          EOR16
 355                 S9xGetWord
 356                 EORS            regA, regA, rscratch
 357                 UPDATE_ZN
 358 .endm
 359 .macro          EOR8
 360                 S9xGetByte
 361                 EORS            regA, regA, rscratch
 362                 UPDATE_ZN
 363 .endm
 364 .macro          A_INC8
 365                 MOV             rscratch3,#0
 366                 ADDS            regA, regA, #0x01000000
 367                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 368                 UPDATE_ZN
 369                 ADD1CYCLE
 370 .endm
 371 .macro          A_INC16
 372                 MOV             rscratch3,#0
 373                 ADDS            regA, regA, #0x00010000
 374                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 375                 UPDATE_ZN
 376                 ADD1CYCLE
 377 .endm
 378 .macro          INC16
 379                 S9xGetWordRegNS rscratch2
 380                 MOV             rscratch3,#0
 381                 ADDS            rscratch2, rscratch2, #0x00010000
 382                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 383                 UPDATE_ZN
 384                 S9xSetWord      rscratch2
 385                 ADD1CYCLE
 386 .endm
 387 .macro          INC8
 388                 S9xGetByteRegNS rscratch2
 389                 MOV             rscratch3,#0
 390                 ADDS            rscratch2, rscratch2, #0x01000000
 391                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 392                 UPDATE_ZN
 393                 S9xSetByte      rscratch2
 394                 ADD1CYCLE
 395 .endm
 396 .macro          LDA16
 397                 S9xGetWordRegStatus regA
 398                 UPDATE_ZN
 399 .endm
 400 .macro          LDA8
 401                 S9xGetByteRegStatus regA
 402                 UPDATE_ZN
 403 .endm
 404 .macro          LDX16
 405                 S9xGetWordRegStatus regX
 406                 UPDATE_ZN
 407 .endm
 408 .macro          LDX8
 409                 S9xGetByteRegStatus regX
 410                 UPDATE_ZN
 411 .endm
 412 .macro          LDY16
 413                 S9xGetWordRegStatus regY
 414                 UPDATE_ZN
 415 .endm
 416 .macro          LDY8
 417                 S9xGetByteRegStatus regY
 418                 UPDATE_ZN
 419 .endm
 420 .macro          A_LSR16
 421                 BIC     rstatus, rstatus, #MASK_NEG      // 0 : AND mask        11111011111 : set N to zero
 422                 MOVS    regA, regA, LSR #17              // hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
 423                 // Update Zero
 424                 BICNE   rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 425                 MOV     regA, regA, LSL #16                     // -> 0lllllll 00000000 00000000        00000000
 426                 ORREQ   rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 427                 // Note : the two MOV are included between instruction, to optimize
 428                 // the pipeline.
 429                 UPDATE_C
 430                 ADD1CYCLE
 431 .endm
 432 .macro          A_LSR8
 433                 BIC     rstatus, rstatus, #MASK_NEG      // 0 : AND mask        11111011111 : set N to zero
 434                 MOVS    regA, regA, LSR #25              // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
 435                 // Update Zero
 436                 BICNE   rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 437                 MOV     regA, regA, LSL #24                     // -> 00000000 00000000 00000000        0lllllll
 438                 ORREQ   rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 439                 // Note : the two MOV are included between instruction, to optimize
 440                 // the pipeline.
 441                 UPDATE_C
 442                 ADD1CYCLE
 443 .endm
 444 .macro          LSR16
 445                 S9xGetWordRegNS rscratch2
 446                 // N set to zero by >> 1 LSR
 447                 BIC             rstatus, rstatus, #MASK_NEG      // 0 : AND mask        11111011111 : set N to zero
 448                 MOVS            rscratch2, rscratch2, LSR #17              // llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
 449                 // Update Carry
 450                 BICCC           rstatus, rstatus, #MASK_CARRY  //       0 : AND mask 11111011111 : set C to zero
 451                 ORRCS           rstatus, rstatus, #MASK_CARRY      //   1 : OR  mask 00000100000 : set C to one
 452                 // Update Zero
 453                 BICNE           rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 454                 ORREQ           rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 455                 S9xSetWordLow   rscratch2
 456                 ADD1CYCLE
 457 .endm
 458 .macro          LSR8
 459                 S9xGetByteRegNS rscratch2
 460                 // N set to zero by >> 1 LSR
 461                 BIC             rstatus, rstatus, #MASK_NEG      // 0 : AND mask        11111011111 : set N to zero
 462                 MOVS            rscratch2, rscratch2, LSR #25              // llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
 463                 // Update Carry
 464                 BICCC           rstatus, rstatus, #MASK_CARRY  //       0 : AND mask 11111011111 : set C to zero
 465                 ORRCS           rstatus, rstatus, #MASK_CARRY      //   1 : OR  mask 00000100000 : set C to one
 466                 // Update Zero
 467                 BICNE           rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 468                 ORREQ           rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 469                 S9xSetByteLow   rscratch2
 470                 ADD1CYCLE
 471 .endm
 472 .macro          ORA8
 473                 S9xGetByte
 474                 ORRS            regA, regA, rscratch
 475                 UPDATE_ZN
 476 .endm
 477 .macro          ORA16
 478                 S9xGetWord
 479                 ORRS            regA, regA, rscratch
 480                 UPDATE_ZN
 481 .endm
 482 .macro          A_ROL16
 483                 TST             rstatus, #MASK_CARRY
 484                 ORRNE           regA, regA, #0x00008000
 485                 MOVS            regA, regA, LSL #1
 486                 UPDATE_ZN
 487                 UPDATE_C
 488                 ADD1CYCLE
 489 .endm
 490 .macro          A_ROL8
 491                 TST             rstatus, #MASK_CARRY
 492                 ORRNE           regA, regA, #0x00800000
 493                 MOVS            regA, regA, LSL #1
 494                 UPDATE_ZN
 495                 UPDATE_C
 496                 ADD1CYCLE
 497 .endm
 498 .macro          ROL16
 499                 S9xGetWordRegNS rscratch2
 500                 TST             rstatus, #MASK_CARRY
 501                 ORRNE           rscratch2, rscratch2, #0x00008000
 502                 MOVS            rscratch2, rscratch2, LSL #1
 503                 UPDATE_ZN
 504                 UPDATE_C
 505                 S9xSetWord      rscratch2
 506                 ADD1CYCLE
 507 .endm
 508 .macro          ROL8
 509                 S9xGetByteRegNS rscratch2
 510                 TST             rstatus, #MASK_CARRY
 511                 ORRNE           rscratch2, rscratch2, #0x00800000
 512                 MOVS            rscratch2, rscratch2, LSL #1
 513                 UPDATE_ZN
 514                 UPDATE_C
 515                 S9xSetByte      rscratch2
 516                 ADD1CYCLE
 517 .endm
 518 .macro          A_ROR16
 519                 MOV                     regA,regA, LSR #16
 520                 TST                     rstatus, #MASK_CARRY
 521                 ORRNE                   regA, regA, #0x00010000
 522                 ORRNE                   rstatus,rstatus,#MASK_NEG
 523                 BICEQ                   rstatus,rstatus,#MASK_NEG
 524                 MOVS                    regA,regA,LSR #1
 525                 UPDATE_C
 526                 UPDATE_Z
 527                 MOV                     regA,regA, LSL #16
 528                 ADD1CYCLE
 529 .endm
 530 .macro          A_ROR8
 531                 MOV                     regA,regA, LSR #24
 532                 TST                     rstatus, #MASK_CARRY
 533                 ORRNE                   regA, regA, #0x00000100
 534                 ORRNE                   rstatus,rstatus,#MASK_NEG
 535                 BICEQ                   rstatus,rstatus,#MASK_NEG
 536                 MOVS                    regA,regA,LSR #1
 537                 UPDATE_C
 538                 UPDATE_Z
 539                 MOV                     regA,regA, LSL #24
 540                 ADD1CYCLE
 541 .endm
 542 .macro          ROR16
 543                 S9xGetWordLowRegNS      rscratch2
 544                 TST                     rstatus, #MASK_CARRY
 545                 ORRNE                   rscratch2, rscratch2, #0x00010000
 546                 ORRNE                   rstatus,rstatus,#MASK_NEG
 547                 BICEQ                   rstatus,rstatus,#MASK_NEG
 548                 MOVS                    rscratch2,rscratch2,LSR #1
 549                 UPDATE_C
 550                 UPDATE_Z
 551                 S9xSetWordLow   rscratch2
 552                 ADD1CYCLE
 553
 554 .endm
 555 .macro          ROR8
 556                 S9xGetByteLowRegNS      rscratch2
 557                 TST                     rstatus, #MASK_CARRY
 558                 ORRNE                   rscratch2, rscratch2, #0x00000100
 559                 ORRNE                   rstatus,rstatus,#MASK_NEG
 560                 BICEQ                   rstatus,rstatus,#MASK_NEG
 561                 MOVS                    rscratch2,rscratch2,LSR #1
 562                 UPDATE_C
 563                 UPDATE_Z
 564                 S9xSetByteLow   rscratch2
 565                 ADD1CYCLE
 566 .endm
 567
 568 .macro SBC16
 569                 TST rstatus, #MASK_DECIMAL
 570                 BEQ 1111f
 571                 //TODO
 572                 S9xGetWord
 573
 574                 STMFD   R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9}
 575                 MOV     rscratch9,#0x000F0000
 576                 //rscratch2=xxxxxxW1xxxxxxxxxx + !Carry
 577                 //rscratch3=xxxxxxW2xxxxxxxxxx
 578                 //rscratch4=xxxxxxW3xxxxxxxxxx
 579                 //rscratch5=xxxxxxW4xxxxxxxxxx
 580                 AND     rscratch2, rscratch9, rscratch
 581                 TST     rstatus, #MASK_CARRY
 582                 ADDEQ   rscratch2, rscratch2, #0x00010000  //W1=W1+!Carry
 583                 AND     rscratch3, rscratch9, rscratch, LSR #4
 584                 AND     rscratch4, rscratch9, rscratch, LSR #8
 585                 AND     rscratch5, rscratch9, rscratch, LSR #12
 586
 587                 //rscratch6=xxxxxxA1xxxxxxxxxx
 588                 //rscratch7=xxxxxxA2xxxxxxxxxx
 589                 //rscratch8=xxxxxxA3xxxxxxxxxx
 590                 //rscratch9=xxxxxxA4xxxxxxxxxx
 591                 AND     rscratch6, rscratch9, regA
 592                 AND     rscratch7, rscratch9, regA, LSR #4
 593                 AND     rscratch8, rscratch9, regA, LSR #8
 594                 AND     rscratch9, rscratch9, regA, LSR #12
 595
 596                 SUB     rscratch2,rscratch6,rscratch2           //R1=A1-W1-!Carry
 597                 CMP     rscratch2, #0x00090000  // if R1 > 9
 598                 ADDHI   rscratch2, rscratch2, #0x000A0000 // then R1 += 10
 599                 ADDHI   rscratch3, rscratch3, #0x00010000  // then (W2++)
 600                 SUB     rscratch3,rscratch7,rscratch3           //R2=A2-W2
 601                 CMP     rscratch3, #0x00090000  // if R2 > 9
 602                 ADDHI   rscratch3, rscratch3, #0x000A0000 // then R2 += 10
 603                 ADDHI   rscratch4, rscratch4, #0x00010000  // then (W3++)
 604                 SUB     rscratch4,rscratch8,rscratch4           //R3=A3-W3
 605                 CMP     rscratch4, #0x00090000  // if R3 > 9
 606                 ADDHI   rscratch4, rscratch4, #0x000A0000 // then R3 += 10
 607                 ADDHI   rscratch5, rscratch5, #0x00010000  // then (W3++)
 608                 SUB     rscratch5,rscratch9,rscratch5           //R4=A4-W4
 609                 CMP     rscratch5, #0x00090000  // if R4 > 9
 610                 ADDHI   rscratch5, rscratch5, #0x000A0000 // then R4 += 10
 611                 BICHI   rstatus, rstatus, #MASK_CARRY   // then ClearCarry
 612                 ORRLS   rstatus, rstatus, #MASK_CARRY   // else SetCarry
 613
 614                 MOV     rscratch9,#0x000F0000
 615                 AND     rscratch2,rscratch9,rscratch2
 616                 AND     rscratch3,rscratch9,rscratch3
 617                 AND     rscratch4,rscratch9,rscratch4
 618                 AND     rscratch5,rscratch9,rscratch5
 619                 ORR     rscratch2,rscratch2,rscratch3,LSL #4
 620                 ORR     rscratch2,rscratch2,rscratch4,LSL #8
 621                 ORR     rscratch2,rscratch2,rscratch5,LSL #12
 622
 623                 LDMFD   R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9}
 624                 //only last bit
 625                 AND     regA,regA,#0x80000000
 626                 // (register.A.W ^ Work8)
 627                 EORS    rscratch3, regA, rscratch
 628                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
 629                 BEQ     1112f
 630                 // (register.A.W ^ Ans8)
 631                 EORS    rscratch3, regA, rscratch2
 632                 // & 0x80
 633                 TSTNE   rscratch3,#0x80000000
 634                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
 635                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
 636 1112:
 637                 MOVS    regA, rscratch2
 638                 UPDATE_ZN
 639                 B 1113f
 640 1111:
 641                 S9xGetWordLow
 642                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
 643                 SBCS regA, regA, rscratch, LSL #16
 644                 //OverFlow
 645                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
 646                 BICVC rstatus, rstatus, #MASK_OVERFLOW
 647                 MOV regA, regA, LSR #16
 648                 //Carry
 649                 UPDATE_C
 650                 MOVS regA, regA, LSL #16
 651                 //Update flag
 652                 UPDATE_ZN
 653 1113:
 654 .endm
 655
 656 .macro SBC8
 657                 TST rstatus, #MASK_DECIMAL
 658                 BEQ 1111f
 659                 S9xGetByte
 660                 STMFD   R13!,{rscratch}
 661                 MOV     rscratch4,#0x0F000000
 662                 //rscratch2=xxW1xxxxxxxxxxxx
 663                 AND     rscratch2, rscratch, rscratch4
 664                 //rscratch=xxW2xxxxxxxxxxxx
 665                 AND     rscratch, rscratch4, rscratch, LSR #4
 666                 //rscratch3=xxA2xxxxxxxxxxxx
 667                 AND     rscratch3, rscratch4, regA, LSR #4
 668                 //rscratch4=xxA1xxxxxxxxxxxx
 669                 AND     rscratch4,regA,rscratch4
 670                 //R1=A1-W1-!CARRY
 671                 TST     rstatus, #MASK_CARRY
 672                 ADDEQ   rscratch2, rscratch2, #0x01000000
 673                 SUB     rscratch2,rscratch4,rscratch2
 674                 // if R1 > 9
 675                 CMP     rscratch2, #0x09000000
 676                 // then R1 += 10
 677                 ADDHI   rscratch2, rscratch2, #0x0A000000
 678                 // then A2-- (W2++)
 679                 ADDHI   rscratch, rscratch, #0x01000000
 680                 // R2=A2-W2
 681                 SUB     rscratch3, rscratch3, rscratch
 682                 // if R2 > 9
 683                 CMP     rscratch3, #0x09000000
 684                 // then R2 -= 10//
 685                 ADDHI   rscratch3, rscratch3, #0x0A000000
 686                 // then SetCarry()
 687                 BICHI   rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
 688                 // else ClearCarry()
 689                 ORRLS   rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
 690                 // gather rscratch3 and rscratch2 into ans8
 691                 AND     rscratch3,rscratch3,#0x0F000000
 692                 AND     rscratch2,rscratch2,#0x0F000000
 693                 // rscratch3 : 0R2000000
 694                 // rscratch2 : 0R1000000
 695                 // -> 0xR2R1000000
 696                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
 697                 LDMFD   R13!,{rscratch}
 698                 //only last bit
 699                 AND     regA,regA,#0x80000000
 700                 // (register.AL ^ Work8)
 701                 EORS    rscratch3, regA, rscratch
 702                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
 703                 BEQ     1112f
 704                 // (register.AL ^ Ans8)
 705                 EORS    rscratch3, regA, rscratch2
 706                 // & 0x80
 707                 TSTNE   rscratch3,#0x80000000
 708                 BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
 709                 ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
 710 1112:
 711                 MOVS regA, rscratch2
 712                 UPDATE_ZN
 713                 B 1113f
 714 1111:
 715                 S9xGetByteLow
 716                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
 717                 SBCS regA, regA, rscratch, LSL #24
 718                 //OverFlow
 719                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
 720                 BICVC rstatus, rstatus, #MASK_OVERFLOW
 721                 //Carry
 722                 UPDATE_C
 723                 //Update flag
 724                 ANDS regA, regA, #0xFF000000
 725                 UPDATE_ZN
 726 1113:
 727 .endm
 728
 729 .macro          STA16
 730                 S9xSetWord      regA
 731 .endm
 732 .macro          STA8
 733                 S9xSetByte      regA
 734 .endm
 735 .macro          STX16
 736                 S9xSetWord      regX
 737 .endm
 738 .macro          STX8
 739                 S9xSetByte      regX
 740 .endm
 741 .macro          STY16
 742                 S9xSetWord      regY
 743 .endm
 744 .macro          STY8
 745                 S9xSetByte      regY
 746 .endm
 747 .macro          STZ16
 748                 S9xSetWordZero
 749 .endm
 750 .macro          STZ8
 751                 S9xSetByteZero
 752 .endm
 753 .macro          TSB16
 754                 S9xGetWordRegNS rscratch2
 755                 TST             regA, rscratch2
 756                 BICNE           rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 757                 ORREQ           rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 758                 ORR             rscratch2, regA, rscratch2
 759                 S9xSetWord      rscratch2
 760                 ADD1CYCLE
 761 .endm
 762 .macro          TSB8
 763                 S9xGetByteRegNS rscratch2
 764                 TST             regA, rscratch2
 765                 BICNE           rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 766                 ORREQ           rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 767                 ORR             rscratch2, regA, rscratch2
 768                 S9xSetByte      rscratch2
 769                 ADD1CYCLE
 770 .endm
 771 .macro          TRB16
 772                 S9xGetWordRegNS rscratch2
 773                 TST             regA, rscratch2
 774                 BICNE           rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 775                 ORREQ           rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 776                 MVN             rscratch3, regA
 777                 AND             rscratch2, rscratch3, rscratch2
 778                 S9xSetWord      rscratch2
 779                 ADD1CYCLE
 780 .endm
 781 .macro          TRB8
 782                 S9xGetByteRegNS rscratch2
 783                 TST             regA, rscratch2
 784                 BICNE           rstatus, rstatus, #MASK_ZERO     // 0 : AND mask        11111011111 : set Z to zero
 785                 ORREQ           rstatus, rstatus, #MASK_ZERO     // 1 : OR  mask        00000100000  : set Z to one
 786                 MVN             rscratch3, regA
 787                 AND             rscratch2, rscratch3, rscratch2
 788                 S9xSetByte      rscratch2
 789                 ADD1CYCLE
 790 .endm
 791 /**************************************************************************/
 792
 793
 794 /**************************************************************************/
 795
 796 .macro          Op09M0          /*ORA*/
 797                 LDRB            rscratch2, [rpc,#1]
 798                 LDRB            rscratch, [rpc], #2
 799                 ORR             rscratch2,rscratch,rscratch2,LSL #8
 800                 ORRS            regA,regA,rscratch2,LSL #16
 801                 UPDATE_ZN
 802                 ADD2MEM
 803 .endm
 804 .macro          Op09M1          /*ORA*/
 805                 LDRB            rscratch, [rpc], #1
 806                 ORRS            regA,regA,rscratch,LSL #24
 807                 UPDATE_ZN
 808                 ADD1MEM
 809 .endm
 810 /***********************************************************************/
 811 .macro          Op90    /*BCC*/
 812                 asmRelative
 813                 BranchCheck0
 814                 TST             rstatus, #MASK_CARRY
 815                 BNE             1111f
 816                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
 817                 ADD1CYCLE
 818                 CPUShutdown
 819 1111:
 820 .endm
 821 .macro          OpB0    /*BCS*/
 822                 asmRelative
 823                 BranchCheck0
 824                 TST             rstatus, #MASK_CARRY
 825                 BEQ             1111f
 826                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
 827                 ADD1CYCLE
 828                 CPUShutdown
 829 1111:
 830 .endm
 831 .macro          OpF0    /*BEQ*/
 832                 asmRelative
 833                 BranchCheck2
 834                 TST             rstatus, #MASK_ZERO
 835                 BEQ             1111f
 836                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
 837                 ADD1CYCLE
 838                 CPUShutdown
 839 1111:
 840 .endm
 841 .macro          OpD0    /*BNE*/
 842                 asmRelative
 843                 BranchCheck1
 844                 TST             rstatus, #MASK_ZERO
 845                 BNE             1111f
 846                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
 847                 ADD1CYCLE
 848                 CPUShutdown
 849 1111:
 850 .endm
 851 .macro          Op30    /*BMI*/
 852                 asmRelative
 853                 BranchCheck0
 854                 TST             rstatus, #MASK_NEG
 855                 BEQ             1111f
 856                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
 857                 ADD1CYCLE
 858                 CPUShutdown
 859 1111:
 860 .endm
 861 .macro          Op10   /*BPL*/
 862                 asmRelative
 863                 BranchCheck1
 864                 TST             rstatus, #MASK_NEG // neg, z!=0, NE
 865                 BNE             1111f
 866                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
 867                 ADD1CYCLE
 868                 CPUShutdown
 869 1111:
 870 .endm
 871 .macro          Op50   /*BVC*/
 872                 asmRelative
 873                 BranchCheck0
 874                 TST             rstatus, #MASK_OVERFLOW // neg, z!=0, NE
 875                 BNE             1111f
 876                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
 877                 ADD1CYCLE
 878                 CPUShutdown
 879 1111:
 880 .endm
 881 .macro          Op70   /*BVS*/
 882                 asmRelative
 883                 BranchCheck0
 884                 TST             rstatus, #MASK_OVERFLOW // neg, z!=0, NE
 885                 BEQ             1111f
 886                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
 887                 ADD1CYCLE
 888                 CPUShutdown
 889 1111:
 890 .endm
 891 .macro          Op80   /*BRA*/
 892                 asmRelative
 893                 ADD             rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
 894                 ADD1CYCLE
 895                 CPUShutdown
 896 1111:
 897 .endm
 898 /*******************************************************************************************/
 899 /************************************************************/
 900 /* SetFlag Instructions ********************************************************************** */
 901 .macro          Op38 /*SEC*/
 902                 ORR             rstatus, rstatus, #MASK_CARRY      //   1 : OR  mask 00000100000 : set C to one
 903                 ADD1CYCLE
 904 .endm
 905 .macro          OpF8 /*SED*/
 906                 SetDecimal
 907                 ADD1CYCLE
 908 .endm
 909 .macro          Op78 /*SEI*/
 910                 SetIRQ
 911                 ADD1CYCLE
 912 .endm
 913
 914
 915 /****************************************************************************************/
 916 /* ClearFlag Instructions ******************************************************************** */
 917 .macro          Op18  /*CLC*/
 918                 BIC             rstatus, rstatus, #MASK_CARRY
 919                 ADD1CYCLE
 920 .endm
 921 .macro          OpD8 /*CLD*/
 922                 ClearDecimal
 923                 ADD1CYCLE
 924 .endm
 925 .macro          Op58  /*CLI*/
 926                 ClearIRQ
 927                 ADD1CYCLE
 928                 //CHECK_FOR_IRQ
 929 .endm
 930 .macro          OpB8 /*CLV*/
 931                 BIC             rstatus, rstatus, #MASK_OVERFLOW
 932                 ADD1CYCLE
 933 .endm
 934
 935 /******************************************************************************************/
 936 /* DEX/DEY *********************************************************************************** */
 937
 938 .macro          OpCAX1  /*DEX*/
 939                 MOV             rscratch3,#0
 940                 SUBS            regX, regX, #0x01000000
 941                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 942                 UPDATE_ZN
 943                 ADD1CYCLE
 944 .endm
 945 .macro          OpCAX0  /*DEX*/
 946                 MOV             rscratch3,#0
 947                 SUBS            regX, regX, #0x00010000
 948                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 949                 UPDATE_ZN
 950                 ADD1CYCLE
 951 .endm
 952 .macro          Op88X1 /*DEY*/
 953                 MOV             rscratch3,#0
 954                 SUBS            regY, regY, #0x01000000
 955                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 956                 UPDATE_ZN
 957                 ADD1CYCLE
 958 .endm
 959 .macro          Op88X0 /*DEY*/
 960                 MOV             rscratch3,#0
 961                 SUBS            regY, regY, #0x00010000
 962                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 963                 UPDATE_ZN
 964                 ADD1CYCLE
 965 .endm
 966
 967 /******************************************************************************************/
 968 /* INX/INY *********************************************************************************** */
 969 .macro          OpE8X1
 970                 MOV             rscratch3,#0
 971                 ADDS            regX, regX, #0x01000000
 972                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 973                 UPDATE_ZN
 974                 ADD1CYCLE
 975 .endm
 976 .macro          OpE8X0
 977                 MOV             rscratch3,#0
 978                 ADDS            regX, regX, #0x00010000
 979                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 980                 UPDATE_ZN
 981                 ADD1CYCLE
 982 .endm
 983 .macro          OpC8X1
 984                 MOV             rscratch3,#0
 985                 ADDS            regY, regY, #0x01000000
 986                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 987                 UPDATE_ZN
 988                 ADD1CYCLE
 989 .endm
 990 .macro          OpC8X0
 991                 MOV             rscratch3,#0
 992                 ADDS            regY, regY, #0x00010000
 993                 STR             rscratch3,[regCPUvar,#WaitAddress_ofs]
 994                 UPDATE_ZN
 995                 ADD1CYCLE
 996 .endm
 997
 998 /**********************************************************************************************/
 999
1000 /* NOP *************************************************************************************** */
1001 .macro          OpEA
1002                 ADD1CYCLE
1003 .endm
1004
1005 /**************************************************************************/
1006 /* PUSH Instructions **************************************************** */
1007 .macro          OpF4
1008                 Absolute
1009                 PushWrLow
1010 .endm
1011 .macro          OpD4
1012                 DirectIndirect
1013                 PushWrLow
1014 .endm
1015 .macro          Op62
1016                 asmRelativeLong
1017                 PushWrLow
1018 .endm
1019 .macro          Op48M0
1020                 PushW           regA
1021                 ADD1CYCLE
1022 .endm
1023 .macro          Op48M1
1024                 PushB           regA
1025                 ADD1CYCLE
1026 .endm
1027 .macro          Op8B
1028                 AND             rscratch2, regDBank, #0xFF
1029                 PushBLow        rscratch2
1030                 ADD1CYCLE
1031 .endm
1032 .macro          Op0B
1033                 PushW           regD
1034                 ADD1CYCLE
1035 .endm
1036 .macro          Op4B
1037                 PushBlow        regPBank
1038                 ADD1CYCLE
1039 .endm
1040 .macro          Op08
1041                 PushB           rstatus
1042                 ADD1CYCLE
1043 .endm
1044 .macro          OpDAX1
1045                 PushB           regX
1046                 ADD1CYCLE
1047 .endm
1048 .macro          OpDAX0
1049                 PushW           regX
1050                 ADD1CYCLE
1051 .endm
1052 .macro          Op5AX1
1053                 PushB           regY
1054                 ADD1CYCLE
1055 .endm
1056 .macro          Op5AX0
1057                 PushW           regY
1058                 ADD1CYCLE
1059 .endm
1060 /**************************************************************************/
1061 /* PULL Instructions **************************************************** */
1062 .macro          Op68M1
1063                 PullBS          regA
1064                 UPDATE_ZN
1065                 ADD2CYCLE
1066 .endm
1067 .macro          Op68M0
1068                 PullWS          regA
1069                 UPDATE_ZN
1070                 ADD2CYCLE
1071 .endm
1072 .macro          OpAB
1073                 BIC             regDBank,regDBank, #0xFF
1074                 PullBrS
1075                 ORR             regDBank,regDBank,rscratch, LSR #24
1076                 UPDATE_ZN
1077                 ADD2CYCLE
1078 .endm
1079 .macro          Op2B
1080                 BIC             regD,regD, #0xFF000000
1081                 BIC             regD,regD, #0x00FF0000
1082                 PullWrS
1083                 ORR             regD,rscratch,regD
1084                 UPDATE_ZN
1085                 ADD2CYCLE
1086 .endm
1087 .macro          Op28X1M1        /*PLP*/
1088                 //INDEX set, MEMORY set
1089                 BIC             rstatus,rstatus,#0xFF000000
1090                 PullBr
1091                 ORR             rstatus,rscratch,rstatus
1092                 TST             rstatus, #MASK_INDEX
1093                 //INDEX clear & was set : 8->16
1094                 MOVEQ           regX,regX,LSR #8
1095                 MOVEQ           regY,regY,LSR #8
1096                 TST             rstatus, #MASK_MEM
1097                 //MEMORY cleared & was set : 8->16
1098                 LDREQB          rscratch,[regCPUvar,#RAH_ofs]
1099                 MOVEQ           regA,regA,LSR #8
1100                 ORREQ           regA,regA,rscratch, LSL #24
1101                 S9xFixCycles
1102                 ADD2CYCLE
1103 .endm
1104 .macro          Op28X0M1        /*PLP*/
1105                 //INDEX cleared, MEMORY set
1106                 BIC             rstatus,rstatus,#0xFF000000
1107                 PullBr
1108                 ORR             rstatus,rscratch,rstatus
1109                 TST             rstatus, #MASK_INDEX
1110                 //INDEX set & was cleared : 16->8
1111                 MOVNE           regX,regX,LSL #8
1112                 MOVNE           regY,regY,LSL #8
1113                 TST             rstatus, #MASK_MEM
1114                 //MEMORY cleared & was set : 8->16
1115                 LDREQB          rscratch,[regCPUvar,#RAH_ofs]
1116                 MOVEQ           regA,regA,LSR #8
1117                 ORREQ           regA,regA,rscratch, LSL #24
1118                 S9xFixCycles
1119                 ADD2CYCLE
1120 .endm
1121 .macro          Op28X1M0        /*PLP*/
1122                 //INDEX set, MEMORY set
1123                 BIC             rstatus,rstatus,#0xFF000000
1124                 PullBr
1125                 ORR             rstatus,rscratch,rstatus
1126                 TST             rstatus, #MASK_INDEX
1127                 //INDEX clear & was set : 8->16
1128                 MOVEQ           regX,regX,LSR #8
1129                 MOVEQ           regY,regY,LSR #8
1130                 TST             rstatus, #MASK_MEM
1131                 //MEMORY set & was cleared : 16->8
1132                 MOVNE           rscratch,regA,LSR #24
1133                 MOVNE           regA,regA,LSL #8
1134                 STRNEB          rscratch,[regCPUvar,#RAH_ofs]
1135                 S9xFixCycles
1136                 ADD2CYCLE
1137 .endm
1138 .macro          Op28X0M0        /*PLP*/
1139                 //INDEX set, MEMORY set
1140                 BIC             rstatus,rstatus,#0xFF000000
1141                 PullBr
1142                 ORR             rstatus,rscratch,rstatus
1143                 TST             rstatus, #MASK_INDEX
1144                 //INDEX set & was cleared : 16->8
1145                 MOVNE           regX,regX,LSL #8
1146                 MOVNE           regY,regY,LSL #8
1147                 TST             rstatus, #MASK_MEM
1148                 //MEMORY set & was cleared : 16->8
1149                 MOVNE           rscratch,regA,LSR #24
1150                 MOVNE           regA,regA,LSL #8
1151                 STRNEB          rscratch,[regCPUvar,#RAH_ofs]
1152                 S9xFixCycles
1153                 ADD2CYCLE
1154 .endm
1155 .macro          OpFAX1
1156                 PullBS          regX
1157                 UPDATE_ZN
1158                 ADD2CYCLE
1159 .endm
1160 .macro          OpFAX0
1161                 PullWS          regX
1162                 UPDATE_ZN
1163                 ADD2CYCLE
1164 .endm
1165 .macro          Op7AX1
1166                 PullBS          regY
1167                 UPDATE_ZN
1168                 ADD2CYCLE
1169 .endm
1170 .macro          Op7AX0
1171                 PullWS          regY
1172                 UPDATE_ZN
1173                 ADD2CYCLE
1174 .endm
1175
1176 /**********************************************************************************************/
1177 /* Transfer Instructions ********************************************************************* */
1178 .macro          OpAAX1M1 /*TAX8*/
1179                 MOVS            regX, regA
1180                 UPDATE_ZN
1181                 ADD1CYCLE
1182 .endm
1183 .macro          OpAAX0M1 /*TAX16*/
1184                 LDRB            regX, [regCPUvar,#RAH_ofs]
1185                 MOV             regX, regX,LSL #24
1186                 ORRS            regX, regX,regA, LSR #8
1187                 UPDATE_ZN
1188                 ADD1CYCLE
1189 .endm
1190 .macro          OpAAX1M0 /*TAX8*/
1191                 MOVS            regX, regA, LSL #8
1192                 UPDATE_ZN
1193                 ADD1CYCLE
1194 .endm
1195 .macro          OpAAX0M0 /*TAX16*/
1196                 MOVS            regX, regA
1197                 UPDATE_ZN
1198                 ADD1CYCLE
1199 .endm
1200 .macro          OpA8X1M1 /*TAY8*/
1201                 MOVS            regY, regA
1202                 UPDATE_ZN
1203                 ADD1CYCLE
1204 .endm
1205 .macro          OpA8X0M1 /*TAY16*/
1206                 LDRB            regY, [regCPUvar,#RAH_ofs]
1207                 MOV             regY, regY,LSL #24
1208                 ORRS            regY, regY,regA, LSR #8
1209                 UPDATE_ZN
1210                 ADD1CYCLE
1211 .endm
1212 .macro          OpA8X1M0 /*TAY8*/
1213                 MOVS            regY, regA, LSL #8
1214                 UPDATE_ZN
1215                 ADD1CYCLE
1216 .endm
1217 .macro          OpA8X0M0 /*TAY16*/
1218                 MOVS            regY, regA
1219                 UPDATE_ZN
1220                 ADD1CYCLE
1221 .endm
1222 .macro          Op5BM1
1223                 LDRB            rscratch, [regCPUvar,#RAH_ofs]
1224                 MOV             regD,regD,LSL #16
1225                 MOV             rscratch,rscratch,LSL #24
1226                 ORRS            rscratch,rscratch,regA, LSR #8
1227                 UPDATE_ZN
1228                 ORR             regD,rscratch,regD,LSR #16
1229                 ADD1CYCLE
1230 .endm
1231 .macro          Op5BM0
1232                 MOV             regD,regD,LSL #16
1233                 MOVS            regA,regA
1234                 UPDATE_ZN
1235                 ORR             regD,regA,regD,LSR #16
1236                 ADD1CYCLE
1237 .endm
1238 .macro          Op1BM1
1239                 TST             rstatus, #MASK_EMUL
1240                 MOVNE           regS, regA, LSR #24
1241                 ORRNE           regS, regS, #0x100
1242                 LDREQB          regS, [regCPUvar,#RAH_ofs]
1243                 ORREQ           regS, regS, regA
1244                 MOVEQ           regS, regS, ROR #24
1245                 ADD1CYCLE
1246 .endm
1247 .macro          Op1BM0
1248                 MOV             regS, regA, LSR #16
1249                 ADD1CYCLE
1250 .endm
1251 .macro          Op7BM1
1252                 MOVS            regA, regD, ASR #16
1253                 UPDATE_ZN
1254                 MOV             rscratch,regA,LSR #8
1255                 MOV             regA,regA, LSL #24
1256                 STRB            rscratch, [regCPUvar,#RAH_ofs]
1257                 ADD1CYCLE
1258 .endm
1259 .macro          Op7BM0
1260                 MOVS            regA, regD, ASR #16
1261                 UPDATE_ZN
1262                 MOV             regA,regA, LSL #16
1263                 ADD1CYCLE
1264 .endm
1265 .macro          Op3BM1
1266                 MOV             rscratch,regS, LSR #8
1267                 MOVS            regA, regS, LSL #16
1268                 STRB            rscratch, [regCPUvar,#RAH_ofs]
1269                 UPDATE_ZN
1270                 MOV             regA,regA, LSL #8
1271                 ADD1CYCLE
1272 .endm
1273 .macro          Op3BM0
1274                 MOVS            regA, regS, LSL #16
1275                 UPDATE_ZN
1276                 ADD1CYCLE
1277 .endm
1278 .macro          OpBAX1
1279                 MOVS            regX, regS, LSL #24
1280                 UPDATE_ZN
1281                 ADD1CYCLE
1282 .endm
1283 .macro          OpBAX0
1284                 MOVS            regX, regS, LSL #16
1285                 UPDATE_ZN
1286                 ADD1CYCLE
1287 .endm
1288 .macro          Op8AM1X1
1289                 MOVS            regA, regX
1290                 UPDATE_ZN
1291                 ADD1CYCLE
1292 .endm
1293 .macro          Op8AM1X0
1294                 MOVS            regA, regX, LSL #8
1295                 UPDATE_ZN
1296                 ADD1CYCLE
1297 .endm
1298 .macro          Op8AM0X1
1299                 MOVS            regA, regX, LSR #8
1300                 UPDATE_ZN
1301                 ADD1CYCLE
1302 .endm
1303 .macro          Op8AM0X0
1304                 MOVS            regA, regX
1305                 UPDATE_ZN
1306                 ADD1CYCLE
1307 .endm
1308 .macro          Op9AX1
1309                 MOV             regS, regX, LSR #24
1310                 TST             rstatus, #MASK_EMUL
1311                 ORRNE           regS, regS, #0x100
1312                 ADD1CYCLE
1313 .endm
1314 .macro          Op9AX0
1315                 MOV             regS, regX, LSR #16
1316                 ADD1CYCLE
1317 .endm
1318 .macro          Op9BX1
1319                 MOVS            regY, regX
1320                 UPDATE_ZN
1321                 ADD1CYCLE
1322 .endm
1323 .macro          Op9BX0
1324                 MOVS            regY, regX
1325                 UPDATE_ZN
1326                 ADD1CYCLE
1327 .endm
1328 .macro          Op98M1X1
1329                 MOVS            regA, regY
1330                 UPDATE_ZN
1331                 ADD1CYCLE
1332 .endm
1333 .macro          Op98M1X0
1334                 MOVS            regA, regY, LSL #8
1335                 UPDATE_ZN
1336                 ADD1CYCLE
1337 .endm
1338 .macro          Op98M0X1
1339                 MOVS            regA, regY, LSR #8
1340                 UPDATE_ZN
1341                 ADD1CYCLE
1342 .endm
1343 .macro          Op98M0X0
1344                 MOVS            regA, regY
1345                 UPDATE_ZN
1346                 ADD1CYCLE
1347 .endm
1348 .macro          OpBBX1
1349                 MOVS            regX, regY
1350                 UPDATE_ZN
1351                 ADD1CYCLE
1352 .endm
1353 .macro          OpBBX0
1354                 MOVS            regX, regY
1355                 UPDATE_ZN
1356                 ADD1CYCLE
1357 .endm
1358
1359 /**********************************************************************************************/
1360 /* XCE *************************************************************************************** */
1361
1362 .macro          OpFB
1363     TST         rstatus,#MASK_CARRY
1364     BEQ         1111f
1365     //CARRY is set
1366     TST         rstatus,#MASK_EMUL
1367     BNE         1112f
1368     //EMUL is cleared
1369     BIC         rstatus,rstatus,#(MASK_CARRY)
1370     TST         rstatus,#MASK_INDEX
1371     //X & Y were 16bits before
1372     MOVEQ       regX,regX,LSL #8
1373     MOVEQ       regY,regY,LSL #8
1374     TST         rstatus,#MASK_MEM
1375     //A was 16bits before
1376     //save AH
1377     MOVEQ       rscratch,regA,LSR #24
1378     STREQB      rscratch,[regCPUvar,#RAH_ofs]
1379     MOVEQ       regA,regA,LSL #8
1380     ORR         rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
1381     AND         regS,regS,#0xFF
1382     ORR         regS,regS,#0x100
1383     B           1113f
1384 1112:
1385     //EMUL is set
1386     TST         rstatus,#MASK_INDEX
1387     //X & Y were 16bits before
1388     MOVEQ       regX,regX,LSL #8
1389     MOVEQ       regY,regY,LSL #8
1390     TST         rstatus,#MASK_MEM
1391     //A was 16bits before
1392     //save AH
1393     MOVEQ       rscratch,regA,LSR #24
1394     STREQB      rscratch,[regCPUvar,#RAH_ofs]
1395     MOVEQ       regA,regA,LSL #8
1396     ORR         rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
1397     AND         regS,regS,#0xFF
1398     ORR         regS,regS,#0x100
1399     B           1113f
1400 1111:
1401     //CARRY is cleared
1402     TST         rstatus,#MASK_EMUL
1403     BEQ         1115f
1404     //EMUL was set : X,Y & A were 8bits
1405     //Now have to check MEMORY & INDEX for potential conversions to 16bits
1406     TST         rstatus,#MASK_INDEX
1407     // X & Y are now 16bits
1408     MOVEQ       regX,regX,LSR #8
1409     MOVEQ       regY,regY,LSR #8
1410     TST         rstatus,#MASK_MEM
1411     // A is now 16bits
1412     MOVEQ       regA,regA,LSR #8
1413     //restore AH
1414     LDREQB      rscratch,[regCPUvar,#RAH_ofs]
1415     ORREQ       regA,regA,rscratch,LSL #24
1416 1115:
1417     BIC         rstatus,rstatus,#(MASK_EMUL)
1418     ORR         rstatus,rstatus,#(MASK_CARRY)
1419 1113:
1420     ADD1CYCLE
1421     S9xFixCycles
1422 .endm
1423
1424 /*******************************************************************************/
1425 /* BRK *************************************************************************/
1426 .macro          Op00            /*BRK*/
1427                 MOV             rscratch,#1
1428                 STRB            rscratch,[regCPUvar,#BRKTriggered_ofs]
1429
1430                 TST             rstatus, #MASK_EMUL
1431                 // EQ is flag to zero (!CheckEmu)
1432                 BNE             2001f//elseOp00
1433                 PushBLow        regPBank
1434                 SUB             rscratch, rpc, regpcbase
1435                 ADD             rscratch2, rscratch, #1
1436                 PushWLow        rscratch2
1437                 // PackStatus
1438                 PushB           rstatus
1439                 ClearDecimal
1440                 SetIRQ
1441                 BIC             regPBank, regPBank, #0xFF
1442                 MOV             rscratch, #0xE6
1443                 ORR             rscratch, rscratch, #0xFF00
1444                 S9xGetWordLow
1445                 S9xSetPCBase
1446                 ADD2CYCLE
1447                 B               2002f//endOp00
1448 2001://elseOp00
1449                 SUB             rscratch2, rpc, regpcbase
1450                 PushWLow        rscratch2
1451                 // PackStatus
1452                 PushB           rstatus
1453                 ClearDecimal
1454                 SetIRQ
1455                 BIC             regPBank,regPBank, #0xFF
1456                 MOV             rscratch, #0xFE
1457                 ORR             rscratch, rscratch, #0xFF00
1458                 S9xGetWordLow
1459                 S9xSetPCBase
1460                 ADD1CYCLE
1461 2002://endOp00
1462 .endm
1463
1464
1465 /**********************************************************************************************/
1466 /* BRL ************************************************************************************** */
1467 .macro          Op82    /*BRL*/
1468                 asmRelativeLong
1469                 ORR             rscratch, rscratch, regPBank, LSL #16
1470                 S9xSetPCBase
1471 .endm
1472 /**********************************************************************************************/
1473 /* IRQ *************************************************************************************** */
1474 //void S9xOpcode_IRQ (void)
1475 /*
1476     if (!CheckEmulation())
1477     {
1478         PushB (Registers.PB);
1479         PushW (CPU.PC - CPU.PCBase);
1480         S9xPackStatus ();
1481         PushB (Registers.PL);
1482         ClearDecimal ();
1483         SetIRQ ();
1484
1485         Registers.PB = 0;
1486         ICPU.ShiftedPB = 0;
1487         if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40))
1488             S9xSetPCBase (Memory.FillRAM [0x220e] |
1489                           (Memory.FillRAM [0x220f] << 8));
1490         else
1491             S9xSetPCBase (S9xGetWord (0xFFEE));
1492         CPU.Cycles += TWO_CYCLES;
1493     }
1494     else
1495     {
1496         PushW (CPU.PC - CPU.PCBase);
1497         S9xPackStatus ();
1498         PushB (Registers.PL);
1499         ClearDecimal ();
1500         SetIRQ ();
1501
1502         Registers.PB = 0;
1503         ICPU.ShiftedPB = 0;
1504         if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40))
1505             S9xSetPCBase (Memory.FillRAM [0x220e] |
1506                           (Memory.FillRAM [0x220f] << 8));
1507         else
1508             S9xSetPCBase (S9xGetWord (0xFFFE));
1509         CPU.Cycles += ONE_CYCLE;
1510     }
1511  }
1512 */
1513
1514 /**********************************************************************************************/
1515 /* NMI *************************************************************************************** */
1516 //void S9xOpcode_NMI (void)
1517 /*{
1518     if (!CheckEmulation())
1519     {
1520         PushB (Registers.PB);
1521         PushW (CPU.PC - CPU.PCBase);
1522         S9xPackStatus ();
1523         PushB (Registers.PL);
1524         ClearDecimal ();
1525         SetIRQ ();
1526
1527         Registers.PB = 0;
1528         ICPU.ShiftedPB = 0;
1529         if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20))
1530             S9xSetPCBase (Memory.FillRAM [0x220c] |
1531                           (Memory.FillRAM [0x220d] << 8));
1532         else
1533             S9xSetPCBase (S9xGetWord (0xFFEA));
1534         CPU.Cycles += TWO_CYCLES;
1535     }
1536     else
1537     {
1538         PushW (CPU.PC - CPU.PCBase);
1539         S9xPackStatus ();
1540         PushB (Registers.PL);
1541         ClearDecimal ();
1542         SetIRQ ();
1543
1544         Registers.PB = 0;
1545         ICPU.ShiftedPB = 0;
1546         if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20))
1547             S9xSetPCBase (Memory.FillRAM [0x220c] |
1548                           (Memory.FillRAM [0x220d] << 8));
1549         else
1550             S9xSetPCBase (S9xGetWord (0xFFFA));
1551         CPU.Cycles += ONE_CYCLE;
1552     }
1553 }
1554 */
1555
1556 /**********************************************************************************************/
1557 /* COP *************************************************************************************** */
1558 .macro          Op02            /*COP*/
1559                 TST             rstatus, #MASK_EMUL
1560                 // EQ is flag to zero (!CheckEmu)
1561                 BNE             2021f//elseOp02
1562                 PushBLow        regPBank
1563                 SUB             rscratch, rpc, regpcbase
1564                 ADD             rscratch2, rscratch, #1
1565                 PushWLow        rscratch2
1566                 // PackStatus
1567                 PushB           rstatus
1568                 ClearDecimal
1569                 SetIRQ
1570                 BIC             regPBank, regPBank,#0xFF
1571                 MOV             rscratch, #0xE4
1572                 ORR             rscratch, rscratch, #0xFF00
1573                 S9xGetWordLow
1574                 S9xSetPCBase
1575                 ADD2CYCLE
1576                 B 2022f//endOp02
1577 2021://elseOp02
1578                 SUB             rscratch2, rpc, regpcbase
1579                 PushWLow        rscratch2
1580                 // PackStatus
1581                 PushB           rstatus
1582                 ClearDecimal
1583                 SetIRQ
1584                 BIC             regPBank,regPBank, #0xFF
1585                 MOV             rscratch, #0xF4
1586                 ORR             rscratch, rscratch, #0xFF00
1587                 S9xGetWordLow
1588                 S9xSetPCBase
1589                 ADD1CYCLE
1590 2022://endOp02
1591 .endm
1592
1593 /**********************************************************************************************/
1594 /* JML *************************************************************************************** */
1595 .macro          OpDC
1596                 AbsoluteIndirectLong
1597                 BIC             regPBank,regPBank,#0xFF
1598                 ORR             regPBank,regPBank, rscratch, LSR #16
1599                 S9xSetPCBase
1600                 ADD2CYCLE
1601 .endm
1602 .macro          Op5C
1603                 AbsoluteLong
1604                 BIC             regPBank,regPBank,#0xFF
1605                 ORR             regPBank,regPBank, rscratch, LSR #16
1606                 S9xSetPCBase
1607 .endm
1608
1609 /**********************************************************************************************/
1610 /* JMP *************************************************************************************** */
1611 .macro          Op4C
1612                 Absolute
1613                 BIC             rscratch, rscratch, #0xFF0000
1614                 ORR             rscratch, rscratch, regPBank, LSL #16
1615                 S9xSetPCBase
1616                 CPUShutdown
1617 .endm
1618 .macro          Op6C
1619                 AbsoluteIndirect
1620                 BIC             rscratch, rscratch, #0xFF0000
1621                 ORR             rscratch, rscratch, regPBank, LSL #16
1622                 S9xSetPCBase
1623 .endm
1624 .macro          Op7C
1625                 ADD             rscratch, rscratch, regPBank, LSL #16
1626                 S9xSetPCBase
1627                 ADD1CYCLE
1628 .endm
1629
1630 /**********************************************************************************************/
1631 /* JSL/RTL *********************************************************************************** */
1632 .macro          Op22
1633                 PushBlow        regPBank
1634                 SUB             rscratch, rpc, regpcbase
1635                 //SUB           rscratch2, rscratch2, #1
1636                 ADD             rscratch2, rscratch, #2
1637                 PushWlow        rscratch2
1638                 AbsoluteLong
1639                 BIC             regPBank,regPBank,#0xFF
1640                 ORR             regPBank, regPBank, rscratch, LSR #16
1641                 S9xSetPCBase
1642 .endm
1643 .macro          Op6B
1644                 PullWLow        rpc
1645                 BIC             regPBank,regPBank,#0xFF
1646                 PullBrLow
1647                 ORR             regPBank, regPBank, rscratch
1648                 ADD             rscratch, rpc, #1
1649                 BIC             rscratch, rscratch,#0xFF0000
1650                 ORR             rscratch, rscratch, regPBank, LSL #16
1651                 S9xSetPCBase
1652                 ADD2CYCLE
1653 .endm
1654 /**********************************************************************************************/
1655 /* JSR/RTS *********************************************************************************** */
1656 .macro          Op20
1657                 SUB             rscratch, rpc, regpcbase
1658                 //SUB           rscratch2, rscratch2, #1
1659                 ADD             rscratch2, rscratch, #1
1660                 PushWlow        rscratch2
1661                 Absolute
1662                 BIC             rscratch, rscratch, #0xFF0000
1663                 ORR             rscratch, rscratch, regPBank, LSL #16
1664                 S9xSetPCBase
1665                 ADD1CYCLE
1666 .endm
1667 .macro          OpFCX0
1668                 SUB             rscratch, rpc, regpcbase
1669                 //SUB           rscratch2, rscratch2, #1
1670                 ADD             rscratch2, rscratch, #1
1671                 PushWlow        rscratch2
1672                 AbsoluteIndexedIndirectX0
1673                 ORR             rscratch, rscratch, regPBank, LSL #16
1674                 S9xSetPCBase
1675                 ADD1CYCLE
1676 .endm
1677 .macro          OpFCX1
1678                 SUB             rscratch, rpc, regpcbase
1679                 //SUB           rscratch2, rscratch2, #1
1680                 ADD             rscratch2, rscratch, #1
1681                 PushWlow        rscratch2
1682                 AbsoluteIndexedIndirectX1
1683                 ORR             rscratch, rscratch, regPBank, LSL #16
1684                 S9xSetPCBase
1685                 ADD1CYCLE
1686 .endm
1687 .macro          Op60
1688                 PullWLow        rpc
1689                 ADD             rscratch, rpc, #1
1690                 BIC             rscratch, rscratch,#0x10000
1691                 ORR             rscratch, rscratch, regPBank, LSL #16
1692                 S9xSetPCBase
1693                 ADD3CYCLE
1694 .endm
1695
1696 /**********************************************************************************************/
1697 /* MVN/MVP *********************************************************************************** */
1698 .macro          Op54X1M1
1699                 //Save RegStatus = regDBank >> 24
1700                 MOV             rscratch, regDBank, LSR #16
1701                 LDRB            regDBank    , [rpc], #1
1702                 LDRB            rscratch2    , [rpc], #1
1703                 //Restore RegStatus = regDBank >> 24
1704                 ORR             regDBank, regDBank, rscratch, LSL #16
1705                 MOV             rscratch    , regX, LSR #24
1706                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1707                 S9xGetByteLow
1708                 MOV             rscratch2, rscratch
1709                 MOV             rscratch   , regY, LSR #24
1710                 ORR             rscratch   , rscratch, regDBank, LSL #16
1711                 S9xSetByteLow   rscratch2
1712                 //load 16bits A
1713                 LDRB            rscratch,[regCPUvar,#RAH_ofs]
1714                 MOV             regA,regA,LSR #8
1715                 ORR             regA,regA,rscratch, LSL #24
1716                 ADD             regX, regX, #0x01000000
1717                 SUB             regA, regA, #0x00010000
1718                 ADD             regY, regY, #0x01000000
1719                 CMP             regA, #0xFFFF0000
1720                 SUBNE           rpc, rpc, #3
1721                 //update AH
1722                 MOV             rscratch, regA, LSR #24
1723                 MOV             regA,regA,LSL #8
1724                 STRB            rscratch,[regCPUvar,#RAH_ofs]
1725                 ADD2CYCLE2MEM
1726 .endm
1727 .macro          Op54X1M0
1728                 //Save RegStatus = regDBank >> 24
1729                 MOV             rscratch, regDBank, LSR #16
1730                 LDRB            regDBank    , [rpc], #1
1731                 LDRB            rscratch2    , [rpc], #1
1732                 //Restore RegStatus = regDBank >> 24
1733                 ORR             regDBank, regDBank, rscratch, LSL #16
1734                 MOV             rscratch    , regX, LSR #24
1735                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1736                 S9xGetByteLow
1737                 MOV             rscratch2, rscratch
1738                 MOV             rscratch   , regY, LSR #24
1739                 ORR             rscratch   , rscratch, regDBank, LSL #16
1740                 S9xSetByteLow   rscratch2
1741                 ADD             regX, regX, #0x01000000
1742                 SUB             regA, regA, #0x00010000
1743                 ADD             regY, regY, #0x01000000
1744                 CMP             regA, #0xFFFF0000
1745                 SUBNE           rpc, rpc, #3
1746                 ADD2CYCLE2MEM
1747 .endm
1748 .macro          Op54X0M1
1749                 //Save RegStatus = regDBank >> 24
1750                 MOV             rscratch, regDBank, LSR #16
1751                 LDRB            regDBank    , [rpc], #1
1752                 LDRB            rscratch2    , [rpc], #1
1753                 //Restore RegStatus = regDBank >> 24
1754                 ORR             regDBank, regDBank, rscratch, LSL #16
1755                 MOV             rscratch    , regX, LSR #16
1756                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1757                 S9xGetByteLow
1758                 MOV             rscratch2, rscratch
1759                 MOV             rscratch   , regY, LSR #16
1760                 ORR             rscratch   , rscratch, regDBank, LSL #16
1761                 S9xSetByteLow   rscratch2
1762                 //load 16bits A
1763                 LDRB            rscratch,[regCPUvar,#RAH_ofs]
1764                 MOV             regA,regA,LSR #8
1765                 ORR             regA,regA,rscratch, LSL #24
1766                 ADD             regX, regX, #0x00010000
1767                 SUB             regA, regA, #0x00010000
1768                 ADD             regY, regY, #0x00010000
1769                 CMP             regA, #0xFFFF0000
1770                 SUBNE           rpc, rpc, #3
1771                 //update AH
1772                 MOV             rscratch, regA, LSR #24
1773                 MOV             regA,regA,LSL #8
1774                 STRB            rscratch,[regCPUvar,#RAH_ofs]
1775                 ADD2CYCLE2MEM
1776 .endm
1777 .macro          Op54X0M0
1778                 //Save RegStatus = regDBank >> 24
1779                 MOV             rscratch, regDBank, LSR #16
1780                 LDRB            regDBank    , [rpc], #1
1781                 LDRB            rscratch2    , [rpc], #1
1782                 //Restore RegStatus = regDBank >> 24
1783                 ORR             regDBank, regDBank, rscratch, LSL #16
1784                 MOV             rscratch    , regX, LSR #16
1785                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1786                 S9xGetByteLow
1787                 MOV             rscratch2, rscratch
1788                 MOV             rscratch   , regY, LSR #16
1789                 ORR             rscratch   , rscratch, regDBank, LSL #16
1790                 S9xSetByteLow   rscratch2
1791                 ADD             regX, regX, #0x00010000
1792                 SUB             regA, regA, #0x00010000
1793                 ADD             regY, regY, #0x00010000
1794                 CMP             regA, #0xFFFF0000
1795                 SUBNE           rpc, rpc, #3
1796                 ADD2CYCLE2MEM
1797 .endm
1798
1799 .macro          Op44X1M1
1800                 //Save RegStatus = regDBank >> 24
1801                 MOV             rscratch, regDBank, LSR #16
1802                 LDRB            regDBank    , [rpc], #1
1803                 LDRB            rscratch2    , [rpc], #1
1804                 //Restore RegStatus = regDBank >> 24
1805                 ORR             regDBank, regDBank, rscratch, LSL #16
1806                 MOV             rscratch    , regX, LSR #24
1807                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1808                 S9xGetByteLow
1809                 MOV             rscratch2, rscratch
1810                 MOV             rscratch   , regY, LSR #24
1811                 ORR             rscratch   , rscratch, regDBank, LSL #16
1812                 S9xSetByteLow   rscratch2
1813                 //load 16bits A
1814                 LDRB            rscratch,[regCPUvar,#RAH_ofs]
1815                 MOV             regA,regA,LSR #8
1816                 ORR             regA,regA,rscratch, LSL #24
1817                 SUB             regX, regX, #0x01000000
1818                 SUB             regA, regA, #0x00010000
1819                 SUB             regY, regY, #0x01000000
1820                 CMP             regA, #0xFFFF0000
1821                 SUBNE           rpc, rpc, #3
1822                 //update AH
1823                 MOV             rscratch, regA, LSR #24
1824                 MOV             regA,regA,LSL #8
1825                 STRB            rscratch,[regCPUvar,#RAH_ofs]
1826                 ADD2CYCLE2MEM
1827 .endm
1828 .macro          Op44X1M0
1829                 //Save RegStatus = regDBank >> 24
1830                 MOV             rscratch, regDBank, LSR #16
1831                 LDRB            regDBank    , [rpc], #1
1832                 LDRB            rscratch2    , [rpc], #1
1833                 //Restore RegStatus = regDBank >> 24
1834                 ORR             regDBank, regDBank, rscratch, LSL #16
1835                 MOV             rscratch    , regX, LSR #24
1836                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1837                 S9xGetByteLow
1838                 MOV             rscratch2, rscratch
1839                 MOV             rscratch   , regY, LSR #24
1840                 ORR             rscratch   , rscratch, regDBank, LSL #16
1841                 S9xSetByteLow   rscratch2
1842                 SUB             regX, regX, #0x01000000
1843                 SUB             regA, regA, #0x00010000
1844                 SUB             regY, regY, #0x01000000
1845                 CMP             regA, #0xFFFF0000
1846                 SUBNE           rpc, rpc, #3
1847                 ADD2CYCLE2MEM
1848 .endm
1849 .macro          Op44X0M1
1850                 //Save RegStatus = regDBank >> 24
1851                 MOV             rscratch, regDBank, LSR #16
1852                 LDRB            regDBank    , [rpc], #1
1853                 LDRB            rscratch2    , [rpc], #1
1854                 //Restore RegStatus = regDBank >> 24
1855                 ORR             regDBank, regDBank, rscratch, LSL #16
1856                 MOV             rscratch    , regX, LSR #16
1857                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1858                 S9xGetByteLow
1859                 MOV             rscratch2, rscratch
1860                 MOV             rscratch   , regY, LSR #16
1861                 ORR             rscratch   , rscratch, regDBank, LSL #16
1862                 S9xSetByteLow   rscratch2
1863                 //load 16bits A
1864                 LDRB            rscratch,[regCPUvar,#RAH_ofs]
1865                 MOV             regA,regA,LSR #8
1866                 ORR             regA,regA,rscratch, LSL #24
1867                 SUB             regX, regX, #0x00010000
1868                 SUB             regA, regA, #0x00010000
1869                 SUB             regY, regY, #0x00010000
1870                 CMP             regA, #0xFFFF0000
1871                 SUBNE           rpc, rpc, #3
1872                 //update AH
1873                 MOV             rscratch, regA, LSR #24
1874                 MOV             regA,regA,LSL #8
1875                 STRB            rscratch,[regCPUvar,#RAH_ofs]
1876                 ADD2CYCLE2MEM
1877 .endm
1878 .macro          Op44X0M0
1879                 //Save RegStatus = regDBank >> 24
1880                 MOV             rscratch, regDBank, LSR #16
1881                 LDRB            regDBank    , [rpc], #1
1882                 LDRB            rscratch2    , [rpc], #1
1883                 //Restore RegStatus = regDBank >> 24
1884                 ORR             regDBank, regDBank, rscratch, LSL #16
1885                 MOV             rscratch    , regX, LSR #16
1886                 ORR             rscratch    , rscratch, rscratch2, LSL #16
1887                 S9xGetByteLow
1888                 MOV             rscratch2, rscratch
1889                 MOV             rscratch   , regY, LSR #16
1890                 ORR             rscratch   , rscratch, regDBank, LSL #16
1891                 S9xSetByteLow   rscratch2
1892                 SUB             regX, regX, #0x00010000
1893                 SUB             regA, regA, #0x00010000
1894                 SUB             regY, regY, #0x00010000
1895                 CMP             regA, #0xFFFF0000
1896                 SUBNE           rpc, rpc, #3
1897                 ADD2CYCLE2MEM
1898 .endm
1899
1900 /**********************************************************************************************/
1901 /* REP/SEP *********************************************************************************** */
1902 .macro          OpC2
1903                 // status&=~(*rpc++);
1904                 // so possible changes are :
1905                 // INDEX = 1 -> 0  : X,Y 8bits -> 16bits
1906                 // MEM = 1 -> 0 : A 8bits -> 16bits
1907                 //SAVE OLD status for MASK_INDEX & MASK_MEM comparison
1908                 MOV             rscratch3, rstatus
1909                 LDRB            rscratch, [rpc], #1
1910                 MVN             rscratch, rscratch
1911                 AND             rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
1912                 TST             rstatus,#MASK_EMUL
1913                 BEQ             1111f
1914                 //emulation mode on : no changes since it was on before opcode
1915                 //just be sure to reset MEM & INDEX accordingly
1916                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
1917                 B               1112f
1918 1111:
1919                 //NOT in Emulation mode, check INDEX & MEMORY bits
1920                 //Now check INDEX
1921                 TST             rscratch3,#MASK_INDEX
1922                 BEQ             1113f
1923                 // X & Y were 8bit before
1924                 TST             rstatus,#MASK_INDEX
1925                 BNE             1113f
1926                 // X & Y are now 16bits
1927                 MOV             regX,regX,LSR #8
1928                 MOV             regY,regY,LSR #8
1929 1113:           //X & Y still in 16bits
1930                 //Now check MEMORY
1931                 TST             rscratch3,#MASK_MEM
1932                 BEQ             1112f
1933                 // A was 8bit before
1934                 TST             rstatus,#MASK_MEM
1935                 BNE             1112f
1936                 // A is now 16bits
1937                 MOV             regA,regA,LSR #8
1938                 //restore AH
1939                 LDREQB          rscratch,[regCPUvar,#RAH_ofs]
1940                 ORREQ           regA,regA,rscratch,LSL #24
1941 1112:
1942                 S9xFixCycles
1943                 ADD1CYCLE1MEM
1944 .endm
1945 .macro          OpE2
1946                 // status|=*rpc++;
1947                 // so possible changes are :
1948                 // INDEX = 0 -> 1  : X,Y 16bits -> 8bits
1949                 // MEM = 0 -> 1 : A 16bits -> 8bits
1950                 //SAVE OLD status for MASK_INDEX & MASK_MEM comparison
1951                 MOV             rscratch3, rstatus
1952                 LDRB            rscratch, [rpc], #1
1953                 ORR             rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
1954                 TST             rstatus,#MASK_EMUL
1955                 BEQ             10111f
1956                 //emulation mode on : no changes sinc eit was on before opcode
1957                 //just be sure to have mem & index set accordingly
1958                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
1959                 B               10112f
1960 10111:
1961                 //NOT in Emulation mode, check INDEX & MEMORY bits
1962                 //Now check INDEX
1963                 TST             rscratch3,#MASK_INDEX
1964                 BNE             10113f
1965                 // X & Y were 16bit before
1966                 TST             rstatus,#MASK_INDEX
1967                 BEQ             10113f
1968                 // X & Y are now 8bits
1969                 MOV             regX,regX,LSL #8
1970                 MOV             regY,regY,LSL #8
1971 10113:          //X & Y still in 16bits
1972                 //Now check MEMORY
1973                 TST             rscratch3,#MASK_MEM
1974                 BNE             10112f
1975                 // A was 16bit before
1976                 TST             rstatus,#MASK_MEM
1977                 BEQ             10112f
1978                 // A is now 8bits
1979                 // save AH
1980                 MOV             rscratch,regA,LSR #24
1981                 MOV             regA,regA,LSL #8
1982                 STRB            rscratch,[regCPUvar,#RAH_ofs]
1983 10112:
1984                 S9xFixCycles
1985                 ADD1CYCLE1MEM
1986 .endm
1987
1988 /**********************************************************************************************/
1989 /* XBA *************************************************************************************** */
1990 .macro          OpEBM1
1991                 //A is 8bits
1992                 ADD             rscratch,regCPUvar,#RAH_ofs
1993                 MOV             regA,regA, LSR #24
1994                 SWPB            regA,regA,[rscratch]
1995                 MOVS            regA,regA, LSL #24
1996                 UPDATE_ZN
1997                 ADD2CYCLE
1998 .endm
1999 .macro          OpEBM0
2000                 //A is 16bits
2001                 MOV             rscratch, regA, ROR #24 // ll0000hh
2002                 ORR             rscratch, rscratch, regA, LSR #8// ll0000hh + 00hhll00 -> llhhllhh
2003                 MOV             regA, rscratch, LSL #16// llhhllhh -> llhh0000
2004                 MOVS            rscratch,rscratch,LSL #24 //to set Z & N flags with AL
2005                 UPDATE_ZN
2006                 ADD2CYCLE
2007 .endm
2008
2009
2010 /**********************************************************************************************/
2011 /* RTI *************************************************************************************** */
2012 .macro          Op40X1M1
2013                 //INDEX set, MEMORY set
2014                 BIC             rstatus,rstatus,#0xFF000000
2015                 PullBr
2016                 ORR             rstatus,rscratch,rstatus
2017                 PullWlow        rpc
2018                 TST             rstatus, #MASK_EMUL
2019                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2020                 BNE             2401f
2021                 PullBrLow
2022                 BIC             regPBank,regPBank,#0xFF
2023                 ORR             regPBank,regPBank,rscratch
2024 2401:
2025                 ADD             rscratch, rpc, regPBank, LSL #16
2026                 S9xSetPCBase
2027                 TST             rstatus, #MASK_INDEX
2028                 //INDEX cleared & was set : 8->16
2029                 MOVEQ           regX,regX,LSR #8
2030                 MOVEQ           regY,regY,LSR #8
2031                 TST             rstatus, #MASK_MEM
2032                 //MEMORY cleared & was set : 8->16
2033                 LDREQB          rscratch,[regCPUvar,#RAH_ofs]
2034                 MOVEQ           regA,regA,LSR #8
2035                 ORREQ           regA,regA,rscratch, LSL #24
2036                 ADD2CYCLE
2037                 S9xFixCycles
2038 .endm
2039 .macro          Op40X0M1
2040                 //INDEX cleared, MEMORY set
2041                 BIC             rstatus,rstatus,#0xFF000000
2042                 PullBr
2043                 ORR             rstatus,rscratch,rstatus
2044                 PullWlow        rpc
2045                 TST             rstatus, #MASK_EMUL
2046                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2047                 BNE             2401f
2048                 PullBrLow
2049                 BIC             regPBank,regPBank,#0xFF
2050                 ORR             regPBank,regPBank,rscratch
2051 2401:
2052                 ADD             rscratch, rpc, regPBank, LSL #16
2053                 S9xSetPCBase
2054                 TST             rstatus, #MASK_INDEX
2055                 //INDEX set & was cleared : 16->8
2056                 MOVNE           regX,regX,LSL #8
2057                 MOVNE           regY,regY,LSL #8
2058                 TST             rstatus, #MASK_MEM
2059                 //MEMORY cleared & was set : 8->16
2060                 LDREQB          rscratch,[regCPUvar,#RAH_ofs]
2061                 MOVEQ           regA,regA,LSR #8
2062                 ORREQ           regA,regA,rscratch, LSL #24
2063                 ADD2CYCLE
2064                 S9xFixCycles
2065 .endm
2066 .macro          Op40X1M0
2067                 //INDEX set, MEMORY cleared
2068                 BIC             rstatus,rstatus,#0xFF000000
2069                 PullBr
2070                 ORR             rstatus,rscratch,rstatus
2071                 PullWlow        rpc
2072                 TST             rstatus, #MASK_EMUL
2073                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2074                 BNE             2401f
2075                 PullBrLow
2076                 BIC             regPBank,regPBank,#0xFF
2077                 ORR             regPBank,regPBank,rscratch
2078 2401:
2079                 ADD             rscratch, rpc, regPBank, LSL #16
2080                 S9xSetPCBase
2081                 TST             rstatus, #MASK_INDEX
2082                 //INDEX cleared & was set : 8->16
2083                 MOVEQ           regX,regX,LSR #8
2084                 MOVEQ           regY,regY,LSR #8
2085                 TST             rstatus, #MASK_MEM
2086                 //MEMORY set & was cleared : 16->8
2087                 MOVNE           rscratch,regA,LSR #24
2088                 MOVNE           regA,regA,LSL #8
2089                 STRNEB          rscratch,[regCPUvar,#RAH_ofs]
2090                 ADD2CYCLE
2091                 S9xFixCycles
2092 .endm
2093 .macro          Op40X0M0
2094                 //INDEX cleared, MEMORY cleared
2095                 BIC             rstatus,rstatus,#0xFF000000
2096                 PullBr
2097                 ORR             rstatus,rscratch,rstatus
2098                 PullWlow        rpc
2099                 TST             rstatus, #MASK_EMUL
2100                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2101                 BNE             2401f
2102                 PullBrLow
2103                 BIC             regPBank,regPBank,#0xFF
2104                 ORR             regPBank,regPBank,rscratch
2105 2401:
2106                 ADD             rscratch, rpc, regPBank, LSL #16
2107                 S9xSetPCBase
2108                 TST             rstatus, #MASK_INDEX
2109                 //INDEX set & was cleared : 16->8
2110                 MOVNE           regX,regX,LSL #8
2111                 MOVNE           regY,regY,LSL #8
2112                 TST             rstatus, #MASK_MEM
2113                 //MEMORY set & was cleared : 16->8
2114                 //MEMORY set & was cleared : 16->8
2115                 MOVNE           rscratch,regA,LSR #24
2116                 MOVNE           regA,regA,LSL #8
2117                 STRNEB          rscratch,[regCPUvar,#RAH_ofs]
2118                 ADD2CYCLE
2119                 S9xFixCycles
2120 .endm
2121
2122
2123 /**********************************************************************************************/
2124 /* STP/WAI/DB ******************************************************************************** */
2125 // WAI
2126 .macro          OpCB    /*WAI*/
2127         LDRB            rscratch,[regCPUvar,#IRQActive_ofs]
2128         MOVS            rscratch,rscratch
2129         //(CPU.IRQActive)
2130         ADD2CYCLENE
2131         BNE             1234f
2132 /*
2133         CPU.WaitingForInterrupt = TRUE;
2134         CPU.PC--;*/
2135         MOV             rscratch,#1
2136         SUB             rpc,rpc,#1
2137 /*
2138             CPU.Cycles = CPU.NextEvent;
2139 */
2140         STRB            rscratch,[regCPUvar,#WaitingForInterrupt_ofs]
2141         LDR             regCycles,[regCPUvar,#NextEvent_ofs]
2142 /*
2143         if (IAPU.APUExecuting)
2144             {
2145                 ICPU.CPUExecuting = FALSE;
2146                 do
2147                 {
2148                     APU_EXECUTE1 ();
2149                 } while (APU.Cycles < CPU.NextEvent);
2150                 ICPU.CPUExecuting = TRUE;
2151             }
2152 */
2153         LDRB            rscratch,[regCPUvar,#APUExecuting_ofs]
2154         MOVS            rscratch,rscratch
2155         BEQ             1234f
2156         asmAPU_EXECUTE2
2157
2158 1234:
2159 .endm
2160 .macro          OpDB    /*STP*/
2161                 SUB     rpc,rpc,#1
2162                 //CPU.Flags |= DEBUG_MODE_FLAG;
2163 .endm
2164 .macro          Op42   /*Reserved Snes9X*/
2165 .endm
2166
2167 /**********************************************************************************************/
2168 /* AND ******************************************************************************** */
2169 .macro          Op29M1
2170                 LDRB    rscratch    , [rpc], #1
2171                 ANDS    regA    , regA, rscratch, LSL #24
2172                 UPDATE_ZN
2173                 ADD1MEM
2174 .endm
2175 .macro          Op29M0
2176                 LDRB    rscratch2  , [rpc,#1]
2177                 LDRB    rscratch   , [rpc], #2
2178                 ORR     rscratch, rscratch, rscratch2, LSL #8
2179                 ANDS    regA    , regA, rscratch, LSL #16
2180                 UPDATE_ZN
2181                 ADD2MEM
2182 .endm
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198 /**********************************************************************************************/
2199 /* EOR ******************************************************************************** */
2200 .macro          Op49M0
2201                 LDRB    rscratch2 , [rpc, #1]
2202                 LDRB    rscratch , [rpc], #2
2203                 ORR     rscratch, rscratch, rscratch2,LSL #8
2204                 EORS    regA, regA, rscratch,LSL #16
2205                 UPDATE_ZN
2206                 ADD2MEM
2207 .endm
2208
2209
2210 .macro          Op49M1
2211                 LDRB    rscratch , [rpc], #1
2212                 EORS    regA, regA, rscratch,LSL #24
2213                 UPDATE_ZN
2214                 ADD1MEM
2215 .endm
2216
2217
2218 /**********************************************************************************************/
2219 /* STA *************************************************************************************** */
2220 .macro          Op81M1
2221                 STA8
2222                 //TST           rstatus, #MASK_INDEX
2223                 //ADD1CYCLENE
2224 .endm
2225 .macro          Op81M0
2226                 STA16
2227                 //TST rstatus, #MASK_INDEX
2228                 //ADD1CYCLENE
2229 .endm
2230
2231
2232 /**********************************************************************************************/
2233 /* BIT *************************************************************************************** */
2234 .macro          Op89M1
2235                 LDRB    rscratch , [rpc], #1
2236                 TST     regA, rscratch, LSL #24
2237                 UPDATE_Z
2238                 ADD1MEM
2239 .endm
2240 .macro          Op89M0
2241                 LDRB    rscratch2 , [rpc, #1]
2242                 LDRB    rscratch , [rpc], #2
2243                 ORR     rscratch, rscratch, rscratch2, LSL #8
2244                 TST     regA, rscratch, LSL #16
2245                 UPDATE_Z
2246                 ADD2MEM
2247 .endm
2248
2249
2250
2251
2252
2253
2254 /**********************************************************************************************/
2255 /* LDY *************************************************************************************** */
2256 .macro          OpA0X1
2257                 LDRB    rscratch , [rpc], #1
2258                 MOVS    regY, rscratch, LSL #24
2259                 UPDATE_ZN
2260                 ADD1MEM
2261 .endm
2262 .macro          OpA0X0
2263                 LDRB    rscratch2 , [rpc, #1]
2264                 LDRB    rscratch , [rpc], #2
2265                 ORR     rscratch, rscratch, rscratch2, LSL #8
2266                 MOVS    regY, rscratch, LSL #16
2267                 UPDATE_ZN
2268                 ADD2MEM
2269 .endm
2270
2271 /**********************************************************************************************/
2272 /* LDX *************************************************************************************** */
2273 .macro          OpA2X1
2274                 LDRB    rscratch , [rpc], #1
2275                 MOVS    regX, rscratch, LSL #24
2276                 UPDATE_ZN
2277                 ADD1MEM
2278 .endm
2279 .macro          OpA2X0
2280                 LDRB    rscratch2 , [rpc, #1]
2281                 LDRB    rscratch , [rpc], #2
2282                 ORR     rscratch, rscratch, rscratch2, LSL #8
2283                 MOVS    regX, rscratch, LSL #16
2284                 UPDATE_ZN
2285                 ADD2MEM
2286 .endm
2287
2288 /**********************************************************************************************/
2289 /* LDA *************************************************************************************** */
2290 .macro          OpA9M1
2291                 LDRB    rscratch , [rpc], #1
2292                 MOVS    regA, rscratch, LSL #24
2293                 UPDATE_ZN
2294                 ADD1MEM
2295 .endm
2296 .macro          OpA9M0
2297                 LDRB    rscratch2 , [rpc, #1]
2298                 LDRB    rscratch , [rpc], #2
2299                 ORR     rscratch, rscratch, rscratch2, LSL #8
2300                 MOVS    regA, rscratch, LSL #16
2301                 UPDATE_ZN
2302                 ADD2MEM
2303 .endm
2304
2305 /**********************************************************************************************/
2306 /* CMY *************************************************************************************** */
2307 .macro          OpC0X1
2308                 LDRB    rscratch    , [rpc], #1
2309                 SUBS    rscratch2   , regY , rscratch, LSL #24
2310                 BICCC   rstatus, rstatus, #MASK_CARRY
2311                 ORRCS   rstatus, rstatus, #MASK_CARRY
2312                 UPDATE_ZN
2313                 ADD1MEM
2314 .endm
2315 .macro          OpC0X0
2316                 LDRB    rscratch2   , [rpc, #1]
2317                 LDRB    rscratch   , [rpc], #2
2318                 ORR     rscratch, rscratch, rscratch2, LSL #8
2319                 SUBS    rscratch2   , regY, rscratch, LSL #16
2320                 BICCC   rstatus, rstatus, #MASK_CARRY
2321                 ORRCS   rstatus, rstatus, #MASK_CARRY
2322                 UPDATE_ZN
2323                 ADD2MEM
2324 .endm
2325
2326
2327
2328
2329
2330 /**********************************************************************************************/
2331 /* CMP *************************************************************************************** */
2332 .macro          OpC9M1
2333                 LDRB    rscratch    , [rpc], #1
2334                 SUBS    rscratch2   , regA , rscratch, LSL #24
2335                 BICCC   rstatus, rstatus, #MASK_CARRY
2336                 ORRCS   rstatus, rstatus, #MASK_CARRY
2337                 UPDATE_ZN
2338                 ADD1MEM
2339 .endm
2340 .macro          OpC9M0
2341                 LDRB    rscratch2   , [rpc,#1]
2342                 LDRB    rscratch   , [rpc], #2
2343                 ORR     rscratch, rscratch, rscratch2, LSL #8
2344                 SUBS    rscratch2   , regA, rscratch, LSL #16
2345                 BICCC   rstatus, rstatus, #MASK_CARRY
2346                 ORRCS   rstatus, rstatus, #MASK_CARRY
2347                 UPDATE_ZN
2348                 ADD2MEM
2349 .endm
2350
2351 /**********************************************************************************************/
2352 /* CMX *************************************************************************************** */
2353 .macro          OpE0X1
2354                 LDRB    rscratch    , [rpc], #1
2355                 SUBS    rscratch2   , regX , rscratch, LSL #24
2356                 BICCC   rstatus, rstatus, #MASK_CARRY
2357                 ORRCS   rstatus, rstatus, #MASK_CARRY
2358                 UPDATE_ZN
2359                 ADD1MEM
2360 .endm
2361 .macro          OpE0X0
2362                 LDRB    rscratch2   , [rpc,#1]
2363                 LDRB    rscratch   , [rpc], #2
2364                 ORR     rscratch, rscratch, rscratch2, LSL #8
2365                 SUBS    rscratch2   , regX, rscratch, LSL #16
2366                 BICCC   rstatus, rstatus, #MASK_CARRY
2367                 ORRCS   rstatus, rstatus, #MASK_CARRY
2368                 UPDATE_ZN
2369                 ADD2MEM
2370 .endm
2371
2372 /*
2373
2374
2375 CLI_OPE_REC_Nos_Layer0
2376         nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103)
2377         nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103)
2378
2379 CLI_OPE_Nos_Ope_Layer0
2380         n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103)
2381         n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103)
2382
2383 CLI_OPE_Nos_Layer0
2384         nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103)
2385         nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103)
2386
2387 Ecrans:
2388 ------
2389
2390
2391 [GNV] : utilisation de la lard (laccdate) pour afficher les openings.
2392    +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate
2393
2394 [Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée
2395 sinon :
2396   +données nécessaires : opening date tréso=date compta=laccdate=BD-1
2397   +données nécessaires : opening date tréso=date compta=laccdate-1
2398   +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate
2399    */
2400
2401
2402 /*
2403
2404
2405
2406
2407
2408 */