git.maemo.org Git - kernel-bfs/blob - kernel-bfs-2.6.28/debian/patches/overclock_smartreflex_900.diff

   1 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/omap3-opp.h kernel-power-2.6.28.SR/arch/arm/mach-omap2/omap3-opp.h
   2 --- kernel-power-2.6.28/arch/arm/mach-omap2/omap3-opp.h 2011-10-11 13:51:21.441301622 +0100
   3 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/omap3-opp.h      2011-10-22 16:31:45.291911000 +0100
   4 @@ -11,8 +11,7 @@
   5  #define S900M   900000000
   6  #define S850M   850000000
   7  #define S805M   805000000
   8 -#define S750M   750000000
   9 -#define S700M   700000000
  10 +#define S720M   720000000
  11  #define S600M   600000000
  12  #define S550M   550000000
  13  #define S500M   500000000
  14 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/pm34xx.c kernel-power-2.6.28.SR/arch/arm/mach-omap2/pm34xx.c
  15 --- kernel-power-2.6.28/arch/arm/mach-omap2/pm34xx.c    2011-10-11 13:51:19.475662264 +0100
  16 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/pm34xx.c 2011-11-14 17:06:15.733128000 +0000
  17 @@ -629,9 +629,9 @@
  18          * Only needed if we are going to enter retention.
  19          */
  20         if (mpu_next_state < PWRDM_POWER_ON)
  21 -               disable_smartreflex(SR1);
  22 +               disable_smartreflex(SR1,0);
  23         if (core_next_state < PWRDM_POWER_ON)
  24 -               disable_smartreflex(SR2);
  25 +               disable_smartreflex(SR2,0);
  26
  27         /* CORE */
  28         if (core_next_state < PWRDM_POWER_ON) {
  29 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/pm.c kernel-power-2.6.28.SR/arch/arm/mach-omap2/pm.c
  30 --- kernel-power-2.6.28/arch/arm/mach-omap2/pm.c        2011-10-11 13:51:21.444897248 +0100
  31 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/pm.c     2011-11-12 13:33:08.600565000 +0000
  32 @@ -44,25 +44,23 @@
  33
  34  struct omap_opp omap3_mpu_rate_table[] = {
  35         {0, 0, 0},
  36 -       {0, 1, 0x1E},
  37 -       /*underclocking*/
  38 -       {S125M, 2, 0x1E},
  39         /*default*/
  40 -       {S250M, 3, 0x26},
  41 -       {S500M, 4, 0x30},
  42 -       {S550M, 5, 0x36},
  43 -       {S600M, 6, 0x3C},
  44 +       {S125M, VDD1_OPP1,  0x1E},
  45 +       {S250M, VDD1_OPP2,  0x26},
  46 +       {S500M, VDD1_OPP3,  0x30},
  47 +       {S550M, VDD1_OPP4,  0x36},
  48 +       {S600M, VDD1_OPP5,  0x3C},
  49         /*overclocking*/
  50 -       {S700M, 7, 0x3C},
  51 -       {S750M, 8, 0x3C},
  52 -       {S805M, 9, 0x3C},
  53 -       {S850M, 10, 0x3C},
  54 -       {S900M, 11, 0x3C},
  55 -       {S950M, 12, 0x3C},
  56 -       {S1000M, 13, 0x3C},
  57 -       {S1100M, 14, 0x48},
  58 -       {S1150M, 15, 0x48},
  59 +       {S720M, VDD1_OPP6,  0x3C},
  60 +       {S805M, VDD1_OPP7,  0x3C},
  61 +       {S850M, VDD1_OPP8,  0x3C},
  62 +       {S900M, VDD1_OPP9,  0x3C},
  63 +       {S950M, VDD1_OPP10, 0x3C},
  64 +       {S1000M,VDD1_OPP11, 0x3C},
  65 +       {S1100M,VDD1_OPP12, 0x48},
  66 +       {S1150M,VDD1_OPP13, 0x48},
  67  };
  68 +EXPORT_SYMBOL(omap3_mpu_rate_table);
  69
  70  struct omap_opp omap3_l3_rate_table[] = {
  71         {0, 0, 0},
  72 @@ -76,25 +74,23 @@
  73
  74  struct omap_opp omap3_dsp_rate_table[] = {
  75         {0, 0, 0},
  76 -       /*underclocking*/
  77 -       {S90M,  1, 0x1E},
  78         /*default*/
  79 -       {S90M,  2, 0x1E},
  80 -       {S180M, 3, 0x26},
  81 -       {S360M, 4, 0x30},
  82 -       {S400M, 5, 0x36},
  83 -       {S430M, 6, 0x3C},
  84 +       {S90M,  VDD1_OPP1,  0x1E},
  85 +       {S180M, VDD1_OPP2,  0x26},
  86 +       {S360M, VDD1_OPP3,  0x30},
  87 +       {S400M, VDD1_OPP4,  0x36},
  88 +       {S430M, VDD1_OPP5,  0x3C},
  89         /*overclocking*/
  90 -       {S430M, 7, 0x3C},
  91 -       {S430M, 8, 0x3C},
  92 -       {S430M, 9, 0x3C},/*800MHz*/
  93 -       {S500M, 10, 0x3C},
  94 -       {S500M, 11, 0x3C},
  95 -       {S500M, 12, 0x3C},
  96 -       {S500M, 13, 0x3C},
  97 -       {S520M, 14, 0x48},
  98 -       {S520M, 15, 0x48},
  99 +       {S520M, VDD1_OPP6,  0x3C},
 100 +       {S520M, VDD1_OPP7,  0x3C},
 101 +       {S520M, VDD1_OPP8,  0x3C},
 102 +       {S520M, VDD1_OPP9,  0x3C},
 103 +       {S520M, VDD1_OPP10, 0x3C},
 104 +       {S520M, VDD1_OPP11, 0x3C},
 105 +       {S520M, VDD1_OPP12, 0x48},
 106 +       {S520M, VDD1_OPP13, 0x48},
 107  };
 108 +EXPORT_SYMBOL(omap3_dsp_rate_table);
 109
 110  unsigned short enable_dyn_sleep;
 111  unsigned short clocks_off_while_idle;
 112 @@ -342,13 +338,13 @@
 113         }
 114
 115         if (attr == &vdd1_opp_attr) {
 116 -               if (value < 1 || value > 5) {
 117 +               if (value < MIN_VDD1_OPP || value > MAX_VDD1_OPP) {
 118                         printk(KERN_ERR "vdd_opp_store: Invalid value\n");
 119                         return -EINVAL;
 120                 }
 121                 resource_set_opp_level(PRCM_VDD1, value, flags);
 122         } else if (attr == &vdd2_opp_attr) {
 123 -               if (value < 1 || value > 3) {
 124 +               if (value < MIN_VDD2_OPP || value > MAX_VDD2_OPP) {
 125                         printk(KERN_ERR "vdd_opp_store: Invalid value\n");
 126                         return -EINVAL;
 127                 }
 128 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/resource34xx.c kernel-power-2.6.28.SR/arch/arm/mach-omap2/resource34xx.c
 129 --- kernel-power-2.6.28/arch/arm/mach-omap2/resource34xx.c      2011-10-11 13:50:56.787174344 +0100
 130 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/resource34xx.c   2011-11-15 10:50:41.556771000 +0000
 131 @@ -279,7 +279,7 @@
 132
 133  #ifdef CONFIG_OMAP_SMARTREFLEX
 134         sr_status = sr_stop_vddautocomap((get_vdd(t_opp) == PRCM_VDD1) ?
 135 -                       SR1 : SR2);
 136 +                       SR1 : SR2,opp[current_level].opp_id);
 137  #endif
 138         for (i = 0; i < 2; i++) {
 139                 if (i == raise)
 140 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.c kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.c
 141 --- kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.c       2011-10-11 13:51:21.441301622 +0100
 142 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.c    2011-11-15 10:54:13.761220000 +0000
 143 @@ -37,6 +37,7 @@
 144  #include "prm.h"
 145  #include "smartreflex.h"
 146  #include "prm-regbits-34xx.h"
 147 +#include "omap3-opp.h"
 148
 149  /*
 150   * VP_TRANXDONE_TIMEOUT: maximum microseconds to wait for the VP to
 151 @@ -73,6 +74,12 @@
 152   */
 153  #define SR_DISABLE_MAX_ATTEMPTS 4
 154
 155 +#define ACCURACY               100
 156 +#define NDELTA_3430            (3.0 * ACCURACY)
 157 +#define PDELTA_3430            (2.6 * ACCURACY)
 158 +#define SR_NVALUE_ADJUST -150000
 159 +#define SR_NVALUE_DSP_ADJUST 12500
 160 +
 161  struct omap_sr {
 162         int             srid;
 163         int             is_sr_reset;
 164 @@ -82,6 +89,7 @@
 165         u32             req_opp_no;
 166         u32             opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue;
 167         u32             opp5_nvalue;
 168 +       u32             opp6_nvalue, opp7_nvalue, opp8_nvalue, opp9_nvalue;
 169         u32             senp_mod, senn_mod;
 170         void __iomem    *srbase_addr;
 171         void __iomem    *vpbase_addr;
 172 @@ -101,6 +109,7 @@
 173
 174         reg_val = __raw_readl(SR_REGADDR(offset));
 175         reg_val &= ~mask;
 176 +
 177         reg_val |= value;
 178
 179         __raw_writel(reg_val, SR_REGADDR(offset));
 180 @@ -211,6 +220,147 @@
 181         }
 182  }
 183
 184 +static u32 calculate_opp_nadj(u32 opp_value, u32 delta_n)
 185 +{
 186 +       u32 sen_ngain_fuse, sen_nrn_fuse;
 187 +
 188 +       sen_ngain_fuse = (opp_value & 0x000F0000) >> 0x10;
 189 +       sen_nrn_fuse = (opp_value & 0x000000FF);
 190 +
 191 +       return ((1 << (sen_ngain_fuse + 8)) / sen_nrn_fuse) + delta_n;
 192 +}
 193 +
 194 +static u32 calculate_opp_padj(u32 opp_value, u32 delta_p)
 195 +{
 196 +       u32 sen_pgain_fuse, sen_prn_fuse;
 197 +
 198 +       sen_pgain_fuse = (opp_value & 0x000F00000) >> 0x14;
 199 +       sen_prn_fuse = (opp_value & 0x0000FF00) >> 8;
 200 +
 201 +       return ((1 << (sen_pgain_fuse + 8)) / sen_prn_fuse) + delta_p;
 202 +}
 203 +
 204 +static u32 get_padj_for_freq(u32 opp0fuse,u32 opp1fuse, u32 freq)
 205 +{
 206 +       u32 padj_0=calculate_opp_padj(opp0fuse,0);
 207 +       u32 padj_1=calculate_opp_padj(opp1fuse,0);
 208 +       u32 p_slope_a=(1000*(padj_1-padj_0))/(250-125);
 209 +       u32 p_slope_b=1000*(padj_1-p_slope_a*250/1000);
 210 +
 211 +       return (u32)(p_slope_a*freq+p_slope_b)/1000;
 212 +}
 213 +
 214 +static u32 get_nadj_for_freq(u32 opp0fuse,u32 opp1fuse, u32 freq)
 215 +{
 216 +       u32 nadj_0=calculate_opp_nadj(opp0fuse,0);
 217 +       u32 nadj_1=calculate_opp_nadj(opp1fuse,0);
 218 +       u32 n_slope_a=(1000*(nadj_1-nadj_0))/(250-125);
 219 +       u32 n_slope_b=1000*(nadj_1-n_slope_a*250/1000);
 220 +
 221 +       return (u32)(n_slope_a*freq+n_slope_b)/1000;
 222 +}
 223 +
 224 +static u32 calculate_freq_efuse_value(u32 opp0fuse,u32 opp1fuse,u32 freq)
 225 +{
 226 +       u32 sen_nrn, sen_ngain, sen_prn, sen_pgain;
 227 +       u32 padj,nadj;
 228 +       cal_reciprocal(padj=get_padj_for_freq(opp0fuse,opp1fuse,freq), &sen_pgain, &sen_prn);
 229 +       cal_reciprocal(nadj=get_nadj_for_freq(opp0fuse,opp1fuse,freq), &sen_ngain, &sen_nrn);
 230 +
 231 +       return (sen_pgain << 0x14) | (sen_ngain << 0x10)
 232 +               | (sen_prn << 0x08) | (sen_nrn);
 233 +}
 234 +
 235 +/**
 236 + * recalc_with_margin() - helper to add margin to reciprocal and gain
 237 + * @uv:                voltage in uVolts to add.
 238 + * @soc_delta: SoC specific delta base
 239 + * @reci:      Reciprocal for the sensor
 240 + * @gain:      Gain for the sensor
 241 + *
 242 + * The algorithm computes an adjustment required to meet the delta voltage
 243 + * to be added to a given sensor's reciprocal and gain. It then does a
 244 + * search for maximum gain for valid reciprocal value. This forms the
 245 + * new reciprocal and gain which incorporates the additional voltage
 246 + * requested.
 247 + *
 248 + * IMPORTANT: since it is not possible to ascertain the actual voltage from
 249 + * ntarget value, the additional voltage will be accurate upto 1 additional
 250 + * pmic step. The algorithm is optimized to adjust to higher end rather than
 251 + * less than requested additional voltage as it could be unsafe to run at
 252 + * voltage lower than requested level.
 253 + *
 254 + * Example: if the PMIC step size is 12.5 and requested margin in 25mV(2 PMIC
 255 + * steps). the actual voltage achieved can be original V achieved + 25mV upto
 256 + * original V + 37.5mV(3 steps) - depending on where V was achieved.
 257 + */
 258 +static __init int recalc_with_margin(long uv, int soc_delta, unsigned int *reci,
 259 +               unsigned int *gain)
 260 +{
 261 +       int r = 0, g = 0;
 262 +       int nadj = 0;
 263 +
 264 +       nadj = ((1 << (*gain + 8)) * ACCURACY) / (*reci) +
 265 +               soc_delta * uv / 1000;
 266 +
 267 +       /* Linear search for the best reciprocal */
 268 +       for (g = 15; g >= 0; g--) {
 269 +               r = ((1 << (g + 8)) * ACCURACY) / nadj;
 270 +               if (r < 256) {
 271 +                       *reci = r;
 272 +                       *gain = g;
 273 +                       return 0;
 274 +               }
 275 +       }
 276 +       /* Dont modify the input, just return error */
 277 +       return -EINVAL;
 278 +}
 279 +
 280 +/**
 281 + * sr_ntarget_add_margin() - Modify h/w ntarget to add a s/w margin
 282 + * @vdata:     voltage data for the OPP to be modified with ntarget populated
 283 + * @add_uv:    voltate to add to nTarget in uVolts
 284 + *
 285 + * Once the sr_device_init is complete and nTargets are populated, using this
 286 + * function nTarget read from h/w efuse and stored in vdata is modified to add
 287 + * a platform(board) specific additional voltage margin. Based on analysis,
 288 + * we might need different margins to be added per vdata.
 289 + */
 290 +int __init sr_ntarget_add_margin(u32 old_ntarget, ulong add_uv)
 291 +{
 292 +       u32 temp_senp_gain, temp_senp_reciprocal;
 293 +       u32 temp_senn_gain, temp_senn_reciprocal;
 294 +       int soc_p_delta, soc_n_delta;
 295 +       int r;
 296 +
 297 +       temp_senp_gain = (old_ntarget & 0x00F00000) >> 20;
 298 +       temp_senn_gain = (old_ntarget & 0x000F0000) >> 16;
 299 +       temp_senp_reciprocal = (old_ntarget & 0x0000FF00) >> 8;
 300 +       temp_senn_reciprocal = old_ntarget & 0x000000FF;
 301 +
 302 +       soc_p_delta = PDELTA_3430;
 303 +       soc_n_delta = NDELTA_3430;
 304 +
 305 +       r = recalc_with_margin(add_uv, soc_n_delta,
 306 +                       &temp_senn_reciprocal, &temp_senn_gain);
 307 +       if (r) {
 308 +               pr_err("%s: unable to add %ld uV to ntarget 0x%08x\n",
 309 +                       __func__, add_uv, old_ntarget);
 310 +               return r;
 311 +       }
 312 +       r = recalc_with_margin(add_uv, soc_p_delta,
 313 +                       &temp_senp_reciprocal, &temp_senp_gain);
 314 +       if (r) {
 315 +           pr_err("%s: unable to add %ld uV to ntarget 0x%08x\n",
 316 +                       __func__, add_uv, old_ntarget);
 317 +               return r;
 318 +       }
 319 +
 320 +       /* Populate the new modified nTarget */
 321 +       return (temp_senp_gain << 20) | (temp_senn_gain << 16) |
 322 +                       (temp_senp_reciprocal << 8) | temp_senn_reciprocal;
 323 +
 324 +}
 325  static void sr_set_efuse_nvalues(struct omap_sr *sr)
 326  {
 327         if (sr->srid == SR1) {
 328 @@ -220,17 +370,24 @@
 329                 sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
 330                                         OMAP343X_SR1_SENPENABLE_MASK) >>
 331                                         OMAP343X_SR1_SENPENABLE_SHIFT;
 332 -
 333 -               sr->opp5_nvalue = omap_ctrl_readl(
 334 -                                       OMAP343X_CONTROL_FUSE_OPP5_VDD1);
 335 -               sr->opp4_nvalue = omap_ctrl_readl(
 336 -                                       OMAP343X_CONTROL_FUSE_OPP4_VDD1);
 337 -               sr->opp3_nvalue = omap_ctrl_readl(
 338 -                                       OMAP343X_CONTROL_FUSE_OPP3_VDD1);
 339 -               sr->opp2_nvalue = omap_ctrl_readl(
 340 -                                       OMAP343X_CONTROL_FUSE_OPP2_VDD1);
 341 -               sr->opp1_nvalue = omap_ctrl_readl(
 342 -                                       OMAP343X_CONTROL_FUSE_OPP1_VDD1);
 343 +               sr->opp1_nvalue = sr_ntarget_add_margin(omap_ctrl_readl(
 344 +                                       OMAP343X_CONTROL_FUSE_OPP1_VDD1),SR_NVALUE_ADJUST);
 345 +               sr->opp2_nvalue = sr_ntarget_add_margin(omap_ctrl_readl(
 346 +                                       OMAP343X_CONTROL_FUSE_OPP2_VDD1),SR_NVALUE_ADJUST);
 347 +               /* 500 */
 348 +               sr->opp3_nvalue = sr_ntarget_add_margin(sr->opp2_nvalue,212500);
 349 +               /* 550 */
 350 +               sr->opp4_nvalue = sr_ntarget_add_margin(sr->opp3_nvalue,50000);
 351 +               /* 600 */
 352 +               sr->opp5_nvalue = sr_ntarget_add_margin(sr->opp4_nvalue,50000);
 353 +               /* 720 */
 354 +               sr->opp6_nvalue = sr_ntarget_add_margin(sr->opp5_nvalue,100000);
 355 +               /* 805 */
 356 +               sr->opp7_nvalue = sr_ntarget_add_margin(sr->opp6_nvalue,75000);
 357 +               /* 850 */
 358 +               sr->opp8_nvalue = sr_ntarget_add_margin(sr->opp7_nvalue,50000);
 359 +               /* 900 */
 360 +               sr->opp9_nvalue = sr_ntarget_add_margin(sr->opp8_nvalue,55000);
 361         } else if (sr->srid == SR2) {
 362                 sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
 363                                         OMAP343X_SR2_SENNENABLE_MASK) >>
 364 @@ -262,6 +419,14 @@
 365                 sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200);
 366                 sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0);
 367                 sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100);
 368 +               sr->opp6_nvalue = calculate_freq_efuse_value(sr->opp1_nvalue,sr->opp2_nvalue,
 369 +                                                            mpu_opps[VDD1_OPP6].rate/1000000);
 370 +               sr->opp7_nvalue = calculate_freq_efuse_value(sr->opp1_nvalue,sr->opp2_nvalue,
 371 +                                                            mpu_opps[VDD1_OPP7].rate/1000000);
 372 +               sr->opp8_nvalue = calculate_freq_efuse_value(sr->opp1_nvalue,sr->opp2_nvalue,
 373 +                                                            mpu_opps[VDD1_OPP8].rate/1000000);
 374 +               sr->opp9_nvalue = calculate_freq_efuse_value(sr->opp1_nvalue,sr->opp2_nvalue,
 375 +                                                            mpu_opps[VDD1_OPP9].rate/1000000);
 376         } else if (sr->srid == SR2) {
 377                 sr->senp_mod = 0x03;
 378                 sr->senn_mod = 0x03;
 379 @@ -426,7 +591,7 @@
 380         sr->is_sr_reset = 0;
 381  }
 382
 383 -static int sr_reset_voltage(int srid)
 384 +static int sr_reset_voltage(int srid,u32 curr_opp_no)
 385  {
 386         u32 target_opp_no, vsel = 0;
 387         u32 reg_addr = 0;
 388 @@ -443,6 +608,14 @@
 389                 reg_addr = R_VDD1_SR_CONTROL;
 390                 prm_vp1_voltage = prm_read_mod_reg(OMAP3430_GR_MOD,
 391                                                 OMAP3_PRM_VP1_VOLTAGE_OFFSET);
 392 +               /* Store current calibrated voltage to be used next time preventing
 393 +                * overvoltage when calibration cycle  starts. if cur_opp_no is 0 don't
 394 +                * store current voltage, we've been called from sram_idle().
 395 +                * Just in case add 1 to it, so we can start a little higher next time
 396 +                */
 397 +               if(curr_opp_no)
 398 +                       mpu_opps[curr_opp_no].vsel = min((u32)mpu_opps[curr_opp_no].vsel,
 399 +                                                         prm_vp1_voltage+1);
 400                 t2_smps_steps = abs(vsel - prm_vp1_voltage);
 401                 errorgain = (target_opp_no > SR_MAX_LOW_OPP) ?
 402                         PRM_VP1_CONFIG_ERRORGAIN_HIGHOPP :
 403 @@ -513,7 +686,19 @@
 404         sr->req_opp_no = target_opp_no;
 405
 406         if (sr->srid == SR1) {
 407 -               switch (min(target_opp_no-1,5)) {
 408 +               switch (min(target_opp_no,(u32)PRCM_NO_VDD1_OPPS)) {
 409 +               case 9:
 410 +                       nvalue_reciprocal = sr->opp9_nvalue;
 411 +                       break;
 412 +               case 8:
 413 +                       nvalue_reciprocal = sr->opp8_nvalue;
 414 +                       break;
 415 +               case 7:
 416 +                       nvalue_reciprocal = sr->opp7_nvalue;
 417 +                       break;
 418 +               case 6:
 419 +                       nvalue_reciprocal = sr->opp6_nvalue;
 420 +                       break;
 421                 case 5:
 422                         nvalue_reciprocal = sr->opp5_nvalue;
 423                         break;
 424 @@ -534,6 +719,11 @@
 425                         nvalue_reciprocal = sr->opp3_nvalue;
 426                         break;
 427                 }
 428 +               /* give a little more just when DSP is overclocked */
 429 +               if(dsp_opps[target_opp_no].rate > S430M)
 430 +                       nvalue_reciprocal = sr_ntarget_add_margin(nvalue_reciprocal,SR_NVALUE_DSP_ADJUST);
 431 +               if(dsp_opps[target_opp_no].rate > S520M)
 432 +                       nvalue_reciprocal = sr_ntarget_add_margin(nvalue_reciprocal,SR_NVALUE_DSP_ADJUST);
 433         } else {
 434                 switch (target_opp_no) {
 435                 case 3:
 436 @@ -556,7 +746,6 @@
 437                                                                 target_opp_no);
 438                 return SR_FALSE;
 439         }
 440 -
 441         sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
 442
 443         /* Enable the interrupt */
 444 @@ -772,7 +961,7 @@
 445  }
 446  EXPORT_SYMBOL(sr_start_vddautocomap);
 447
 448 -int sr_stop_vddautocomap(int srid)
 449 +int sr_stop_vddautocomap(int srid,u32 cur_opp_no)
 450  {
 451         struct omap_sr *sr = NULL;
 452
 453 @@ -789,7 +978,7 @@
 454                 sr_clk_disable(sr);
 455                 sr->is_autocomp_active = 0;
 456                 /* Reset the volatage for current OPP */
 457 -               sr_reset_voltage(srid);
 458 +               sr_reset_voltage(srid,cur_opp_no);
 459                 return SR_TRUE;
 460         } else
 461                 return SR_FALSE;
 462 @@ -823,7 +1012,7 @@
 463         }
 464  }
 465
 466 -void disable_smartreflex(int srid)
 467 +void disable_smartreflex(int srid,u32 cur_opp_no)
 468  {
 469         struct omap_sr *sr = NULL;
 470
 471 @@ -843,7 +1032,7 @@
 472                         /* Disable SR clk */
 473                         sr_clk_disable(sr);
 474                         /* Reset the volatage for current OPP */
 475 -                       sr_reset_voltage(srid);
 476 +                       sr_reset_voltage(srid,cur_opp_no);
 477                 }
 478         }
 479  }
 480 @@ -953,22 +1142,22 @@
 481                                         const char *buf, size_t n)
 482  {
 483         unsigned short value;
 484 -
 485 +       u32 current_vdd1opp_no;
 486         if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
 487                 printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n");
 488                 return -EINVAL;
 489         }
 490
 491         mutex_lock(&dvfs_mutex);
 492 +       current_vdd1opp_no = resource_get_level("vdd1_opp");
 493 +       if (IS_ERR_VALUE(current_vdd1opp_no)) {
 494 +               mutex_unlock(&dvfs_mutex);
 495 +               return -ENODEV;
 496 +       }
 497
 498         if (value == 0) {
 499 -               sr_stop_vddautocomap(SR1);
 500 +               sr_stop_vddautocomap(SR1,current_vdd1opp_no);
 501         } else {
 502 -               u32 current_vdd1opp_no = resource_get_level("vdd1_opp");
 503 -               if (IS_ERR_VALUE(current_vdd1opp_no)) {
 504 -                       mutex_unlock(&dvfs_mutex);
 505 -                       return -ENODEV;
 506 -               }
 507                 sr_start_vddautocomap(SR1, current_vdd1opp_no);
 508         }
 509
 510 @@ -1008,9 +1197,13 @@
 511         mutex_lock(&dvfs_mutex);
 512
 513         current_vdd2opp_no = resource_get_level("vdd2_opp");
 514 +       if (IS_ERR_VALUE(current_vdd2opp_no)) {
 515 +               mutex_unlock(&dvfs_mutex);
 516 +               return -ENODEV;
 517 +       }
 518
 519         if (value == 0)
 520 -               sr_stop_vddautocomap(SR2);
 521 +               sr_stop_vddautocomap(SR2, current_vdd2opp_no);
 522         else
 523                 sr_start_vddautocomap(SR2, current_vdd2opp_no);
 524
 525 @@ -1028,23 +1221,87 @@
 526         .store = omap_sr_vdd2_autocomp_store,
 527  };
 528
 529 -static ssize_t omap_sr_opp1_efuse_show(struct kobject *kobj,
 530 +static ssize_t omap_sr_efuse_vdd1_show(struct kobject *kobj,
 531                                         struct kobj_attribute *attr,
 532                                         char *buf)
 533  {
 534 -       return sprintf(buf, "%08x\n%08x\n%08x\n%08x\n%08x\n", sr1.opp1_nvalue,
 535 +       return sprintf(buf, "%08x\n%08x\n%08x\n%08x\n%08x\n%08x\n%08x\n%08x\n%08x\n",
 536 +                                                       sr1.opp1_nvalue,
 537                                                         sr1.opp2_nvalue,
 538                                                         sr1.opp3_nvalue,
 539                                                         sr1.opp4_nvalue,
 540 -                                                       sr1.opp5_nvalue);
 541 +                                                       sr1.opp5_nvalue,
 542 +                                                       sr1.opp6_nvalue,
 543 +                                                       sr1.opp7_nvalue,
 544 +                                                       sr1.opp8_nvalue,
 545 +                                                       sr1.opp9_nvalue
 546 +                      );
 547 +}
 548 +
 549 +static struct kobj_attribute sr_efuse_vdd1 = {
 550 +       .attr = {
 551 +       .name = "efuse_vdd1",
 552 +       .mode = 0444,
 553 +       },
 554 +       .show = omap_sr_efuse_vdd1_show,
 555 +};
 556 +
 557 +static ssize_t omap_sr_vdd1_voltage_show(struct kobject *kobj,
 558 +                                       struct kobj_attribute *attr,
 559 +                                       char *buf)
 560 +{
 561 +       u32 prm_vp1_voltage;
 562 +       mutex_lock(&dvfs_mutex);
 563 +       prm_vp1_voltage = prm_read_mod_reg(OMAP3430_GR_MOD,
 564 +                                          OMAP3_PRM_VP1_VOLTAGE_OFFSET);
 565 +       mutex_unlock(&dvfs_mutex);
 566 +       return sprintf(buf,"%u\n",prm_vp1_voltage);
 567 +}
 568 +
 569 +static struct kobj_attribute sr_vdd1_voltage = {
 570 +       .attr = {
 571 +       .name = "sr_vdd1_voltage",
 572 +       .mode = 0444,
 573 +       },
 574 +       .show = omap_sr_vdd1_voltage_show,
 575 +};
 576 +
 577 +static ssize_t omap_sr_efuse_vdd2_show(struct kobject *kobj,
 578 +                                       struct kobj_attribute *attr,
 579 +                                       char *buf)
 580 +{
 581 +       return sprintf(buf, "%08x\n%08x\n%08x\n",       sr2.opp1_nvalue,
 582 +                                                       sr2.opp2_nvalue,
 583 +                                                       sr2.opp3_nvalue
 584 +                      );
 585 +}
 586 +
 587 +static struct kobj_attribute sr_efuse_vdd2 = {
 588 +       .attr = {
 589 +       .name = "efuse_vdd2",
 590 +       .mode = 0444,
 591 +       },
 592 +       .show = omap_sr_efuse_vdd2_show,
 593 +};
 594 +
 595 +static ssize_t omap_sr_vdd2_voltage_show(struct kobject *kobj,
 596 +                                       struct kobj_attribute *attr,
 597 +                                       char *buf)
 598 +{
 599 +       u32 prm_vp2_voltage;
 600 +       mutex_lock(&dvfs_mutex);
 601 +       prm_vp2_voltage = prm_read_mod_reg(OMAP3430_GR_MOD,
 602 +                                          OMAP3_PRM_VP2_VOLTAGE_OFFSET);
 603 +       mutex_unlock(&dvfs_mutex);
 604 +       return sprintf(buf,"%u\n",prm_vp2_voltage);
 605  }
 606
 607 -static struct kobj_attribute sr_efuse = {
 608 +static struct kobj_attribute sr_vdd2_voltage = {
 609         .attr = {
 610 -       .name = "Efuse",
 611 +       .name = "sr_vdd2_voltage",
 612         .mode = 0444,
 613         },
 614 -       .show = omap_sr_opp1_efuse_show,
 615 +       .show = omap_sr_vdd2_voltage_show,
 616  };
 617
 618  static int __init omap3_sr_init(void)
 619 @@ -1084,10 +1341,21 @@
 620         if (ret)
 621                 printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
 622
 623 -       ret = sysfs_create_file(power_kobj, &sr_efuse.attr);
 624 +       ret = sysfs_create_file(power_kobj, &sr_efuse_vdd1.attr);
 625         if (ret)
 626 -               printk(KERN_ERR "sysfs_create_file failed for OPP data: %d\n", ret);
 627 +               printk(KERN_ERR "sysfs_create_file failed for VDD1 efuse data: %d\n", ret);
 628
 629 +       ret = sysfs_create_file(power_kobj, &sr_vdd1_voltage.attr);
 630 +       if (ret)
 631 +               printk(KERN_ERR "sysfs_create_file failed for VDD1 voltage data: %d\n", ret);
 632 +
 633 +       ret = sysfs_create_file(power_kobj, &sr_efuse_vdd2.attr);
 634 +       if (ret)
 635 +               printk(KERN_ERR "sysfs_create_file failed for VDD2 efuse data: %d\n", ret);
 636 +
 637 +       ret = sysfs_create_file(power_kobj, &sr_vdd2_voltage.attr);
 638 +       if (ret)
 639 +               printk(KERN_ERR "sysfs_create_file failed for VDD2 voltage data: %d\n", ret);
 640         return 0;
 641  }
 642
 643 diff -urN kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.h kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.h
 644 --- kernel-power-2.6.28/arch/arm/mach-omap2/smartreflex.h       2011-10-11 13:51:21.441301622 +0100
 645 +++ kernel-power-2.6.28.SR/arch/arm/mach-omap2/smartreflex.h    2011-11-14 21:08:28.136636000 +0000
 646 @@ -63,7 +63,7 @@
 647
 648  /* PRM_VP1_VSTEPMAX */
 649  #define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX       (0x01F4 << 8)
 650 -#define PRM_VP1_VSTEPMAX_VSTEPMAX              (0x04 << 0)
 651 +#define PRM_VP1_VSTEPMAX_VSTEPMAX              (0x01 << 0)
 652
 653  /* PRM_VP1_VLIMITTO */
 654  #define PRM_VP1_VLIMITTO_VDDMAX                (0x3C << 24)
 655 @@ -240,7 +240,15 @@
 656                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
 657  #define PRCM_VDD1_OPP5         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 658                                         ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
 659 -#define PRCM_NO_VDD1_OPPS      5
 660 +#define PRCM_VDD1_OPP6         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 661 +                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x6))
 662 +#define PRCM_VDD1_OPP7         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 663 +                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x7))
 664 +#define PRCM_VDD1_OPP8         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 665 +                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x8))
 666 +#define PRCM_VDD1_OPP9         (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
 667 +                                       ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x9))
 668 +#define PRCM_NO_VDD1_OPPS      VDD1_OPP9
 669
 670
 671  /* VDD2 OPPs */
 672 @@ -254,7 +262,7 @@
 673  /* XXX: end remove/move */
 674
 675  /* SR_MAX_LOW_OPP: the highest of the "low OPPs", 1 and 2. */
 676 -#define SR_MAX_LOW_OPP         3
 677 +#define SR_MAX_LOW_OPP         VDD1_OPP2
 678
 679  /* XXX: find more appropriate place for these once DVFS is in place */
 680  extern u32 current_vdd1_opp;
 681 @@ -273,10 +281,10 @@
 682   */
 683  #ifdef CONFIG_OMAP_SMARTREFLEX
 684  void enable_smartreflex(int srid);
 685 -void disable_smartreflex(int srid);
 686 +void disable_smartreflex(int srid,u32 cur_opp_no);
 687  int sr_voltagescale_vcbypass(u32 t_opp, u32 c_opp, u8 t_vsel, u8 c_vsel);
 688  void sr_start_vddautocomap(int srid, u32 target_opp_no);
 689 -int sr_stop_vddautocomap(int srid);
 690 +int sr_stop_vddautocomap(int srid,u32 cur_opp_no);
 691  #else
 692  static inline void enable_smartreflex(int srid) {}
 693  static inline void disable_smartreflex(int srid) {}
 694 diff -urN kernel-power-2.6.28/arch/arm/plat-omap/include/mach/omap34xx.h kernel-power-2.6.28.SR/arch/arm/plat-omap/include/mach/omap34xx.h
 695 --- kernel-power-2.6.28/arch/arm/plat-omap/include/mach/omap34xx.h      2011-10-11 13:51:21.441301622 +0100
 696 +++ kernel-power-2.6.28.SR/arch/arm/plat-omap/include/mach/omap34xx.h   2011-10-22 15:52:18.063235000 +0100
 697 @@ -107,6 +107,14 @@
 698  #define VDD1_OPP3      0x3
 699  #define VDD1_OPP4      0x4
 700  #define VDD1_OPP5      0x5
 701 +#define VDD1_OPP6      0x6\r
 702 +#define VDD1_OPP7      0x7\r
 703 +#define VDD1_OPP8      0x8\r
 704 +#define VDD1_OPP9      0x9\r
 705 +#define VDD1_OPP10     0xA\r
 706 +#define VDD1_OPP11     0xB\r
 707 +#define VDD1_OPP12     0xC\r
 708 +#define VDD1_OPP13     0xD\r
 709
 710  /* VDD2 OPPS */
 711  #define VDD2_OPP1      0x1
 712 @@ -114,8 +122,7 @@
 713  #define VDD2_OPP3      0x3
 714
 715  #define MIN_VDD1_OPP   VDD1_OPP1
 716 -/*#define MAX_VDD1_OPP VDD1_OPP5*/
 717 -#define MAX_VDD1_OPP   15
 718 +#define MAX_VDD1_OPP   VDD1_OPP13
 719  #define MIN_VDD2_OPP   VDD2_OPP1
 720  #define MAX_VDD2_OPP   VDD2_OPP3
 721