2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 static struct musb *the_musb;
116 static struct musb_ctx ctx;
118 #ifndef CONFIG_MUSB_PIO_ONLY
119 static int __initdata use_dma = 1;
121 static int __initdata use_dma;
123 module_param(use_dma, bool, 0);
124 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
126 unsigned musb_debug = 0;
127 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
128 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
130 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
131 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
133 #define MUSB_VERSION "6.0"
135 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
137 #define MUSB_DRIVER_NAME "musb_hdrc"
138 const char musb_driver_name[] = MUSB_DRIVER_NAME;
140 MODULE_DESCRIPTION(DRIVER_INFO);
141 MODULE_AUTHOR(DRIVER_AUTHOR);
142 MODULE_LICENSE("GPL");
143 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
145 static inline int musb_verify_charger(void __iomem *addr)
149 /* Reset the transceiver */
150 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
151 r |= ISP1704_FUNC_CTRL_RESET;
152 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
155 /* Set normal mode */
156 r &= ~(ISP1704_FUNC_CTRL_RESET | (3 << ISP1704_FUNC_CTRL_OPMODE));
157 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
159 /* Clear the DP and DM pull-down bits */
160 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
161 r &= ~(ISP1704_OTG_CTRL_DP_PULLDOWN | ISP1704_OTG_CTRL_DM_PULLDOWN);
162 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
164 /* Enable strong pull-up on DP (1.5K) and reset */
165 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
166 r |= ISP1704_FUNC_CTRL_TERMSELECT | ISP1704_FUNC_CTRL_RESET;
167 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
170 /* Read the line state */
171 if (musb_ulpi_readb(addr, ISP1704_DEBUG)) {
172 /* Is it a charger or PS2 connection */
174 /* Enable weak pull-up resistor on DP */
175 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
176 r |= ISP1704_PWR_CTRL_DP_WKPU_EN;
177 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
179 /* Disable strong pull-up on DP (1.5K) */
180 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
181 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
182 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
184 /* Enable weak pull-down resistor on DM */
185 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
186 r |= ISP1704_OTG_CTRL_DM_PULLDOWN;
187 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
189 /* It's a charger if the line states are clear */
190 if (!(musb_ulpi_readb(addr, ISP1704_DEBUG)))
193 /* Disable weak pull-up resistor on DP */
194 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
195 r &= ~ISP1704_PWR_CTRL_DP_WKPU_EN;
196 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
200 /* Disable strong pull-up on DP (1.5K) */
201 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
202 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
203 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
209 /* Bad connections with the charger may lead into the transceiver
210 * thinking that a device was just connected. We can wait for 5 ms to
211 * ensure that these cases will generate SUSPEND interrupt and not
212 * RESET. Reading and writing to the transceiver may still cause
213 * RESET interrupts. We mask out RESET/RESUME interrupts to
216 static int check_charger;
217 static int musb_charger_detect(struct musb *musb)
219 unsigned long timeout;
226 /* Using ulpi with musb is quite tricky. The following code
227 * was written based on the ulpi application note.
229 * The order of reads and writes and quite important, don't
230 * change it unless you really know what you're doing
233 switch(musb->xceiv->state) {
234 case OTG_STATE_B_IDLE:
235 /* we always reset transceiver */
238 /* HACK: ULPI tends to get stuck when booting with
239 * the cable connected
241 r = musb_readb(musb->mregs, MUSB_DEVCTL);
242 if ((r & MUSB_DEVCTL_VBUS)
243 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
244 musb_save_ctx_and_suspend(&musb->g, 0);
245 musb_restore_ctx_and_resume(&musb->g);
246 if (musb->board && musb->board->set_pm_limits)
247 musb->board->set_pm_limits(
248 musb->controller, 1);
251 /* disable RESET and RESUME interrupts */
252 r = musb_readb(musb->mregs, MUSB_INTRUSBE);
253 r &= ~(MUSB_INTR_RESUME | MUSB_INTR_RESET);
254 musb_writeb(musb->mregs, MUSB_INTRUSBE, r);
256 if (musb->board && musb->board->xceiv_reset)
257 musb->board->xceiv_reset();
259 /* then we resume to sync with controller */
260 r = musb_readb(musb->mregs, MUSB_POWER);
261 musb_writeb(musb->mregs, MUSB_POWER,
262 r | MUSB_POWER_RESUME);
264 musb_writeb(musb->mregs, MUSB_POWER,
265 r & ~MUSB_POWER_RESUME);
267 /* now we set SW control bit in PWR_CTRL register */
268 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL,
269 ISP1704_PWR_CTRL_SWCTRL);
271 r = musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL);
272 r |= (ISP1704_PWR_CTRL_SWCTRL | ISP1704_PWR_CTRL_DPVSRC_EN);
274 /* and finally enable manual charger detection */
275 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
278 timeout = jiffies + msecs_to_jiffies(300);
279 while (!time_after(jiffies, timeout)) {
280 /* Check if there is a charger */
281 vdat = !!(musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL)
282 & ISP1704_PWR_CTRL_VDAT_DET);
287 vdat = musb_verify_charger(musb->mregs);
289 r &= ~ISP1704_PWR_CTRL_DPVSRC_EN;
291 /* Clear DPVSRC_EN, otherwise usb communication doesn't work */
292 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
301 /* REVISIT: This code works only with dedicated chargers!
302 * When support for HOST/HUB chargers is added, don't
307 otg_set_suspend(musb->xceiv, 1);
308 musb->is_charger = 1;
310 /* enable interrupts */
311 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
313 /* Make sure the communication starts normally */
314 r = musb_readb(musb->mregs, MUSB_POWER);
315 musb_writeb(musb->mregs, MUSB_POWER,
316 r | MUSB_POWER_RESUME);
318 musb_writeb(musb->mregs, MUSB_POWER,
319 r & ~MUSB_POWER_RESUME);
327 /*-------------------------------------------------------------------------*/
329 static inline struct musb *dev_to_musb(struct device *dev)
331 #ifdef CONFIG_USB_MUSB_HDRC_HCD
332 /* usbcore insists dev->driver_data is a "struct hcd *" */
333 return hcd_to_musb(dev_get_drvdata(dev));
335 return dev_get_drvdata(dev);
339 /*-------------------------------------------------------------------------*/
341 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
344 * Load an endpoint's FIFO
346 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
348 void __iomem *fifo = hw_ep->fifo;
352 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
353 'T', hw_ep->epnum, fifo, len, src);
355 /* we can't assume unaligned reads work */
356 if (likely((0x01 & (unsigned long) src) == 0)) {
359 /* best case is 32bit-aligned source address */
360 if ((0x02 & (unsigned long) src) == 0) {
362 writesl(fifo, src + index, len >> 2);
363 index += len & ~0x03;
366 musb_writew(fifo, 0, *(u16 *)&src[index]);
371 writesw(fifo, src + index, len >> 1);
372 index += len & ~0x01;
376 musb_writeb(fifo, 0, src[index]);
379 writesb(fifo, src, len);
384 * Unload an endpoint's FIFO
386 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
388 void __iomem *fifo = hw_ep->fifo;
390 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
391 'R', hw_ep->epnum, fifo, len, dst);
393 /* we can't assume unaligned writes work */
394 if (likely((0x01 & (unsigned long) dst) == 0)) {
397 /* best case is 32bit-aligned destination address */
398 if ((0x02 & (unsigned long) dst) == 0) {
400 readsl(fifo, dst, len >> 2);
404 *(u16 *)&dst[index] = musb_readw(fifo, 0);
409 readsw(fifo, dst, len >> 1);
414 dst[index] = musb_readb(fifo, 0);
417 readsb(fifo, dst, len);
421 #endif /* normal PIO */
424 /*-------------------------------------------------------------------------*/
426 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
427 static const u8 musb_test_packet[53] = {
428 /* implicit SYNC then DATA0 to start */
431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
433 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
435 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
436 /* JJJJJJJKKKKKKK x8 */
437 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
439 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
440 /* JKKKKKKK x10, JK */
441 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
443 /* implicit CRC16 then EOP to end */
446 void musb_load_testpacket(struct musb *musb)
448 void __iomem *regs = musb->endpoints[0].regs;
450 musb_ep_select(musb->mregs, 0);
451 musb_write_fifo(musb->control_ep,
452 sizeof(musb_test_packet), musb_test_packet);
453 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
456 /*-------------------------------------------------------------------------*/
458 const char *otg_state_string(struct musb *musb)
460 switch (musb->xceiv->state) {
461 case OTG_STATE_A_IDLE: return "a_idle";
462 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
463 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
464 case OTG_STATE_A_HOST: return "a_host";
465 case OTG_STATE_A_SUSPEND: return "a_suspend";
466 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
467 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
468 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
469 case OTG_STATE_B_IDLE: return "b_idle";
470 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
471 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
472 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
473 case OTG_STATE_B_HOST: return "b_host";
474 default: return "UNDEFINED";
478 #ifdef CONFIG_USB_MUSB_OTG
481 * See also USB_OTG_1-3.pdf 6.6.5 Timers
482 * REVISIT: Are the other timers done in the hardware?
484 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
487 * Handles OTG hnp timeouts, such as b_ase0_brst
489 void musb_otg_timer_func(unsigned long data)
491 struct musb *musb = (struct musb *)data;
494 spin_lock_irqsave(&musb->lock, flags);
495 switch (musb->xceiv->state) {
496 case OTG_STATE_B_WAIT_ACON:
497 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
498 musb_g_disconnect(musb);
499 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
502 case OTG_STATE_A_WAIT_BCON:
503 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
507 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
509 musb->ignore_disconnect = 0;
510 spin_unlock_irqrestore(&musb->lock, flags);
513 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
516 * Stops the B-device HNP state. Caller must take care of locking.
518 void musb_hnp_stop(struct musb *musb)
520 struct usb_hcd *hcd = musb_to_hcd(musb);
521 void __iomem *mbase = musb->mregs;
524 switch (musb->xceiv->state) {
525 case OTG_STATE_A_PERIPHERAL:
526 case OTG_STATE_A_WAIT_VFALL:
527 case OTG_STATE_A_WAIT_BCON:
528 DBG(1, "HNP: Switching back to A-host\n");
529 musb_g_disconnect(musb);
530 musb->xceiv->state = OTG_STATE_A_IDLE;
534 case OTG_STATE_B_HOST:
535 DBG(1, "HNP: Disabling HR\n");
536 hcd->self.is_b_host = 0;
537 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
539 reg = musb_readb(mbase, MUSB_POWER);
540 reg |= MUSB_POWER_SUSPENDM;
541 musb_writeb(mbase, MUSB_POWER, reg);
542 /* REVISIT: Start SESSION_REQUEST here? */
545 DBG(1, "HNP: Stopping in unknown state %s\n",
546 otg_state_string(musb));
550 * When returning to A state after HNP, avoid hub_port_rebounce(),
551 * which cause occasional OPT A "Did not receive reset after connect"
554 musb->port1_status &=
555 ~(1 << USB_PORT_FEAT_C_CONNECTION);
561 * Interrupt Service Routine to record USB "global" interrupts.
562 * Since these do not happen often and signify things of
563 * paramount importance, it seems OK to check them individually;
564 * the order of the tests is specified in the manual
566 * @param musb instance pointer
567 * @param int_usb register contents
572 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
575 irqreturn_t handled = IRQ_NONE;
576 void __iomem *mbase = musb->mregs;
579 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
582 /* in host mode, the peripheral may issue remote wakeup.
583 * in peripheral mode, the host may resume the link.
584 * spurious RESUME irqs happen too, paired with SUSPEND.
586 if (int_usb & MUSB_INTR_RESUME) {
587 handled = IRQ_HANDLED;
588 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
590 if (devctl & MUSB_DEVCTL_HM) {
591 #ifdef CONFIG_USB_MUSB_HDRC_HCD
592 switch (musb->xceiv->state) {
593 case OTG_STATE_A_SUSPEND:
594 /* remote wakeup? later, GetPortStatus
595 * will stop RESUME signaling
598 if (power & MUSB_POWER_SUSPENDM) {
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
601 DBG(2, "Spurious SUSPENDM\n");
605 power &= ~MUSB_POWER_SUSPENDM;
606 musb_writeb(mbase, MUSB_POWER,
607 power | MUSB_POWER_RESUME);
609 musb->port1_status |=
610 (USB_PORT_STAT_C_SUSPEND << 16)
611 | MUSB_PORT_STAT_RESUME;
612 musb->rh_timer = jiffies
613 + msecs_to_jiffies(20);
615 musb->xceiv->state = OTG_STATE_A_HOST;
617 usb_hcd_resume_root_hub(musb_to_hcd(musb));
619 case OTG_STATE_B_WAIT_ACON:
620 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
625 WARNING("bogus %s RESUME (%s)\n",
627 otg_state_string(musb));
631 switch (musb->xceiv->state) {
632 #ifdef CONFIG_USB_MUSB_HDRC_HCD
633 case OTG_STATE_A_SUSPEND:
634 /* possibly DISCONNECT is upcoming */
635 musb->xceiv->state = OTG_STATE_A_HOST;
636 usb_hcd_resume_root_hub(musb_to_hcd(musb));
639 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
640 case OTG_STATE_B_WAIT_ACON:
641 case OTG_STATE_B_PERIPHERAL:
642 /* disconnect while suspended? we may
643 * not get a disconnect irq...
645 if ((devctl & MUSB_DEVCTL_VBUS)
646 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
648 musb->int_usb |= MUSB_INTR_DISCONNECT;
649 musb->int_usb &= ~MUSB_INTR_SUSPEND;
654 case OTG_STATE_B_IDLE:
655 musb->int_usb &= ~MUSB_INTR_SUSPEND;
659 WARNING("bogus %s RESUME (%s)\n",
661 otg_state_string(musb));
666 #ifdef CONFIG_USB_MUSB_HDRC_HCD
667 /* see manual for the order of the tests */
668 if (int_usb & MUSB_INTR_SESSREQ) {
669 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
671 /* IRQ arrives from ID pin sense or (later, if VBUS power
672 * is removed) SRP. responses are time critical:
673 * - turn on VBUS (with silicon-specific mechanism)
674 * - go through A_WAIT_VRISE
675 * - ... to A_WAIT_BCON.
676 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
677 * NOTE : Spurious SESS_REQ int's detected, which should
678 * be discarded silently.
680 if ((devctl & MUSB_DEVCTL_VBUS)
681 && !(devctl & MUSB_DEVCTL_BDEVICE)) {
682 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
683 musb->ep0_stage = MUSB_EP0_START;
684 musb->xceiv->state = OTG_STATE_A_IDLE;
686 musb_set_vbus(musb, 1);
688 DBG(5,"discarding SESSREQ INT: VBUS < SessEnd\n");
691 handled = IRQ_HANDLED;
694 if (int_usb & MUSB_INTR_VBUSERROR) {
697 /* During connection as an A-Device, we may see a short
698 * current spikes causing voltage drop, because of cable
699 * and peripheral capacitance combined with vbus draw.
700 * (So: less common with truly self-powered devices, where
701 * vbus doesn't act like a power supply.)
703 * Such spikes are short; usually less than ~500 usec, max
704 * of ~2 msec. That is, they're not sustained overcurrent
705 * errors, though they're reported using VBUSERROR irqs.
707 * Workarounds: (a) hardware: use self powered devices.
708 * (b) software: ignore non-repeated VBUS errors.
710 * REVISIT: do delays from lots of DEBUG_KERNEL checks
711 * make trouble here, keeping VBUS < 4.4V ?
713 switch (musb->xceiv->state) {
714 case OTG_STATE_A_HOST:
715 /* recovery is dicey once we've gotten past the
716 * initial stages of enumeration, but if VBUS
717 * stayed ok at the other end of the link, and
718 * another reset is due (at least for high speed,
719 * to redo the chirp etc), it might work OK...
721 case OTG_STATE_A_WAIT_BCON:
722 case OTG_STATE_A_WAIT_VRISE:
723 if (musb->vbuserr_retry) {
724 musb->vbuserr_retry--;
726 devctl |= MUSB_DEVCTL_SESSION;
727 musb_writeb(mbase, MUSB_DEVCTL, devctl);
729 musb->port1_status |=
730 (1 << USB_PORT_FEAT_OVER_CURRENT)
731 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
738 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
739 otg_state_string(musb),
742 switch (devctl & MUSB_DEVCTL_VBUS) {
743 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
744 s = "<SessEnd"; break;
745 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
746 s = "<AValid"; break;
747 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
748 s = "<VBusValid"; break;
749 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
753 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
756 /* go through A_WAIT_VFALL then start a new session */
758 musb_set_vbus(musb, 0);
759 handled = IRQ_HANDLED;
762 if (int_usb & MUSB_INTR_SUSPEND) {
763 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
764 otg_state_string(musb), devctl, power);
765 handled = IRQ_HANDLED;
767 switch (musb->xceiv->state) {
768 #ifdef CONFIG_USB_MUSB_OTG
769 case OTG_STATE_A_PERIPHERAL:
771 * We cannot stop HNP here, devctl BDEVICE might be
776 case OTG_STATE_B_IDLE:
777 if (!musb->is_active)
779 case OTG_STATE_B_PERIPHERAL:
780 musb_g_suspend(musb);
781 musb->is_active = is_otg_enabled(musb)
782 && musb->xceiv->gadget->b_hnp_enable;
783 if (musb->is_active) {
784 #ifdef CONFIG_USB_MUSB_OTG
785 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
786 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
787 musb_otg_timer.data = (unsigned long)musb;
788 mod_timer(&musb_otg_timer, jiffies
789 + msecs_to_jiffies(TB_ASE0_BRST));
793 case OTG_STATE_A_WAIT_BCON:
794 if (musb->a_wait_bcon != 0)
795 musb_platform_try_idle(musb, jiffies
796 + msecs_to_jiffies(musb->a_wait_bcon));
798 case OTG_STATE_A_HOST:
799 musb->xceiv->state = OTG_STATE_A_SUSPEND;
800 musb->is_active = is_otg_enabled(musb)
801 && musb->xceiv->host->b_hnp_enable;
803 case OTG_STATE_B_HOST:
804 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
805 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
808 /* "should not happen" */
814 if (int_usb & MUSB_INTR_CONNECT) {
815 struct usb_hcd *hcd = musb_to_hcd(musb);
817 handled = IRQ_HANDLED;
819 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
821 musb->ep0_stage = MUSB_EP0_START;
823 #ifdef CONFIG_USB_MUSB_OTG
824 /* flush endpoints when transitioning from Device Mode */
825 if (is_peripheral_active(musb)) {
826 /* REVISIT HNP; just force disconnect */
828 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
829 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
830 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
832 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
833 |USB_PORT_STAT_HIGH_SPEED
834 |USB_PORT_STAT_ENABLE
836 musb->port1_status |= USB_PORT_STAT_CONNECTION
837 |(USB_PORT_STAT_C_CONNECTION << 16);
839 /* high vs full speed is just a guess until after reset */
840 if (devctl & MUSB_DEVCTL_LSDEV)
841 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
844 usb_hcd_poll_rh_status(hcd);
846 usb_hcd_resume_root_hub(hcd);
850 /* indicate new connection to OTG machine */
851 switch (musb->xceiv->state) {
852 case OTG_STATE_B_PERIPHERAL:
853 if (int_usb & MUSB_INTR_SUSPEND) {
854 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
855 musb->xceiv->state = OTG_STATE_B_HOST;
856 hcd->self.is_b_host = 1;
857 int_usb &= ~MUSB_INTR_SUSPEND;
859 DBG(1, "CONNECT as b_peripheral???\n");
861 case OTG_STATE_B_WAIT_ACON:
862 DBG(1, "HNP: Waiting to switch to b_host state\n");
863 musb->xceiv->state = OTG_STATE_B_HOST;
864 hcd->self.is_b_host = 1;
867 if ((devctl & MUSB_DEVCTL_VBUS)
868 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
869 musb->xceiv->state = OTG_STATE_A_HOST;
870 hcd->self.is_b_host = 0;
874 DBG(1, "CONNECT (%s) devctl %02x\n",
875 otg_state_string(musb), devctl);
877 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
879 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
880 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
881 otg_state_string(musb),
882 MUSB_MODE(musb), devctl);
883 handled = IRQ_HANDLED;
885 switch (musb->xceiv->state) {
886 #ifdef CONFIG_USB_MUSB_HDRC_HCD
887 case OTG_STATE_A_HOST:
888 case OTG_STATE_A_SUSPEND:
889 usb_hcd_resume_root_hub(musb_to_hcd(musb));
890 musb_root_disconnect(musb);
891 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
892 musb_platform_try_idle(musb, jiffies
893 + msecs_to_jiffies(musb->a_wait_bcon));
896 #ifdef CONFIG_USB_MUSB_OTG
897 case OTG_STATE_B_HOST:
900 case OTG_STATE_A_PERIPHERAL:
902 musb_root_disconnect(musb);
904 case OTG_STATE_B_WAIT_ACON:
907 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
908 case OTG_STATE_B_PERIPHERAL:
909 case OTG_STATE_B_IDLE:
910 /* Workaround for a problem of Vbus quickly dropping
911 * during Certification tests.
913 * Undo the workaround on disconnect
916 /* Disable suspend so we can write to ULPI */
917 r = musb_readb(musb->mregs, MUSB_POWER);
918 musb_writeb(musb->mregs, MUSB_POWER,
919 r & ~MUSB_POWER_ENSUSPEND);
920 musb_ulpi_writeb(musb->mregs,
921 ISP1704_USB_INTFALL, 0x1f);
922 musb_ulpi_writeb(musb->mregs,
923 ISP1704_USB_INTRISE, 0x1f);
924 musb_writeb(musb->mregs, MUSB_POWER,
925 r | MUSB_POWER_ENSUSPEND);
927 musb_g_disconnect(musb);
928 /** UGLY UGLY HACK: Windows problems with multiple
931 * This is necessary to notify gadget driver this was
932 * a physical disconnection and not only a port reset.
934 if (musb->gadget_driver->vbus_disconnect)
935 musb->gadget_driver->vbus_disconnect(&musb->g);
940 WARNING("unhandled DISCONNECT transition (%s)\n",
941 otg_state_string(musb));
946 /* mentor saves a bit: bus reset and babble share the same irq.
947 * only host sees babble; only peripheral sees bus reset.
949 if (int_usb & MUSB_INTR_RESET) {
950 handled = IRQ_HANDLED;
951 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
953 * Looks like non-HS BABBLE can be ignored, but
954 * HS BABBLE is an error condition. For HS the solution
955 * is to avoid babble in the first place and fix what
956 * caused BABBLE. When HS BABBLE happens we can only
959 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
960 DBG(1, "BABBLE devctl: %02x\n", devctl);
962 ERR("Stopping host session -- babble\n");
963 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
965 } else if (is_peripheral_capable()) {
966 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
967 switch (musb->xceiv->state) {
968 #ifdef CONFIG_USB_OTG
969 case OTG_STATE_A_SUSPEND:
970 /* We need to ignore disconnect on suspend
971 * otherwise tusb 2.0 won't reconnect after a
972 * power cycle, which breaks otg compliance.
974 musb->ignore_disconnect = 1;
977 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
978 DBG(1, "HNP: Setting timer as %s\n",
979 otg_state_string(musb));
980 musb_otg_timer.data = (unsigned long)musb;
981 mod_timer(&musb_otg_timer, jiffies
982 + msecs_to_jiffies(100));
984 case OTG_STATE_A_PERIPHERAL:
987 case OTG_STATE_B_WAIT_ACON:
988 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
989 otg_state_string(musb));
990 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
994 case OTG_STATE_B_IDLE:
995 /* Workaround the charger detection problems */
996 if ((devctl & MUSB_DEVCTL_VBUS)
997 != (3 << MUSB_DEVCTL_VBUS_SHIFT))
1001 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1003 case OTG_STATE_B_PERIPHERAL:
1004 /* Workaround for a problem of Vbus quickly dropping
1005 * during Certification tests.
1007 * The guess is that vbus drops due to the circuitry
1008 * for overcurrent protection and that makes transceiver
1009 * think VBUS is not valid anymore. Transceiver will
1010 * then send an RXCMD to PHY which will cause it to
1011 * disconnect from the bus even though we disable the
1014 musb_ulpi_writeb(musb->mregs,
1015 ISP1704_USB_INTFALL, 0x1d);
1016 musb_ulpi_writeb(musb->mregs,
1017 ISP1704_USB_INTRISE, 0x1d);
1022 DBG(1, "Unhandled BUS RESET as %s\n",
1023 otg_state_string(musb));
1029 /* REVISIT ... this would be for multiplexing periodic endpoints, or
1030 * supporting transfer phasing to prevent exceeding ISO bandwidth
1031 * limits of a given frame or microframe.
1033 * It's not needed for peripheral side, which dedicates endpoints;
1034 * though it _might_ use SOF irqs for other purposes.
1036 * And it's not currently needed for host side, which also dedicates
1037 * endpoints, relies on TX/RX interval registers, and isn't claimed
1038 * to support ISO transfers yet.
1040 if (int_usb & MUSB_INTR_SOF) {
1041 void __iomem *mbase = musb->mregs;
1042 struct musb_hw_ep *ep;
1046 DBG(6, "START_OF_FRAME\n");
1047 handled = IRQ_HANDLED;
1049 /* start any periodic Tx transfers waiting for current frame */
1050 frame = musb_readw(mbase, MUSB_FRAME);
1051 ep = musb->endpoints;
1052 for (epnum = 1; (epnum < musb->nr_endpoints)
1053 && (musb->epmask >= (1 << epnum));
1056 * FIXME handle framecounter wraps (12 bits)
1057 * eliminate duplicated StartUrb logic
1059 if (ep->dwWaitFrame >= frame) {
1060 ep->dwWaitFrame = 0;
1061 pr_debug("SOF --> periodic TX%s on %d\n",
1062 ep->tx_channel ? " DMA" : "",
1064 if (!ep->tx_channel)
1065 musb_h_tx_start(musb, epnum);
1067 cppi_hostdma_start(musb, epnum);
1069 } /* end of for loop */
1073 schedule_work(&musb->irq_work);
1078 /*-------------------------------------------------------------------------*/
1081 * Program the HDRC to start (enable interrupts, dma, etc.).
1083 void musb_start(struct musb *musb)
1085 void __iomem *regs = musb->mregs;
1086 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1089 DBG(2, "<== devctl %02x\n", devctl);
1091 /* Ensure the clocks are on */
1092 if (musb->set_clock)
1093 musb->set_clock(musb->clock, 1);
1095 clk_enable(musb->clock);
1097 /* Set INT enable registers, enable interrupts */
1098 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
1099 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
1100 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1102 musb_writeb(regs, MUSB_TESTMODE, 0);
1104 power = MUSB_POWER_ISOUPDATE | MUSB_POWER_SOFTCONN
1105 | MUSB_POWER_HSENAB;
1107 /* ENSUSPEND wedges tusb */
1109 power |= MUSB_POWER_ENSUSPEND;
1111 /* put into basic highspeed mode and start session */
1112 musb_writeb(regs, MUSB_POWER, power);
1114 musb->is_active = 0;
1115 devctl = musb_readb(regs, MUSB_DEVCTL);
1116 devctl &= ~MUSB_DEVCTL_SESSION;
1118 if (is_otg_enabled(musb)) {
1119 /* session started after:
1120 * (a) ID-grounded irq, host mode;
1121 * (b) vbus present/connect IRQ, peripheral mode;
1122 * (c) peripheral initiates, using SRP
1124 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1125 musb->is_active = 1;
1127 devctl |= MUSB_DEVCTL_SESSION;
1129 } else if (is_host_enabled(musb)) {
1130 /* assume ID pin is hard-wired to ground */
1131 devctl |= MUSB_DEVCTL_SESSION;
1133 } else /* peripheral is enabled */ {
1134 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1135 musb->is_active = 1;
1137 musb_platform_enable(musb);
1138 musb_writeb(regs, MUSB_DEVCTL, devctl);
1142 static void musb_generic_disable(struct musb *musb)
1144 void __iomem *mbase = musb->mregs;
1147 /* Clocks need to be turned on with OFF-mode */
1148 if (musb->set_clock)
1149 musb->set_clock(musb->clock, 1);
1151 clk_enable(musb->clock);
1153 /* disable interrupts */
1154 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1155 musb_writew(mbase, MUSB_INTRTXE, 0);
1156 musb_writew(mbase, MUSB_INTRRXE, 0);
1159 musb_writeb(mbase, MUSB_DEVCTL, 0);
1161 /* flush pending interrupts */
1162 temp = musb_readb(mbase, MUSB_INTRUSB);
1163 temp = musb_readw(mbase, MUSB_INTRTX);
1164 temp = musb_readw(mbase, MUSB_INTRRX);
1168 void musb_emergency_stop(void)
1173 musb_stop(the_musb);
1175 EXPORT_SYMBOL_GPL(musb_emergency_stop);
1178 * Make the HDRC stop (disable interrupts, etc.);
1179 * reversible by musb_start
1180 * called on gadget driver unregister
1181 * with controller locked, irqs blocked
1182 * acts as a NOP unless some role activated the hardware
1184 void musb_stop(struct musb *musb)
1186 /* stop IRQs, timers, ... */
1187 musb_platform_disable(musb);
1188 musb_generic_disable(musb);
1189 DBG(3, "HDRC disabled\n");
1192 * - mark host and/or peripheral drivers unusable/inactive
1193 * - disable DMA (and enable it in HdrcStart)
1194 * - make sure we can musb_start() after musb_stop(); with
1195 * OTG mode, gadget driver module rmmod/modprobe cycles that
1198 musb_platform_try_idle(musb, 0);
1201 static void musb_shutdown(struct platform_device *pdev)
1203 struct musb *musb = dev_to_musb(&pdev->dev);
1204 unsigned long flags;
1206 spin_lock_irqsave(&musb->lock, flags);
1207 musb_platform_disable(musb);
1208 musb_generic_disable(musb);
1210 clk_put(musb->clock);
1213 spin_unlock_irqrestore(&musb->lock, flags);
1215 /* FIXME power down */
1219 /*-------------------------------------------------------------------------*/
1222 * The silicon either has hard-wired endpoint configurations, or else
1223 * "dynamic fifo" sizing. The driver has support for both, though at this
1224 * writing only the dynamic sizing is very well tested. Since we switched
1225 * away from compile-time hardware parameters, we can no longer rely on
1226 * dead code elimination to leave only the relevant one in the object file.
1228 * We don't currently use dynamic fifo setup capability to do anything
1229 * more than selecting one of a bunch of predefined configurations.
1231 #if defined(CONFIG_USB_TUSB6010) || \
1232 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1233 static ushort __initdata fifo_mode = 4;
1235 static ushort __initdata fifo_mode = 2;
1238 /* "modprobe ... fifo_mode=1" etc */
1239 module_param(fifo_mode, ushort, 0);
1240 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1243 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1244 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1248 enum fifo_style style;
1254 * tables defining fifo_mode values. define more if you like.
1255 * for host side, make sure both halves of ep1 are set up.
1258 /* mode 0 - fits in 2KB */
1259 static struct fifo_cfg __initdata mode_0_cfg[] = {
1260 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1261 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1262 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1263 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1264 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1267 /* mode 1 - fits in 4KB */
1268 static struct fifo_cfg __initdata mode_1_cfg[] = {
1269 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1270 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1271 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1272 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1273 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1276 /* mode 2 - fits in 4KB */
1277 static struct fifo_cfg __initdata mode_2_cfg[] = {
1278 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1279 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1280 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1281 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1282 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1283 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1286 /* mode 3 - fits in 4KB */
1287 static struct fifo_cfg __initdata mode_3_cfg[] = {
1288 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1289 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1290 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1291 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1292 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1293 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1296 /* mode 4 - fits in 16KB */
1297 static struct fifo_cfg __initdata mode_4_cfg[] = {
1298 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1299 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1300 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1301 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1302 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1303 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1304 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1305 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1306 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1307 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1308 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1309 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1310 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1311 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1312 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1313 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 64, },
1314 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1315 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 64, },
1316 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1317 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1318 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1319 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 256, },
1320 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1321 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 256, },
1322 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 256, },
1323 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 4096, },
1324 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1325 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1328 /* mode 5 - fits in 16KB */
1329 static struct fifo_cfg __initdata mode_5_cfg[] = {
1330 /* phonet or mass storage */
1331 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1332 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1335 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1336 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1339 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1340 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1343 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1344 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1345 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 16, },
1348 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1349 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1350 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 16, },
1353 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1354 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1356 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1357 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1359 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1360 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1362 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1363 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1367 * configure a fifo; for non-shared endpoints, this may be called
1368 * once for a tx fifo and once for an rx fifo.
1370 * returns negative errno or offset for next fifo.
1373 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1374 const struct fifo_cfg *cfg, u16 offset)
1376 void __iomem *mbase = musb->mregs;
1378 u16 maxpacket = cfg->maxpacket;
1379 u16 c_off = offset >> 3;
1382 /* expect hw_ep has already been zero-initialized */
1384 size = ffs(max(maxpacket, (u16) 8)) - 1;
1385 maxpacket = 1 << size;
1388 if (cfg->mode == BUF_DOUBLE) {
1389 if ((offset + (maxpacket << 1)) >
1390 (1 << (musb->config->ram_bits + 2)))
1392 c_size |= MUSB_FIFOSZ_DPB;
1394 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1398 /* configure the FIFO */
1399 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1401 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1402 /* EP0 reserved endpoint for control, bidirectional;
1403 * EP1 reserved for bulk, two unidirection halves.
1405 if (hw_ep->epnum == 1)
1406 musb->bulk_ep = hw_ep;
1407 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1409 switch (cfg->style) {
1411 musb_write_txfifosz(mbase, c_size);
1412 musb_write_txfifoadd(mbase, c_off);
1413 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1414 hw_ep->max_packet_sz_tx = maxpacket;
1415 ctx.txfifosz[hw_ep->epnum] = c_size;
1416 ctx.txfifoadd[hw_ep->epnum] = c_off;
1419 musb_write_rxfifosz(mbase, c_size);
1420 musb_write_rxfifoadd(mbase, c_off);
1421 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1422 hw_ep->max_packet_sz_rx = maxpacket;
1423 ctx.rxfifosz[hw_ep->epnum] = c_size;
1424 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1427 musb_write_txfifosz(mbase, c_size);
1428 musb_write_txfifoadd(mbase, c_off);
1429 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1430 hw_ep->max_packet_sz_rx = maxpacket;
1432 musb_write_rxfifosz(mbase, c_size);
1433 musb_write_rxfifoadd(mbase, c_off);
1434 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1435 hw_ep->max_packet_sz_tx = maxpacket;
1437 /* Save the context of endpoints. */
1438 ctx.rxfifosz[hw_ep->epnum] = c_size;
1439 ctx.txfifosz[hw_ep->epnum] = c_size;
1440 ctx.txfifoadd[hw_ep->epnum] = c_off;
1441 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1443 hw_ep->is_shared_fifo = true;
1447 /* NOTE rx and tx endpoint irqs aren't managed separately,
1448 * which happens to be ok
1450 musb->epmask |= (1 << hw_ep->epnum);
1452 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1455 static struct fifo_cfg __initdata ep0_cfg = {
1456 .style = FIFO_RXTX, .maxpacket = 64,
1459 static int __init ep_config_from_table(struct musb *musb)
1461 const struct fifo_cfg *cfg;
1464 struct musb_hw_ep *hw_ep = musb->endpoints;
1466 if (machine_is_nokia_rx51())
1469 switch (fifo_mode) {
1475 n = ARRAY_SIZE(mode_0_cfg);
1479 n = ARRAY_SIZE(mode_1_cfg);
1483 n = ARRAY_SIZE(mode_2_cfg);
1487 n = ARRAY_SIZE(mode_3_cfg);
1491 n = ARRAY_SIZE(mode_4_cfg);
1495 n = ARRAY_SIZE(mode_5_cfg);
1499 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1500 musb_driver_name, fifo_mode);
1503 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1504 /* assert(offset > 0) */
1506 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1507 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1510 for (i = 0; i < n; i++) {
1511 u8 epn = cfg->hw_ep_num;
1513 if (epn >= musb->config->num_eps) {
1514 pr_debug("%s: invalid ep %d\n",
1515 musb_driver_name, epn);
1518 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1520 pr_debug("%s: mem overrun, ep %d\n",
1521 musb_driver_name, epn);
1525 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1528 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1530 n + 1, musb->config->num_eps * 2 - 1,
1531 offset, (1 << (musb->config->ram_bits + 2)));
1533 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1534 if (!musb->bulk_ep) {
1535 pr_debug("%s: missing bulk\n", musb_driver_name);
1545 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1546 * @param musb the controller
1548 static int __init ep_config_from_hw(struct musb *musb)
1551 struct musb_hw_ep *hw_ep;
1552 void *mbase = musb->mregs;
1555 DBG(2, "<== static silicon ep config\n");
1557 /* FIXME pick up ep0 maxpacket size */
1559 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1560 musb_ep_select(mbase, epnum);
1561 hw_ep = musb->endpoints + epnum;
1563 ret = musb_read_fifosize(musb, hw_ep, epnum);
1567 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1569 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1570 /* pick an RX/TX endpoint for bulk */
1571 if (hw_ep->max_packet_sz_tx < 512
1572 || hw_ep->max_packet_sz_rx < 512)
1575 /* REVISIT: this algorithm is lazy, we should at least
1576 * try to pick a double buffered endpoint.
1580 musb->bulk_ep = hw_ep;
1584 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1585 if (!musb->bulk_ep) {
1586 pr_debug("%s: missing bulk\n", musb_driver_name);
1594 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1596 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1597 * configure endpoints, or take their config from silicon
1599 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1606 u16 hwvers, rev_major, rev_minor;
1607 char aInfo[78], aRevision[32], aDate[12];
1608 void __iomem *mbase = musb->mregs;
1612 /* log core options (read using indexed model) */
1613 musb_ep_select(mbase, 0);
1614 reg = musb_read_configdata(mbase);
1616 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1617 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1618 strcat(aInfo, ", dyn FIFOs");
1619 if (reg & MUSB_CONFIGDATA_MPRXE) {
1620 strcat(aInfo, ", bulk combine");
1622 musb->bulk_combine = true;
1624 strcat(aInfo, " (X)"); /* no driver support */
1627 if (reg & MUSB_CONFIGDATA_MPTXE) {
1628 strcat(aInfo, ", bulk split");
1630 musb->bulk_split = true;
1632 strcat(aInfo, " (X)"); /* no driver support */
1635 if (reg & MUSB_CONFIGDATA_HBRXE) {
1636 strcat(aInfo, ", HB-ISO Rx");
1637 strcat(aInfo, " (X)"); /* no driver support */
1639 if (reg & MUSB_CONFIGDATA_HBTXE) {
1640 strcat(aInfo, ", HB-ISO Tx");
1641 strcat(aInfo, " (X)"); /* no driver support */
1643 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1644 strcat(aInfo, ", SoftConn");
1646 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1647 musb_driver_name, reg, aInfo);
1650 data = musb_readl(mbase, 0x404);
1651 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1652 (data >> 16) & 0xff, (data >> 24) & 0xff);
1653 /* FIXME ID2 and ID3 are unused */
1654 data = musb_readl(mbase, 0x408);
1655 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1656 data = musb_readl(mbase, 0x40c);
1657 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1658 reg = musb_readb(mbase, 0x400);
1659 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1663 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1664 musb->is_multipoint = 1;
1667 musb->is_multipoint = 0;
1669 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1670 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1672 "%s: kernel must blacklist external hubs\n",
1678 /* log release info */
1679 hwvers = musb_read_hwvers(mbase);
1680 rev_major = (hwvers >> 10) & 0x1f;
1681 rev_minor = hwvers & 0x3ff;
1682 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1683 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1684 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1685 musb_driver_name, type, aRevision, aDate);
1688 musb_configure_ep0(musb);
1690 /* discover endpoint configuration */
1691 musb->nr_endpoints = 1;
1694 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1695 if (musb->config->dyn_fifo)
1696 status = ep_config_from_table(musb);
1698 ERR("reconfigure software for Dynamic FIFOs\n");
1702 if (!musb->config->dyn_fifo)
1703 status = ep_config_from_hw(musb);
1705 ERR("reconfigure software for static FIFOs\n");
1713 /* finish init, and print endpoint config */
1714 for (i = 0; i < musb->nr_endpoints; i++) {
1715 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1717 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1718 #ifdef CONFIG_USB_TUSB6010
1719 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1720 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1721 hw_ep->fifo_sync_va =
1722 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1725 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1727 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1730 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1731 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1732 /* init list of in and out qhs */
1733 INIT_LIST_HEAD(&hw_ep->in_list);
1734 INIT_LIST_HEAD(&hw_ep->out_list);
1735 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1736 hw_ep->rx_reinit = 1;
1737 hw_ep->tx_reinit = 1;
1740 if (hw_ep->max_packet_sz_tx) {
1742 "%s: hw_ep %d%s, %smax %d\n",
1743 musb_driver_name, i,
1744 hw_ep->is_shared_fifo ? "shared" : "tx",
1745 hw_ep->tx_double_buffered
1746 ? "doublebuffer, " : "",
1747 hw_ep->max_packet_sz_tx);
1749 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1751 "%s: hw_ep %d%s, %smax %d\n",
1752 musb_driver_name, i,
1754 hw_ep->rx_double_buffered
1755 ? "doublebuffer, " : "",
1756 hw_ep->max_packet_sz_rx);
1758 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1759 DBG(1, "hw_ep %d not configured\n", i);
1765 /*-------------------------------------------------------------------------*/
1767 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1769 static irqreturn_t generic_interrupt(int irq, void *__hci)
1771 unsigned long flags;
1772 irqreturn_t retval = IRQ_NONE;
1773 struct musb *musb = __hci;
1775 spin_lock_irqsave(&musb->lock, flags);
1777 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1778 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1779 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1781 while (musb->int_usb || musb->int_tx || musb->int_rx)
1782 retval |= musb_interrupt(musb);
1784 spin_unlock_irqrestore(&musb->lock, flags);
1786 /* REVISIT we sometimes get spurious IRQs on g_ep0
1789 if (retval != IRQ_HANDLED)
1790 DBG(5, "spurious?\n");
1796 #define generic_interrupt NULL
1800 * handle all the irqs defined by the HDRC core. for now we expect: other
1801 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1802 * will be assigned, and the irq will already have been acked.
1804 * called in irq context with spinlock held, irqs blocked
1806 irqreturn_t musb_interrupt(struct musb *musb)
1808 irqreturn_t retval = IRQ_NONE;
1809 u8 devctl, power, int_usb;
1813 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1814 power = musb_readb(musb->mregs, MUSB_POWER);
1816 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1817 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1818 musb->int_usb, musb->int_tx, musb->int_rx);
1820 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1821 if (is_otg_enabled(musb)|| is_peripheral_enabled(musb))
1822 if (!musb->gadget_driver) {
1823 DBG(5, "No gadget driver loaded\n");
1831 /* the core can interrupt us for multiple reasons; docs have
1832 * a generic interrupt flowchart to follow
1834 int_usb = musb->int_usb;
1836 int_usb &= ~MUSB_INTR_SOF;
1838 retval |= musb_stage0_irq(musb, int_usb, devctl, power);
1840 /* "stage 1" is handling endpoint irqs */
1842 /* handle endpoint 0 first */
1843 if (musb->int_tx & 1) {
1845 if (devctl & MUSB_DEVCTL_HM)
1846 retval |= musb_h_ep0_irq(musb);
1848 retval |= musb_g_ep0_irq(musb);
1851 /* TX on endpoints 1-15 */
1852 reg = musb->int_tx >> 1;
1857 /* musb_ep_select(musb->mregs, ep_num); */
1858 /* REVISIT just retval |= ep->tx_irq(...) */
1859 retval = IRQ_HANDLED;
1860 if (devctl & MUSB_DEVCTL_HM) {
1861 if (is_host_capable())
1862 musb_host_tx(musb, ep_num);
1864 if (is_peripheral_capable())
1865 musb_g_tx(musb, ep_num);
1872 /* RX on endpoints 1-15 */
1873 reg = musb->int_rx >> 1;
1878 /* musb_ep_select(musb->mregs, ep_num); */
1879 /* REVISIT just retval = ep->rx_irq(...) */
1880 retval = IRQ_HANDLED;
1881 if (devctl & MUSB_DEVCTL_HM) {
1882 if (is_host_capable())
1883 musb_host_rx(musb, ep_num);
1885 if (is_peripheral_capable())
1886 musb_g_rx(musb, ep_num, false);
1898 #ifndef CONFIG_MUSB_PIO_ONLY
1899 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1901 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1903 /* called with controller lock already held */
1906 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1907 if (!cppi_ti_dma()) {
1909 if (devctl & MUSB_DEVCTL_HM)
1910 musb_h_ep0_irq(musb);
1912 musb_g_ep0_irq(musb);
1916 /* endpoints 1..15 */
1918 if (devctl & MUSB_DEVCTL_HM) {
1919 if (is_host_capable())
1920 musb_host_tx(musb, epnum);
1922 if (is_peripheral_capable())
1923 musb_g_tx(musb, epnum);
1927 if (devctl & MUSB_DEVCTL_HM) {
1928 if (is_host_capable())
1929 musb_host_rx(musb, epnum);
1931 if (is_peripheral_capable())
1932 musb_g_rx(musb, epnum, true);
1939 /*-------------------------------------------------------------------------*/
1944 musb_charger_show(struct device *dev, struct device_attribute *attr, char *buf)
1946 struct musb *musb = dev_to_musb(dev);
1948 return sprintf(buf, "%d\n", (musb->is_charger ?
1949 musb->is_charger : musb_charger_detect(musb)));
1951 static DEVICE_ATTR(charger, 0444, musb_charger_show, NULL);
1954 musb_amp_show(struct device *dev, struct device_attribute *attr, char *buf)
1956 struct musb *musb = dev_to_musb(dev);
1958 return sprintf(buf, "%d\n", musb->power_draw);
1960 static DEVICE_ATTR(mA, 0444, musb_amp_show, NULL);
1963 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1965 struct musb *musb = dev_to_musb(dev);
1968 mutex_lock(&musb->mutex);
1969 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1970 mutex_unlock(&musb->mutex);
1976 musb_connect_show(struct device *dev, struct device_attribute *attr, char *buf)
1978 struct musb *musb = dev_to_musb(dev);
1979 unsigned long flags;
1982 spin_lock_irqsave(&musb->lock, flags);
1983 ret = sprintf(buf, "%d\n", musb->softconnect);
1984 spin_unlock_irqrestore(&musb->lock, flags);
1990 musb_connect_store(struct device *dev, struct device_attribute *attr,
1991 const char *buf, size_t n)
1993 struct musb *musb = dev_to_musb(dev);
1994 unsigned long flags;
1999 status = sscanf(buf, "%u", &val);
2001 printk(KERN_ERR "invalid parameter, %d\n", status);
2005 spin_lock_irqsave(&musb->lock, flags);
2007 power = musb_readb(musb->mregs, MUSB_POWER);
2010 power |= MUSB_POWER_SOFTCONN;
2012 power &= ~MUSB_POWER_SOFTCONN;
2014 musb->softconnect = !!val;
2015 musb_writeb(musb->mregs, MUSB_POWER, power);
2017 spin_unlock_irqrestore(&musb->lock, flags);
2021 static DEVICE_ATTR(connect, 0644, musb_connect_show, musb_connect_store);
2024 musb_mode_store(struct device *dev, struct device_attribute *attr,
2025 const char *buf, size_t n)
2027 struct musb *musb = dev_to_musb(dev);
2030 mutex_lock(&musb->mutex);
2031 if (sysfs_streq(buf, "host"))
2032 status = musb_platform_set_mode(musb, MUSB_HOST);
2033 else if (sysfs_streq(buf, "peripheral"))
2034 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2035 else if (sysfs_streq(buf, "otg"))
2036 status = musb_platform_set_mode(musb, MUSB_OTG);
2039 mutex_unlock(&musb->mutex);
2041 return (status == 0) ? n : status;
2043 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
2046 musb_vbus_store(struct device *dev, struct device_attribute *attr,
2047 const char *buf, size_t n)
2049 struct musb *musb = dev_to_musb(dev);
2050 unsigned long flags;
2053 if (sscanf(buf, "%lu", &val) < 1) {
2054 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
2058 spin_lock_irqsave(&musb->lock, flags);
2059 musb->a_wait_bcon = val;
2060 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
2061 musb->is_active = 0;
2062 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
2063 spin_unlock_irqrestore(&musb->lock, flags);
2069 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
2071 struct musb *musb = dev_to_musb(dev);
2072 unsigned long flags;
2076 spin_lock_irqsave(&musb->lock, flags);
2077 val = musb->a_wait_bcon;
2078 vbus = musb_platform_get_vbus_status(musb);
2079 spin_unlock_irqrestore(&musb->lock, flags);
2081 return sprintf(buf, "Vbus %s, timeout %lu\n",
2082 vbus ? "on" : "off", val);
2084 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
2086 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2089 musb_suspend_show(struct device *dev, struct device_attribute *attr, char *buf)
2091 struct musb *musb = dev_to_musb(dev);
2093 return sprintf(buf, "%d\n", musb->is_suspended);
2095 static DEVICE_ATTR(suspend, 0444, musb_suspend_show, NULL);
2097 /* Gadget drivers can't know that a host is connected so they might want
2098 * to start SRP, but users can. This allows userspace to trigger SRP.
2101 musb_srp_store(struct device *dev, struct device_attribute *attr,
2102 const char *buf, size_t n)
2104 struct musb *musb = dev_to_musb(dev);
2107 if (sscanf(buf, "%hu", &srp) != 1
2109 printk(KERN_ERR "SRP: Value must be 1\n");
2114 musb_g_wakeup(musb);
2118 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
2120 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2124 /* Only used to provide driver mode change events */
2125 static void musb_irq_work(struct work_struct *data)
2127 struct musb *musb = container_of(data, struct musb, irq_work);
2128 static int old_state, old_ma, old_suspend;
2130 if (musb->xceiv->state != old_state) {
2131 old_state = musb->xceiv->state;
2132 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2134 if (musb->power_draw != old_ma) {
2135 old_ma = musb->power_draw;
2136 sysfs_notify(&musb->controller->kobj, NULL, "mA");
2138 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2139 if (old_suspend != musb->is_suspended) {
2140 old_suspend = musb->is_suspended;
2141 sysfs_notify(&musb->controller->kobj, NULL, "suspend");
2146 /* --------------------------------------------------------------------------
2150 static struct musb *__init
2151 allocate_instance(struct device *dev,
2152 struct musb_hdrc_config *config, void __iomem *mbase)
2155 struct musb_hw_ep *ep;
2157 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2158 struct usb_hcd *hcd;
2160 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2163 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2165 musb = hcd_to_musb(hcd);
2167 hcd->uses_new_polling = 1;
2169 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2171 musb = kzalloc(sizeof *musb, GFP_KERNEL);
2174 dev_set_drvdata(dev, musb);
2178 musb->mregs = mbase;
2179 musb->ctrl_base = mbase;
2180 musb->nIrq = -ENODEV;
2181 musb->config = config;
2182 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2183 for (epnum = 0, ep = musb->endpoints;
2184 epnum < musb->config->num_eps;
2190 musb->controller = dev;
2194 static void musb_free(struct musb *musb)
2196 /* this has multiple entry modes. it handles fault cleanup after
2197 * probe(), where things may be partially set up, as well as rmmod
2198 * cleanup after everything's been de-activated.
2202 device_remove_file(musb->controller, &dev_attr_mA);
2203 device_remove_file(musb->controller, &dev_attr_connect);
2204 device_remove_file(musb->controller, &dev_attr_charger);
2205 device_remove_file(musb->controller, &dev_attr_mode);
2206 device_remove_file(musb->controller, &dev_attr_vbus);
2207 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2208 device_remove_file(musb->controller, &dev_attr_suspend);
2209 device_remove_file(musb->controller, &dev_attr_srp);
2213 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2214 musb_gadget_cleanup(musb);
2217 if (musb->nIrq >= 0) {
2219 disable_irq_wake(musb->nIrq);
2220 free_irq(musb->nIrq, musb);
2222 if (is_dma_capable() && musb->dma_controller) {
2223 struct dma_controller *c = musb->dma_controller;
2226 dma_controller_destroy(c);
2229 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2230 musb_platform_exit(musb);
2231 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2234 clk_disable(musb->clock);
2235 clk_put(musb->clock);
2238 #ifdef CONFIG_USB_MUSB_OTG
2239 put_device(musb->xceiv->dev);
2242 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2243 usb_put_hcd(musb_to_hcd(musb));
2250 * Perform generic per-controller initialization.
2252 * @pDevice: the controller (already clocked, etc)
2254 * @mregs: virtual address of controller registers,
2255 * not yet corrected for platform-specific offsets
2258 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2262 struct musb_hdrc_platform_data *plat = dev->platform_data;
2264 /* The driver might handle more features than the board; OK.
2265 * Fail when the board needs a feature that's not enabled.
2268 dev_dbg(dev, "no platform_data?\n");
2271 switch (plat->mode) {
2273 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2278 case MUSB_PERIPHERAL:
2279 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2285 #ifdef CONFIG_USB_MUSB_OTG
2291 dev_err(dev, "incompatible Kconfig role setting\n");
2296 musb = allocate_instance(dev, plat->config, ctrl);
2302 spin_lock_init(&musb->lock);
2303 mutex_init(&musb->mutex);
2304 musb->board = plat->board;
2305 musb->board_mode = plat->mode;
2306 musb->board_set_power = plat->set_power;
2307 musb->set_clock = plat->set_clock;
2308 musb->min_power = plat->min_power;
2309 musb->use_dma = use_dma;
2311 /* Clock usage is chip-specific ... functional clock (DaVinci,
2312 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2313 * code does is make sure a clock handle is available; platform
2314 * code manages it during start/stop and suspend/resume.
2317 musb->clock = clk_get(dev, plat->clock);
2318 if (IS_ERR(musb->clock)) {
2319 status = PTR_ERR(musb->clock);
2325 /* assume vbus is off */
2327 /* platform adjusts musb->mregs and musb->isr if needed,
2328 * and activates clocks
2330 musb->isr = generic_interrupt;
2331 status = musb_platform_init(musb);
2340 #ifndef CONFIG_MUSB_PIO_ONLY
2341 if (use_dma && dev->dma_mask) {
2342 struct dma_controller *c;
2344 c = dma_controller_create(musb, musb->mregs);
2345 musb->dma_controller = c;
2350 /* ideally this would be abstracted in platform setup */
2351 if (!musb->use_dma || !musb->dma_controller)
2352 dev->dma_mask = NULL;
2354 /* be sure interrupts are disabled before connecting ISR */
2355 musb_platform_disable(musb);
2356 musb_generic_disable(musb);
2358 /* setup musb parts of the core (especially endpoints) */
2359 status = musb_core_init(plat->config->multipoint
2360 ? MUSB_CONTROLLER_MHDRC
2361 : MUSB_CONTROLLER_HDRC, musb);
2365 /* Init IRQ workqueue before request_irq */
2366 INIT_WORK(&musb->irq_work, musb_irq_work);
2368 /* attach to the IRQ */
2369 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2370 dev_err(dev, "request_irq %d failed!\n", nIrq);
2375 /* FIXME this handles wakeup irqs wrong */
2376 if (enable_irq_wake(nIrq) == 0) {
2378 device_init_wakeup(dev, 1);
2383 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2386 switch (musb->board_mode) {
2387 case MUSB_HOST: s = "Host"; break;
2388 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2389 default: s = "OTG"; break;
2392 (is_dma_capable() && musb->dma_controller)
2396 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2397 /* host side needs more setup, except for no-host modes */
2398 if (musb->board_mode != MUSB_PERIPHERAL) {
2399 struct usb_hcd *hcd = musb_to_hcd(musb);
2401 if (musb->board_mode == MUSB_OTG)
2402 hcd->self.otg_port = 1;
2403 musb->xceiv->host = &hcd->self;
2404 hcd->power_budget = 2 * (plat->power ? : 250);
2406 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2408 /* For the host-only role, we can activate right away.
2409 * (We expect the ID pin to be forcibly grounded!!)
2410 * Otherwise, wait till the gadget driver hooks up.
2412 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2413 MUSB_HST_MODE(musb);
2414 musb->xceiv->default_a = 1;
2415 musb->xceiv->state = OTG_STATE_A_IDLE;
2417 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2421 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2423 musb_readb(musb->mregs, MUSB_DEVCTL),
2424 (musb_readb(musb->mregs, MUSB_DEVCTL)
2425 & MUSB_DEVCTL_BDEVICE
2428 } else /* peripheral is enabled */ {
2429 MUSB_DEV_MODE(musb);
2430 musb->xceiv->default_a = 0;
2431 musb->xceiv->state = OTG_STATE_B_IDLE;
2433 status = musb_gadget_setup(musb);
2437 DBG(1, "%s mode, status %d, dev%02x\n",
2438 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2440 musb_readb(musb->mregs, MUSB_DEVCTL));
2444 if (!(musb_debug_create("driver/musb_hdrc", musb)))
2445 DBG(1, "could not create procfs entry\n");
2448 status = device_create_file(dev, &dev_attr_mA);
2449 status = device_create_file(dev, &dev_attr_connect);
2450 status = device_create_file(dev, &dev_attr_charger);
2451 status = device_create_file(dev, &dev_attr_mode);
2452 status = device_create_file(dev, &dev_attr_vbus);
2453 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2454 status = device_create_file(dev, &dev_attr_suspend);
2455 status = device_create_file(dev, &dev_attr_srp);
2456 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2462 /* Resets the controller. Has to be done. Without this, most likely
2463 * the state machine inside the transceiver doesn't get fixed properly
2465 musb_save_ctx_and_suspend(&musb->g, 0);
2466 musb_restore_ctx_and_resume(&musb->g);
2472 device_remove_file(dev, &dev_attr_mA);
2473 device_remove_file(dev, &dev_attr_connect);
2474 device_remove_file(dev, &dev_attr_charger);
2475 device_remove_file(musb->controller, &dev_attr_mode);
2476 device_remove_file(musb->controller, &dev_attr_vbus);
2477 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2478 device_remove_file(musb->controller, &dev_attr_suspend);
2479 device_remove_file(musb->controller, &dev_attr_srp);
2482 musb_platform_exit(musb);
2484 dev_err(musb->controller,
2485 "musb_init_controller failed with status %d\n", status);
2488 clk_put(musb->clock);
2489 device_init_wakeup(dev, 0);
2496 /*-------------------------------------------------------------------------*/
2498 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2499 * bridge to a platform device; this driver then suffices.
2502 #ifndef CONFIG_MUSB_PIO_ONLY
2503 static u64 *orig_dma_mask;
2506 static int __init musb_probe(struct platform_device *pdev)
2508 struct device *dev = &pdev->dev;
2509 int irq = platform_get_irq(pdev, 0);
2510 struct resource *iomem;
2513 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2514 if (!iomem || irq == 0)
2517 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2519 dev_err(dev, "ioremap failed\n");
2523 #ifndef CONFIG_MUSB_PIO_ONLY
2524 /* clobbered by use_dma=n */
2525 orig_dma_mask = dev->dma_mask;
2527 /* Store initial mask for USB interrupts */
2528 ctx.intrusbe = 0xf7;
2530 return musb_init_controller(dev, irq, base);
2533 static int __devexit musb_remove(struct platform_device *pdev)
2535 struct musb *musb = dev_to_musb(&pdev->dev);
2536 void __iomem *ctrl_base = musb->ctrl_base;
2538 /* this gets called on rmmod.
2539 * - Host mode: host may still be active
2540 * - Peripheral mode: peripheral is deactivated (or never-activated)
2541 * - OTG mode: both roles are deactivated (or never-activated)
2543 musb_shutdown(pdev);
2544 musb_debug_delete("driver/musb_hdrc", musb);
2545 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2546 if (musb->board_mode == MUSB_HOST)
2547 usb_remove_hcd(musb_to_hcd(musb));
2551 device_init_wakeup(&pdev->dev, 0);
2552 #ifndef CONFIG_MUSB_PIO_ONLY
2553 pdev->dev.dma_mask = orig_dma_mask;
2560 void musb_save_ctx(struct musb *musb)
2562 ctx.power = musb_readb(musb->mregs, MUSB_POWER);
2563 ctx.intrtxe = musb_readw(musb->mregs, MUSB_INTRTXE);
2564 ctx.intrrxe = musb_readw(musb->mregs, MUSB_INTRRXE);
2565 ctx.intrusbe = musb_readb(musb->mregs, MUSB_INTRUSBE);
2566 ctx.devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2569 void musb_restore_ctx(struct musb *musb)
2572 musb_writeb(musb->mregs, MUSB_POWER, ctx.power);
2573 musb_writew(musb->mregs, MUSB_INTRTX, 0x00);
2574 musb_writew(musb->mregs, MUSB_INTRTXE, ctx.intrtxe);
2575 musb_writew(musb->mregs, MUSB_INTRRX, 0x00);
2576 musb_writew(musb->mregs, MUSB_INTRRXE, ctx.intrrxe);
2577 musb_writeb(musb->mregs, MUSB_INTRUSB, 0x00);
2578 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
2579 musb_writeb(musb->mregs, MUSB_DEVCTL, ctx.devctl);
2581 /* iterate over every endpoint, select it and restore its context */
2582 for (i = 0; i < musb->config->num_eps; i++) {
2583 musb_writeb(musb->mregs, MUSB_INDEX, i);
2584 musb_writeb(musb->mregs, MUSB_RXFIFOSZ, ctx.rxfifosz[i]);
2585 musb_writeb(musb->mregs, MUSB_TXFIFOSZ, ctx.txfifosz[i]);
2586 musb_writew(musb->mregs, MUSB_TXFIFOADD, ctx.txfifoadd[i]);
2587 musb_writew(musb->mregs, MUSB_RXFIFOADD, ctx.rxfifoadd[i]);
2591 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2593 unsigned long flags;
2594 struct musb *musb = dev_to_musb(&pdev->dev);
2599 spin_lock_irqsave(&musb->lock, flags);
2601 if (is_peripheral_active(musb)) {
2602 /* FIXME force disconnect unless we know USB will wake
2603 * the system up quickly enough to respond ...
2605 } else if (is_host_active(musb)) {
2606 /* we know all the children are suspended; sometimes
2607 * they will even be wakeup-enabled.
2612 musb_save_ctx(musb);
2614 if (musb->set_clock)
2615 musb->set_clock(musb->clock, 0);
2617 clk_disable(musb->clock);
2619 spin_unlock_irqrestore(&musb->lock, flags);
2623 static int musb_resume(struct platform_device *pdev)
2625 unsigned long flags;
2626 struct musb *musb = dev_to_musb(&pdev->dev);
2631 spin_lock_irqsave(&musb->lock, flags);
2633 if (musb->set_clock)
2634 musb->set_clock(musb->clock, 1);
2636 clk_enable(musb->clock);
2638 /* restore context */
2639 musb_restore_ctx(musb);
2641 /* for static cmos like DaVinci, register values were preserved
2642 * unless for some reason the whole soc powered down and we're
2643 * not treating that as a whole-system restart (e.g. swsusp)
2645 spin_unlock_irqrestore(&musb->lock, flags);
2650 #define musb_suspend NULL
2651 #define musb_resume NULL
2654 static struct platform_driver musb_driver = {
2656 .name = (char *)musb_driver_name,
2657 .bus = &platform_bus_type,
2658 .owner = THIS_MODULE,
2660 .remove = __devexit_p(musb_remove),
2661 .shutdown = musb_shutdown,
2662 .suspend = musb_suspend,
2663 .resume = musb_resume,
2666 /*-------------------------------------------------------------------------*/
2668 static int __init musb_init(void)
2670 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2675 pr_info("%s: version " MUSB_VERSION ", "
2676 #ifdef CONFIG_MUSB_PIO_ONLY
2678 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2680 #elif defined(CONFIG_USB_INVENTRA_DMA)
2682 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2688 #ifdef CONFIG_USB_MUSB_OTG
2689 "otg (peripheral+host)"
2690 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2692 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2696 musb_driver_name, musb_debug);
2697 return platform_driver_probe(&musb_driver, musb_probe);
2700 /* make us init after usbcore and before usb
2701 * gadget and host-side drivers start to register
2703 subsys_initcall(musb_init);
2705 static void __exit musb_cleanup(void)
2707 platform_driver_unregister(&musb_driver);
2709 module_exit(musb_cleanup);