1 /* alpha-dis.c -- Disassemble Alpha AXP instructions
2 Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Richard Henderson <rth@tamu.edu>,
4 patterned after the PPC opcode handling written by Ian Lance Taylor.
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, see
20 <http://www.gnu.org/licenses/>. */
25 /* The opcode table is an array of struct alpha_opcode. */
29 /* The opcode name. */
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
42 /* One bit flags for the opcode. These are primarily used to
43 indicate specific processors and environments support the
44 instructions. The defined values are listed below. */
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[4];
53 /* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
56 extern const struct alpha_opcode alpha_opcodes[];
57 extern const unsigned alpha_num_opcodes;
59 /* Values defined for the flags field of a struct alpha_opcode. */
61 /* CPU Availability */
62 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
63 #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
64 #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
65 #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
66 #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
67 #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
68 #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
70 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
72 /* A macro to extract the major opcode from an instruction. */
73 #define AXP_OP(i) (((i) >> 26) & 0x3F)
75 /* The total number of major opcodes. */
79 /* The operands table is an array of struct alpha_operand. */
83 /* The number of bits in the operand. */
84 unsigned int bits : 5;
86 /* How far the operand is left shifted in the instruction. */
87 unsigned int shift : 5;
89 /* The default relocation type for this operand. */
90 signed int default_reloc : 16;
92 /* One bit syntax flags. */
93 unsigned int flags : 16;
95 /* Insertion function. This is used by the assembler. To insert an
96 operand value into an instruction, check this field.
98 If it is NULL, execute
99 i |= (op & ((1 << o->bits) - 1)) << o->shift;
100 (i is the instruction which we are filling in, o is a pointer to
101 this structure, and op is the opcode value; this assumes twos
102 complement arithmetic).
104 If this field is not NULL, then simply call it with the
105 instruction and the operand value. It will return the new value
106 of the instruction. If the ERRMSG argument is not NULL, then if
107 the operand value is illegal, *ERRMSG will be set to a warning
108 string (the operand will be inserted in any case). If the
109 operand value is legal, *ERRMSG will be unchanged (most operands
110 can accept any value). */
111 unsigned (*insert) PARAMS ((unsigned instruction, int op,
112 const char **errmsg));
114 /* Extraction function. This is used by the disassembler. To
115 extract this operand type from an instruction, check this field.
117 If it is NULL, compute
118 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
119 if ((o->flags & AXP_OPERAND_SIGNED) != 0
120 && (op & (1 << (o->bits - 1))) != 0)
122 (i is the instruction, o is a pointer to this structure, and op
123 is the result; this assumes twos complement arithmetic).
125 If this field is not NULL, then simply call it with the
126 instruction value. It will return the value of the operand. If
127 the INVALID argument is not NULL, *INVALID will be set to
128 non-zero if this operand type can not actually be extracted from
129 this operand (i.e., the instruction does not match). If the
130 operand is valid, *INVALID will not be changed. */
131 int (*extract) PARAMS ((unsigned instruction, int *invalid));
134 /* Elements in the table are retrieved by indexing with values from
135 the operands field of the alpha_opcodes table. */
137 extern const struct alpha_operand alpha_operands[];
138 extern const unsigned alpha_num_operands;
140 /* Values defined for the flags field of a struct alpha_operand. */
142 /* Mask for selecting the type for typecheck purposes */
143 #define AXP_OPERAND_TYPECHECK_MASK \
144 (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \
145 AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \
146 AXP_OPERAND_UNSIGNED)
148 /* This operand does not actually exist in the assembler input. This
149 is used to support extended mnemonics, for which two operands fields
150 are identical. The assembler should call the insert function with
151 any op value. The disassembler should call the extract function,
152 ignore the return value, and check the value placed in the invalid
154 #define AXP_OPERAND_FAKE 01
156 /* The operand should be wrapped in parentheses rather than separated
157 from the previous by a comma. This is used for the load and store
158 instructions which want their operands to look like "Ra,disp(Rb)". */
159 #define AXP_OPERAND_PARENS 02
161 /* Used in combination with PARENS, this supresses the supression of
162 the comma. This is used for "jmp Ra,(Rb),hint". */
163 #define AXP_OPERAND_COMMA 04
165 /* This operand names an integer register. */
166 #define AXP_OPERAND_IR 010
168 /* This operand names a floating point register. */
169 #define AXP_OPERAND_FPR 020
171 /* This operand is a relative branch displacement. The disassembler
172 prints these symbolically if possible. */
173 #define AXP_OPERAND_RELATIVE 040
175 /* This operand takes signed values. */
176 #define AXP_OPERAND_SIGNED 0100
178 /* This operand takes unsigned values. This exists primarily so that
179 a flags value of 0 can be treated as end-of-arguments. */
180 #define AXP_OPERAND_UNSIGNED 0200
182 /* Supress overflow detection on this field. This is used for hints. */
183 #define AXP_OPERAND_NOOVERFLOW 0400
185 /* Mask for optional argument default value. */
186 #define AXP_OPERAND_OPTIONAL_MASK 07000
188 /* This operand defaults to zero. This is used for jump hints. */
189 #define AXP_OPERAND_DEFAULT_ZERO 01000
191 /* This operand should default to the first (real) operand and is used
192 in conjunction with AXP_OPERAND_OPTIONAL. This allows
193 "and $0,3,$0" to be written as "and $0,3", etc. I don't like
194 it, but it's what DEC does. */
195 #define AXP_OPERAND_DEFAULT_FIRST 02000
197 /* Similarly, this operand should default to the second (real) operand.
198 This allows "negl $0" instead of "negl $0,$0". */
199 #define AXP_OPERAND_DEFAULT_SECOND 04000
202 /* Register common names */
214 #define AXP_REG_S1 10
215 #define AXP_REG_S2 11
216 #define AXP_REG_S3 12
217 #define AXP_REG_S4 13
218 #define AXP_REG_S5 14
219 #define AXP_REG_FP 15
220 #define AXP_REG_A0 16
221 #define AXP_REG_A1 17
222 #define AXP_REG_A2 18
223 #define AXP_REG_A3 19
224 #define AXP_REG_A4 20
225 #define AXP_REG_A5 21
226 #define AXP_REG_T8 22
227 #define AXP_REG_T9 23
228 #define AXP_REG_T10 24
229 #define AXP_REG_T11 25
230 #define AXP_REG_RA 26
231 #define AXP_REG_PV 27
232 #define AXP_REG_T12 27
233 #define AXP_REG_AT 28
234 #define AXP_REG_GP 29
235 #define AXP_REG_SP 30
236 #define AXP_REG_ZERO 31
238 #define bfd_mach_alpha_ev4 0x10
239 #define bfd_mach_alpha_ev5 0x20
240 #define bfd_mach_alpha_ev6 0x30
242 enum bfd_reloc_code_real {
243 BFD_RELOC_23_PCREL_S2,
247 /* This file holds the Alpha AXP opcode table. The opcode table includes
248 almost all of the extended instruction mnemonics. This permits the
249 disassembler to use them, and simplifies the assembler logic, at the
250 cost of increasing the table size. The table is strictly constant
251 data, so the compiler should be able to put it in the text segment.
253 This file also holds the operand table. All knowledge about inserting
254 and extracting operands from instructions is kept in this file.
256 The information for the base instruction set was compiled from the
257 _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
260 The information for the post-ev5 architecture extensions BWX, CIX and
261 MAX came from version 3 of this same document, which is also available
262 on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
263 /literature/alphahb2.pdf
265 The information for the EV4 PALcode instructions was compiled from
266 _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
267 Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
268 revision dated June 1994.
270 The information for the EV5 PALcode instructions was compiled from
271 _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
272 Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */
274 /* Local insertion and extraction functions */
276 static unsigned insert_rba PARAMS((unsigned, int, const char **));
277 static unsigned insert_rca PARAMS((unsigned, int, const char **));
278 static unsigned insert_za PARAMS((unsigned, int, const char **));
279 static unsigned insert_zb PARAMS((unsigned, int, const char **));
280 static unsigned insert_zc PARAMS((unsigned, int, const char **));
281 static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
282 static unsigned insert_jhint PARAMS((unsigned, int, const char **));
283 static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
285 static int extract_rba PARAMS((unsigned, int *));
286 static int extract_rca PARAMS((unsigned, int *));
287 static int extract_za PARAMS((unsigned, int *));
288 static int extract_zb PARAMS((unsigned, int *));
289 static int extract_zc PARAMS((unsigned, int *));
290 static int extract_bdisp PARAMS((unsigned, int *));
291 static int extract_jhint PARAMS((unsigned, int *));
292 static int extract_ev6hwjhint PARAMS((unsigned, int *));
295 /* The operands table */
297 const struct alpha_operand alpha_operands[] =
299 /* The fields are bits, shift, insert, extract, flags */
300 /* The zero index is used to indicate end-of-list */
302 { 0, 0, 0, 0, 0, 0 },
304 /* The plain integer register fields */
305 #define RA (UNUSED + 1)
306 { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
308 { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
310 { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
312 /* The plain fp register fields */
314 { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
316 { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
318 { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
320 /* The integer registers when they are ZERO */
322 { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
324 { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
326 { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
328 /* The RB field when it needs parentheses */
330 { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
332 /* The RB field when it needs parentheses _and_ a preceding comma */
333 #define CPRB (PRB + 1)
335 AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
337 /* The RB field when it must be the same as the RA field */
338 #define RBA (CPRB + 1)
339 { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
341 /* The RC field when it must be the same as the RB field */
342 #define RCA (RBA + 1)
343 { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
345 /* The RC field when it can *default* to RA */
346 #define DRC1 (RCA + 1)
348 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
350 /* The RC field when it can *default* to RB */
351 #define DRC2 (DRC1 + 1)
353 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
355 /* The FC field when it can *default* to RA */
356 #define DFC1 (DRC2 + 1)
358 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
360 /* The FC field when it can *default* to RB */
361 #define DFC2 (DFC1 + 1)
363 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
365 /* The unsigned 8-bit literal of Operate format insns */
366 #define LIT (DFC2 + 1)
367 { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
369 /* The signed 16-bit displacement of Memory format insns. From here
370 we can't tell what relocation should be used, so don't use a default. */
371 #define MDISP (LIT + 1)
372 { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
374 /* The signed "23-bit" aligned displacement of Branch format insns */
375 #define BDISP (MDISP + 1)
376 { 21, 0, BFD_RELOC_23_PCREL_S2,
377 AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
379 /* The 26-bit PALcode function */
380 #define PALFN (BDISP + 1)
381 { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
383 /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
384 #define JMPHINT (PALFN + 1)
385 { 14, 0, BFD_RELOC_ALPHA_HINT,
386 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
387 insert_jhint, extract_jhint },
389 /* The optional hint to RET/JSR_COROUTINE */
390 #define RETHINT (JMPHINT + 1)
392 AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
394 /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
395 #define EV4HWDISP (RETHINT + 1)
396 #define EV6HWDISP (EV4HWDISP)
397 { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
399 /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
400 #define EV4HWINDEX (EV4HWDISP + 1)
401 { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
403 /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
404 that occur in DEC PALcode. */
405 #define EV4EXTHWINDEX (EV4HWINDEX + 1)
406 { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
408 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
409 #define EV5HWDISP (EV4EXTHWINDEX + 1)
410 { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
412 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
413 #define EV5HWINDEX (EV5HWDISP + 1)
414 { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
416 /* The 16-bit combined index/scoreboard mask for the ev6
417 hw_m[ft]pr (pal19/pal1d) insns */
418 #define EV6HWINDEX (EV5HWINDEX + 1)
419 { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
421 /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
422 #define EV6HWJMPHINT (EV6HWINDEX+ 1)
423 { 8, 0, -EV6HWJMPHINT,
424 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
425 insert_ev6hwjhint, extract_ev6hwjhint }
428 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
430 /* The RB field when it is the same as the RA field in the same insn.
431 This operand is marked fake. The insertion function just copies
432 the RA field into the RB field, and the extraction function just
433 checks that the fields are the same. */
437 insert_rba(insn, value, errmsg)
439 int value ATTRIBUTE_UNUSED;
440 const char **errmsg ATTRIBUTE_UNUSED;
442 return insn | (((insn >> 21) & 0x1f) << 16);
446 extract_rba(insn, invalid)
450 if (invalid != (int *) NULL
451 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
457 /* The same for the RC field */
461 insert_rca(insn, value, errmsg)
463 int value ATTRIBUTE_UNUSED;
464 const char **errmsg ATTRIBUTE_UNUSED;
466 return insn | ((insn >> 21) & 0x1f);
470 extract_rca(insn, invalid)
474 if (invalid != (int *) NULL
475 && ((insn >> 21) & 0x1f) != (insn & 0x1f))
481 /* Fake arguments in which the registers must be set to ZERO */
485 insert_za(insn, value, errmsg)
487 int value ATTRIBUTE_UNUSED;
488 const char **errmsg ATTRIBUTE_UNUSED;
490 return insn | (31 << 21);
494 extract_za(insn, invalid)
498 if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
505 insert_zb(insn, value, errmsg)
507 int value ATTRIBUTE_UNUSED;
508 const char **errmsg ATTRIBUTE_UNUSED;
510 return insn | (31 << 16);
514 extract_zb(insn, invalid)
518 if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
525 insert_zc(insn, value, errmsg)
527 int value ATTRIBUTE_UNUSED;
528 const char **errmsg ATTRIBUTE_UNUSED;
534 extract_zc(insn, invalid)
538 if (invalid != (int *) NULL && (insn & 0x1f) != 31)
544 /* The displacement field of a Branch format insn. */
547 insert_bdisp(insn, value, errmsg)
552 if (errmsg != (const char **)NULL && (value & 3))
553 *errmsg = _("branch operand unaligned");
554 return insn | ((value / 4) & 0x1FFFFF);
559 extract_bdisp(insn, invalid)
561 int *invalid ATTRIBUTE_UNUSED;
563 return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
567 /* The hint field of a JMP/JSR insn. */
570 insert_jhint(insn, value, errmsg)
575 if (errmsg != (const char **)NULL && (value & 3))
576 *errmsg = _("jump hint unaligned");
577 return insn | ((value / 4) & 0x3FFF);
582 extract_jhint(insn, invalid)
584 int *invalid ATTRIBUTE_UNUSED;
586 return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
589 /* The hint field of an EV6 HW_JMP/JSR insn. */
592 insert_ev6hwjhint(insn, value, errmsg)
597 if (errmsg != (const char **)NULL && (value & 3))
598 *errmsg = _("jump hint unaligned");
599 return insn | ((value / 4) & 0x1FFF);
604 extract_ev6hwjhint(insn, invalid)
606 int *invalid ATTRIBUTE_UNUSED;
608 return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
612 /* Macros used to form opcodes */
614 /* The main opcode */
615 #define OP(x) (((x) & 0x3F) << 26)
616 #define OP_MASK 0xFC000000
618 /* Branch format instructions */
619 #define BRA_(oo) OP(oo)
620 #define BRA_MASK OP_MASK
621 #define BRA(oo) BRA_(oo), BRA_MASK
623 /* Floating point format instructions */
624 #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))
625 #define FP_MASK (OP_MASK | 0xFFE0)
626 #define FP(oo,fff) FP_(oo,fff), FP_MASK
628 /* Memory format instructions */
629 #define MEM_(oo) OP(oo)
630 #define MEM_MASK OP_MASK
631 #define MEM(oo) MEM_(oo), MEM_MASK
633 /* Memory/Func Code format instructions */
634 #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))
635 #define MFC_MASK (OP_MASK | 0xFFFF)
636 #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
638 /* Memory/Branch format instructions */
639 #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14))
640 #define MBR_MASK (OP_MASK | 0xC000)
641 #define MBR(oo,h) MBR_(oo,h), MBR_MASK
643 /* Operate format instructions. The OPRL variant specifies a
644 literal second argument. */
645 #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))
646 #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)
647 #define OPR_MASK (OP_MASK | 0x1FE0)
648 #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK
649 #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK
651 /* Generic PALcode format instructions */
652 #define PCD_(oo) OP(oo)
653 #define PCD_MASK OP_MASK
654 #define PCD(oo) PCD_(oo), PCD_MASK
656 /* Specific PALcode instructions */
657 #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))
658 #define SPCD_MASK 0xFFFFFFFF
659 #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK
661 /* Hardware memory (hw_{ld,st}) instructions */
662 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
663 #define EV4HWMEM_MASK (OP_MASK | 0xF000)
664 #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK
666 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
667 #define EV5HWMEM_MASK (OP_MASK | 0xF800)
668 #define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK
670 #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
671 #define EV6HWMEM_MASK (OP_MASK | 0xF000)
672 #define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK
674 #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))
675 #define EV6HWMBR_MASK (OP_MASK | 0xE000)
676 #define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK
678 /* Abbreviations for instruction subsets. */
679 #define BASE AXP_OPCODE_BASE
680 #define EV4 AXP_OPCODE_EV4
681 #define EV5 AXP_OPCODE_EV5
682 #define EV6 AXP_OPCODE_EV6
683 #define BWX AXP_OPCODE_BWX
684 #define CIX AXP_OPCODE_CIX
685 #define MAX AXP_OPCODE_MAX
687 /* Common combinations of arguments */
688 #define ARG_NONE { 0 }
689 #define ARG_BRA { RA, BDISP }
690 #define ARG_FBRA { FA, BDISP }
691 #define ARG_FP { FA, FB, DFC1 }
692 #define ARG_FPZ1 { ZA, FB, DFC1 }
693 #define ARG_MEM { RA, MDISP, PRB }
694 #define ARG_FMEM { FA, MDISP, PRB }
695 #define ARG_OPR { RA, RB, DRC1 }
696 #define ARG_OPRL { RA, LIT, DRC1 }
697 #define ARG_OPRZ1 { ZA, RB, DRC1 }
698 #define ARG_OPRLZ1 { ZA, LIT, RC }
699 #define ARG_PCD { PALFN }
700 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
701 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
702 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
703 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
707 The format of the opcode table is:
709 NAME OPCODE MASK { OPERANDS }
711 NAME is the name of the instruction.
713 OPCODE is the instruction opcode.
715 MASK is the opcode mask; this is used to tell the disassembler
716 which bits in the actual opcode must match OPCODE.
718 OPERANDS is the list of operands.
720 The preceding macros merge the text of the OPCODE and MASK fields.
722 The disassembler reads the table in order and prints the first
723 instruction which matches, so this table is sorted to put more
724 specific instructions before more general instructions.
726 Otherwise, it is sorted by major opcode and minor function code.
728 There are three classes of not-really-instructions in this table:
730 ALIAS is another name for another instruction. Some of
731 these come from the Architecture Handbook, some
732 come from the original gas opcode tables. In all
733 cases, the functionality of the opcode is unchanged.
735 PSEUDO a stylized code form endorsed by Chapter A.4 of the
736 Architecture Handbook.
738 EXTRA a stylized code form found in the original gas tables.
742 EV56 BUT opcodes that are officially introduced as of the ev56,
743 but with defined results on previous implementations.
745 EV56 UNA opcodes that were introduced as of the ev56 with
746 presumably undefined results on previous implementations
747 that were not assigned to a particular extension.
750 const struct alpha_opcode alpha_opcodes[] = {
751 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
752 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
753 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },
754 { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE },
755 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE },
756 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE },
757 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE },
758 { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE },
759 { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE },
760 { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE },
761 { "call_pal", PCD(0x00), BASE, ARG_PCD },
762 { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */
764 { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */
765 { "lda", MEM(0x08), BASE, ARG_MEM },
766 { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */
767 { "ldah", MEM(0x09), BASE, ARG_MEM },
768 { "ldbu", MEM(0x0A), BWX, ARG_MEM },
769 { "unop", MEM_(0x0B) | (30 << 16),
770 MEM_MASK, BASE, { ZA } }, /* pseudo */
771 { "ldq_u", MEM(0x0B), BASE, ARG_MEM },
772 { "ldwu", MEM(0x0C), BWX, ARG_MEM },
773 { "stw", MEM(0x0D), BWX, ARG_MEM },
774 { "stb", MEM(0x0E), BWX, ARG_MEM },
775 { "stq_u", MEM(0x0F), BASE, ARG_MEM },
777 { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */
778 { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */
779 { "addl", OPR(0x10,0x00), BASE, ARG_OPR },
780 { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL },
781 { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR },
782 { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL },
783 { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */
784 { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */
785 { "subl", OPR(0x10,0x09), BASE, ARG_OPR },
786 { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL },
787 { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR },
788 { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL },
789 { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR },
790 { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL },
791 { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR },
792 { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL },
793 { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR },
794 { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL },
795 { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR },
796 { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL },
797 { "addq", OPR(0x10,0x20), BASE, ARG_OPR },
798 { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL },
799 { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR },
800 { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL },
801 { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */
802 { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */
803 { "subq", OPR(0x10,0x29), BASE, ARG_OPR },
804 { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL },
805 { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR },
806 { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL },
807 { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR },
808 { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL },
809 { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR },
810 { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL },
811 { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR },
812 { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL },
813 { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR },
814 { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL },
815 { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR },
816 { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL },
817 { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */
818 { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */
819 { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR },
820 { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL },
821 { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR },
822 { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL },
823 { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR },
824 { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL },
825 { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */
826 { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */
827 { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR },
828 { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL },
829 { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR },
830 { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL },
832 { "and", OPR(0x11,0x00), BASE, ARG_OPR },
833 { "and", OPRL(0x11,0x00), BASE, ARG_OPRL },
834 { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */
835 { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */
836 { "bic", OPR(0x11,0x08), BASE, ARG_OPR },
837 { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL },
838 { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR },
839 { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL },
840 { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR },
841 { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL },
842 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
843 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
844 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
845 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
846 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
847 { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */
848 { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */
849 { "bis", OPR(0x11,0x20), BASE, ARG_OPR },
850 { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL },
851 { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR },
852 { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL },
853 { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR },
854 { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL },
855 { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */
856 { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */
857 { "ornot", OPR(0x11,0x28), BASE, ARG_OPR },
858 { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL },
859 { "xor", OPR(0x11,0x40), BASE, ARG_OPR },
860 { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL },
861 { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR },
862 { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL },
863 { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR },
864 { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL },
865 { "eqv", OPR(0x11,0x48), BASE, ARG_OPR },
866 { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL },
867 { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */
868 { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */
869 { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */
870 { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */
871 { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR },
872 { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL },
873 { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR },
874 { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL },
875 { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
876 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */
878 { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR },
879 { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL },
880 { "extbl", OPR(0x12,0x06), BASE, ARG_OPR },
881 { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL },
882 { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR },
883 { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL },
884 { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR },
885 { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL },
886 { "extwl", OPR(0x12,0x16), BASE, ARG_OPR },
887 { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL },
888 { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR },
889 { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL },
890 { "mskll", OPR(0x12,0x22), BASE, ARG_OPR },
891 { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL },
892 { "extll", OPR(0x12,0x26), BASE, ARG_OPR },
893 { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL },
894 { "insll", OPR(0x12,0x2B), BASE, ARG_OPR },
895 { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL },
896 { "zap", OPR(0x12,0x30), BASE, ARG_OPR },
897 { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL },
898 { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR },
899 { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL },
900 { "mskql", OPR(0x12,0x32), BASE, ARG_OPR },
901 { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL },
902 { "srl", OPR(0x12,0x34), BASE, ARG_OPR },
903 { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL },
904 { "extql", OPR(0x12,0x36), BASE, ARG_OPR },
905 { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL },
906 { "sll", OPR(0x12,0x39), BASE, ARG_OPR },
907 { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL },
908 { "insql", OPR(0x12,0x3B), BASE, ARG_OPR },
909 { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL },
910 { "sra", OPR(0x12,0x3C), BASE, ARG_OPR },
911 { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL },
912 { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR },
913 { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL },
914 { "inswh", OPR(0x12,0x57), BASE, ARG_OPR },
915 { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL },
916 { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR },
917 { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL },
918 { "msklh", OPR(0x12,0x62), BASE, ARG_OPR },
919 { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL },
920 { "inslh", OPR(0x12,0x67), BASE, ARG_OPR },
921 { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL },
922 { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR },
923 { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL },
924 { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR },
925 { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL },
926 { "insqh", OPR(0x12,0x77), BASE, ARG_OPR },
927 { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL },
928 { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR },
929 { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL },
931 { "mull", OPR(0x13,0x00), BASE, ARG_OPR },
932 { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL },
933 { "mulq", OPR(0x13,0x20), BASE, ARG_OPR },
934 { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL },
935 { "umulh", OPR(0x13,0x30), BASE, ARG_OPR },
936 { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL },
937 { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR },
938 { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL },
939 { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR },
940 { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL },
942 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
943 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
944 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
945 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
946 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
947 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
948 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
949 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
950 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 },
951 { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 },
952 { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 },
953 { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 },
954 { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 },
955 { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 },
956 { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 },
957 { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 },
958 { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 },
959 { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 },
960 { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 },
961 { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 },
962 { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 },
963 { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 },
964 { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 },
965 { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 },
966 { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 },
967 { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 },
968 { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 },
969 { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 },
970 { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 },
971 { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 },
972 { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 },
973 { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 },
974 { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 },
975 { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 },
976 { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 },
977 { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 },
978 { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 },
979 { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 },
980 { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 },
981 { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 },
982 { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 },
983 { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 },
984 { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 },
985 { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 },
986 { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 },
987 { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 },
988 { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 },
989 { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 },
990 { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 },
991 { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 },
992 { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 },
994 { "addf/c", FP(0x15,0x000), BASE, ARG_FP },
995 { "subf/c", FP(0x15,0x001), BASE, ARG_FP },
996 { "mulf/c", FP(0x15,0x002), BASE, ARG_FP },
997 { "divf/c", FP(0x15,0x003), BASE, ARG_FP },
998 { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 },
999 { "addg/c", FP(0x15,0x020), BASE, ARG_FP },
1000 { "subg/c", FP(0x15,0x021), BASE, ARG_FP },
1001 { "mulg/c", FP(0x15,0x022), BASE, ARG_FP },
1002 { "divg/c", FP(0x15,0x023), BASE, ARG_FP },
1003 { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 },
1004 { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 },
1005 { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 },
1006 { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 },
1007 { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 },
1008 { "addf", FP(0x15,0x080), BASE, ARG_FP },
1009 { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */
1010 { "subf", FP(0x15,0x081), BASE, ARG_FP },
1011 { "mulf", FP(0x15,0x082), BASE, ARG_FP },
1012 { "divf", FP(0x15,0x083), BASE, ARG_FP },
1013 { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 },
1014 { "addg", FP(0x15,0x0A0), BASE, ARG_FP },
1015 { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
1016 { "subg", FP(0x15,0x0A1), BASE, ARG_FP },
1017 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP },
1018 { "divg", FP(0x15,0x0A3), BASE, ARG_FP },
1019 { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP },
1020 { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP },
1021 { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP },
1022 { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 },
1023 { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 },
1024 { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 },
1025 { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 },
1026 { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 },
1027 { "addf/uc", FP(0x15,0x100), BASE, ARG_FP },
1028 { "subf/uc", FP(0x15,0x101), BASE, ARG_FP },
1029 { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP },
1030 { "divf/uc", FP(0x15,0x103), BASE, ARG_FP },
1031 { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 },
1032 { "addg/uc", FP(0x15,0x120), BASE, ARG_FP },
1033 { "subg/uc", FP(0x15,0x121), BASE, ARG_FP },
1034 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP },
1035 { "divg/uc", FP(0x15,0x123), BASE, ARG_FP },
1036 { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 },
1037 { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 },
1038 { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 },
1039 { "addf/u", FP(0x15,0x180), BASE, ARG_FP },
1040 { "subf/u", FP(0x15,0x181), BASE, ARG_FP },
1041 { "mulf/u", FP(0x15,0x182), BASE, ARG_FP },
1042 { "divf/u", FP(0x15,0x183), BASE, ARG_FP },
1043 { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 },
1044 { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP },
1045 { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP },
1046 { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP },
1047 { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP },
1048 { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 },
1049 { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 },
1050 { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 },
1051 { "addf/sc", FP(0x15,0x400), BASE, ARG_FP },
1052 { "subf/sc", FP(0x15,0x401), BASE, ARG_FP },
1053 { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP },
1054 { "divf/sc", FP(0x15,0x403), BASE, ARG_FP },
1055 { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 },
1056 { "addg/sc", FP(0x15,0x420), BASE, ARG_FP },
1057 { "subg/sc", FP(0x15,0x421), BASE, ARG_FP },
1058 { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP },
1059 { "divg/sc", FP(0x15,0x423), BASE, ARG_FP },
1060 { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 },
1061 { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 },
1062 { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 },
1063 { "addf/s", FP(0x15,0x480), BASE, ARG_FP },
1064 { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */
1065 { "subf/s", FP(0x15,0x481), BASE, ARG_FP },
1066 { "mulf/s", FP(0x15,0x482), BASE, ARG_FP },
1067 { "divf/s", FP(0x15,0x483), BASE, ARG_FP },
1068 { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 },
1069 { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP },
1070 { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */
1071 { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP },
1072 { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP },
1073 { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP },
1074 { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP },
1075 { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP },
1076 { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP },
1077 { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 },
1078 { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 },
1079 { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 },
1080 { "addf/suc", FP(0x15,0x500), BASE, ARG_FP },
1081 { "subf/suc", FP(0x15,0x501), BASE, ARG_FP },
1082 { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP },
1083 { "divf/suc", FP(0x15,0x503), BASE, ARG_FP },
1084 { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 },
1085 { "addg/suc", FP(0x15,0x520), BASE, ARG_FP },
1086 { "subg/suc", FP(0x15,0x521), BASE, ARG_FP },
1087 { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP },
1088 { "divg/suc", FP(0x15,0x523), BASE, ARG_FP },
1089 { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 },
1090 { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 },
1091 { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 },
1092 { "addf/su", FP(0x15,0x580), BASE, ARG_FP },
1093 { "subf/su", FP(0x15,0x581), BASE, ARG_FP },
1094 { "mulf/su", FP(0x15,0x582), BASE, ARG_FP },
1095 { "divf/su", FP(0x15,0x583), BASE, ARG_FP },
1096 { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 },
1097 { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP },
1098 { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP },
1099 { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP },
1100 { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP },
1101 { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 },
1102 { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 },
1103 { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 },
1105 { "adds/c", FP(0x16,0x000), BASE, ARG_FP },
1106 { "subs/c", FP(0x16,0x001), BASE, ARG_FP },
1107 { "muls/c", FP(0x16,0x002), BASE, ARG_FP },
1108 { "divs/c", FP(0x16,0x003), BASE, ARG_FP },
1109 { "addt/c", FP(0x16,0x020), BASE, ARG_FP },
1110 { "subt/c", FP(0x16,0x021), BASE, ARG_FP },
1111 { "mult/c", FP(0x16,0x022), BASE, ARG_FP },
1112 { "divt/c", FP(0x16,0x023), BASE, ARG_FP },
1113 { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 },
1114 { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 },
1115 { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 },
1116 { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 },
1117 { "adds/m", FP(0x16,0x040), BASE, ARG_FP },
1118 { "subs/m", FP(0x16,0x041), BASE, ARG_FP },
1119 { "muls/m", FP(0x16,0x042), BASE, ARG_FP },
1120 { "divs/m", FP(0x16,0x043), BASE, ARG_FP },
1121 { "addt/m", FP(0x16,0x060), BASE, ARG_FP },
1122 { "subt/m", FP(0x16,0x061), BASE, ARG_FP },
1123 { "mult/m", FP(0x16,0x062), BASE, ARG_FP },
1124 { "divt/m", FP(0x16,0x063), BASE, ARG_FP },
1125 { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 },
1126 { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 },
1127 { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 },
1128 { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 },
1129 { "adds", FP(0x16,0x080), BASE, ARG_FP },
1130 { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */
1131 { "subs", FP(0x16,0x081), BASE, ARG_FP },
1132 { "muls", FP(0x16,0x082), BASE, ARG_FP },
1133 { "divs", FP(0x16,0x083), BASE, ARG_FP },
1134 { "addt", FP(0x16,0x0A0), BASE, ARG_FP },
1135 { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
1136 { "subt", FP(0x16,0x0A1), BASE, ARG_FP },
1137 { "mult", FP(0x16,0x0A2), BASE, ARG_FP },
1138 { "divt", FP(0x16,0x0A3), BASE, ARG_FP },
1139 { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP },
1140 { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP },
1141 { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP },
1142 { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP },
1143 { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 },
1144 { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 },
1145 { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 },
1146 { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 },
1147 { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP },
1148 { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP },
1149 { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP },
1150 { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP },
1151 { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP },
1152 { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP },
1153 { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP },
1154 { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP },
1155 { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 },
1156 { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 },
1157 { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 },
1158 { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 },
1159 { "adds/uc", FP(0x16,0x100), BASE, ARG_FP },
1160 { "subs/uc", FP(0x16,0x101), BASE, ARG_FP },
1161 { "muls/uc", FP(0x16,0x102), BASE, ARG_FP },
1162 { "divs/uc", FP(0x16,0x103), BASE, ARG_FP },
1163 { "addt/uc", FP(0x16,0x120), BASE, ARG_FP },
1164 { "subt/uc", FP(0x16,0x121), BASE, ARG_FP },
1165 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP },
1166 { "divt/uc", FP(0x16,0x123), BASE, ARG_FP },
1167 { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 },
1168 { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 },
1169 { "adds/um", FP(0x16,0x140), BASE, ARG_FP },
1170 { "subs/um", FP(0x16,0x141), BASE, ARG_FP },
1171 { "muls/um", FP(0x16,0x142), BASE, ARG_FP },
1172 { "divs/um", FP(0x16,0x143), BASE, ARG_FP },
1173 { "addt/um", FP(0x16,0x160), BASE, ARG_FP },
1174 { "subt/um", FP(0x16,0x161), BASE, ARG_FP },
1175 { "mult/um", FP(0x16,0x162), BASE, ARG_FP },
1176 { "divt/um", FP(0x16,0x163), BASE, ARG_FP },
1177 { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 },
1178 { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 },
1179 { "adds/u", FP(0x16,0x180), BASE, ARG_FP },
1180 { "subs/u", FP(0x16,0x181), BASE, ARG_FP },
1181 { "muls/u", FP(0x16,0x182), BASE, ARG_FP },
1182 { "divs/u", FP(0x16,0x183), BASE, ARG_FP },
1183 { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP },
1184 { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP },
1185 { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP },
1186 { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP },
1187 { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 },
1188 { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 },
1189 { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP },
1190 { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP },
1191 { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP },
1192 { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP },
1193 { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP },
1194 { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP },
1195 { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP },
1196 { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP },
1197 { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 },
1198 { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 },
1199 { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 },
1200 { "adds/suc", FP(0x16,0x500), BASE, ARG_FP },
1201 { "subs/suc", FP(0x16,0x501), BASE, ARG_FP },
1202 { "muls/suc", FP(0x16,0x502), BASE, ARG_FP },
1203 { "divs/suc", FP(0x16,0x503), BASE, ARG_FP },
1204 { "addt/suc", FP(0x16,0x520), BASE, ARG_FP },
1205 { "subt/suc", FP(0x16,0x521), BASE, ARG_FP },
1206 { "mult/suc", FP(0x16,0x522), BASE, ARG_FP },
1207 { "divt/suc", FP(0x16,0x523), BASE, ARG_FP },
1208 { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 },
1209 { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 },
1210 { "adds/sum", FP(0x16,0x540), BASE, ARG_FP },
1211 { "subs/sum", FP(0x16,0x541), BASE, ARG_FP },
1212 { "muls/sum", FP(0x16,0x542), BASE, ARG_FP },
1213 { "divs/sum", FP(0x16,0x543), BASE, ARG_FP },
1214 { "addt/sum", FP(0x16,0x560), BASE, ARG_FP },
1215 { "subt/sum", FP(0x16,0x561), BASE, ARG_FP },
1216 { "mult/sum", FP(0x16,0x562), BASE, ARG_FP },
1217 { "divt/sum", FP(0x16,0x563), BASE, ARG_FP },
1218 { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 },
1219 { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 },
1220 { "adds/su", FP(0x16,0x580), BASE, ARG_FP },
1221 { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */
1222 { "subs/su", FP(0x16,0x581), BASE, ARG_FP },
1223 { "muls/su", FP(0x16,0x582), BASE, ARG_FP },
1224 { "divs/su", FP(0x16,0x583), BASE, ARG_FP },
1225 { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP },
1226 { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */
1227 { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP },
1228 { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP },
1229 { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP },
1230 { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP },
1231 { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP },
1232 { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP },
1233 { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP },
1234 { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 },
1235 { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 },
1236 { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP },
1237 { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP },
1238 { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP },
1239 { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP },
1240 { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP },
1241 { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP },
1242 { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP },
1243 { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP },
1244 { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 },
1245 { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 },
1246 { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 },
1247 { "adds/suic", FP(0x16,0x700), BASE, ARG_FP },
1248 { "subs/suic", FP(0x16,0x701), BASE, ARG_FP },
1249 { "muls/suic", FP(0x16,0x702), BASE, ARG_FP },
1250 { "divs/suic", FP(0x16,0x703), BASE, ARG_FP },
1251 { "addt/suic", FP(0x16,0x720), BASE, ARG_FP },
1252 { "subt/suic", FP(0x16,0x721), BASE, ARG_FP },
1253 { "mult/suic", FP(0x16,0x722), BASE, ARG_FP },
1254 { "divt/suic", FP(0x16,0x723), BASE, ARG_FP },
1255 { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 },
1256 { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 },
1257 { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 },
1258 { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 },
1259 { "adds/suim", FP(0x16,0x740), BASE, ARG_FP },
1260 { "subs/suim", FP(0x16,0x741), BASE, ARG_FP },
1261 { "muls/suim", FP(0x16,0x742), BASE, ARG_FP },
1262 { "divs/suim", FP(0x16,0x743), BASE, ARG_FP },
1263 { "addt/suim", FP(0x16,0x760), BASE, ARG_FP },
1264 { "subt/suim", FP(0x16,0x761), BASE, ARG_FP },
1265 { "mult/suim", FP(0x16,0x762), BASE, ARG_FP },
1266 { "divt/suim", FP(0x16,0x763), BASE, ARG_FP },
1267 { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 },
1268 { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 },
1269 { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 },
1270 { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 },
1271 { "adds/sui", FP(0x16,0x780), BASE, ARG_FP },
1272 { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */
1273 { "subs/sui", FP(0x16,0x781), BASE, ARG_FP },
1274 { "muls/sui", FP(0x16,0x782), BASE, ARG_FP },
1275 { "divs/sui", FP(0x16,0x783), BASE, ARG_FP },
1276 { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP },
1277 { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */
1278 { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP },
1279 { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP },
1280 { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP },
1281 { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1282 { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1283 { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1284 { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1285 { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP },
1286 { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP },
1287 { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP },
1288 { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP },
1289 { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP },
1290 { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP },
1291 { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP },
1292 { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP },
1293 { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1294 { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1295 { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1296 { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1298 { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 },
1299 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
1300 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
1301 { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */
1302 { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1303 { "cpys", FP(0x17,0x020), BASE, ARG_FP },
1304 { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1305 { "cpysn", FP(0x17,0x021), BASE, ARG_FP },
1306 { "cpyse", FP(0x17,0x022), BASE, ARG_FP },
1307 { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1308 { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1309 { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP },
1310 { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP },
1311 { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP },
1312 { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP },
1313 { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP },
1314 { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP },
1315 { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 },
1316 { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 },
1317 { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 },
1319 { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE },
1320 { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */
1321 { "excb", MFC(0x18,0x0400), BASE, ARG_NONE },
1322 { "mb", MFC(0x18,0x4000), BASE, ARG_NONE },
1323 { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE },
1324 { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } },
1325 { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } },
1326 { "rpcc", MFC(0x18,0xC000), BASE, { RA } },
1327 { "rc", MFC(0x18,0xE000), BASE, { RA } },
1328 { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */
1329 { "rs", MFC(0x18,0xF000), BASE, { RA } },
1330 { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */
1331 { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */
1333 { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1334 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1335 { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1336 { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1337 { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1338 { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1339 { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1340 { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1341 { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1342 { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1343 { "pal19", PCD(0x19), BASE, ARG_PCD },
1345 { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */
1346 BASE, { ZA, CPRB } },
1347 { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1348 { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1349 { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
1350 0xFFFFFFFF, BASE, { 0 } },
1351 { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1352 { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1353 { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1355 { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1356 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1357 { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1358 { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1359 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1360 { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1361 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1362 { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1363 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1364 { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1365 { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1366 { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1367 { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1368 { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1369 { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1370 { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1371 { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1372 { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1373 { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1374 { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1375 { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1376 { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1377 { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1378 { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1379 { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1380 { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1381 { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1382 { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1383 { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1384 { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1385 { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1386 { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1387 { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1388 { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1389 { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1390 { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1391 { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1392 { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1393 { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1394 { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1395 { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1396 { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1397 { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1398 { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1399 { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1400 { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1401 { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1402 { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1403 { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1404 { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1405 { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1406 { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1407 { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1408 { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1409 { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1410 { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1411 { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1412 { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1413 { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1414 { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1415 { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1416 { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1417 { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1418 { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1419 { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1420 { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1421 { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1422 { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1423 { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1424 { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1425 { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1426 { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1427 { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1428 { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1429 { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1430 { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1431 { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1432 { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1433 { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1434 { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1435 { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1436 { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1437 { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1438 { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1439 { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1440 { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1441 { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1442 { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1443 { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1444 { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1445 { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1446 { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1447 { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1448 { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1449 { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1450 { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1451 { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1452 { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1453 { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1454 { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1455 { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1456 { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1457 { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1458 { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1459 { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1460 { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1461 { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1462 { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1463 { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1464 { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1465 { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1466 { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1467 { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1468 { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1469 { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1470 { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1471 { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1472 { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1473 { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1474 { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1475 { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1476 { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1477 { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1478 { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1479 { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1480 { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1481 { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1482 { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1483 { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1484 { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1485 { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1486 { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1487 { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1488 { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1489 { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1490 { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1491 { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1492 { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1493 { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1494 { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1495 { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1496 { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1497 { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1498 { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1499 { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1500 { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1501 { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1502 { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1503 { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1504 { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1505 { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1506 { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1507 { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1508 { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1509 { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1510 { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1511 { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1512 { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1513 { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1514 { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1515 { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1516 { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1517 { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1518 { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1519 { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1520 { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1521 { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1522 { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1523 { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1524 { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1525 { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1526 { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1527 { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1528 { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1529 { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1530 { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1531 { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1532 { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1533 { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1534 { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1535 { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1536 { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1537 { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1538 { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1539 { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1540 { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1541 { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1542 { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1543 { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1544 { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1545 { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1546 { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1547 { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1548 { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1549 { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1550 { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1551 { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1552 { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1553 { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1554 { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1555 { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1556 { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1557 { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1558 { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1559 { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1560 { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1561 { "pal1b", PCD(0x1B), BASE, ARG_PCD },
1563 { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1564 { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1565 { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1566 { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR },
1567 { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1568 { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1569 { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1570 { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1571 { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1572 { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1573 { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR },
1574 { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1575 { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR },
1576 { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1577 { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR },
1578 { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1579 { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR },
1580 { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1581 { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR },
1582 { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1583 { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR },
1584 { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1585 { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR },
1586 { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1587 { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR },
1588 { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1589 { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1590 { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1592 { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1593 { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1594 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1595 { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1596 { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1597 { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1598 { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1599 { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1600 { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1601 { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1602 { "pal1d", PCD(0x1D), BASE, ARG_PCD },
1604 { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1605 { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1606 { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1607 { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1608 { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1609 { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1610 { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1611 { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1612 { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1613 { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1614 { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1615 { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1616 { "pal1e", PCD(0x1E), BASE, ARG_PCD },
1618 { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1619 { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1620 { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1621 { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1622 { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1623 { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1624 { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1625 { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1626 { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1627 { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1628 { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1629 { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1630 { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1631 { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1632 { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1633 { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1634 { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1635 { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1636 { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1637 { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1638 { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1639 { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1640 { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1641 { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1642 { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1643 { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1644 { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1645 { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1646 { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1647 { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1648 { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1649 { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1650 { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1651 { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1652 { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1653 { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1654 { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1655 { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1656 { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1657 { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1658 { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1659 { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1660 { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1661 { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1662 { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1663 { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1664 { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1665 { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1666 { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1667 { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1668 { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1669 { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1670 { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1671 { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1672 { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1673 { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1674 { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1675 { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1676 { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1677 { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1678 { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1679 { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1680 { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1681 { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1682 { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1683 { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1684 { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1685 { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1686 { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1687 { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1688 { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1689 { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1690 { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1691 { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1692 { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1693 { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1694 { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1695 { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1696 { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1697 { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1698 { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1699 { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1700 { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1701 { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1702 { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1703 { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1704 { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1705 { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1706 { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1707 { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1708 { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1709 { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1710 { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1711 { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1712 { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1713 { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1714 { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1715 { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1716 { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1717 { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1718 { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1719 { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1720 { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1721 { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1722 { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1723 { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1724 { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1725 { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1726 { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1727 { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1728 { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1729 { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1730 { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1731 { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1732 { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1733 { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1734 { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1735 { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1736 { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1737 { "pal1f", PCD(0x1F), BASE, ARG_PCD },
1739 { "ldf", MEM(0x20), BASE, ARG_FMEM },
1740 { "ldg", MEM(0x21), BASE, ARG_FMEM },
1741 { "lds", MEM(0x22), BASE, ARG_FMEM },
1742 { "ldt", MEM(0x23), BASE, ARG_FMEM },
1743 { "stf", MEM(0x24), BASE, ARG_FMEM },
1744 { "stg", MEM(0x25), BASE, ARG_FMEM },
1745 { "sts", MEM(0x26), BASE, ARG_FMEM },
1746 { "stt", MEM(0x27), BASE, ARG_FMEM },
1748 { "ldl", MEM(0x28), BASE, ARG_MEM },
1749 { "ldq", MEM(0x29), BASE, ARG_MEM },
1750 { "ldl_l", MEM(0x2A), BASE, ARG_MEM },
1751 { "ldq_l", MEM(0x2B), BASE, ARG_MEM },
1752 { "stl", MEM(0x2C), BASE, ARG_MEM },
1753 { "stq", MEM(0x2D), BASE, ARG_MEM },
1754 { "stl_c", MEM(0x2E), BASE, ARG_MEM },
1755 { "stq_c", MEM(0x2F), BASE, ARG_MEM },
1757 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */
1758 { "br", BRA(0x30), BASE, ARG_BRA },
1759 { "fbeq", BRA(0x31), BASE, ARG_FBRA },
1760 { "fblt", BRA(0x32), BASE, ARG_FBRA },
1761 { "fble", BRA(0x33), BASE, ARG_FBRA },
1762 { "bsr", BRA(0x34), BASE, ARG_BRA },
1763 { "fbne", BRA(0x35), BASE, ARG_FBRA },
1764 { "fbge", BRA(0x36), BASE, ARG_FBRA },
1765 { "fbgt", BRA(0x37), BASE, ARG_FBRA },
1766 { "blbc", BRA(0x38), BASE, ARG_BRA },
1767 { "beq", BRA(0x39), BASE, ARG_BRA },
1768 { "blt", BRA(0x3A), BASE, ARG_BRA },
1769 { "ble", BRA(0x3B), BASE, ARG_BRA },
1770 { "blbs", BRA(0x3C), BASE, ARG_BRA },
1771 { "bne", BRA(0x3D), BASE, ARG_BRA },
1772 { "bge", BRA(0x3E), BASE, ARG_BRA },
1773 { "bgt", BRA(0x3F), BASE, ARG_BRA },
1776 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
1778 /* OSF register names. */
1780 static const char * const osf_regnames[64] = {
1781 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
1782 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
1783 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
1784 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
1785 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1786 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1787 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1788 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
1791 /* VMS register names. */
1793 static const char * const vms_regnames[64] = {
1794 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
1795 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
1796 "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
1797 "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
1798 "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
1799 "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
1800 "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
1801 "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
1804 /* Disassemble Alpha instructions. */
1807 print_insn_alpha (memaddr, info)
1809 struct disassemble_info *info;
1811 static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
1812 const char * const * regnames;
1813 const struct alpha_opcode *opcode, *opcode_end;
1814 const unsigned char *opindex;
1815 unsigned insn, op, isa_mask;
1818 /* Initialize the majorop table the first time through */
1819 if (!opcode_index[0])
1821 opcode = alpha_opcodes;
1822 opcode_end = opcode + alpha_num_opcodes;
1824 for (op = 0; op < AXP_NOPS; ++op)
1826 opcode_index[op] = opcode;
1827 while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
1830 opcode_index[op] = opcode;
1833 if (info->flavour == bfd_target_evax_flavour)
1834 regnames = vms_regnames;
1836 regnames = osf_regnames;
1838 isa_mask = AXP_OPCODE_NOPAL;
1841 case bfd_mach_alpha_ev4:
1842 isa_mask |= AXP_OPCODE_EV4;
1844 case bfd_mach_alpha_ev5:
1845 isa_mask |= AXP_OPCODE_EV5;
1847 case bfd_mach_alpha_ev6:
1848 isa_mask |= AXP_OPCODE_EV6;
1852 /* Read the insn into a host word */
1855 int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
1858 (*info->memory_error_func) (status, memaddr, info);
1861 insn = bfd_getl32 (buffer);
1864 /* Get the major opcode of the instruction. */
1867 /* Find the first match in the opcode table. */
1868 opcode_end = opcode_index[op + 1];
1869 for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
1871 if ((insn ^ opcode->opcode) & opcode->mask)
1874 if (!(opcode->flags & isa_mask))
1877 /* Make two passes over the operands. First see if any of them
1878 have extraction functions, and, if they do, make sure the
1879 instruction is valid. */
1882 for (opindex = opcode->operands; *opindex != 0; opindex++)
1884 const struct alpha_operand *operand = alpha_operands + *opindex;
1885 if (operand->extract)
1886 (*operand->extract) (insn, &invalid);
1892 /* The instruction is valid. */
1896 /* No instruction found */
1897 (*info->fprintf_func) (info->stream, ".long %#08x", insn);
1902 (*info->fprintf_func) (info->stream, "%s", opcode->name);
1903 if (opcode->operands[0] != 0)
1904 (*info->fprintf_func) (info->stream, "\t");
1906 /* Now extract and print the operands. */
1908 for (opindex = opcode->operands; *opindex != 0; opindex++)
1910 const struct alpha_operand *operand = alpha_operands + *opindex;
1913 /* Operands that are marked FAKE are simply ignored. We
1914 already made sure that the extract function considered
1915 the instruction to be valid. */
1916 if ((operand->flags & AXP_OPERAND_FAKE) != 0)
1919 /* Extract the value from the instruction. */
1920 if (operand->extract)
1921 value = (*operand->extract) (insn, (int *) NULL);
1924 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
1925 if (operand->flags & AXP_OPERAND_SIGNED)
1927 int signbit = 1 << (operand->bits - 1);
1928 value = (value ^ signbit) - signbit;
1933 ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
1934 != AXP_OPERAND_PARENS))
1936 (*info->fprintf_func) (info->stream, ",");
1938 if (operand->flags & AXP_OPERAND_PARENS)
1939 (*info->fprintf_func) (info->stream, "(");
1941 /* Print the operand as directed by the flags. */
1942 if (operand->flags & AXP_OPERAND_IR)
1943 (*info->fprintf_func) (info->stream, "%s", regnames[value]);
1944 else if (operand->flags & AXP_OPERAND_FPR)
1945 (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
1946 else if (operand->flags & AXP_OPERAND_RELATIVE)
1947 (*info->print_address_func) (memaddr + 4 + value, info);
1948 else if (operand->flags & AXP_OPERAND_SIGNED)
1949 (*info->fprintf_func) (info->stream, "%d", value);
1951 (*info->fprintf_func) (info->stream, "%#x", value);
1953 if (operand->flags & AXP_OPERAND_PARENS)
1954 (*info->fprintf_func) (info->stream, ")");
projects / qemu / blob