2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
23 #include "qemu-common.h"
25 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
29 /* some important defines:
31 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
34 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
35 * otherwise little endian.
37 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
39 * TARGET_WORDS_BIGENDIAN : same for target cpu
43 #include "softfloat.h"
45 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
51 static inline uint16_t tswap16(uint16_t s)
56 static inline uint32_t tswap32(uint32_t s)
61 static inline uint64_t tswap64(uint64_t s)
66 static inline void tswap16s(uint16_t *s)
71 static inline void tswap32s(uint32_t *s)
76 static inline void tswap64s(uint64_t *s)
83 static inline uint16_t tswap16(uint16_t s)
88 static inline uint32_t tswap32(uint32_t s)
93 static inline uint64_t tswap64(uint64_t s)
98 static inline void tswap16s(uint16_t *s)
102 static inline void tswap32s(uint32_t *s)
106 static inline void tswap64s(uint64_t *s)
112 #if TARGET_LONG_SIZE == 4
113 #define tswapl(s) tswap32(s)
114 #define tswapls(s) tswap32s((uint32_t *)(s))
115 #define bswaptls(s) bswap32s(s)
117 #define tswapl(s) tswap64(s)
118 #define tswapls(s) tswap64s((uint64_t *)(s))
119 #define bswaptls(s) bswap64s(s)
127 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
131 #if defined(WORDS_BIGENDIAN) \
132 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
149 #if defined(WORDS_BIGENDIAN) \
150 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
176 /* CPU memory access without any memory or io remapping */
179 * the generic syntax for the memory accesses is:
181 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
183 * store: st{type}{size}{endian}_{access_type}(ptr, val)
186 * (empty): integer access
190 * (empty): for floats or 32 bit size
201 * (empty): target cpu endianness or 8 bit access
202 * r : reversed target cpu endianness (not implemented yet)
203 * be : big endian (not implemented yet)
204 * le : little endian (not implemented yet)
207 * raw : host memory access
208 * user : user mode access using soft MMU
209 * kernel : kernel mode access using soft MMU
211 static inline int ldub_p(const void *ptr)
213 return *(uint8_t *)ptr;
216 static inline int ldsb_p(const void *ptr)
218 return *(int8_t *)ptr;
221 static inline void stb_p(void *ptr, int v)
226 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
227 kernel handles unaligned load/stores may give better results, but
228 it is a system wide setting : bad */
229 #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
231 /* conservative code for little endian unaligned accesses */
232 static inline int lduw_le_p(const void *ptr)
236 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
239 const uint8_t *p = ptr;
240 return p[0] | (p[1] << 8);
244 static inline int ldsw_le_p(const void *ptr)
248 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
251 const uint8_t *p = ptr;
252 return (int16_t)(p[0] | (p[1] << 8));
256 static inline int ldl_le_p(const void *ptr)
260 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
263 const uint8_t *p = ptr;
264 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
268 static inline uint64_t ldq_le_p(const void *ptr)
270 const uint8_t *p = ptr;
273 v2 = ldl_le_p(p + 4);
274 return v1 | ((uint64_t)v2 << 32);
277 static inline void stw_le_p(void *ptr, int v)
280 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
288 static inline void stl_le_p(void *ptr, int v)
291 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
301 static inline void stq_le_p(void *ptr, uint64_t v)
304 stl_le_p(p, (uint32_t)v);
305 stl_le_p(p + 4, v >> 32);
310 static inline float32 ldfl_le_p(const void *ptr)
320 static inline void stfl_le_p(void *ptr, float32 v)
330 static inline float64 ldfq_le_p(const void *ptr)
333 u.l.lower = ldl_le_p(ptr);
334 u.l.upper = ldl_le_p(ptr + 4);
338 static inline void stfq_le_p(void *ptr, float64 v)
342 stl_le_p(ptr, u.l.lower);
343 stl_le_p(ptr + 4, u.l.upper);
348 static inline int lduw_le_p(const void *ptr)
350 return *(uint16_t *)ptr;
353 static inline int ldsw_le_p(const void *ptr)
355 return *(int16_t *)ptr;
358 static inline int ldl_le_p(const void *ptr)
360 return *(uint32_t *)ptr;
363 static inline uint64_t ldq_le_p(const void *ptr)
365 return *(uint64_t *)ptr;
368 static inline void stw_le_p(void *ptr, int v)
370 *(uint16_t *)ptr = v;
373 static inline void stl_le_p(void *ptr, int v)
375 *(uint32_t *)ptr = v;
378 static inline void stq_le_p(void *ptr, uint64_t v)
380 *(uint64_t *)ptr = v;
385 static inline float32 ldfl_le_p(const void *ptr)
387 return *(float32 *)ptr;
390 static inline float64 ldfq_le_p(const void *ptr)
392 return *(float64 *)ptr;
395 static inline void stfl_le_p(void *ptr, float32 v)
400 static inline void stfq_le_p(void *ptr, float64 v)
406 #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
408 static inline int lduw_be_p(const void *ptr)
410 #if defined(__i386__)
412 asm volatile ("movzwl %1, %0\n"
415 : "m" (*(uint16_t *)ptr));
418 const uint8_t *b = ptr;
419 return ((b[0] << 8) | b[1]);
423 static inline int ldsw_be_p(const void *ptr)
425 #if defined(__i386__)
427 asm volatile ("movzwl %1, %0\n"
430 : "m" (*(uint16_t *)ptr));
433 const uint8_t *b = ptr;
434 return (int16_t)((b[0] << 8) | b[1]);
438 static inline int ldl_be_p(const void *ptr)
440 #if defined(__i386__) || defined(__x86_64__)
442 asm volatile ("movl %1, %0\n"
445 : "m" (*(uint32_t *)ptr));
448 const uint8_t *b = ptr;
449 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
453 static inline uint64_t ldq_be_p(const void *ptr)
457 b = ldl_be_p((uint8_t *)ptr + 4);
458 return (((uint64_t)a<<32)|b);
461 static inline void stw_be_p(void *ptr, int v)
463 #if defined(__i386__)
464 asm volatile ("xchgb %b0, %h0\n"
467 : "m" (*(uint16_t *)ptr), "0" (v));
469 uint8_t *d = (uint8_t *) ptr;
475 static inline void stl_be_p(void *ptr, int v)
477 #if defined(__i386__) || defined(__x86_64__)
478 asm volatile ("bswap %0\n"
481 : "m" (*(uint32_t *)ptr), "0" (v));
483 uint8_t *d = (uint8_t *) ptr;
491 static inline void stq_be_p(void *ptr, uint64_t v)
493 stl_be_p(ptr, v >> 32);
494 stl_be_p((uint8_t *)ptr + 4, v);
499 static inline float32 ldfl_be_p(const void *ptr)
509 static inline void stfl_be_p(void *ptr, float32 v)
519 static inline float64 ldfq_be_p(const void *ptr)
522 u.l.upper = ldl_be_p(ptr);
523 u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
527 static inline void stfq_be_p(void *ptr, float64 v)
531 stl_be_p(ptr, u.l.upper);
532 stl_be_p((uint8_t *)ptr + 4, u.l.lower);
537 static inline int lduw_be_p(const void *ptr)
539 return *(uint16_t *)ptr;
542 static inline int ldsw_be_p(const void *ptr)
544 return *(int16_t *)ptr;
547 static inline int ldl_be_p(const void *ptr)
549 return *(uint32_t *)ptr;
552 static inline uint64_t ldq_be_p(const void *ptr)
554 return *(uint64_t *)ptr;
557 static inline void stw_be_p(void *ptr, int v)
559 *(uint16_t *)ptr = v;
562 static inline void stl_be_p(void *ptr, int v)
564 *(uint32_t *)ptr = v;
567 static inline void stq_be_p(void *ptr, uint64_t v)
569 *(uint64_t *)ptr = v;
574 static inline float32 ldfl_be_p(const void *ptr)
576 return *(float32 *)ptr;
579 static inline float64 ldfq_be_p(const void *ptr)
581 return *(float64 *)ptr;
584 static inline void stfl_be_p(void *ptr, float32 v)
589 static inline void stfq_be_p(void *ptr, float64 v)
596 /* target CPU memory access functions */
597 #if defined(TARGET_WORDS_BIGENDIAN)
598 #define lduw_p(p) lduw_be_p(p)
599 #define ldsw_p(p) ldsw_be_p(p)
600 #define ldl_p(p) ldl_be_p(p)
601 #define ldq_p(p) ldq_be_p(p)
602 #define ldfl_p(p) ldfl_be_p(p)
603 #define ldfq_p(p) ldfq_be_p(p)
604 #define stw_p(p, v) stw_be_p(p, v)
605 #define stl_p(p, v) stl_be_p(p, v)
606 #define stq_p(p, v) stq_be_p(p, v)
607 #define stfl_p(p, v) stfl_be_p(p, v)
608 #define stfq_p(p, v) stfq_be_p(p, v)
610 #define lduw_p(p) lduw_le_p(p)
611 #define ldsw_p(p) ldsw_le_p(p)
612 #define ldl_p(p) ldl_le_p(p)
613 #define ldq_p(p) ldq_le_p(p)
614 #define ldfl_p(p) ldfl_le_p(p)
615 #define ldfq_p(p) ldfq_le_p(p)
616 #define stw_p(p, v) stw_le_p(p, v)
617 #define stl_p(p, v) stl_le_p(p, v)
618 #define stq_p(p, v) stq_le_p(p, v)
619 #define stfl_p(p, v) stfl_le_p(p, v)
620 #define stfq_p(p, v) stfq_le_p(p, v)
623 /* MMU memory access macros */
625 #if defined(CONFIG_USER_ONLY)
627 #include "qemu-types.h"
629 /* On some host systems the guest address space is reserved on the host.
630 * This allows the guest address space to be offset to a convenient location.
632 #if defined(CONFIG_USE_GUEST_BASE)
633 extern unsigned long guest_base;
634 #define GUEST_BASE guest_base
639 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
640 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
642 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
643 /* Check if given address fits target address space */ \
644 assert(__ret == (abi_ulong)__ret); \
647 #define h2g_valid(x) ({ \
648 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
649 (__guest == (abi_ulong)__guest); \
652 #define saddr(x) g2h(x)
653 #define laddr(x) g2h(x)
655 #else /* !CONFIG_USER_ONLY */
656 /* NOTE: we use double casts if pointers and target_ulong have
658 #define saddr(x) (uint8_t *)(long)(x)
659 #define laddr(x) (uint8_t *)(long)(x)
662 #define ldub_raw(p) ldub_p(laddr((p)))
663 #define ldsb_raw(p) ldsb_p(laddr((p)))
664 #define lduw_raw(p) lduw_p(laddr((p)))
665 #define ldsw_raw(p) ldsw_p(laddr((p)))
666 #define ldl_raw(p) ldl_p(laddr((p)))
667 #define ldq_raw(p) ldq_p(laddr((p)))
668 #define ldfl_raw(p) ldfl_p(laddr((p)))
669 #define ldfq_raw(p) ldfq_p(laddr((p)))
670 #define stb_raw(p, v) stb_p(saddr((p)), v)
671 #define stw_raw(p, v) stw_p(saddr((p)), v)
672 #define stl_raw(p, v) stl_p(saddr((p)), v)
673 #define stq_raw(p, v) stq_p(saddr((p)), v)
674 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
675 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
678 #if defined(CONFIG_USER_ONLY)
680 /* if user mode, no other memory access functions */
681 #define ldub(p) ldub_raw(p)
682 #define ldsb(p) ldsb_raw(p)
683 #define lduw(p) lduw_raw(p)
684 #define ldsw(p) ldsw_raw(p)
685 #define ldl(p) ldl_raw(p)
686 #define ldq(p) ldq_raw(p)
687 #define ldfl(p) ldfl_raw(p)
688 #define ldfq(p) ldfq_raw(p)
689 #define stb(p, v) stb_raw(p, v)
690 #define stw(p, v) stw_raw(p, v)
691 #define stl(p, v) stl_raw(p, v)
692 #define stq(p, v) stq_raw(p, v)
693 #define stfl(p, v) stfl_raw(p, v)
694 #define stfq(p, v) stfq_raw(p, v)
696 #define ldub_code(p) ldub_raw(p)
697 #define ldsb_code(p) ldsb_raw(p)
698 #define lduw_code(p) lduw_raw(p)
699 #define ldsw_code(p) ldsw_raw(p)
700 #define ldl_code(p) ldl_raw(p)
701 #define ldq_code(p) ldq_raw(p)
703 #define ldub_kernel(p) ldub_raw(p)
704 #define ldsb_kernel(p) ldsb_raw(p)
705 #define lduw_kernel(p) lduw_raw(p)
706 #define ldsw_kernel(p) ldsw_raw(p)
707 #define ldl_kernel(p) ldl_raw(p)
708 #define ldq_kernel(p) ldq_raw(p)
709 #define ldfl_kernel(p) ldfl_raw(p)
710 #define ldfq_kernel(p) ldfq_raw(p)
711 #define stb_kernel(p, v) stb_raw(p, v)
712 #define stw_kernel(p, v) stw_raw(p, v)
713 #define stl_kernel(p, v) stl_raw(p, v)
714 #define stq_kernel(p, v) stq_raw(p, v)
715 #define stfl_kernel(p, v) stfl_raw(p, v)
716 #define stfq_kernel(p, vt) stfq_raw(p, v)
718 #endif /* defined(CONFIG_USER_ONLY) */
720 /* page related stuff */
722 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
723 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
724 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
726 /* ??? These should be the larger of unsigned long and target_ulong. */
727 extern unsigned long qemu_real_host_page_size;
728 extern unsigned long qemu_host_page_bits;
729 extern unsigned long qemu_host_page_size;
730 extern unsigned long qemu_host_page_mask;
732 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
734 /* same as PROT_xxx */
735 #define PAGE_READ 0x0001
736 #define PAGE_WRITE 0x0002
737 #define PAGE_EXEC 0x0004
738 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
739 #define PAGE_VALID 0x0008
740 /* original state of the write flag (used when tracking self-modifying
742 #define PAGE_WRITE_ORG 0x0010
743 #define PAGE_RESERVED 0x0020
745 void page_dump(FILE *f);
746 int walk_memory_regions(void *,
747 int (*fn)(void *, unsigned long, unsigned long, unsigned long));
748 int page_get_flags(target_ulong address);
749 void page_set_flags(target_ulong start, target_ulong end, int flags);
750 int page_check_range(target_ulong start, target_ulong len, int flags);
752 void cpu_exec_init_all(unsigned long tb_size);
753 CPUState *cpu_copy(CPUState *env);
755 void cpu_dump_state(CPUState *env, FILE *f,
756 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
758 void cpu_dump_statistics (CPUState *env, FILE *f,
759 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
762 void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
763 __attribute__ ((__format__ (__printf__, 2, 3)));
764 extern CPUState *first_cpu;
765 extern CPUState *cpu_single_env;
766 extern int64_t qemu_icount;
767 extern int use_icount;
769 #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
770 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
771 #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
772 #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
773 #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
774 #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
775 #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
776 #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */
777 #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */
779 void cpu_interrupt(CPUState *s, int mask);
780 void cpu_reset_interrupt(CPUState *env, int mask);
782 void cpu_exit(CPUState *s);
784 int qemu_cpu_has_work(CPUState *env);
786 /* Breakpoint/watchpoint flags */
787 #define BP_MEM_READ 0x01
788 #define BP_MEM_WRITE 0x02
789 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
790 #define BP_STOP_BEFORE_ACCESS 0x04
791 #define BP_WATCHPOINT_HIT 0x08
795 int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
796 CPUBreakpoint **breakpoint);
797 int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags);
798 void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
799 void cpu_breakpoint_remove_all(CPUState *env, int mask);
800 int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
801 int flags, CPUWatchpoint **watchpoint);
802 int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
803 target_ulong len, int flags);
804 void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
805 void cpu_watchpoint_remove_all(CPUState *env, int mask);
807 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
808 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
809 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
811 void cpu_single_step(CPUState *env, int enabled);
812 void cpu_reset(CPUState *s);
814 /* Return the physical page corresponding to a virtual one. Use it
815 only for debugging because no protection checks are done. Return -1
817 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
819 #define CPU_LOG_TB_OUT_ASM (1 << 0)
820 #define CPU_LOG_TB_IN_ASM (1 << 1)
821 #define CPU_LOG_TB_OP (1 << 2)
822 #define CPU_LOG_TB_OP_OPT (1 << 3)
823 #define CPU_LOG_INT (1 << 4)
824 #define CPU_LOG_EXEC (1 << 5)
825 #define CPU_LOG_PCALL (1 << 6)
826 #define CPU_LOG_IOPORT (1 << 7)
827 #define CPU_LOG_TB_CPU (1 << 8)
828 #define CPU_LOG_RESET (1 << 9)
830 /* define log items */
831 typedef struct CPULogItem {
837 extern const CPULogItem cpu_log_items[];
839 void cpu_set_log(int log_flags);
840 void cpu_set_log_filename(const char *filename);
841 int cpu_str_to_log_mask(const char *str);
845 /* NOTE: as these functions may be even used when there is an isa
846 brige on non x86 targets, we always defined them */
847 #ifndef NO_CPU_IO_DEFS
848 void cpu_outb(CPUState *env, int addr, int val);
849 void cpu_outw(CPUState *env, int addr, int val);
850 void cpu_outl(CPUState *env, int addr, int val);
851 int cpu_inb(CPUState *env, int addr);
852 int cpu_inw(CPUState *env, int addr);
853 int cpu_inl(CPUState *env, int addr);
856 /* address in the RAM (different from a physical address) */
858 typedef uint32_t ram_addr_t;
860 typedef unsigned long ram_addr_t;
865 extern int phys_ram_fd;
866 extern uint8_t *phys_ram_dirty;
867 extern ram_addr_t ram_size;
868 extern ram_addr_t last_ram_offset;
870 /* physical memory access */
872 /* MMIO pages are identified by a combination of an IO device index and
873 3 flags. The ROMD code stores the page ram offset in iotlb entry,
874 so only a limited number of ids are avaiable. */
876 #define IO_MEM_SHIFT 3
877 #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
879 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
880 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
881 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
882 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
884 /* Acts like a ROM when read and like a device when written. */
885 #define IO_MEM_ROMD (1)
886 #define IO_MEM_SUBPAGE (2)
887 #define IO_MEM_SUBWIDTH (4)
889 /* Flags stored in the low bits of the TLB virtual address. These are
890 defined so that fast path ram access is all zeros. */
891 /* Zero if TLB entry is valid. */
892 #define TLB_INVALID_MASK (1 << 3)
893 /* Set if TLB entry references a clean RAM page. The iotlb entry will
894 contain the page physical address. */
895 #define TLB_NOTDIRTY (1 << 4)
896 /* Set if TLB entry is an IO callback. */
897 #define TLB_MMIO (1 << 5)
899 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
900 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
902 void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
904 ram_addr_t phys_offset,
905 ram_addr_t region_offset);
906 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
908 ram_addr_t phys_offset)
910 cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
913 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
914 ram_addr_t qemu_ram_alloc(ram_addr_t);
915 void qemu_ram_free(ram_addr_t addr);
916 /* This should only be used for ram local to a device. */
917 void *qemu_get_ram_ptr(ram_addr_t addr);
918 /* This should not be used by devices. */
919 ram_addr_t qemu_ram_addr_from_host(void *ptr);
921 int cpu_register_io_memory(int io_index,
922 CPUReadMemoryFunc **mem_read,
923 CPUWriteMemoryFunc **mem_write,
925 void cpu_unregister_io_memory(int table_address);
927 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
928 int len, int is_write);
929 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
930 uint8_t *buf, int len)
932 cpu_physical_memory_rw(addr, buf, len, 0);
934 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
935 const uint8_t *buf, int len)
937 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
939 void *cpu_physical_memory_map(target_phys_addr_t addr,
940 target_phys_addr_t *plen,
942 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
943 int is_write, target_phys_addr_t access_len);
944 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
945 void cpu_unregister_map_client(void *cookie);
947 uint32_t ldub_phys(target_phys_addr_t addr);
948 uint32_t lduw_phys(target_phys_addr_t addr);
949 uint32_t ldl_phys(target_phys_addr_t addr);
950 uint64_t ldq_phys(target_phys_addr_t addr);
951 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
952 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
953 void stb_phys(target_phys_addr_t addr, uint32_t val);
954 void stw_phys(target_phys_addr_t addr, uint32_t val);
955 void stl_phys(target_phys_addr_t addr, uint32_t val);
956 void stq_phys(target_phys_addr_t addr, uint64_t val);
958 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
959 const uint8_t *buf, int len);
960 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
961 uint8_t *buf, int len, int is_write);
963 #define VGA_DIRTY_FLAG 0x01
964 #define CODE_DIRTY_FLAG 0x02
965 #define KQEMU_DIRTY_FLAG 0x04
966 #define MIGRATION_DIRTY_FLAG 0x08
968 /* read dirty bit (return 0 or 1) */
969 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
971 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
974 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
977 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
980 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
982 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
985 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
987 void cpu_tlb_update_dirty(CPUState *env);
989 int cpu_physical_memory_set_dirty_tracking(int enable);
991 int cpu_physical_memory_get_dirty_tracking(void);
993 void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr);
995 void dump_exec_info(FILE *f,
996 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
998 /* Coalesced MMIO regions are areas where write operations can be reordered.
999 * This usually implies that write operations are side-effect free. This allows
1000 * batching which can make a major impact on performance when using
1003 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
1005 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
1007 /*******************************************/
1008 /* host CPU ticks (if available) */
1010 #if defined(_ARCH_PPC)
1012 static inline int64_t cpu_get_real_ticks(void)
1016 /* This reads timebase in one 64bit go and includes Cell workaround from:
1017 http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html
1019 __asm__ __volatile__ (
1025 /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */
1027 __asm__ __volatile__ (
1033 : "=r" (retval), "=r" (junk));
1038 #elif defined(__i386__)
1040 static inline int64_t cpu_get_real_ticks(void)
1043 asm volatile ("rdtsc" : "=A" (val));
1047 #elif defined(__x86_64__)
1049 static inline int64_t cpu_get_real_ticks(void)
1053 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1060 #elif defined(__hppa__)
1062 static inline int64_t cpu_get_real_ticks(void)
1065 asm volatile ("mfctl %%cr16, %0" : "=r"(val));
1069 #elif defined(__ia64)
1071 static inline int64_t cpu_get_real_ticks(void)
1074 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
1078 #elif defined(__s390__)
1080 static inline int64_t cpu_get_real_ticks(void)
1083 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
1087 #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
1089 static inline int64_t cpu_get_real_ticks (void)
1093 asm volatile("rd %%tick,%0" : "=r"(rval));
1103 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1104 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1109 #elif defined(__mips__)
1111 static inline int64_t cpu_get_real_ticks(void)
1113 #if __mips_isa_rev >= 2
1115 static uint32_t cyc_per_count = 0;
1118 __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count));
1120 __asm__ __volatile__("rdhwr %1, $2" : "=r" (count));
1121 return (int64_t)(count * cyc_per_count);
1124 static int64_t ticks = 0;
1130 /* The host CPU doesn't have an easily accessible cycle counter.
1131 Just return a monotonically increasing value. This will be
1132 totally wrong, but hopefully better than nothing. */
1133 static inline int64_t cpu_get_real_ticks (void)
1135 static int64_t ticks = 0;
1141 #ifdef CONFIG_PROFILER
1142 static inline int64_t profile_getclock(void)
1144 return cpu_get_real_ticks();
1147 extern int64_t kqemu_time, kqemu_time_start;
1148 extern int64_t qemu_time, qemu_time_start;
1149 extern int64_t tlb_flush_time;
1150 extern int64_t kqemu_exec_count;
1151 extern int64_t dev_time;
1152 extern int64_t kqemu_ret_int_count;
1153 extern int64_t kqemu_ret_excp_count;
1154 extern int64_t kqemu_ret_intr_count;
1157 #endif /* CPU_ALL_H */