git.maemo.org Git - qemu/blob - cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_DEFS_H
  21 #define CPU_DEFS_H
  22
  23 #ifndef NEED_CPU_H
  24 #error cpu.h included from common code
  25 #endif
  26
  27 #include "config.h"
  28 #include <setjmp.h>
  29 #include <inttypes.h>
  30 #include "osdep.h"
  31
  32 #ifndef TARGET_LONG_BITS
  33 #error TARGET_LONG_BITS must be defined before including this header
  34 #endif
  35
  36 #ifndef TARGET_PHYS_ADDR_BITS
  37 #if TARGET_LONG_BITS >= HOST_LONG_BITS
  38 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
  39 #else
  40 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
  41 #endif
  42 #endif
  43
  44 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  45
  46 /* target_ulong is the type of a virtual address */
  47 #if TARGET_LONG_SIZE == 4
  48 typedef int32_t target_long;
  49 typedef uint32_t target_ulong;
  50 #define TARGET_FMT_lx "%08x"
  51 #define TARGET_FMT_ld "%d"
  52 #define TARGET_FMT_lu "%u"
  53 #elif TARGET_LONG_SIZE == 8
  54 typedef int64_t target_long;
  55 typedef uint64_t target_ulong;
  56 #define TARGET_FMT_lx "%016" PRIx64
  57 #define TARGET_FMT_ld "%" PRId64
  58 #define TARGET_FMT_lu "%" PRIu64
  59 #else
  60 #error TARGET_LONG_SIZE undefined
  61 #endif
  62
  63 /* target_phys_addr_t is the type of a physical address (its size can
  64    be different from 'target_ulong'). We have sizeof(target_phys_addr)
  65    = max(sizeof(unsigned long),
  66    sizeof(size_of_target_physical_address)) because we must pass a
  67    host pointer to memory operations in some cases */
  68
  69 #if TARGET_PHYS_ADDR_BITS == 32
  70 typedef uint32_t target_phys_addr_t;
  71 #define TARGET_FMT_plx "%08x"
  72 #elif TARGET_PHYS_ADDR_BITS == 64
  73 typedef uint64_t target_phys_addr_t;
  74 #define TARGET_FMT_plx "%016" PRIx64
  75 #else
  76 #error TARGET_PHYS_ADDR_BITS undefined
  77 #endif
  78
  79 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
  80
  81 #define EXCP_INTERRUPT  0x10000 /* async interruption */
  82 #define EXCP_HLT        0x10001 /* hlt instruction reached */
  83 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  84 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  85 #define MAX_BREAKPOINTS 32
  86 #define MAX_WATCHPOINTS 32
  87
  88 #define TB_JMP_CACHE_BITS 12
  89 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
  90
  91 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
  92    addresses on the same page.  The top bits are the same.  This allows
  93    TLB invalidation to quickly clear a subset of the hash table.  */
  94 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
  95 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
  96 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
  97 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
  98
  99 #define CPU_TLB_BITS 8
 100 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
 101
 102 #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
 103 #define CPU_TLB_ENTRY_BITS 4
 104 #else
 105 #define CPU_TLB_ENTRY_BITS 5
 106 #endif
 107
 108 typedef struct CPUTLBEntry {
 109     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
 110        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
 111                                     go directly to ram.
 112        bit 3                      : indicates that the entry is invalid
 113        bit 2..0                   : zero
 114     */
 115     target_ulong addr_read;
 116     target_ulong addr_write;
 117     target_ulong addr_code;
 118     /* Addend to virtual address to get physical address.  IO accesses
 119        use the correcponding iotlb value.  */
 120 #if TARGET_PHYS_ADDR_BITS == 64
 121     /* on i386 Linux make sure it is aligned */
 122     target_phys_addr_t addend __attribute__((aligned(8)));
 123 #else
 124     target_phys_addr_t addend;
 125 #endif
 126     /* padding to get a power of two size */
 127     uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
 128                   (sizeof(target_ulong) * 3 +
 129                    ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
 130                    sizeof(target_phys_addr_t))];
 131 } CPUTLBEntry;
 132
 133 #ifdef WORDS_BIGENDIAN
 134 typedef struct icount_decr_u16 {
 135     uint16_t high;
 136     uint16_t low;
 137 } icount_decr_u16;
 138 #else
 139 typedef struct icount_decr_u16 {
 140     uint16_t low;
 141     uint16_t high;
 142 } icount_decr_u16;
 143 #endif
 144
 145 #define CPU_TEMP_BUF_NLONGS 128
 146 #define CPU_COMMON                                                      \
 147     struct TranslationBlock *current_tb; /* currently executing TB  */  \
 148     /* soft mmu support */                                              \
 149     /* in order to avoid passing too many arguments to the MMIO         \
 150        helpers, we store some rarely used information in the CPU        \
 151        context) */                                                      \
 152     unsigned long mem_io_pc; /* host pc at which the memory was         \
 153                                 accessed */                             \
 154     target_ulong mem_io_vaddr; /* target virtual addr at which the      \
 155                                      memory was accessed */             \
 156     uint32_t halted; /* Nonzero if the CPU is in suspend state */       \
 157     uint32_t interrupt_request;                                         \
 158     /* The meaning of the MMU modes is defined in the target code. */   \
 159     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 160     target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
 161     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
 162     /* buffer for temporaries in the code generator */                  \
 163     long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
 164                                                                         \
 165     int64_t icount_extra; /* Instructions until next timer event.  */   \
 166     /* Number of cycles left, with interrupt flag in high bit.          \
 167        This allows a single read-compare-cbranch-write sequence to test \
 168        for both decrementer underflow and exceptions.  */               \
 169     union {                                                             \
 170         uint32_t u32;                                                   \
 171         icount_decr_u16 u16;                                            \
 172     } icount_decr;                                                      \
 173     uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
 174                                                                         \
 175     /* from this point: preserved by CPU reset */                       \
 176     /* ice debug support */                                             \
 177     target_ulong breakpoints[MAX_BREAKPOINTS];                          \
 178     int nb_breakpoints;                                                 \
 179     int singlestep_enabled;                                             \
 180                                                                         \
 181     struct {                                                            \
 182         target_ulong vaddr;                                             \
 183         int type; /* PAGE_READ/PAGE_WRITE */                            \
 184     } watchpoint[MAX_WATCHPOINTS];                                      \
 185     int nb_watchpoints;                                                 \
 186     int watchpoint_hit;                                                 \
 187                                                                         \
 188     /* Core interrupt code */                                           \
 189     jmp_buf jmp_env;                                                    \
 190     int exception_index;                                                \
 191                                                                         \
 192     int user_mode_only;                                                 \
 193                                                                         \
 194     void *next_cpu; /* next CPU sharing TB cache */                     \
 195     int cpu_index; /* CPU index (informative) */                        \
 196     int running; /* Nonzero if cpu is currently running(usermode).  */  \
 197     /* user data */                                                     \
 198     void *opaque;                                                       \
 199                                                                         \
 200     const char *cpu_model_str;
 201
 202 #endif