4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifdef CONFIG_USER_ONLY
35 #include "qemu_socket.h"
37 /* XXX: these constants may be independent of the host ones even for Unix */
56 /* XXX: This is not thread safe. Do we care? */
57 static int gdbserver_fd = -1;
59 typedef struct GDBState {
60 CPUState *env; /* current CPU */
61 enum RSState state; /* parsing state */
66 #ifdef CONFIG_USER_ONLY
71 #ifdef CONFIG_USER_ONLY
72 /* XXX: remove this hack. */
73 static GDBState gdbserver_state;
76 static int get_char(GDBState *s)
82 ret = recv(s->fd, &ch, 1, 0);
84 if (errno != EINTR && errno != EAGAIN)
86 } else if (ret == 0) {
95 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
100 ret = send(s->fd, buf, len, 0);
102 if (errno != EINTR && errno != EAGAIN)
111 static inline int fromhex(int v)
113 if (v >= '0' && v <= '9')
115 else if (v >= 'A' && v <= 'F')
117 else if (v >= 'a' && v <= 'f')
123 static inline int tohex(int v)
131 static void memtohex(char *buf, const uint8_t *mem, int len)
136 for(i = 0; i < len; i++) {
138 *q++ = tohex(c >> 4);
139 *q++ = tohex(c & 0xf);
144 static void hextomem(uint8_t *mem, const char *buf, int len)
148 for(i = 0; i < len; i++) {
149 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
154 /* return -1 if error, 0 if OK */
155 static int put_packet(GDBState *s, char *buf)
158 int len, csum, ch, i;
161 printf("reply='%s'\n", buf);
166 put_buffer(s, buf1, 1);
168 put_buffer(s, buf, len);
170 for(i = 0; i < len; i++) {
174 buf1[1] = tohex((csum >> 4) & 0xf);
175 buf1[2] = tohex((csum) & 0xf);
177 put_buffer(s, buf1, 3);
188 #if defined(TARGET_I386)
190 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
192 uint32_t *registers = (uint32_t *)mem_buf;
195 for(i = 0; i < 8; i++) {
196 registers[i] = env->regs[i];
198 registers[8] = env->eip;
199 registers[9] = env->eflags;
200 registers[10] = env->segs[R_CS].selector;
201 registers[11] = env->segs[R_SS].selector;
202 registers[12] = env->segs[R_DS].selector;
203 registers[13] = env->segs[R_ES].selector;
204 registers[14] = env->segs[R_FS].selector;
205 registers[15] = env->segs[R_GS].selector;
206 /* XXX: convert floats */
207 for(i = 0; i < 8; i++) {
208 memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
210 registers[36] = env->fpuc;
211 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
212 registers[37] = fpus;
213 registers[38] = 0; /* XXX: convert tags */
214 registers[39] = 0; /* fiseg */
215 registers[40] = 0; /* fioff */
216 registers[41] = 0; /* foseg */
217 registers[42] = 0; /* fooff */
218 registers[43] = 0; /* fop */
220 for(i = 0; i < 16; i++)
221 tswapls(®isters[i]);
222 for(i = 36; i < 44; i++)
223 tswapls(®isters[i]);
227 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
229 uint32_t *registers = (uint32_t *)mem_buf;
232 for(i = 0; i < 8; i++) {
233 env->regs[i] = tswapl(registers[i]);
235 env->eip = tswapl(registers[8]);
236 env->eflags = tswapl(registers[9]);
237 #if defined(CONFIG_USER_ONLY)
238 #define LOAD_SEG(index, sreg)\
239 if (tswapl(registers[index]) != env->segs[sreg].selector)\
240 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
250 #elif defined (TARGET_PPC)
251 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
253 uint32_t *registers = (uint32_t *)mem_buf, tmp;
257 for(i = 0; i < 32; i++) {
258 registers[i] = tswapl(env->gpr[i]);
261 for (i = 0; i < 32; i++) {
262 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
263 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
265 /* nip, msr, ccr, lnk, ctr, xer, mq */
266 registers[96] = tswapl(env->nip);
267 registers[97] = tswapl(do_load_msr(env));
269 for (i = 0; i < 8; i++)
270 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
271 registers[98] = tswapl(tmp);
272 registers[99] = tswapl(env->lr);
273 registers[100] = tswapl(env->ctr);
274 registers[101] = tswapl(do_load_xer(env));
280 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
282 uint32_t *registers = (uint32_t *)mem_buf;
286 for (i = 0; i < 32; i++) {
287 env->gpr[i] = tswapl(registers[i]);
290 for (i = 0; i < 32; i++) {
291 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
292 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
294 /* nip, msr, ccr, lnk, ctr, xer, mq */
295 env->nip = tswapl(registers[96]);
296 do_store_msr(env, tswapl(registers[97]));
297 registers[98] = tswapl(registers[98]);
298 for (i = 0; i < 8; i++)
299 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
300 env->lr = tswapl(registers[99]);
301 env->ctr = tswapl(registers[100]);
302 do_store_xer(env, tswapl(registers[101]));
304 #elif defined (TARGET_SPARC)
305 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
307 target_ulong *registers = (target_ulong *)mem_buf;
311 for(i = 0; i < 8; i++) {
312 registers[i] = tswapl(env->gregs[i]);
314 /* fill in register window */
315 for(i = 0; i < 24; i++) {
316 registers[i + 8] = tswapl(env->regwptr[i]);
318 #ifndef TARGET_SPARC64
320 for (i = 0; i < 32; i++) {
321 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
323 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
324 registers[64] = tswapl(env->y);
329 registers[65] = tswapl(tmp);
331 registers[66] = tswapl(env->wim);
332 registers[67] = tswapl(env->tbr);
333 registers[68] = tswapl(env->pc);
334 registers[69] = tswapl(env->npc);
335 registers[70] = tswapl(env->fsr);
336 registers[71] = 0; /* csr */
338 return 73 * sizeof(target_ulong);
341 for (i = 0; i < 64; i += 2) {
344 tmp = (uint64_t)tswap32(*((uint32_t *)&env->fpr[i])) << 32;
345 tmp |= tswap32(*((uint32_t *)&env->fpr[i + 1]));
346 registers[i/2 + 32] = tmp;
348 registers[64] = tswapl(env->pc);
349 registers[65] = tswapl(env->npc);
350 registers[66] = tswapl(env->tstate[env->tl]);
351 registers[67] = tswapl(env->fsr);
352 registers[68] = tswapl(env->fprs);
353 registers[69] = tswapl(env->y);
354 return 70 * sizeof(target_ulong);
358 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
360 target_ulong *registers = (target_ulong *)mem_buf;
364 for(i = 0; i < 7; i++) {
365 env->gregs[i] = tswapl(registers[i]);
367 /* fill in register window */
368 for(i = 0; i < 24; i++) {
369 env->regwptr[i] = tswapl(registers[i + 8]);
371 #ifndef TARGET_SPARC64
373 for (i = 0; i < 32; i++) {
374 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
376 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
377 env->y = tswapl(registers[64]);
378 PUT_PSR(env, tswapl(registers[65]));
379 env->wim = tswapl(registers[66]);
380 env->tbr = tswapl(registers[67]);
381 env->pc = tswapl(registers[68]);
382 env->npc = tswapl(registers[69]);
383 env->fsr = tswapl(registers[70]);
385 for (i = 0; i < 64; i += 2) {
386 *((uint32_t *)&env->fpr[i]) = tswap32(registers[i/2 + 32] >> 32);
387 *((uint32_t *)&env->fpr[i + 1]) = tswap32(registers[i/2 + 32] & 0xffffffff);
389 env->pc = tswapl(registers[64]);
390 env->npc = tswapl(registers[65]);
391 env->tstate[env->tl] = tswapl(registers[66]);
392 env->fsr = tswapl(registers[67]);
393 env->fprs = tswapl(registers[68]);
394 env->y = tswapl(registers[69]);
397 #elif defined (TARGET_ARM)
398 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
404 /* 16 core integer registers (4 bytes each). */
405 for (i = 0; i < 16; i++)
407 *(uint32_t *)ptr = tswapl(env->regs[i]);
410 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
411 Not yet implemented. */
412 memset (ptr, 0, 8 * 12 + 4);
414 /* CPSR (4 bytes). */
415 *(uint32_t *)ptr = tswapl (cpsr_read(env));
418 return ptr - mem_buf;
421 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
427 /* Core integer registers. */
428 for (i = 0; i < 16; i++)
430 env->regs[i] = tswapl(*(uint32_t *)ptr);
433 /* Ignore FPA regs and scr. */
435 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
437 #elif defined (TARGET_M68K)
438 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
446 for (i = 0; i < 8; i++) {
447 *(uint32_t *)ptr = tswapl(env->dregs[i]);
451 for (i = 0; i < 8; i++) {
452 *(uint32_t *)ptr = tswapl(env->aregs[i]);
455 *(uint32_t *)ptr = tswapl(env->sr);
457 *(uint32_t *)ptr = tswapl(env->pc);
459 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
460 ColdFire has 8-bit double precision registers. */
461 for (i = 0; i < 8; i++) {
463 *(uint32_t *)ptr = tswap32(u.l.upper);
464 *(uint32_t *)ptr = tswap32(u.l.lower);
466 /* FP control regs (not implemented). */
467 memset (ptr, 0, 3 * 4);
470 return ptr - mem_buf;
473 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
481 for (i = 0; i < 8; i++) {
482 env->dregs[i] = tswapl(*(uint32_t *)ptr);
486 for (i = 0; i < 8; i++) {
487 env->aregs[i] = tswapl(*(uint32_t *)ptr);
490 env->sr = tswapl(*(uint32_t *)ptr);
492 env->pc = tswapl(*(uint32_t *)ptr);
494 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
495 ColdFire has 8-bit double precision registers. */
496 for (i = 0; i < 8; i++) {
497 u.l.upper = tswap32(*(uint32_t *)ptr);
498 u.l.lower = tswap32(*(uint32_t *)ptr);
501 /* FP control regs (not implemented). */
504 #elif defined (TARGET_MIPS)
505 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
511 for (i = 0; i < 32; i++)
513 *(uint32_t *)ptr = tswapl(env->gpr[i]);
517 *(uint32_t *)ptr = tswapl(env->CP0_Status);
520 *(uint32_t *)ptr = tswapl(env->LO);
523 *(uint32_t *)ptr = tswapl(env->HI);
526 *(uint32_t *)ptr = tswapl(env->CP0_BadVAddr);
529 *(uint32_t *)ptr = tswapl(env->CP0_Cause);
532 *(uint32_t *)ptr = tswapl(env->PC);
535 /* 32 FP registers, fsr, fir, fp. Not yet implemented. */
537 return ptr - mem_buf;
540 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
546 for (i = 0; i < 32; i++)
548 env->gpr[i] = tswapl(*(uint32_t *)ptr);
552 env->CP0_Status = tswapl(*(uint32_t *)ptr);
555 env->LO = tswapl(*(uint32_t *)ptr);
558 env->HI = tswapl(*(uint32_t *)ptr);
561 env->CP0_BadVAddr = tswapl(*(uint32_t *)ptr);
564 env->CP0_Cause = tswapl(*(uint32_t *)ptr);
567 env->PC = tswapl(*(uint32_t *)ptr);
570 #elif defined (TARGET_SH4)
571 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
573 uint32_t *ptr = (uint32_t *)mem_buf;
576 #define SAVE(x) *ptr++=tswapl(x)
577 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
578 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
580 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
582 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
590 SAVE (0); /* TICKS */
591 SAVE (0); /* STALLS */
592 SAVE (0); /* CYCLES */
593 SAVE (0); /* INSTS */
596 return ((uint8_t *)ptr - mem_buf);
599 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
601 uint32_t *ptr = (uint32_t *)mem_buf;
604 #define LOAD(x) (x)=*ptr++;
605 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
606 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
608 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
610 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
620 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
625 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
631 static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
634 int ch, reg_size, type;
636 uint8_t mem_buf[2000];
638 target_ulong addr, len;
641 printf("command='%s'\n", line_buf);
647 /* TODO: Make this return the correct value for user-mode. */
648 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
653 addr = strtoull(p, (char **)&p, 16);
654 #if defined(TARGET_I386)
656 #elif defined (TARGET_PPC)
658 #elif defined (TARGET_SPARC)
661 #elif defined (TARGET_ARM)
662 env->regs[15] = addr;
663 #elif defined (TARGET_SH4)
667 #ifdef CONFIG_USER_ONLY
668 s->running_state = 1;
675 addr = strtoul(p, (char **)&p, 16);
676 #if defined(TARGET_I386)
678 #elif defined (TARGET_PPC)
680 #elif defined (TARGET_SPARC)
683 #elif defined (TARGET_ARM)
684 env->regs[15] = addr;
685 #elif defined (TARGET_SH4)
689 cpu_single_step(env, 1);
690 #ifdef CONFIG_USER_ONLY
691 s->running_state = 1;
697 reg_size = cpu_gdb_read_registers(env, mem_buf);
698 memtohex(buf, mem_buf, reg_size);
702 registers = (void *)mem_buf;
704 hextomem((uint8_t *)registers, p, len);
705 cpu_gdb_write_registers(env, mem_buf, len);
709 addr = strtoull(p, (char **)&p, 16);
712 len = strtoull(p, NULL, 16);
713 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
714 put_packet (s, "E14");
716 memtohex(buf, mem_buf, len);
721 addr = strtoull(p, (char **)&p, 16);
724 len = strtoull(p, (char **)&p, 16);
727 hextomem(mem_buf, p, len);
728 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
729 put_packet(s, "E14");
734 type = strtoul(p, (char **)&p, 16);
737 addr = strtoull(p, (char **)&p, 16);
740 len = strtoull(p, (char **)&p, 16);
741 if (type == 0 || type == 1) {
742 if (cpu_breakpoint_insert(env, addr) < 0)
743 goto breakpoint_error;
747 put_packet(s, "E22");
751 type = strtoul(p, (char **)&p, 16);
754 addr = strtoull(p, (char **)&p, 16);
757 len = strtoull(p, (char **)&p, 16);
758 if (type == 0 || type == 1) {
759 cpu_breakpoint_remove(env, addr);
762 goto breakpoint_error;
765 #ifdef CONFIG_USER_ONLY
767 if (strncmp(p, "Offsets", 7) == 0) {
768 TaskState *ts = env->opaque;
770 sprintf(buf, "Text=%x;Data=%x;Bss=%x", ts->info->code_offset,
771 ts->info->data_offset, ts->info->data_offset);
779 /* put empty packet */
787 extern void tb_flush(CPUState *env);
789 #ifndef CONFIG_USER_ONLY
790 static void gdb_vm_stopped(void *opaque, int reason)
792 GDBState *s = opaque;
796 /* disable single step if it was enable */
797 cpu_single_step(s->env, 0);
799 if (reason == EXCP_DEBUG) {
802 } else if (reason == EXCP_INTERRUPT) {
807 snprintf(buf, sizeof(buf), "S%02x", ret);
812 static void gdb_read_byte(GDBState *s, int ch)
814 CPUState *env = s->env;
818 #ifndef CONFIG_USER_ONLY
820 /* when the CPU is running, we cannot do anything except stop
821 it when receiving a char */
822 vm_stop(EXCP_INTERRUPT);
829 s->line_buf_index = 0;
830 s->state = RS_GETLINE;
835 s->state = RS_CHKSUM1;
836 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
839 s->line_buf[s->line_buf_index++] = ch;
843 s->line_buf[s->line_buf_index] = '\0';
844 s->line_csum = fromhex(ch) << 4;
845 s->state = RS_CHKSUM2;
848 s->line_csum |= fromhex(ch);
850 for(i = 0; i < s->line_buf_index; i++) {
851 csum += s->line_buf[i];
853 if (s->line_csum != (csum & 0xff)) {
855 put_buffer(s, reply, 1);
859 put_buffer(s, reply, 1);
860 s->state = gdb_handle_packet(s, env, s->line_buf);
867 #ifdef CONFIG_USER_ONLY
869 gdb_handlesig (CPUState *env, int sig)
875 if (gdbserver_fd < 0)
878 s = &gdbserver_state;
880 /* disable single step if it was enabled */
881 cpu_single_step(env, 0);
886 snprintf(buf, sizeof(buf), "S%02x", sig);
892 s->running_state = 0;
893 while (s->running_state == 0) {
894 n = read (s->fd, buf, 256);
899 for (i = 0; i < n; i++)
900 gdb_read_byte (s, buf[i]);
902 else if (n == 0 || errno != EAGAIN)
904 /* XXX: Connection closed. Should probably wait for annother
905 connection before continuing. */
912 /* Tell the remote gdb that the process has exited. */
913 void gdb_exit(CPUState *env, int code)
918 if (gdbserver_fd < 0)
921 s = &gdbserver_state;
923 snprintf(buf, sizeof(buf), "W%02x", code);
928 static void gdb_read(void *opaque)
930 GDBState *s = opaque;
934 size = recv(s->fd, buf, sizeof(buf), 0);
938 /* end of connection */
939 qemu_del_vm_stop_handler(gdb_vm_stopped, s);
940 qemu_set_fd_handler(s->fd, NULL, NULL, NULL);
944 for(i = 0; i < size; i++)
945 gdb_read_byte(s, buf[i]);
951 static void gdb_accept(void *opaque)
954 struct sockaddr_in sockaddr;
959 len = sizeof(sockaddr);
960 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
961 if (fd < 0 && errno != EINTR) {
964 } else if (fd >= 0) {
969 /* set short latency */
971 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
973 #ifdef CONFIG_USER_ONLY
974 s = &gdbserver_state;
975 memset (s, 0, sizeof (GDBState));
977 s = qemu_mallocz(sizeof(GDBState));
983 s->env = first_cpu; /* XXX: allow to change CPU */
986 #ifdef CONFIG_USER_ONLY
987 fcntl(fd, F_SETFL, O_NONBLOCK);
989 socket_set_nonblock(fd);
992 vm_stop(EXCP_INTERRUPT);
994 /* start handling I/O */
995 qemu_set_fd_handler(s->fd, gdb_read, NULL, s);
996 /* when the VM is stopped, the following callback is called */
997 qemu_add_vm_stop_handler(gdb_vm_stopped, s);
1001 static int gdbserver_open(int port)
1003 struct sockaddr_in sockaddr;
1006 fd = socket(PF_INET, SOCK_STREAM, 0);
1012 /* allow fast reuse */
1014 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
1016 sockaddr.sin_family = AF_INET;
1017 sockaddr.sin_port = htons(port);
1018 sockaddr.sin_addr.s_addr = 0;
1019 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1024 ret = listen(fd, 0);
1029 #ifndef CONFIG_USER_ONLY
1030 socket_set_nonblock(fd);
1035 int gdbserver_start(int port)
1037 gdbserver_fd = gdbserver_open(port);
1038 if (gdbserver_fd < 0)
1040 /* accept connections */
1041 #ifdef CONFIG_USER_ONLY
1044 qemu_set_fd_handler(gdbserver_fd, gdb_accept, NULL, NULL);