2 * Epson S1D13744/S1D13745 (Blizzard/Hailstorm/Tornado) LCD/TV controller.
4 * Copyright (C) 2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "qemu-common.h"
27 #include "pixel_ops.h"
29 typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int);
77 uint8_t hssi_config[3];
84 uint8_t tv_filter_config;
85 uint8_t tv_filter_idx;
86 uint8_t tv_filter_coeff[0x20];
92 uint8_t gamma_lut[0x100];
94 uint8_t matrix_coeff[0x12];
104 uint8_t gpio_edge[2];
123 /* Bytes(!) per pixel */
124 static const int blizzard_iformat_bpp[0x10] = {
127 3, /* RGB 6:6:6 mode 1 */
128 3, /* RGB 8:8:8 mode 1 */
130 4, /* RGB 6:6:6 mode 2 */
131 4, /* RGB 8:8:8 mode 2 */
138 #include "blizzard_template.h"
140 #include "blizzard_template.h"
142 #include "blizzard_template.h"
144 #include "blizzard_template.h"
146 #include "blizzard_template.h"
148 static inline void blizzard_rgb2yuv(int r, int g, int b,
149 int *y, int *u, int *v)
151 *y = 0x10 + ((0x838 * r + 0x1022 * g + 0x322 * b) >> 13);
152 *u = 0x80 + ((0xe0e * b - 0x04c1 * r - 0x94e * g) >> 13);
153 *v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13);
156 static void blizzard_window(struct blizzard_s *s)
162 blizzard_fn_t fn = 0;
164 /* FIXME: this is a hack - but nseries.c will use this function
165 * before correct DisplayState is initialized so we need a way to
166 * avoid drawing something when we actually have no clue about host bpp */
167 if (!s->state->listeners)
170 switch (ds_get_bits_per_pixel(s->state)) {
173 ? blizzard_draw_fn_r_8[s->iformat]
174 : blizzard_draw_fn_8[s->iformat];
178 ? blizzard_draw_fn_r_15[s->iformat]
179 : blizzard_draw_fn_15[s->iformat];
183 ? blizzard_draw_fn_r_16[s->iformat]
184 : blizzard_draw_fn_16[s->iformat];
188 ? blizzard_draw_fn_r_24[s->iformat]
189 : blizzard_draw_fn_24[s->iformat];
193 ? blizzard_draw_fn_r_32[s->iformat]
194 : blizzard_draw_fn_32[s->iformat];
201 if (s->mx[0] > s->data.x)
202 s->mx[0] = s->data.x;
203 if (s->my[0] > s->data.y)
204 s->my[0] = s->data.y;
205 if (s->mx[1] < s->data.x + s->data.dx)
206 s->mx[1] = s->data.x + s->data.dx;
207 if (s->my[1] < s->data.y + s->data.dy)
208 s->my[1] = s->data.y + s->data.dy;
211 bypp[1] = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
212 bypl[0] = bypp[0] * s->data.pitch;
213 bypl[1] = bypp[1] * s->x;
214 bypl[2] = bypp[0] * s->data.dx;
217 dst = s->fb + bypl[1] * s->data.y + bypp[1] * s->data.x;
218 for (y = s->data.dy; y > 0; y --, src += bypl[0], dst += bypl[1])
219 fn(dst, src, bypl[2]);
222 static int blizzard_transfer_setup(struct blizzard_s *s)
224 if (s->source > 3 || !s->bpp ||
225 s->ix[1] < s->ix[0] || s->iy[1] < s->iy[0])
228 s->data.angle = s->effect & 3;
229 s->data.x = s->ix[0];
230 s->data.y = s->iy[0];
231 s->data.dx = s->ix[1] - s->ix[0] + 1;
232 s->data.dy = s->iy[1] - s->iy[0] + 1;
233 s->data.len = s->bpp * s->data.dx * s->data.dy;
234 s->data.pitch = s->data.dx;
235 if (s->data.len > s->data.buflen) {
236 s->data.buf = qemu_realloc(s->data.buf, s->data.len);
237 s->data.buflen = s->data.len;
239 s->data.ptr = s->data.buf;
240 s->data.data = s->data.buf;
245 static void blizzard_reset(struct blizzard_s *s)
256 s->memrefresh = 0x25c;
262 s->lcd_config = 0x74;
289 s->bpp = blizzard_iformat_bpp[s->iformat];
291 s->hssi_config[0] = 0x00;
292 s->hssi_config[1] = 0x00;
293 s->hssi_config[2] = 0x01;
295 s->tv_timing[0] = 0x00;
296 s->tv_timing[1] = 0x00;
297 s->tv_timing[2] = 0x00;
298 s->tv_timing[3] = 0x00;
303 s->tv_filter_config = 0x80;
304 s->tv_filter_idx = 0x00;
308 s->gamma_config = 0x00;
310 s->matrix_ena = 0x00;
311 memset(&s->matrix_coeff, 0, sizeof(s->matrix_coeff));
317 s->rgbgpio_dir = 0x00;
319 s->gpio_edge[0] = 0x00;
320 s->gpio_edge[1] = 0x00;
322 s->gpio_pdown = 0xff;
325 static inline void blizzard_invalidate_display(void *opaque) {
326 struct blizzard_s *s = (struct blizzard_s *) opaque;
331 static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
333 struct blizzard_s *s = (struct blizzard_s *) opaque;
336 case 0x00: /* Revision Code */
339 case 0x02: /* Configuration Readback */
340 return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
342 case 0x04: /* PLL M-Divider */
343 return (s->pll - 1) | (1 << 7);
344 case 0x06: /* PLL Lock Range Control */
346 case 0x08: /* PLL Lock Synthesis Control 0 */
347 return s->pll_ctrl & 0xff;
348 case 0x0a: /* PLL Lock Synthesis Control 1 */
349 return s->pll_ctrl >> 8;
350 case 0x0c: /* PLL Mode Control 0 */
353 case 0x0e: /* Clock-Source Select */
356 case 0x10: /* Memory Controller Activate */
357 case 0x14: /* Memory Controller Bank 0 Status Flag */
360 case 0x18: /* Auto-Refresh Interval Setting 0 */
361 return s->memrefresh & 0xff;
362 case 0x1a: /* Auto-Refresh Interval Setting 1 */
363 return s->memrefresh >> 8;
365 case 0x1c: /* Power-On Sequence Timing Control */
367 case 0x1e: /* Timing Control 0 */
369 case 0x20: /* Timing Control 1 */
372 case 0x24: /* Arbitration Priority Control */
375 case 0x28: /* LCD Panel Configuration */
376 return s->lcd_config;
378 case 0x2a: /* LCD Horizontal Display Width */
380 case 0x2c: /* LCD Horizontal Non-display Period */
382 case 0x2e: /* LCD Vertical Display Height 0 */
384 case 0x30: /* LCD Vertical Display Height 1 */
386 case 0x32: /* LCD Vertical Non-display Period */
388 case 0x34: /* LCD HS Pulse-width */
390 case 0x36: /* LCd HS Pulse Start Position */
391 return s->skipx >> 3;
392 case 0x38: /* LCD VS Pulse-width */
394 case 0x3a: /* LCD VS Pulse Start Position */
397 case 0x3c: /* PCLK Polarity */
400 case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
401 return s->hssi_config[0];
402 case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
403 return s->hssi_config[1];
404 case 0x42: /* High-speed Serial Interface Tx Mode */
405 return s->hssi_config[2];
406 case 0x44: /* TV Display Configuration */
408 case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
409 return s->tv_timing[(reg - 0x46) >> 1];
410 case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
412 case 0x50: /* TV Horizontal Start Position */
414 case 0x52: /* TV Vertical Start Position */
416 case 0x54: /* TV Test Pattern Setting */
418 case 0x56: /* TV Filter Setting */
419 return s->tv_filter_config;
420 case 0x58: /* TV Filter Coefficient Index */
421 return s->tv_filter_idx;
422 case 0x5a: /* TV Filter Coefficient Data */
423 if (s->tv_filter_idx < 0x20)
424 return s->tv_filter_coeff[s->tv_filter_idx ++];
427 case 0x60: /* Input YUV/RGB Translate Mode 0 */
429 case 0x62: /* Input YUV/RGB Translate Mode 1 */
431 case 0x64: /* U Data Fix */
433 case 0x66: /* V Data Fix */
436 case 0x68: /* Display Mode */
439 case 0x6a: /* Special Effects */
442 case 0x6c: /* Input Window X Start Position 0 */
443 return s->ix[0] & 0xff;
444 case 0x6e: /* Input Window X Start Position 1 */
445 return s->ix[0] >> 3;
446 case 0x70: /* Input Window Y Start Position 0 */
447 return s->ix[0] & 0xff;
448 case 0x72: /* Input Window Y Start Position 1 */
449 return s->ix[0] >> 3;
450 case 0x74: /* Input Window X End Position 0 */
451 return s->ix[1] & 0xff;
452 case 0x76: /* Input Window X End Position 1 */
453 return s->ix[1] >> 3;
454 case 0x78: /* Input Window Y End Position 0 */
455 return s->ix[1] & 0xff;
456 case 0x7a: /* Input Window Y End Position 1 */
457 return s->ix[1] >> 3;
458 case 0x7c: /* Output Window X Start Position 0 */
459 return s->ox[0] & 0xff;
460 case 0x7e: /* Output Window X Start Position 1 */
461 return s->ox[0] >> 3;
462 case 0x80: /* Output Window Y Start Position 0 */
463 return s->oy[0] & 0xff;
464 case 0x82: /* Output Window Y Start Position 1 */
465 return s->oy[0] >> 3;
466 case 0x84: /* Output Window X End Position 0 */
467 return s->ox[1] & 0xff;
468 case 0x86: /* Output Window X End Position 1 */
469 return s->ox[1] >> 3;
470 case 0x88: /* Output Window Y End Position 0 */
471 return s->oy[1] & 0xff;
472 case 0x8a: /* Output Window Y End Position 1 */
473 return s->oy[1] >> 3;
475 case 0x8c: /* Input Data Format */
477 case 0x8e: /* Data Source Select */
479 case 0x90: /* Display Memory Data Port */
482 case 0xa8: /* Border Color 0 */
484 case 0xaa: /* Border Color 1 */
486 case 0xac: /* Border Color 2 */
489 case 0xb4: /* Gamma Correction Enable */
490 return s->gamma_config;
491 case 0xb6: /* Gamma Correction Table Index */
493 case 0xb8: /* Gamma Correction Table Data */
494 return s->gamma_lut[s->gamma_idx ++];
496 case 0xba: /* 3x3 Matrix Enable */
497 return s->matrix_ena;
498 case 0xbc ... 0xde: /* Coefficient Registers */
499 return s->matrix_coeff[(reg - 0xbc) >> 1];
500 case 0xe0: /* 3x3 Matrix Red Offset */
502 case 0xe2: /* 3x3 Matrix Green Offset */
504 case 0xe4: /* 3x3 Matrix Blue Offset */
507 case 0xe6: /* Power-save */
509 case 0xe8: /* Non-display Period Control / Status */
510 return s->status | (1 << 5);
511 case 0xea: /* RGB Interface Control */
512 return s->rgbgpio_dir;
513 case 0xec: /* RGB Interface Status */
515 case 0xee: /* General-purpose IO Pins Configuration */
517 case 0xf0: /* General-purpose IO Pins Status / Control */
519 case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
520 return s->gpio_edge[0];
521 case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
522 return s->gpio_edge[1];
523 case 0xf6: /* GPIO Interrupt Status */
525 case 0xf8: /* GPIO Pull-down Control */
526 return s->gpio_pdown;
529 fprintf(stderr, "%s: unknown register %02x\n", __FUNCTION__, reg);
534 static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
536 struct blizzard_s *s = (struct blizzard_s *) opaque;
539 case 0x04: /* PLL M-Divider */
540 s->pll = (value & 0x3f) + 1;
542 case 0x06: /* PLL Lock Range Control */
543 s->pll_range = value & 3;
545 case 0x08: /* PLL Lock Synthesis Control 0 */
546 s->pll_ctrl &= 0xf00;
547 s->pll_ctrl |= (value << 0) & 0x0ff;
549 case 0x0a: /* PLL Lock Synthesis Control 1 */
550 s->pll_ctrl &= 0x0ff;
551 s->pll_ctrl |= (value << 8) & 0xf00;
553 case 0x0c: /* PLL Mode Control 0 */
554 s->pll_mode = value & 0x77;
555 if ((value & 3) == 0 || (value & 3) == 3)
556 fprintf(stderr, "%s: wrong PLL Control bits (%i)\n",
557 __FUNCTION__, value & 3);
560 case 0x0e: /* Clock-Source Select */
561 s->clksel = value & 0xff;
564 case 0x10: /* Memory Controller Activate */
565 s->memenable = value & 1;
567 case 0x14: /* Memory Controller Bank 0 Status Flag */
570 case 0x18: /* Auto-Refresh Interval Setting 0 */
571 s->memrefresh &= 0xf00;
572 s->memrefresh |= (value << 0) & 0x0ff;
574 case 0x1a: /* Auto-Refresh Interval Setting 1 */
575 s->memrefresh &= 0x0ff;
576 s->memrefresh |= (value << 8) & 0xf00;
579 case 0x1c: /* Power-On Sequence Timing Control */
580 s->timing[0] = value & 0x7f;
582 case 0x1e: /* Timing Control 0 */
583 s->timing[1] = value & 0x17;
585 case 0x20: /* Timing Control 1 */
586 s->timing[2] = value & 0x35;
589 case 0x24: /* Arbitration Priority Control */
590 s->priority = value & 1;
593 case 0x28: /* LCD Panel Configuration */
594 s->lcd_config = value & 0xff;
595 if (value & (1 << 7))
596 fprintf(stderr, "%s: data swap not supported!\n", __FUNCTION__);
599 case 0x2a: /* LCD Horizontal Display Width */
602 case 0x2c: /* LCD Horizontal Non-display Period */
603 s->hndp = value & 0xff;
605 case 0x2e: /* LCD Vertical Display Height 0 */
607 s->y |= (value << 0) & 0x0ff;
609 case 0x30: /* LCD Vertical Display Height 1 */
611 s->y |= (value << 8) & 0x300;
613 case 0x32: /* LCD Vertical Non-display Period */
614 s->vndp = value & 0xff;
616 case 0x34: /* LCD HS Pulse-width */
617 s->hsync = value & 0xff;
619 case 0x36: /* LCD HS Pulse Start Position */
620 s->skipx = value & 0xff;
622 case 0x38: /* LCD VS Pulse-width */
623 s->vsync = value & 0xbf;
625 case 0x3a: /* LCD VS Pulse Start Position */
626 s->skipy = value & 0xff;
629 case 0x3c: /* PCLK Polarity */
630 s->pclk = value & 0x82;
631 /* Affects calculation of s->hndp, s->hsync and s->skipx. */
634 case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
635 s->hssi_config[0] = value;
637 case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
638 s->hssi_config[1] = value;
639 if (((value >> 4) & 3) == 3)
640 fprintf(stderr, "%s: Illegal active-data-links value\n",
643 case 0x42: /* High-speed Serial Interface Tx Mode */
644 s->hssi_config[2] = value & 0xbd;
647 case 0x44: /* TV Display Configuration */
648 s->tv_config = value & 0xfe;
650 case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
651 s->tv_timing[(reg - 0x46) >> 1] = value;
653 case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
656 case 0x50: /* TV Horizontal Start Position */
659 case 0x52: /* TV Vertical Start Position */
660 s->tv_y = value & 0x7f;
662 case 0x54: /* TV Test Pattern Setting */
665 case 0x56: /* TV Filter Setting */
666 s->tv_filter_config = value & 0xbf;
668 case 0x58: /* TV Filter Coefficient Index */
669 s->tv_filter_idx = value & 0x1f;
671 case 0x5a: /* TV Filter Coefficient Data */
672 if (s->tv_filter_idx < 0x20)
673 s->tv_filter_coeff[s->tv_filter_idx ++] = value;
676 case 0x60: /* Input YUV/RGB Translate Mode 0 */
677 s->yrc[0] = value & 0xb0;
679 case 0x62: /* Input YUV/RGB Translate Mode 1 */
680 s->yrc[1] = value & 0x30;
682 case 0x64: /* U Data Fix */
685 case 0x66: /* V Data Fix */
689 case 0x68: /* Display Mode */
690 if ((s->mode ^ value) & 3)
692 s->mode = value & 0xb7;
693 s->enable = value & 1;
694 s->blank = (value >> 1) & 1;
695 if (value & (1 << 4))
696 fprintf(stderr, "%s: Macrovision enable attempt!\n", __FUNCTION__);
699 case 0x6a: /* Special Effects */
700 s->effect = value & 0xfb;
703 case 0x6c: /* Input Window X Start Position 0 */
705 s->ix[0] |= (value << 0) & 0x0ff;
707 case 0x6e: /* Input Window X Start Position 1 */
709 s->ix[0] |= (value << 8) & 0x300;
711 case 0x70: /* Input Window Y Start Position 0 */
713 s->iy[0] |= (value << 0) & 0x0ff;
715 case 0x72: /* Input Window Y Start Position 1 */
717 s->iy[0] |= (value << 8) & 0x300;
719 case 0x74: /* Input Window X End Position 0 */
721 s->ix[1] |= (value << 0) & 0x0ff;
723 case 0x76: /* Input Window X End Position 1 */
725 s->ix[1] |= (value << 8) & 0x300;
727 case 0x78: /* Input Window Y End Position 0 */
729 s->iy[1] |= (value << 0) & 0x0ff;
731 case 0x7a: /* Input Window Y End Position 1 */
733 s->iy[1] |= (value << 8) & 0x300;
735 case 0x7c: /* Output Window X Start Position 0 */
737 s->ox[0] |= (value << 0) & 0x0ff;
739 case 0x7e: /* Output Window X Start Position 1 */
741 s->ox[0] |= (value << 8) & 0x300;
743 case 0x80: /* Output Window Y Start Position 0 */
745 s->oy[0] |= (value << 0) & 0x0ff;
747 case 0x82: /* Output Window Y Start Position 1 */
749 s->oy[0] |= (value << 8) & 0x300;
751 case 0x84: /* Output Window X End Position 0 */
753 s->ox[1] |= (value << 0) & 0x0ff;
755 case 0x86: /* Output Window X End Position 1 */
757 s->ox[1] |= (value << 8) & 0x300;
759 case 0x88: /* Output Window Y End Position 0 */
761 s->oy[1] |= (value << 0) & 0x0ff;
763 case 0x8a: /* Output Window Y End Position 1 */
765 s->oy[1] |= (value << 8) & 0x300;
768 case 0x8c: /* Input Data Format */
769 s->iformat = value & 0xf;
770 s->bpp = blizzard_iformat_bpp[s->iformat];
772 fprintf(stderr, "%s: Illegal or unsupported input format %x\n",
773 __FUNCTION__, s->iformat);
775 case 0x8e: /* Data Source Select */
776 s->source = value & 7;
777 /* Currently all windows will be "destructive overlays". */
778 if ((!(s->effect & (1 << 3)) && (s->ix[0] != s->ox[0] ||
779 s->iy[0] != s->oy[0] ||
780 s->ix[1] != s->ox[1] ||
781 s->iy[1] != s->oy[1])) ||
782 !((s->ix[1] - s->ix[0]) & (s->iy[1] - s->iy[0]) &
783 (s->ox[1] - s->ox[0]) & (s->oy[1] - s->oy[0]) & 1))
784 fprintf(stderr, "%s: Illegal input/output window positions\n",
787 blizzard_transfer_setup(s);
790 case 0x90: /* Display Memory Data Port */
791 if (!s->data.len && !blizzard_transfer_setup(s))
794 *s->data.ptr ++ = value;
795 if (-- s->data.len == 0)
799 case 0xa8: /* Border Color 0 */
802 case 0xaa: /* Border Color 1 */
805 case 0xac: /* Border Color 2 */
809 case 0xb4: /* Gamma Correction Enable */
810 s->gamma_config = value & 0x87;
812 case 0xb6: /* Gamma Correction Table Index */
813 s->gamma_idx = value;
815 case 0xb8: /* Gamma Correction Table Data */
816 s->gamma_lut[s->gamma_idx ++] = value;
819 case 0xba: /* 3x3 Matrix Enable */
820 s->matrix_ena = value & 1;
822 case 0xbc ... 0xde: /* Coefficient Registers */
823 s->matrix_coeff[(reg - 0xbc) >> 1] = value & ((reg & 2) ? 0x80 : 0xff);
825 case 0xe0: /* 3x3 Matrix Red Offset */
828 case 0xe2: /* 3x3 Matrix Green Offset */
831 case 0xe4: /* 3x3 Matrix Blue Offset */
835 case 0xe6: /* Power-save */
836 s->pm = value & 0x83;
837 if (value & s->mode & 1)
838 fprintf(stderr, "%s: The display must be disabled before entering "
839 "Standby Mode\n", __FUNCTION__);
841 case 0xe8: /* Non-display Period Control / Status */
842 s->status = value & 0x1b;
844 case 0xea: /* RGB Interface Control */
845 s->rgbgpio_dir = value & 0x8f;
847 case 0xec: /* RGB Interface Status */
848 s->rgbgpio = value & 0xcf;
850 case 0xee: /* General-purpose IO Pins Configuration */
853 case 0xf0: /* General-purpose IO Pins Status / Control */
856 case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
857 s->gpio_edge[0] = value;
859 case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
860 s->gpio_edge[1] = value;
862 case 0xf6: /* GPIO Interrupt Status */
863 s->gpio_irq &= value;
865 case 0xf8: /* GPIO Pull-down Control */
866 s->gpio_pdown = value;
870 fprintf(stderr, "%s: unknown register %02x\n", __FUNCTION__, reg);
875 uint16_t s1d13745_read(void *opaque, int dc)
877 struct blizzard_s *s = (struct blizzard_s *) opaque;
878 uint16_t value = blizzard_reg_read(s, s->reg);
880 if (s->swallow -- > 0)
888 void s1d13745_write(void *opaque, int dc, uint16_t value)
890 struct blizzard_s *s = (struct blizzard_s *) opaque;
892 if (s->swallow -- > 0)
895 blizzard_reg_write(s, s->reg, value);
897 if (s->reg != 0x90 && s->reg != 0x5a && s->reg != 0xb8)
900 s->reg = value & 0xff;
903 void s1d13745_write_block(void *opaque, int dc,
904 void *buf, size_t len, int pitch)
906 struct blizzard_s *s = (struct blizzard_s *) opaque;
909 if (s->reg == 0x90 && dc &&
910 (s->data.len || blizzard_transfer_setup(s)) &&
911 len >= (s->data.len << 1)) {
912 len -= s->data.len << 1;
916 s->data.pitch = pitch;
918 s->data.data = s->data.buf;
922 s1d13745_write(opaque, dc, *(uint16_t *) buf);
930 static void blizzard_update_display(void *opaque)
932 struct blizzard_s *s = (struct blizzard_s *) opaque;
933 int y, bypp, bypl, bwidth;
939 if (s->x != ds_get_width(s->state) || s->y != ds_get_height(s->state)) {
941 qemu_console_resize(s->state, s->x, s->y);
948 bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
949 memset(ds_get_data(s->state), 0, bypp * s->x * s->y);
959 if (s->mx[1] <= s->mx[0])
962 bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
964 bwidth = bypp * (s->mx[1] - s->mx[0]);
966 src = s->fb + bypl * y + bypp * s->mx[0];
967 dst = ds_get_data(s->state) + bypl * y + bypp * s->mx[0];
968 for (; y < s->my[1]; y ++, src += bypl, dst += bypl)
969 memcpy(dst, src, bwidth);
971 dpy_update(s->state, s->mx[0], s->my[0],
972 s->mx[1] - s->mx[0], y - s->my[0]);
980 static void blizzard_screen_dump(void *opaque, const char *filename) {
981 struct blizzard_s *s = (struct blizzard_s *) opaque;
983 blizzard_update_display(opaque);
984 if (s && ds_get_data(s->state))
985 ppm_save(filename, s->state->surface);
988 void *s1d13745_init(qemu_irq gpio_int)
990 struct blizzard_s *s = (struct blizzard_s *) qemu_mallocz(sizeof(*s));
992 s->fb = qemu_malloc(0x180000);
993 /* Fill the framebuffer with white color here because the corresponding
994 * code in nseries.c is broken since the DisplayState change in QEMU.
995 * This is supposedly ok since nseries.c is the only user of blizzard.c */
996 memset(s->fb, 0xff, 0x180000);
998 s->state = graphic_console_init(blizzard_update_display,
999 blizzard_invalidate_display,
1000 blizzard_screen_dump, NULL, s);