2 * QEMU ETRAX System Emulator
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-char.h"
33 #define RW_TR_CTRL 0x00
34 #define RW_TR_DMA_EN 0x04
35 #define RW_REC_CTRL 0x08
37 #define RS_STAT_DIN 0x20
38 #define R_STAT_DIN 0x24
39 #define RW_INTR_MASK 0x2c
40 #define RW_ACK_INTR 0x30
42 #define R_MASKED_INTR 0x38
45 #define STAT_TR_IDLE 22
46 #define STAT_TR_RDY 24
56 /* Control registers. */
58 uint32_t rw_tr_dma_en;
62 uint32_t rw_intr_mask;
65 uint32_t r_masked_intr;
68 static void ser_update_irq(struct etrax_serial_t *s)
70 uint32_t o_irq = s->r_masked_intr;
72 s->r_intr &= ~(s->rw_ack_intr);
73 s->r_masked_intr = s->r_intr & s->rw_intr_mask;
75 if (o_irq != s->r_masked_intr) {
76 D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
77 s->rw_intr_mask, s->r_intr,
78 s->r_masked_intr, s->rw_ack_intr));
80 qemu_irq_raise(s->irq[0]);
82 qemu_irq_lower(s->irq[0]);
88 static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
90 D(CPUState *env = opaque);
91 D(printf ("%s %x\n", __func__, addr));
95 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
97 struct etrax_serial_t *s = opaque;
98 D(CPUState *env = s->env);
112 s->rs_stat_din &= ~(1 << STAT_DAV);
118 D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
125 D(printf("load r_intr=%x\n", s->r_intr));
129 D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
130 r = s->r_masked_intr;
134 D(printf ("%s %x\n", __func__, addr));
141 ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
143 D(struct etrax_serial_t *s = opaque);
144 D(CPUState *env = s->env);
145 D(printf ("%s %x %x\n", __func__, addr, value));
148 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
150 struct etrax_serial_t *s = opaque;
151 unsigned char ch = value;
152 D(CPUState *env = s->env);
157 D(printf("rw_tr_ctrl=%x\n", value));
158 s->rw_tr_ctrl = value;
161 D(printf("rw_tr_dma_en=%x\n", value));
162 s->rw_tr_dma_en = value;
165 qemu_chr_write(s->chr, &ch, 1);
170 D(printf("rw_ack_intr=%x\n", value));
171 s->rw_ack_intr = value;
172 if (s->pending_tx && (s->rw_ack_intr & 1)) {
175 s->rw_ack_intr &= ~1;
179 D(printf("r_intr_mask=%x\n", value));
180 s->rw_intr_mask = value;
183 D(printf ("%s %x %x\n", __func__, addr, value));
189 static CPUReadMemoryFunc *ser_read[] = {
195 static CPUWriteMemoryFunc *ser_write[] = {
201 static void serial_receive(void *opaque, const uint8_t *buf, int size)
203 struct etrax_serial_t *s = opaque;
206 s->rs_stat_din &= ~0xff;
207 s->rs_stat_din |= (buf[0] & 0xff);
208 s->rs_stat_din |= (1 << STAT_DAV); /* dav. */
212 static int serial_can_receive(void *opaque)
214 struct etrax_serial_t *s = opaque;
217 /* Is the receiver enabled? */
218 r = s->rw_rec_ctrl & 1;
220 /* Pending rx data? */
221 r |= !(s->r_intr & 8);
225 static void serial_event(void *opaque, int event)
230 void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
231 target_phys_addr_t base)
233 struct etrax_serial_t *s;
236 s = qemu_mallocz(sizeof *s);
242 /* transmitter begins ready and idle. */
243 s->rs_stat_din |= (1 << STAT_TR_RDY);
244 s->rs_stat_din |= (1 << STAT_TR_IDLE);
246 qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
249 ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
250 cpu_register_physical_memory (base, 0x3c, ser_regs);