git.maemo.org Git - qemu/blob - hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32
  33 //#define HPET_DEBUG
  34 #ifdef HPET_DEBUG
  35 #define dprintf printf
  36 #else
  37 #define dprintf(...)
  38 #endif
  39
  40 static HPETState *hpet_statep;
  41
  42 uint32_t hpet_in_legacy_mode(void)
  43 {
  44     if (hpet_statep)
  45         return hpet_statep->config & HPET_CFG_LEGACY;
  46     else
  47         return 0;
  48 }
  49
  50 static uint32_t timer_int_route(struct HPETTimer *timer)
  51 {
  52     uint32_t route;
  53     route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  54     return route;
  55 }
  56
  57 static uint32_t hpet_enabled(void)
  58 {
  59     return hpet_statep->config & HPET_CFG_ENABLE;
  60 }
  61
  62 static uint32_t timer_is_periodic(HPETTimer *t)
  63 {
  64     return t->config & HPET_TN_PERIODIC;
  65 }
  66
  67 static uint32_t timer_enabled(HPETTimer *t)
  68 {
  69     return t->config & HPET_TN_ENABLE;
  70 }
  71
  72 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
  73 {
  74     return ((int32_t)(b) - (int32_t)(a) < 0);
  75 }
  76
  77 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
  78 {
  79     return ((int64_t)(b) - (int64_t)(a) < 0);
  80 }
  81
  82 static uint64_t ticks_to_ns(uint64_t value)
  83 {
  84     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
  85 }
  86
  87 static uint64_t ns_to_ticks(uint64_t value)
  88 {
  89     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
  90 }
  91
  92 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
  93 {
  94     new &= mask;
  95     new |= old & ~mask;
  96     return new;
  97 }
  98
  99 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 100 {
 101     return (!(old & mask) && (new & mask));
 102 }
 103
 104 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 105 {
 106     return ((old & mask) && !(new & mask));
 107 }
 108
 109 static uint64_t hpet_get_ticks(void)
 110 {
 111     uint64_t ticks;
 112     ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
 113     return ticks;
 114 }
 115
 116 /*
 117  * calculate diff between comparator value and current ticks
 118  */
 119 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 120 {
 121
 122     if (t->config & HPET_TN_32BIT) {
 123         uint32_t diff, cmp;
 124         cmp = (uint32_t)t->cmp;
 125         diff = cmp - (uint32_t)current;
 126         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 127         return (uint64_t)diff;
 128     } else {
 129         uint64_t diff, cmp;
 130         cmp = t->cmp;
 131         diff = cmp - current;
 132         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 133         return diff;
 134     }
 135 }
 136
 137 static void update_irq(struct HPETTimer *timer)
 138 {
 139     qemu_irq irq;
 140     int route;
 141
 142     if (timer->tn <= 1 && hpet_in_legacy_mode()) {
 143         /* if LegacyReplacementRoute bit is set, HPET specification requires
 144          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 145          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 146          */
 147         if (timer->tn == 0) {
 148             irq=timer->state->irqs[0];
 149         } else
 150             irq=timer->state->irqs[8];
 151     } else {
 152         route=timer_int_route(timer);
 153         irq=timer->state->irqs[route];
 154     }
 155     if (timer_enabled(timer) && hpet_enabled()) {
 156         qemu_irq_pulse(irq);
 157     }
 158 }
 159
 160 static void hpet_pre_save(const void *opaque)
 161 {
 162     HPETState *s = (void *)opaque;
 163     /* save current counter value */
 164     s->hpet_counter = hpet_get_ticks();
 165 }
 166
 167 static int hpet_post_load(void *opaque)
 168 {
 169     HPETState *s = opaque;
 170
 171     /* Recalculate the offset between the main counter and guest time */
 172     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 173     return 0;
 174 }
 175
 176 static const VMStateDescription vmstate_hpet_timer = {
 177     .name = "hpet_timer",
 178     .version_id = 1,
 179     .minimum_version_id = 1,
 180     .minimum_version_id_old = 1,
 181     .fields      = (VMStateField []) {
 182         VMSTATE_UINT8(tn, HPETTimer),
 183         VMSTATE_UINT64(config, HPETTimer),
 184         VMSTATE_UINT64(cmp, HPETTimer),
 185         VMSTATE_UINT64(fsb, HPETTimer),
 186         VMSTATE_UINT64(period, HPETTimer),
 187         VMSTATE_UINT8(wrap_flag, HPETTimer),
 188         VMSTATE_TIMER(qemu_timer, HPETTimer),
 189         VMSTATE_END_OF_LIST()
 190     }
 191 };
 192
 193 static const VMStateDescription vmstate_hpet = {
 194     .name = "hpet",
 195     .version_id = 1,
 196     .minimum_version_id = 1,
 197     .minimum_version_id_old = 1,
 198     .pre_save = hpet_pre_save,
 199     .post_load = hpet_post_load,
 200     .fields      = (VMStateField []) {
 201         VMSTATE_UINT64(config, HPETState),
 202         VMSTATE_UINT64(isr, HPETState),
 203         VMSTATE_UINT64(hpet_counter, HPETState),
 204         VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
 205                              vmstate_hpet_timer, HPETTimer),
 206         VMSTATE_END_OF_LIST()
 207     }
 208 };
 209
 210 /*
 211  * timer expiration callback
 212  */
 213 static void hpet_timer(void *opaque)
 214 {
 215     HPETTimer *t = (HPETTimer*)opaque;
 216     uint64_t diff;
 217
 218     uint64_t period = t->period;
 219     uint64_t cur_tick = hpet_get_ticks();
 220
 221     if (timer_is_periodic(t) && period != 0) {
 222         if (t->config & HPET_TN_32BIT) {
 223             while (hpet_time_after(cur_tick, t->cmp))
 224                 t->cmp = (uint32_t)(t->cmp + t->period);
 225         } else
 226             while (hpet_time_after64(cur_tick, t->cmp))
 227                 t->cmp += period;
 228
 229         diff = hpet_calculate_diff(t, cur_tick);
 230         qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
 231                        + (int64_t)ticks_to_ns(diff));
 232     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 233         if (t->wrap_flag) {
 234             diff = hpet_calculate_diff(t, cur_tick);
 235             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
 236                            + (int64_t)ticks_to_ns(diff));
 237             t->wrap_flag = 0;
 238         }
 239     }
 240     update_irq(t);
 241 }
 242
 243 static void hpet_set_timer(HPETTimer *t)
 244 {
 245     uint64_t diff;
 246     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 247     uint64_t cur_tick = hpet_get_ticks();
 248
 249     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 250     t->wrap_flag = 0;
 251     diff = hpet_calculate_diff(t, cur_tick);
 252
 253     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 254      * counter wraps in addition to an interrupt with comparator match.
 255      */
 256     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 257         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 258         if (wrap_diff < (uint32_t)diff) {
 259             diff = wrap_diff;
 260             t->wrap_flag = 1;
 261         }
 262     }
 263     qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
 264                    + (int64_t)ticks_to_ns(diff));
 265 }
 266
 267 static void hpet_del_timer(HPETTimer *t)
 268 {
 269     qemu_del_timer(t->qemu_timer);
 270 }
 271
 272 #ifdef HPET_DEBUG
 273 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 274 {
 275     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 276     return 0;
 277 }
 278
 279 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 280 {
 281     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 282     return 0;
 283 }
 284 #endif
 285
 286 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 287 {
 288     HPETState *s = (HPETState *)opaque;
 289     uint64_t cur_tick, index;
 290
 291     dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 292     index = addr;
 293     /*address range of all TN regs*/
 294     if (index >= 0x100 && index <= 0x3ff) {
 295         uint8_t timer_id = (addr - 0x100) / 0x20;
 296         if (timer_id > HPET_NUM_TIMERS - 1) {
 297             printf("qemu: timer id out of range\n");
 298             return 0;
 299         }
 300         HPETTimer *timer = &s->timer[timer_id];
 301
 302         switch ((addr - 0x100) % 0x20) {
 303             case HPET_TN_CFG:
 304                 return timer->config;
 305             case HPET_TN_CFG + 4: // Interrupt capabilities
 306                 return timer->config >> 32;
 307             case HPET_TN_CMP: // comparator register
 308                 return timer->cmp;
 309             case HPET_TN_CMP + 4:
 310                 return timer->cmp >> 32;
 311             case HPET_TN_ROUTE:
 312                 return timer->fsb >> 32;
 313             default:
 314                 dprintf("qemu: invalid hpet_ram_readl\n");
 315                 break;
 316         }
 317     } else {
 318         switch (index) {
 319             case HPET_ID:
 320                 return s->capability;
 321             case HPET_PERIOD:
 322                 return s->capability >> 32;
 323             case HPET_CFG:
 324                 return s->config;
 325             case HPET_CFG + 4:
 326                 dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 327                 return 0;
 328             case HPET_COUNTER:
 329                 if (hpet_enabled())
 330                     cur_tick = hpet_get_ticks();
 331                 else
 332                     cur_tick = s->hpet_counter;
 333                 dprintf("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 334                 return cur_tick;
 335             case HPET_COUNTER + 4:
 336                 if (hpet_enabled())
 337                     cur_tick = hpet_get_ticks();
 338                 else
 339                     cur_tick = s->hpet_counter;
 340                 dprintf("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 341                 return cur_tick >> 32;
 342             case HPET_STATUS:
 343                 return s->isr;
 344             default:
 345                 dprintf("qemu: invalid hpet_ram_readl\n");
 346                 break;
 347         }
 348     }
 349     return 0;
 350 }
 351
 352 #ifdef HPET_DEBUG
 353 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 354                             uint32_t value)
 355 {
 356     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 357            addr, value);
 358 }
 359
 360 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 361                             uint32_t value)
 362 {
 363     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 364            addr, value);
 365 }
 366 #endif
 367
 368 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 369                             uint32_t value)
 370 {
 371     int i;
 372     HPETState *s = (HPETState *)opaque;
 373     uint64_t old_val, new_val, val, index;
 374
 375     dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 376     index = addr;
 377     old_val = hpet_ram_readl(opaque, addr);
 378     new_val = value;
 379
 380     /*address range of all TN regs*/
 381     if (index >= 0x100 && index <= 0x3ff) {
 382         uint8_t timer_id = (addr - 0x100) / 0x20;
 383         dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 384         HPETTimer *timer = &s->timer[timer_id];
 385
 386         switch ((addr - 0x100) % 0x20) {
 387             case HPET_TN_CFG:
 388                 dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
 389                 val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 390                 timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 391                 if (new_val & HPET_TN_32BIT) {
 392                     timer->cmp = (uint32_t)timer->cmp;
 393                     timer->period = (uint32_t)timer->period;
 394                 }
 395                 if (new_val & HPET_TIMER_TYPE_LEVEL) {
 396                     printf("qemu: level-triggered hpet not supported\n");
 397                     exit (-1);
 398                 }
 399
 400                 break;
 401             case HPET_TN_CFG + 4: // Interrupt capabilities
 402                 dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
 403                 break;
 404             case HPET_TN_CMP: // comparator register
 405                 dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
 406                 if (timer->config & HPET_TN_32BIT)
 407                     new_val = (uint32_t)new_val;
 408                 if (!timer_is_periodic(timer) ||
 409                            (timer->config & HPET_TN_SETVAL))
 410                     timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
 411                                   | new_val;
 412                 if (timer_is_periodic(timer)) {
 413                     /*
 414                      * FIXME: Clamp period to reasonable min value?
 415                      * Clamp period to reasonable max value
 416                      */
 417                     new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 418                     timer->period = (timer->period & 0xffffffff00000000ULL)
 419                                      | new_val;
 420                 }
 421                 timer->config &= ~HPET_TN_SETVAL;
 422                 if (hpet_enabled())
 423                     hpet_set_timer(timer);
 424                 break;
 425             case HPET_TN_CMP + 4: // comparator register high order
 426                 dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 427                 if (!timer_is_periodic(timer) ||
 428                            (timer->config & HPET_TN_SETVAL))
 429                     timer->cmp = (timer->cmp & 0xffffffffULL)
 430                                   | new_val << 32;
 431                 else {
 432                     /*
 433                      * FIXME: Clamp period to reasonable min value?
 434                      * Clamp period to reasonable max value
 435                      */
 436                     new_val &= (timer->config
 437                                 & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 438                     timer->period = (timer->period & 0xffffffffULL)
 439                                      | new_val << 32;
 440                 }
 441                 timer->config &= ~HPET_TN_SETVAL;
 442                 if (hpet_enabled())
 443                     hpet_set_timer(timer);
 444                 break;
 445             case HPET_TN_ROUTE + 4:
 446                 dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
 447                 break;
 448             default:
 449                 dprintf("qemu: invalid hpet_ram_writel\n");
 450                 break;
 451         }
 452         return;
 453     } else {
 454         switch (index) {
 455             case HPET_ID:
 456                 return;
 457             case HPET_CFG:
 458                 val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 459                 s->config = (s->config & 0xffffffff00000000ULL) | val;
 460                 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 461                     /* Enable main counter and interrupt generation. */
 462                     s->hpet_offset = ticks_to_ns(s->hpet_counter)
 463                                      - qemu_get_clock(vm_clock);
 464                     for (i = 0; i < HPET_NUM_TIMERS; i++)
 465                         if ((&s->timer[i])->cmp != ~0ULL)
 466                             hpet_set_timer(&s->timer[i]);
 467                 }
 468                 else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 469                     /* Halt main counter and disable interrupt generation. */
 470                     s->hpet_counter = hpet_get_ticks();
 471                     for (i = 0; i < HPET_NUM_TIMERS; i++)
 472                         hpet_del_timer(&s->timer[i]);
 473                 }
 474                 /* i8254 and RTC are disabled when HPET is in legacy mode */
 475                 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 476                     hpet_pit_disable();
 477                 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 478                     hpet_pit_enable();
 479                 }
 480                 break;
 481             case HPET_CFG + 4:
 482                 dprintf("qemu: invalid HPET_CFG+4 write \n");
 483                 break;
 484             case HPET_STATUS:
 485                 /* FIXME: need to handle level-triggered interrupts */
 486                 break;
 487             case HPET_COUNTER:
 488                if (hpet_enabled())
 489                    printf("qemu: Writing counter while HPET enabled!\n");
 490                s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
 491                                   | value;
 492                dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 493                         value, s->hpet_counter);
 494                break;
 495             case HPET_COUNTER + 4:
 496                if (hpet_enabled())
 497                    printf("qemu: Writing counter while HPET enabled!\n");
 498                s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
 499                                   | (((uint64_t)value) << 32);
 500                dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 501                         value, s->hpet_counter);
 502                break;
 503             default:
 504                dprintf("qemu: invalid hpet_ram_writel\n");
 505                break;
 506         }
 507     }
 508 }
 509
 510 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 511 #ifdef HPET_DEBUG
 512     hpet_ram_readb,
 513     hpet_ram_readw,
 514 #else
 515     NULL,
 516     NULL,
 517 #endif
 518     hpet_ram_readl,
 519 };
 520
 521 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 522 #ifdef HPET_DEBUG
 523     hpet_ram_writeb,
 524     hpet_ram_writew,
 525 #else
 526     NULL,
 527     NULL,
 528 #endif
 529     hpet_ram_writel,
 530 };
 531
 532 static void hpet_reset(void *opaque) {
 533     HPETState *s = opaque;
 534     int i;
 535     static int count = 0;
 536
 537     for (i=0; i<HPET_NUM_TIMERS; i++) {
 538         HPETTimer *timer = &s->timer[i];
 539         hpet_del_timer(timer);
 540         timer->tn = i;
 541         timer->cmp = ~0ULL;
 542         timer->config =  HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 543         /* advertise availability of ioapic inti2 */
 544         timer->config |=  0x00000004ULL << 32;
 545         timer->state = s;
 546         timer->period = 0ULL;
 547         timer->wrap_flag = 0;
 548     }
 549
 550     s->hpet_counter = 0ULL;
 551     s->hpet_offset = 0ULL;
 552     /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
 553     s->capability = 0x8086a201ULL;
 554     s->capability |= ((HPET_CLK_PERIOD) << 32);
 555     s->config = 0ULL;
 556     if (count > 0)
 557         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 558          * because hpet is taking over for pit here. On subsequent invocations,
 559          * hpet_reset is called due to system reset. At this point control must
 560          * be returned to pit until SW reenables hpet.
 561          */
 562         hpet_pit_enable();
 563     count = 1;
 564 }
 565
 566
 567 void hpet_init(qemu_irq *irq) {
 568     int i, iomemtype;
 569     HPETState *s;
 570
 571     dprintf ("hpet_init\n");
 572
 573     s = qemu_mallocz(sizeof(HPETState));
 574     hpet_statep = s;
 575     s->irqs = irq;
 576     for (i=0; i<HPET_NUM_TIMERS; i++) {
 577         HPETTimer *timer = &s->timer[i];
 578         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 579     }
 580     hpet_reset(s);
 581     vmstate_register(-1, &vmstate_hpet, s);
 582     qemu_register_reset(hpet_reset, s);
 583     /* HPET Area */
 584     iomemtype = cpu_register_io_memory(hpet_ram_read,
 585                                        hpet_ram_write, s);
 586     cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
 587 }