2 * ColdFire UART emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licenced under the GPL
10 #include "qemu-char.h"
29 /* UART Status Register bits. */
30 #define MCF_UART_RxRDY 0x01
31 #define MCF_UART_FFULL 0x02
32 #define MCF_UART_TxRDY 0x04
33 #define MCF_UART_TxEMP 0x08
34 #define MCF_UART_OE 0x10
35 #define MCF_UART_PE 0x20
36 #define MCF_UART_FE 0x40
37 #define MCF_UART_RB 0x80
39 /* Interrupt flags. */
40 #define MCF_UART_TxINT 0x01
41 #define MCF_UART_RxINT 0x02
42 #define MCF_UART_DBINT 0x04
43 #define MCF_UART_COSINT 0x80
46 #define MCF_UART_BC0 0x01
47 #define MCF_UART_BC1 0x02
48 #define MCF_UART_PT 0x04
49 #define MCF_UART_PM0 0x08
50 #define MCF_UART_PM1 0x10
51 #define MCF_UART_ERR 0x20
52 #define MCF_UART_RxIRQ 0x40
53 #define MCF_UART_RxRTS 0x80
55 static void mcf_uart_update(mcf_uart_state *s)
57 s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT);
58 if (s->sr & MCF_UART_TxRDY)
59 s->isr |= MCF_UART_TxINT;
60 if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
61 ? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
62 s->isr |= MCF_UART_RxINT;
64 qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
67 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
69 mcf_uart_state *s = (mcf_uart_state *)opaque;
70 switch (addr & 0x3f) {
72 return s->mr[s->current_mr];
85 for (i = 0; i < s->fifo_len; i++)
86 s->fifo[i] = s->fifo[i + 1];
87 s->sr &= ~MCF_UART_FFULL;
89 s->sr &= ~MCF_UART_RxRDY;
94 /* TODO: Implement IPCR. */
107 /* Update TxRDY flag and set data if present and enabled. */
108 static void mcf_uart_do_tx(mcf_uart_state *s)
110 if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
112 qemu_chr_write(s->chr, (unsigned char *)&s->tb, 1);
113 s->sr |= MCF_UART_TxEMP;
116 s->sr |= MCF_UART_TxRDY;
118 s->sr &= ~MCF_UART_TxRDY;
122 static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
125 switch ((cmd >> 4) & 3) {
128 case 1: /* Reset mode register pointer. */
131 case 2: /* Reset receiver. */
134 s->sr &= ~(MCF_UART_RxRDY | MCF_UART_FFULL);
136 case 3: /* Reset transmitter. */
138 s->sr |= MCF_UART_TxEMP;
139 s->sr &= ~MCF_UART_TxRDY;
141 case 4: /* Reset error status. */
143 case 5: /* Reset break-change interrupt. */
144 s->isr &= ~MCF_UART_DBINT;
146 case 6: /* Start break. */
147 case 7: /* Stop break. */
151 /* Transmitter command. */
152 switch ((cmd >> 2) & 3) {
155 case 1: /* Enable. */
159 case 2: /* Disable. */
163 case 3: /* Reserved. */
164 fprintf(stderr, "mcf_uart: Bad TX command\n");
168 /* Receiver command. */
172 case 1: /* Enable. */
178 case 3: /* Reserved. */
179 fprintf(stderr, "mcf_uart: Bad RX command\n");
184 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
186 mcf_uart_state *s = (mcf_uart_state *)opaque;
187 switch (addr & 0x3f) {
189 s->mr[s->current_mr] = val;
193 /* CSR is ignored. */
195 case 0x08: /* Command Register. */
196 mcf_do_command(s, val);
198 case 0x0c: /* Transmit Buffer. */
199 s->sr &= ~MCF_UART_TxEMP;
204 /* ACR is ignored. */
215 static void mcf_uart_reset(mcf_uart_state *s)
220 s->sr = MCF_UART_TxEMP;
227 static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
229 /* Break events overwrite the last byte if the fifo is full. */
230 if (s->fifo_len == 4)
233 s->fifo[s->fifo_len] = data;
235 s->sr |= MCF_UART_RxRDY;
236 if (s->fifo_len == 4)
237 s->sr |= MCF_UART_FFULL;
242 static void mcf_uart_event(void *opaque, int event)
244 mcf_uart_state *s = (mcf_uart_state *)opaque;
247 case CHR_EVENT_BREAK:
248 s->isr |= MCF_UART_DBINT;
249 mcf_uart_push_byte(s, 0);
256 static int mcf_uart_can_receive(void *opaque)
258 mcf_uart_state *s = (mcf_uart_state *)opaque;
260 return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
263 static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
265 mcf_uart_state *s = (mcf_uart_state *)opaque;
267 mcf_uart_push_byte(s, buf[0]);
270 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
274 s = qemu_mallocz(sizeof(mcf_uart_state));
278 qemu_chr_add_handlers(chr, mcf_uart_can_receive, mcf_uart_receive,
286 static CPUReadMemoryFunc *mcf_uart_readfn[] = {
292 static CPUWriteMemoryFunc *mcf_uart_writefn[] = {
298 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
299 CharDriverState *chr)
304 s = mcf_uart_init(irq, chr);
305 iomemtype = cpu_register_io_memory(0, mcf_uart_readfn,
306 mcf_uart_writefn, s);
307 cpu_register_physical_memory(base, 0x40, iomemtype);