2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #ifdef TARGET_WORDS_BIGENDIAN
28 #define BIOS_FILENAME "mips_bios.bin"
30 #define BIOS_FILENAME "mipsel_bios.bin"
34 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
36 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
39 #define ENVP_ADDR (int32_t)0x80002000
40 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
42 #define ENVP_NB_ENTRIES 16
43 #define ENVP_ENTRY_SIZE 256
55 CharDriverState *display;
62 static struct _loaderparams {
64 const char *kernel_filename;
65 const char *kernel_cmdline;
66 const char *initrd_filename;
70 static void malta_fpga_update_display(void *opaque)
74 MaltaFPGAState *s = opaque;
76 for (i = 7 ; i >= 0 ; i--) {
77 if (s->leds & (1 << i))
84 qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
85 qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
89 * EEPROM 24C01 / 24C02 emulation.
91 * Emulation for serial EEPROMs:
92 * 24C01 - 1024 bit (128 x 8)
93 * 24C02 - 2048 bit (256 x 8)
95 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
101 # define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
103 # define logout(fmt, args...) ((void)0)
106 struct _eeprom24c0x_t {
115 uint8_t contents[256];
118 typedef struct _eeprom24c0x_t eeprom24c0x_t;
120 static eeprom24c0x_t eeprom = {
122 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
123 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
124 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
125 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
126 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
127 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
128 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
129 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
130 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
131 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
132 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
133 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
134 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
135 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
136 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
137 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
141 static uint8_t eeprom24c0x_read()
143 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
144 eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
148 static void eeprom24c0x_write(int scl, int sda)
150 if (eeprom.scl && scl && (eeprom.sda != sda)) {
151 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
152 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
157 } else if (eeprom.tick == 0 && !eeprom.ack) {
158 /* Waiting for start. */
159 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
160 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
161 } else if (!eeprom.scl && scl) {
162 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
163 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
165 logout("\ti2c ack bit = 0\n");
168 } else if (eeprom.sda == sda) {
169 uint8_t bit = (sda != 0);
170 logout("\ti2c bit = %d\n", bit);
171 if (eeprom.tick < 9) {
172 eeprom.command <<= 1;
173 eeprom.command += bit;
175 if (eeprom.tick == 9) {
176 logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
179 } else if (eeprom.tick < 17) {
180 if (eeprom.command & 1) {
181 sda = ((eeprom.data & 0x80) != 0);
183 eeprom.address <<= 1;
184 eeprom.address += bit;
187 if (eeprom.tick == 17) {
188 eeprom.data = eeprom.contents[eeprom.address];
189 logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
193 } else if (eeprom.tick >= 17) {
197 logout("\tsda changed with raising scl\n");
200 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
206 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
208 MaltaFPGAState *s = opaque;
212 saddr = (addr & 0xfffff);
216 /* SWITCH Register */
218 val = 0x00000000; /* All switches closed */
221 /* STATUS Register */
223 #ifdef TARGET_WORDS_BIGENDIAN
235 /* LEDBAR Register */
240 /* BRKRES Register */
245 /* UART Registers are handled directly by the serial device */
252 /* XXX: implement a real I2C controller */
256 /* IN = OUT until a real I2C control is implemented */
263 /* I2CINP Register */
265 val = ((s->i2cin & ~1) | eeprom24c0x_read());
273 /* I2COUT Register */
278 /* I2CSEL Register */
285 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
293 static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
296 MaltaFPGAState *s = opaque;
299 saddr = (addr & 0xfffff);
303 /* SWITCH Register */
311 /* LEDBAR Register */
312 /* XXX: implement a 8-LED array */
314 s->leds = val & 0xff;
317 /* ASCIIWORD Register */
319 snprintf(s->display_text, 9, "%08X", val);
320 malta_fpga_update_display(s);
323 /* ASCIIPOS0 to ASCIIPOS7 Registers */
332 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
333 malta_fpga_update_display(s);
336 /* SOFTRES Register */
339 qemu_system_reset_request ();
342 /* BRKRES Register */
347 /* UART Registers are handled directly by the serial device */
351 s->gpout = val & 0xff;
356 s->i2coe = val & 0x03;
359 /* I2COUT Register */
361 eeprom24c0x_write(val & 0x02, val & 0x01);
365 /* I2CSEL Register */
367 s->i2csel = val & 0x01;
372 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
379 static CPUReadMemoryFunc *malta_fpga_read[] = {
385 static CPUWriteMemoryFunc *malta_fpga_write[] = {
391 void malta_fpga_reset(void *opaque)
393 MaltaFPGAState *s = opaque;
403 s->display_text[8] = '\0';
404 snprintf(s->display_text, 9, " ");
405 malta_fpga_update_display(s);
408 MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
411 CharDriverState *uart_chr;
414 s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
416 malta = cpu_register_io_memory(0, malta_fpga_read,
417 malta_fpga_write, s);
419 cpu_register_physical_memory(base, 0x900, malta);
420 cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
422 s->display = qemu_chr_open("vc");
423 qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
424 qemu_chr_printf(s->display, "+--------+\r\n");
425 qemu_chr_printf(s->display, "+ +\r\n");
426 qemu_chr_printf(s->display, "+--------+\r\n");
427 qemu_chr_printf(s->display, "\n");
428 qemu_chr_printf(s->display, "Malta ASCII\r\n");
429 qemu_chr_printf(s->display, "+--------+\r\n");
430 qemu_chr_printf(s->display, "+ +\r\n");
431 qemu_chr_printf(s->display, "+--------+\r\n");
433 uart_chr = qemu_chr_open("vc");
434 qemu_chr_printf(uart_chr, "CBUS UART\r\n");
435 s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
438 qemu_register_reset(malta_fpga_reset, s);
445 static void audio_init (PCIBus *pci_bus)
448 int audio_enabled = 0;
450 for (c = soundhw; !audio_enabled && c->name; ++c) {
451 audio_enabled = c->enabled;
459 for (c = soundhw; c->name; ++c) {
461 c->init.init_pci (pci_bus, s);
468 /* Network support */
469 static void network_init (PCIBus *pci_bus)
474 for(i = 0; i < nb_nics; i++) {
479 if (i == 0 && strcmp(nd->model, "pcnet") == 0) {
480 /* The malta board has a PCNet card using PCI SLOT 11 */
481 pci_nic_init(pci_bus, nd, 88);
483 pci_nic_init(pci_bus, nd, -1);
488 /* ROM and pseudo bootloader
490 The following code implements a very very simple bootloader. It first
491 loads the registers a0 to a3 to the values expected by the OS, and
492 then jump at the kernel address.
494 The bootloader should pass the locations of the kernel arguments and
495 environment variables tables. Those tables contain the 32-bit address
496 of NULL terminated strings. The environment variables table should be
497 terminated by a NULL address.
499 For a simpler implementation, the number of kernel arguments is fixed
500 to two (the name of the kernel and the command line), and the two
501 tables are actually the same one.
503 The registers a0 to a3 should contain the following values:
504 a0 - number of kernel arguments
505 a1 - 32-bit address of the kernel arguments table
506 a2 - 32-bit address of the environment variables table
507 a3 - RAM size in bytes
510 static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry)
514 /* Small bootloader */
515 p = (uint32_t *) (phys_ram_base + bios_offset);
516 stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
517 stl_raw(p++, 0x00000000); /* nop */
519 /* YAMON service vector */
520 stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
521 stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
522 stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
523 stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
524 stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
525 stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
526 stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
527 stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
528 stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
529 stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
530 stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
531 stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
532 stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
535 /* Second part of the bootloader */
536 p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
537 stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
538 stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
539 stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
540 stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
541 stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
542 stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
543 stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
544 stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
545 stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
547 /* Load BAR registers as done by YAMON */
548 stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
550 #ifdef TARGET_WORDS_BIGENDIAN
551 stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
553 stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
555 stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
557 stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
559 #ifdef TARGET_WORDS_BIGENDIAN
560 stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
562 stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
564 stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
565 #ifdef TARGET_WORDS_BIGENDIAN
566 stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
568 stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
570 stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
572 #ifdef TARGET_WORDS_BIGENDIAN
573 stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
575 stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
577 stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
578 #ifdef TARGET_WORDS_BIGENDIAN
579 stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
581 stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
583 stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
585 #ifdef TARGET_WORDS_BIGENDIAN
586 stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
588 stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
590 stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
591 #ifdef TARGET_WORDS_BIGENDIAN
592 stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
594 stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
596 stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
598 /* Jump to kernel code */
599 stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
600 stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
601 stl_raw(p++, 0x03e00008); /* jr ra */
602 stl_raw(p++, 0x00000000); /* nop */
604 /* YAMON subroutines */
605 p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
606 stl_raw(p++, 0x03e00008); /* jr ra */
607 stl_raw(p++, 0x24020000); /* li v0,0 */
608 /* 808 YAMON print */
609 stl_raw(p++, 0x03e06821); /* move t5,ra */
610 stl_raw(p++, 0x00805821); /* move t3,a0 */
611 stl_raw(p++, 0x00a05021); /* move t2,a1 */
612 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
613 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
614 stl_raw(p++, 0x10800005); /* beqz a0,834 */
615 stl_raw(p++, 0x00000000); /* nop */
616 stl_raw(p++, 0x0ff0021c); /* jal 870 */
617 stl_raw(p++, 0x00000000); /* nop */
618 stl_raw(p++, 0x08000205); /* j 814 */
619 stl_raw(p++, 0x00000000); /* nop */
620 stl_raw(p++, 0x01a00008); /* jr t5 */
621 stl_raw(p++, 0x01602021); /* move a0,t3 */
622 /* 0x83c YAMON print_count */
623 stl_raw(p++, 0x03e06821); /* move t5,ra */
624 stl_raw(p++, 0x00805821); /* move t3,a0 */
625 stl_raw(p++, 0x00a05021); /* move t2,a1 */
626 stl_raw(p++, 0x00c06021); /* move t4,a2 */
627 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
628 stl_raw(p++, 0x0ff0021c); /* jal 870 */
629 stl_raw(p++, 0x00000000); /* nop */
630 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
631 stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
632 stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
633 stl_raw(p++, 0x00000000); /* nop */
634 stl_raw(p++, 0x01a00008); /* jr t5 */
635 stl_raw(p++, 0x01602021); /* move a0,t3 */
637 stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
638 stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
639 stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
640 stl_raw(p++, 0x00000000); /* nop */
641 stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
642 stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
643 stl_raw(p++, 0x00000000); /* nop */
644 stl_raw(p++, 0x03e00008); /* jr ra */
645 stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
649 static void prom_set(int index, const char *string, ...)
656 if (index >= ENVP_NB_ENTRIES)
659 p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
662 if (string == NULL) {
667 table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
668 s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
670 stl_raw(p, table_addr);
672 va_start(ap, string);
673 vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
678 static int64_t load_kernel (CPUState *env)
680 int64_t kernel_entry, kernel_low, kernel_high;
683 ram_addr_t initrd_offset;
685 if (load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
686 &kernel_entry, &kernel_low, &kernel_high) < 0) {
687 fprintf(stderr, "qemu: could not load kernel '%s'\n",
688 loaderparams.kernel_filename);
695 if (loaderparams.initrd_filename) {
696 initrd_size = get_image_size (loaderparams.initrd_filename);
697 if (initrd_size > 0) {
698 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
699 if (initrd_offset + initrd_size > ram_size) {
701 "qemu: memory too small for initial ram disk '%s'\n",
702 loaderparams.initrd_filename);
705 initrd_size = load_image(loaderparams.initrd_filename,
706 phys_ram_base + initrd_offset);
708 if (initrd_size == (target_ulong) -1) {
709 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
710 loaderparams.initrd_filename);
715 /* Store command line. */
716 prom_set(index++, loaderparams.kernel_filename);
718 prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
719 PHYS_TO_VIRT(initrd_offset), initrd_size,
720 loaderparams.kernel_cmdline);
722 prom_set(index++, loaderparams.kernel_cmdline);
724 /* Setup minimum environment variables */
725 prom_set(index++, "memsize");
726 prom_set(index++, "%i", loaderparams.ram_size);
727 prom_set(index++, "modetty0");
728 prom_set(index++, "38400n8r");
729 prom_set(index++, NULL);
734 static void main_cpu_reset(void *opaque)
736 CPUState *env = opaque;
739 /* The bootload does not need to be rewritten as it is located in a
740 read only location. The kernel location and the arguments table
741 location does not change. */
742 if (loaderparams.kernel_filename) {
743 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
749 void mips_malta_init (int ram_size, int vga_ram_size, const char *boot_device,
750 DisplayState *ds, const char **fd_filename, int snapshot,
751 const char *kernel_filename, const char *kernel_cmdline,
752 const char *initrd_filename, const char *cpu_model)
755 unsigned long bios_offset;
756 int64_t kernel_entry;
760 /* fdctrl_t *floppy_controller; */
761 MaltaFPGAState *malta_fpga;
770 if (cpu_model == NULL) {
777 env = cpu_init(cpu_model);
779 fprintf(stderr, "Unable to find CPU definition\n");
782 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
783 qemu_register_reset(main_cpu_reset, env);
786 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
788 /* Map the bios at two physical locations, as on the real board */
789 bios_offset = ram_size + vga_ram_size;
790 cpu_register_physical_memory(0x1e000000LL,
791 BIOS_SIZE, bios_offset | IO_MEM_ROM);
792 cpu_register_physical_memory(0x1fc00000LL,
793 BIOS_SIZE, bios_offset | IO_MEM_ROM);
796 malta_fpga = malta_fpga_init(0x1f000000LL, env);
798 /* Load a BIOS image unless a kernel image has been specified. */
799 if (!kernel_filename) {
800 if (bios_name == NULL)
801 bios_name = BIOS_FILENAME;
802 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
803 ret = load_image(buf, phys_ram_base + bios_offset);
804 if (ret < 0 || ret > BIOS_SIZE) {
806 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
810 /* In little endian mode the 32bit words in the bios are swapped,
811 a neat trick which allows bi-endian firmware. */
812 #ifndef TARGET_WORDS_BIGENDIAN
815 for (addr = (uint32_t *)(phys_ram_base + bios_offset);
816 addr < (uint32_t *)(phys_ram_base + bios_offset + ret);
818 *addr = bswap32(*addr);
824 /* If a kernel image has been specified, write a small bootloader
825 to the flash location. */
826 if (kernel_filename) {
827 loaderparams.ram_size = ram_size;
828 loaderparams.kernel_filename = kernel_filename;
829 loaderparams.kernel_cmdline = kernel_cmdline;
830 loaderparams.initrd_filename = initrd_filename;
831 kernel_entry = load_kernel(env);
832 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
833 write_bootloader(env, bios_offset, kernel_entry);
836 /* Board ID = 0x420 (Malta Board with CoreLV)
837 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
838 map to the board ID. */
839 stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
841 /* Init internal devices */
842 cpu_mips_irq_init_cpu(env);
843 cpu_mips_clock_init(env);
844 cpu_mips_irqctrl_init();
846 /* Interrupt controller */
847 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
848 i8259 = i8259_init(env->irq[2]);
851 pci_bus = pci_gt64120_init(i8259);
854 piix4_devfn = piix4_init(pci_bus, 80);
855 pci_piix4_ide_init(pci_bus, bs_table, piix4_devfn + 1, i8259);
856 usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
857 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100);
858 eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
859 for (i = 0; i < 8; i++) {
860 /* TODO: Populate SPD eeprom data. */
861 smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
863 pit = pit_init(0x40, i8259[0]);
867 i8042_init(i8259[1], i8259[12], 0x60);
868 rtc_state = rtc_init(0x70, i8259[8]);
870 serial_init(0x3f8, i8259[4], serial_hds[0]);
872 serial_init(0x2f8, i8259[3], serial_hds[1]);
874 parallel_init(0x378, i8259[7], parallel_hds[0]);
875 /* XXX: The floppy controller does not work correctly, something is
877 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); */
885 network_init(pci_bus);
887 /* Optional PCI video card */
888 pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size,
889 ram_size, vga_ram_size);
892 QEMUMachine mips_malta_machine = {
894 "MIPS Malta Core LV",