git.maemo.org Git - qemu/blob - hw/omap3.c

   1 /*
   2  * TI OMAP3 processors emulation.
   3  *
   4  * Copyright (C) 2008 yajin <yajin@vm-kernel.org>
   5  * Copyright (C) 2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include "hw.h"
  24 #include "arm-misc.h"
  25 #include "omap.h"
  26 #include "sysemu.h"
  27 #include "qemu-timer.h"
  28 #include "qemu-char.h"
  29 #include "flash.h"
  30 #include "soc_dma.h"
  31 #include "audio/audio.h"
  32 #include "block.h"
  33
  34 /*
  35  * When the flag below is defined, the "less important" I/O regions
  36  * will not be mapped -- this is needed because the current maximum
  37  * number of I/O regions in qemu-system-arm (128) is easily reached
  38  * when everything is mapped.
  39  */
  40 #define OMAP3_REDUCE_IOREGIONS
  41
  42 //#define OMAP3_DEBUG_
  43
  44 #ifdef OMAP3_DEBUG_
  45 #define TRACE(fmt, ...) fprintf(stderr, "%s " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
  46 #else
  47 #define TRACE(...)
  48 #endif
  49
  50 typedef enum {
  51     /* 68000000-680003FF */ L3ID_L3RT = 0,
  52     /* 68000400-680007FF */ L3ID_L3SI,
  53     /* 68000800-680013FF */
  54     /* 68001400-680017FF */ L3ID_MPUSS_IA,
  55     /* 68001800-68001BFF */ L3ID_IVASS_IA,
  56     /* 68001C00-68001FFF */ L3ID_SGXSS_IA,
  57     /* 68002000-680023FF */ L3ID_SMS_TA,
  58     /* 68002400-680027FF */ L3ID_GPMC_TA,
  59     /* 68002800-68002BFF */ L3ID_OCM_RAM_TA,
  60     /* 68002C00-68002FFF */ L3ID_OCM_ROM_TA,
  61     /* 68003000-680033FF */ L3ID_D2D_IA,
  62     /* 68003400-680037FF */ L3ID_D2D_TA,
  63     /* 68003800-68003FFF */
  64     /* 68004000-680043FF */ L3ID_HSUSB_HOST_IA,
  65     /* 68004400-680047FF */ L3ID_HSUSB_OTG_IA,
  66     /* 68004800-68004BFF */
  67     /* 68004C00-68004FFF */ L3ID_SDMA_RD_IA,
  68     /* 68005000-680053FF */ L3ID_SDMA_WR_IA,
  69     /* 68005400-680057FF */ L3ID_DSS_IA,
  70     /* 68005800-68005BFF */ L3ID_CAMISP_IA,
  71     /* 68005C00-68005FFF */ L3ID_DAP_IA,
  72     /* 68006000-680063FF */ L3ID_IVASS_TA,
  73     /* 68006400-680067FF */ L3ID_SGXSS_TA,
  74     /* 68006800-68006BFF */ L3ID_L4_CORE_TA,
  75     /* 68006C00-68006FFF */ L3ID_L4_PER_TA,
  76     /* 68007000-680073FF */ L3ID_L4_EMU_TA,
  77     /* 68007400-6800FFFF */
  78     /* 68010000-680103FF */ L3ID_RT_PM,
  79     /* 68010400-680123FF */
  80     /* 68012400-680127FF */ L3ID_GPMC_PM,
  81     /* 68012800-68012BFF */ L3ID_OCM_RAM_PM,
  82     /* 68012C00-68012FFF */ L3ID_OCM_ROM_PM,
  83     /* 68013000-680133FF */ L3ID_D2D_PM,
  84     /* 68013400-68013FFF */
  85     /* 68014000-680143FF */ L3ID_IVA_PM,
  86     /* 68014400-68FFFFFF */
  87 } omap3_l3_region_id_t;
  88
  89 struct omap_l3_region_s {
  90     target_phys_addr_t offset;
  91     size_t size;
  92     enum {
  93         L3TYPE_GENERIC = 0, /* needs to be mapped separately */
  94         L3TYPE_IA,          /* initiator agent */
  95         L3TYPE_TA,          /* target agent */
  96         L3TYPE_PM,          /* protection mechanism */
  97         L3TYPE_UNDEFINED,   /* every access will emit an error message */
  98     } type;
  99 };
 100
 101 struct omap3_l3_initiator_agent_s {
 102     target_phys_addr_t base;
 103
 104     uint32_t component;
 105     uint32_t control;
 106     uint32_t status;
 107 };
 108
 109 struct omap3_l3pm_s {
 110     target_phys_addr_t base;
 111
 112     uint32_t error_log;
 113     uint8_t  control;
 114     uint16_t req_info_permission[8];
 115     uint16_t read_permission[8];
 116     uint16_t write_permission[8];
 117     uint32_t addr_match[7];
 118 };
 119
 120 union omap3_l3_port_s {
 121     struct omap_target_agent_s ta;
 122     struct omap3_l3_initiator_agent_s ia;
 123     struct omap3_l3pm_s pm;
 124 };
 125
 126 struct omap_l3_s {
 127     target_phys_addr_t base;
 128     int region_count;
 129     union omap3_l3_port_s region[0];
 130 };
 131
 132 static struct omap_l3_region_s omap3_l3_region[] = {
 133     [L3ID_L3RT         ] = {0x00000000, 0x0400, L3TYPE_UNDEFINED},
 134     [L3ID_L3SI         ] = {0x00000400, 0x0400, L3TYPE_UNDEFINED},
 135     [L3ID_MPUSS_IA     ] = {0x00001400, 0x0400, L3TYPE_IA},
 136     [L3ID_IVASS_IA     ] = {0x00001800, 0x0400, L3TYPE_IA},
 137     [L3ID_SGXSS_IA     ] = {0x00001c00, 0x0400, L3TYPE_IA},
 138     [L3ID_SMS_TA       ] = {0x00002000, 0x0400, L3TYPE_TA},
 139     [L3ID_GPMC_TA      ] = {0x00002400, 0x0400, L3TYPE_TA},
 140     [L3ID_OCM_RAM_TA   ] = {0x00002800, 0x0400, L3TYPE_TA},
 141     [L3ID_OCM_ROM_TA   ] = {0x00002c00, 0x0400, L3TYPE_TA},
 142     [L3ID_D2D_IA       ] = {0x00003000, 0x0400, L3TYPE_IA},
 143     [L3ID_D2D_TA       ] = {0x00003400, 0x0400, L3TYPE_TA},
 144     [L3ID_HSUSB_HOST_IA] = {0x00004000, 0x0400, L3TYPE_IA},
 145     [L3ID_HSUSB_OTG_IA ] = {0x00004400, 0x0400, L3TYPE_IA},
 146     [L3ID_SDMA_RD_IA   ] = {0x00004c00, 0x0400, L3TYPE_IA},
 147     [L3ID_SDMA_WR_IA   ] = {0x00005000, 0x0400, L3TYPE_IA},
 148     [L3ID_DSS_IA       ] = {0x00005400, 0x0400, L3TYPE_IA},
 149     [L3ID_CAMISP_IA    ] = {0x00005800, 0x0400, L3TYPE_IA},
 150     [L3ID_DAP_IA       ] = {0x00005c00, 0x0400, L3TYPE_IA},
 151     [L3ID_IVASS_TA     ] = {0x00006000, 0x0400, L3TYPE_TA},
 152     [L3ID_SGXSS_TA     ] = {0x00006400, 0x0400, L3TYPE_TA},
 153     [L3ID_L4_CORE_TA   ] = {0x00006800, 0x0400, L3TYPE_TA},
 154     [L3ID_L4_PER_TA    ] = {0x00006c00, 0x0400, L3TYPE_TA},
 155     [L3ID_L4_EMU_TA    ] = {0x00007000, 0x0400, L3TYPE_TA},
 156     [L3ID_RT_PM        ] = {0x00010000, 0x0400, L3TYPE_PM},
 157     [L3ID_GPMC_PM      ] = {0x00012400, 0x0400, L3TYPE_PM},
 158     [L3ID_OCM_RAM_PM   ] = {0x00012800, 0x0400, L3TYPE_PM},
 159     [L3ID_OCM_ROM_PM   ] = {0x00012c00, 0x0400, L3TYPE_PM},
 160     [L3ID_D2D_PM       ] = {0x00013000, 0x0400, L3TYPE_PM},
 161     [L3ID_IVA_PM       ] = {0x00014000, 0x0400, L3TYPE_PM},
 162 };
 163
 164 #ifndef OMAP3_REDUCE_IOREGIONS
 165 static uint32_t omap3_l3ia_read(void *opaque, target_phys_addr_t addr)
 166 {
 167     struct omap3_l3_initiator_agent_s *s = (struct omap3_l3_initiator_agent_s *)opaque;
 168
 169     switch (addr) {
 170         case 0x00: /* COMPONENT_L */
 171             return s->component;
 172         case 0x04: /* COMPONENT_H */
 173             return 0;
 174         case 0x18: /* CORE_L */
 175             return s->component;
 176         case 0x1c: /* CORE_H */
 177             return (s->component >> 16);
 178         case 0x20: /* AGENT_CONTROL_L */
 179             return s->control;
 180         case 0x24: /* AGENT_CONTROL_H */
 181             return 0;
 182         case 0x28: /* AGENT_STATUS_L */
 183             return s->status;
 184         case 0x2c: /* AGENT_STATUS_H */
 185             return 0;
 186         case 0x58: /* ERROR_LOG_L */
 187             return 0;
 188         case 0x5c: /* ERROR_LOG_H */
 189             return 0;
 190         case 0x60: /* ERROR_LOG_ADDR_L */
 191             return 0;
 192         case 0x64: /* ERROR_LOG_ADDR_H */
 193             return 0;
 194         default:
 195             break;
 196     }
 197
 198     OMAP_BAD_REG(s->base + addr);
 199     return 0;
 200 }
 201
 202 static void omap3_l3ia_write(void *opaque, target_phys_addr_t addr,
 203                              uint32_t value)
 204 {
 205     struct omap3_l3_initiator_agent_s *s = (struct omap3_l3_initiator_agent_s *)opaque;
 206
 207     switch (addr) {
 208         case 0x00: /* COMPONENT_L */
 209         case 0x04: /* COMPONENT_H */
 210         case 0x18: /* CORE_L */
 211         case 0x1c: /* CORE_H */
 212         case 0x60: /* ERROR_LOG_ADDR_L */
 213         case 0x64: /* ERROR_LOG_ADDR_H */
 214             OMAP_RO_REG(s->base + addr);
 215             break;
 216         case 0x24: /* AGENT_CONTROL_H */
 217         case 0x2c: /* AGENT_STATUS_H */
 218         case 0x5c: /* ERROR_LOG_H */
 219             /* RW register but all bits are reserved/read-only */
 220             break;
 221         case 0x20: /* AGENT_CONTROL_L */
 222             s->control = value & 0x3e070711;
 223             /* TODO: some bits are reserved for some IA instances */
 224             break;
 225         case 0x28: /* AGENT_STATUS_L */
 226             s->status &= ~(value & 0x30000000);
 227             break;
 228         case 0x58: /* ERROR_LOG_L */
 229             /* error logging is not implemented, so ignore */
 230             break;
 231         default:
 232             OMAP_BAD_REG(s->base + addr);
 233             break;
 234     }
 235 }
 236
 237 static void omap3_l3ia_save_state(QEMUFile *f, void *opaque)
 238 {
 239     struct omap3_l3_initiator_agent_s *s =
 240         (struct omap3_l3_initiator_agent_s *)opaque;
 241
 242     qemu_put_be32(f, s->control);
 243     qemu_put_be32(f, s->status);
 244 }
 245
 246 static int omap3_l3ia_load_state(QEMUFile *f, void *opaque, int version_id)
 247 {
 248     struct omap3_l3_initiator_agent_s *s =
 249         (struct omap3_l3_initiator_agent_s *)opaque;
 250
 251     if (version_id)
 252         return -EINVAL;
 253
 254     s->control = qemu_get_be32(f);
 255     s->status = qemu_get_be32(f);
 256
 257     return 0;
 258 }
 259
 260 static void omap3_l3ia_init(struct omap3_l3_initiator_agent_s *s)
 261 {
 262     s->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
 263     s->control = 0x3e000000;
 264     s->status = 0;
 265
 266     register_savevm("omap3_l3ia", (s->base >> 8) & 0xffff, 0,
 267                     omap3_l3ia_save_state, omap3_l3ia_load_state, s);
 268 }
 269
 270 static CPUReadMemoryFunc *omap3_l3ia_readfn[] = {
 271     omap_badwidth_read32,
 272     omap_badwidth_read32,
 273     omap3_l3ia_read,
 274 };
 275
 276 static CPUWriteMemoryFunc *omap3_l3ia_writefn[] = {
 277     omap_badwidth_write32,
 278     omap_badwidth_write32,
 279     omap3_l3ia_write,
 280 };
 281
 282 static uint32_t omap3_l3ta_read(void *opaque, target_phys_addr_t addr)
 283 {
 284     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
 285
 286     switch (addr) {
 287         case 0x00: /* COMPONENT_L */
 288             return s->component;
 289         case 0x04: /* COMPONENT_H */
 290             return 0;
 291         case 0x18: /* CORE_L */
 292             return s->component;
 293         case 0x1c: /* CORE_H */
 294             return (s->component >> 16);
 295         case 0x20: /* AGENT_CONTROL_L */
 296             return s->control;
 297         case 0x24: /* AGENT_CONTROL_H */
 298             return s->control_h;
 299         case 0x28: /* AGENT_STATUS_L */
 300             return s->status;
 301         case 0x2c: /* AGENT_STATUS_H */
 302             return 0;
 303         case 0x58: /* ERROR_LOG_L */
 304             return 0;
 305         case 0x5c: /* ERROR_LOG_H */
 306             return 0;
 307         case 0x60: /* ERROR_LOG_ADDR_L */
 308             return 0;
 309         case 0x64: /* ERROR_LOG_ADDR_H */
 310             return 0;
 311         default:
 312             break;
 313     }
 314
 315     OMAP_BAD_REG(s->base + addr);
 316     return 0;
 317 }
 318
 319 static void omap3_l3ta_write(void *opaque, target_phys_addr_t addr,
 320                              uint32_t value)
 321 {
 322     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
 323
 324     switch (addr) {
 325         case 0x00: /* COMPONENT_L */
 326         case 0x04: /* COMPONENT_H */
 327         case 0x18: /* CORE_L */
 328         case 0x1c: /* CORE_H */
 329         case 0x60: /* ERROR_LOG_ADDR_L */
 330         case 0x64: /* ERROR_LOG_ADDR_H */
 331             OMAP_RO_REG(s->base + addr);
 332             break;
 333         case 0x24: /* AGENT_CONTROL_H */
 334         case 0x5c: /* ERROR_LOG_H */
 335             /* RW register but all bits are reserved/read-only */
 336             break;
 337         case 0x20: /* AGENT_CONTROL_L */
 338             s->control = value & 0x03000711;
 339             break;
 340         case 0x28: /* AGENT_STATUS_L */
 341             if (s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_CORE_TA].offset
 342                 || s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_PER_TA].offset
 343                 || s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_EMU_TA].offset) {
 344                 s->status &= ~(value & (1 << 24));
 345             } else
 346                 OMAP_RO_REG(s->base + addr);
 347             break;
 348         case 0x2c: /* AGENT_STATUS_H */
 349             if (s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_CORE_TA].offset
 350                 && s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_PER_TA].offset
 351                 && s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_EMU_TA].offset)
 352                 OMAP_RO_REG(s->base + addr);
 353             /* for L4 core, per, emu TAs this is RW reg */
 354             break;
 355         case 0x58: /* ERROR_LOG_L */
 356             /* error logging is not implemented, so ignore */
 357             break;
 358         default:
 359             OMAP_BAD_REG(s->base + addr);
 360             break;
 361     }
 362 }
 363
 364 static void omap3_l3ta_save_state(QEMUFile *f, void *opaque)
 365 {
 366     struct omap_target_agent_s *s =
 367         (struct omap_target_agent_s *)opaque;
 368
 369     qemu_put_be32(f, s->control);
 370     qemu_put_be32(f, s->status);
 371 }
 372
 373 static int omap3_l3ta_load_state(QEMUFile *f, void *opaque, int version_id)
 374 {
 375     struct omap_target_agent_s *s =
 376         (struct omap_target_agent_s *)opaque;
 377
 378     if (version_id)
 379         return -EINVAL;
 380
 381     s->control = qemu_get_be32(f);
 382     s->status = qemu_get_be32(f);
 383
 384     return 0;
 385 }
 386
 387 static void omap3_l3ta_init(struct omap_target_agent_s *s)
 388 {
 389     s->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
 390     s->control = 0x03000000;
 391     s->status = 0;
 392
 393     register_savevm("omap3_l3ta", (s->base >> 8) & 0xffff, 0,
 394                     omap3_l3ta_save_state, omap3_l3ta_load_state, s);
 395 }
 396
 397 static CPUReadMemoryFunc *omap3_l3ta_readfn[] = {
 398     omap_badwidth_read32,
 399     omap_badwidth_read32,
 400     omap3_l3ta_read,
 401 };
 402
 403 static CPUWriteMemoryFunc *omap3_l3ta_writefn[] = {
 404     omap_badwidth_write32,
 405     omap_badwidth_write32,
 406     omap3_l3ta_write,
 407 };
 408
 409 static uint32_t omap3_l3pm_read8(void *opaque, target_phys_addr_t addr)
 410 {
 411     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 412     int i;
 413
 414     switch (addr) {
 415         case 0x00 ... 0x1f:
 416         case 0x40 ... 0x47:
 417             OMAP_BAD_REG(s->base + addr);
 418             return 0;
 419         /* ERROR_LOG */
 420         case 0x20: return s->error_log & 0xff;
 421         case 0x21: return (s->error_log >> 8) & 0xff;
 422         case 0x22: return (s->error_log >> 16) & 0xff;
 423         case 0x23: return (s->error_log >> 24) & 0xff;
 424         case 0x24 ... 0x27: return 0;
 425         /* CONTROL */
 426         case 0x28 ... 0x2a: return 0;
 427         case 0x2b: return s->control;
 428         case 0x2c ... 0x2f: return 0;
 429         /* ERROR_CLEAR_SINGLE */
 430         case 0x30: return 0; /* TODO: clear single error from log */
 431         case 0x31 ... 0x37: return 0;
 432         /* ERROR_CLEAR_MULTI */
 433         case 0x38: return 0; /* TODO: clear multiple errors from log */
 434         case 0x39 ... 0x3f: return 0;
 435         default:
 436             break;
 437     }
 438
 439     i = (addr - 0x48) / 0x20;
 440     addr -= i * 0x20;
 441     if (i < 7 || (i < 8 && addr < 0x60))
 442         switch (addr) {
 443             /* REQ_INFO_PERMISSION_i */
 444             case 0x48: return s->req_info_permission[i] & 0xff;
 445             case 0x49: return (s->req_info_permission[i] >> 8) & 0xff;
 446             case 0x4a ... 0x4f: return 0;
 447             /* READ_PERMISSION_i */
 448             case 0x50: return s->read_permission[i] & 0xff;
 449             case 0x51: return (s->read_permission[i] >> 8) & 0xff;
 450             case 0x52 ... 0x57: return 0;
 451             /* WRITE_PERMISSION_i */
 452             case 0x58: return s->write_permission[i] & 0xff;
 453             case 0x59: return (s->write_permission[i] >> 8) & 0xff;
 454             case 0x5a ... 0x5f: return 0;
 455             /* ADDR_MATCH_i */
 456             case 0x60: return s->addr_match[i] & 0xff;
 457             case 0x61: return (s->addr_match[i] >> 8) & 0xff;
 458             case 0x62: return (s->addr_match[i] >> 16) & 0xff;
 459             case 0x63 ... 0x67: return 0;
 460             default:
 461                 break;
 462         }
 463
 464     OMAP_BAD_REG(s->base + addr);
 465     return 0;
 466 }
 467
 468 static uint32_t omap3_l3pm_read16(void *opaque, target_phys_addr_t addr)
 469 {
 470     return omap3_l3pm_read8(opaque, addr)
 471         | (omap3_l3pm_read8(opaque, addr + 1) << 8);
 472 }
 473
 474 static uint32_t omap3_l3pm_read32(void *opaque, target_phys_addr_t addr)
 475 {
 476     return omap3_l3pm_read16(opaque, addr)
 477         | (omap3_l3pm_read16(opaque, addr + 2) << 16);
 478 }
 479
 480 static void omap3_l3pm_write8(void *opaque, target_phys_addr_t addr,
 481                               uint32_t value)
 482 {
 483     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 484     int i;
 485
 486     switch (addr) {
 487         case 0x00 ... 0x1f:
 488         case 0x40 ... 0x47:
 489             OMAP_BAD_REGV(s->base + addr, value);
 490             return;
 491         /* ERROR_LOG */
 492         case 0x23:
 493             s->error_log &= ~((value & 0xcf) << 24);
 494         case 0x20 ... 0x22:
 495         case 0x24 ... 0x27:
 496             return;
 497         /* CONTROL */
 498         case 0x2b:
 499             s->control = value & 3;
 500         case 0x28 ... 0x2a:
 501         case 0x2c ... 0x2f:
 502             return;
 503         /* ERROR_CLEAR_SINGLE / ERROR_CLEAR_MULTI */
 504         case 0x30 ... 0x3f:
 505             OMAP_RO_REGV(s->base + addr, value);
 506             return;
 507         default:
 508             break;
 509     }
 510
 511     i = (addr - 0x48) / 0x20;
 512     addr -= i * 0x20;
 513     if (i < 7 || (i < 8 && addr < 0x60))
 514         switch (addr) {
 515             /* REQ_INFO_PERMISSION_i */
 516             case 0x48:
 517                 s->req_info_permission[i] =
 518                     (s->req_info_permission[i] & ~0xff) | (value & 0xff);
 519                 return;
 520             case 0x49:
 521                 s->req_info_permission[i] =
 522                     (s->req_info_permission[i] & ~0xff00) | ((value & 0xff) << 8);
 523                 return;
 524             case 0x4a ... 0x4f:
 525                 return;
 526             /* READ_PERMISSION_i */
 527             case 0x50:
 528                 s->read_permission[i] =
 529                     (s->read_permission[i] & ~0xff) | (value & 0x3e);
 530                 return;
 531             case 0x51:
 532                 s->read_permission[i] =
 533                     (s->read_permission[i] & ~0xff00) | ((value & 0x5f) << 8);
 534                 return;
 535             case 0x52 ... 0x57:
 536                 return;
 537             /* WRITE_PERMISSION_i */
 538             case 0x58:
 539                 s->write_permission[i] =
 540                     (s->write_permission[i] & ~0xff) | (value & 0x3e);
 541                 return;
 542             case 0x59:
 543                 s->write_permission[i] =
 544                     (s->write_permission[i] & ~0xff00) | ((value & 0x5f) << 8);
 545                 return;
 546             case 0x5a ... 0x5f:
 547                 return;
 548             /* ADDR_MATCH_i */
 549             case 0x60:
 550                 s->addr_match[i] = (s->addr_match[i] & ~0xff) | (value & 0xff);
 551                 return;
 552             case 0x61:
 553                 s->addr_match[i] =
 554                     (s->addr_match[i] & ~0xfe00) | ((value & 0xfe) << 8);
 555                 return;
 556             case 0x62:
 557                 s->addr_match[i] =
 558                     (s->addr_match[i] & ~0x0f0000) | ((value & 0x0f) << 16);
 559                 return;
 560             case 0x63 ... 0x67:
 561                 return;
 562             default:
 563                 break;
 564         }
 565
 566     OMAP_BAD_REGV(s->base + addr, value);
 567 }
 568
 569 static void omap3_l3pm_write16(void *opaque, target_phys_addr_t addr,
 570                                uint32_t value)
 571 {
 572     omap3_l3pm_write8(opaque, addr + 0, value & 0xff);
 573     omap3_l3pm_write8(opaque, addr + 1, (value >> 8) & 0xff);
 574 }
 575
 576 static void omap3_l3pm_write32(void *opaque, target_phys_addr_t addr,
 577                                uint32_t value)
 578 {
 579     omap3_l3pm_write16(opaque, addr + 0, value & 0xffff);
 580     omap3_l3pm_write16(opaque, addr + 2, (value >> 16) & 0xffff);
 581 }
 582
 583 static void omap3_l3pm_save_state(QEMUFile *f, void *opaque)
 584 {
 585     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 586     int i;
 587
 588     qemu_put_be32(f, s->error_log);
 589     qemu_put_byte(f, s->control);
 590     for (i = 0; i < 8; i++) {
 591         qemu_put_be16(f, s->req_info_permission[i]);
 592         qemu_put_be16(f, s->read_permission[i]);
 593         qemu_put_be16(f, s->write_permission[i]);
 594         if (i < 7)
 595             qemu_put_be32(f, s->addr_match[i]);
 596     }
 597 }
 598
 599 static int omap3_l3pm_load_state(QEMUFile *f, void *opaque, int version_id)
 600 {
 601     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 602     int i;
 603
 604     if (version_id)
 605         return -EINVAL;
 606
 607     s->error_log = qemu_get_be32(f);
 608     s->control = qemu_get_byte(f);
 609     for (i = 0; i < 8; i++) {
 610         s->req_info_permission[i] = qemu_get_be16(f);
 611         s->read_permission[i] = qemu_get_be16(f);
 612         s->write_permission[i] = qemu_get_be16(f);
 613         if (i < 7)
 614             s->addr_match[i] = qemu_get_be32(f);
 615     }
 616     return 0;
 617 }
 618
 619 static void omap3_l3pm_init(struct omap3_l3pm_s *s)
 620 {
 621     int i;
 622
 623     s->error_log = 0;
 624     s->control = 0x03;
 625     switch (s->base) {
 626         case 0x68010000: /* PM_RT */
 627             s->req_info_permission[0] = 0xffff;
 628             s->req_info_permission[1] = 0;
 629             for (i = 0; i < 2; i++)
 630                 s->read_permission[i] = s->write_permission[i] = 0x1406;
 631             s->addr_match[0] = 0x10230;
 632             break;
 633         case 0x68012400: /* PM_GPMC */
 634             s->req_info_permission[0] = 0;
 635             for (i = 3; i < 8; i++)
 636                 s->req_info_permission[i] = 0xffff;
 637             for (i = 0; i < 8; i++)
 638                 s->read_permission[i] = s->write_permission[i] = 0x563e;
 639             s->addr_match[0] = 0x00098;
 640             break;
 641         case 0x68012800: /* PM_OCM_RAM */
 642             s->req_info_permission[0] = 0;
 643             for (i = 1; i < 8; i++)
 644                 s->req_info_permission[i] = 0xffff;
 645             for (i = 0; i < 8; i++)
 646                 s->read_permission[i] = s->write_permission[i] = 0x5f3e;
 647             s->addr_match[1] = 0x0f810;
 648             break;
 649         case 0x68012C00: /* PM_OCM_ROM */
 650             s->req_info_permission[1] = 0xffff;
 651             for (i = 0; i < 2; i++) {
 652                 s->read_permission[i] = 0x1002;
 653                 s->write_permission[i] = 0;
 654             }
 655             s->addr_match[0] = 0x14028;
 656             break;
 657         case 0x68013000: /* PM_MAD2D */
 658             s->req_info_permission[0] = 0;
 659             for (i = 1; i < 8; i++)
 660                 s->req_info_permission[i] = 0xffff;
 661             for (i = 0; i < 8; i++)
 662                 s->read_permission[i] = s->write_permission[i] = 0x5f1e;
 663             break;
 664         case 0x68014000: /* PM_IVA2.2 */
 665             s->req_info_permission[0] = 0;
 666             for (i = 1; i < 4; i++)
 667                 s->req_info_permission[i] = 0xffff;
 668             for (i = 0; i < 4; i++)
 669                 s->read_permission[i] = s->write_permission[i] = 0x140e;
 670             break;
 671         default:
 672             fprintf(stderr, "%s: unknown PM region (0x%08llx)\n",
 673                     __FUNCTION__, s->base);
 674             exit(-1);
 675             break;
 676     }
 677
 678     register_savevm("omap3_l3pm", (s->base >> 8) & 0xffff, 0,
 679                     omap3_l3pm_save_state, omap3_l3pm_load_state, s);
 680 }
 681
 682 static CPUReadMemoryFunc *omap3_l3pm_readfn[] = {
 683     omap3_l3pm_read8,
 684     omap3_l3pm_read16,
 685     omap3_l3pm_read32,
 686 };
 687
 688 static CPUWriteMemoryFunc *omap3_l3pm_writefn[] = {
 689     omap3_l3pm_write8,
 690     omap3_l3pm_write16,
 691     omap3_l3pm_write32,
 692 };
 693
 694 static uint32_t omap3_l3undef_read8(void *opaque, target_phys_addr_t addr)
 695 {
 696     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 697             __FUNCTION__, addr);
 698     return 0;
 699 }
 700
 701 static uint32_t omap3_l3undef_read16(void *opaque, target_phys_addr_t addr)
 702 {
 703     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 704             __FUNCTION__, addr);
 705     return 0;
 706 }
 707
 708 static uint32_t omap3_l3undef_read32(void *opaque, target_phys_addr_t addr)
 709 {
 710     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 711             __FUNCTION__, addr);
 712     return 0;
 713 }
 714
 715 static void omap3_l3undef_write8(void *opaque, target_phys_addr_t addr,
 716                                uint32_t value)
 717 {
 718     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %02x\n",
 719             __FUNCTION__, addr, value);
 720 }
 721
 722 static void omap3_l3undef_write16(void *opaque, target_phys_addr_t addr,
 723                                 uint32_t value)
 724 {
 725     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %04x\n",
 726             __FUNCTION__, addr, value);
 727 }
 728
 729 static void omap3_l3undef_write32(void *opaque, target_phys_addr_t addr,
 730                                 uint32_t value)
 731 {
 732     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %08x\n",
 733             __FUNCTION__, addr, value);
 734 }
 735
 736 static CPUReadMemoryFunc *omap3_l3undef_readfn[] = {
 737     omap3_l3undef_read8,
 738     omap3_l3undef_read16,
 739     omap3_l3undef_read32,
 740 };
 741
 742 static CPUWriteMemoryFunc *omap3_l3undef_writefn[] = {
 743     omap3_l3undef_write8,
 744     omap3_l3undef_write16,
 745     omap3_l3undef_write32,
 746 };
 747 #endif
 748
 749 static struct omap_l3_s *omap3_l3_init(target_phys_addr_t base,
 750                                        struct omap_l3_region_s *regions,
 751                                        int n)
 752 {
 753 #ifdef OMAP3_REDUCE_IOREGIONS
 754     return NULL;
 755 #else
 756     int i, iomemtype = 0;
 757
 758     struct omap_l3_s *bus = qemu_mallocz(sizeof(*bus) + n * sizeof(*bus->region));
 759     bus->region_count = n;
 760     bus->base = base;
 761
 762     for (i = 0; i < n; i++) {
 763         switch (regions[i].type) {
 764             case L3TYPE_GENERIC:
 765                 /* not mapped for now, mapping will be done later by
 766                    specialized code */
 767                 break;
 768             case L3TYPE_IA:
 769                 iomemtype = cpu_register_io_memory(0, omap3_l3ia_readfn,
 770                                                    omap3_l3ia_writefn,
 771                                                    &bus->region[i].ia);
 772                 bus->region[i].ia.base = base + regions[i].offset;
 773                 omap3_l3ia_init(&bus->region[i].ia);
 774                 break;
 775             case L3TYPE_TA:
 776                 iomemtype = cpu_register_io_memory(0, omap3_l3ta_readfn,
 777                                                    omap3_l3ta_writefn,
 778                                                    &bus->region[i].ta);
 779                 bus->region[i].ta.base = base + regions[i].offset;
 780                 omap3_l3ta_init(&bus->region[i].ta);
 781                 break;
 782             case L3TYPE_PM:
 783                 iomemtype = cpu_register_io_memory(0, omap3_l3pm_readfn,
 784                                                    omap3_l3pm_writefn,
 785                                                    &bus->region[i].pm);
 786                 bus->region[i].pm.base = base + regions[i].offset;
 787                 omap3_l3pm_init(&bus->region[i].pm);
 788                 break;
 789             case L3TYPE_UNDEFINED:
 790                 iomemtype = cpu_register_io_memory(0, omap3_l3undef_readfn,
 791                                                    omap3_l3undef_writefn,
 792                                                    &bus->region[i]);
 793                 break;
 794             default:
 795                 fprintf(stderr, "%s: unknown L3 region type: %d\n",
 796                         __FUNCTION__, regions[i].type);
 797                 exit(-1);
 798                 break;
 799         }
 800         cpu_register_physical_memory(base + regions[i].offset,
 801                                      regions[i].size,
 802                                      iomemtype);
 803     }
 804
 805     return bus;
 806 #endif
 807 }
 808
 809 typedef enum {
 810     /* 48000000-48001FFF */
 811     /* 48002000-48002FFF */ L4ID_SCM = 0,
 812     /* 48003000-48003FFF */ L4ID_SCM_TA,
 813     /* 48004000-48005FFF */ L4ID_CM_A,
 814     /* 48006000-480067FF */ L4ID_CM_B,
 815     /* 48006800-48006FFF */
 816     /* 48007000-48007FFF */ L4ID_CM_TA,
 817     /* 48008000-48023FFF */
 818     /* 48024000-48024FFF */
 819     /* 48025000-48025FFF */
 820     /* 48026000-4803FFFF */
 821     /* 48040000-480407FF */ L4ID_CORE_AP,
 822     /* 48040800-48040FFF */ L4ID_CORE_IP,
 823     /* 48041000-48041FFF */ L4ID_CORE_LA,
 824     /* 48042000-4804FBFF */
 825     /* 4804FC00-4804FFFF */ L4ID_DSI,
 826     /* 48050000-480503FF */ L4ID_DSS,
 827     /* 48050400-480507FF */ L4ID_DISPC,
 828     /* 48050800-48050BFF */ L4ID_RFBI,
 829     /* 48050C00-48050FFF */ L4ID_VENC,
 830     /* 48051000-48051FFF */ L4ID_DSS_TA,
 831     /* 48052000-48055FFF */
 832     /* 48056000-48056FFF */ L4ID_SDMA,
 833     /* 48057000-48057FFF */ L4ID_SDMA_TA,
 834     /* 48058000-4805FFFF */
 835     /* 48060000-48060FFF */ L4ID_I2C3,
 836     /* 48061000-48061FFF */ L4ID_I2C3_TA,
 837     /* 48062000-48062FFF */ L4ID_USBTLL,
 838     /* 48063000-48063FFF */ L4ID_USBTLL_TA,
 839     /* 48064000-480643FF */ L4ID_USBHOST,
 840     /* 48064400-480647FF */ L4ID_USBHOST_OHCI,
 841     /* 48064800-4806BFFF */ L4ID_USBHOST_EHCI,
 842     /* 48065000-48065FFF */ L4ID_USBHOST_TA,
 843     /* 48066000-48069FFF */
 844     /* 4806A000-4806AFFF */ L4ID_UART1,
 845     /* 4806B000-4806BFFF */ L4ID_UART1_TA,
 846     /* 4806C000-4806CFFF */ L4ID_UART2,
 847     /* 4806D000-4806DFFF */ L4ID_UART2_TA,
 848     /* 4806E000-4806FFFF */
 849     /* 48070000-48070FFF */ L4ID_I2C1,
 850     /* 48071000-48071FFF */ L4ID_I2C1_TA,
 851     /* 48072000-48072FFF */ L4ID_I2C2,
 852     /* 48073000-48073FFF */ L4ID_I2C2_TA,
 853     /* 48074000-48074FFF */ L4ID_MCBSP1,
 854     /* 48075000-48075FFF */ L4ID_MCBSP1_TA,
 855     /* 48076000-48085FFF */
 856     /* 48086000-48086FFF */ L4ID_GPTIMER10,
 857     /* 48087000-48087FFF */ L4ID_GPTIMER10_TA,
 858     /* 48088000-48088FFF */ L4ID_GPTIMER11,
 859     /* 48089000-48089FFF */ L4ID_GPTIMER11_TA,
 860     /* 4808A000-4808AFFF */
 861     /* 4808B000-4808BFFF */
 862     /* 4808C000-48093FFF */
 863     /* 48094000-48094FFF */ L4ID_MAILBOX,
 864     /* 48095000-48095FFF */ L4ID_MAILBOX_TA,
 865     /* 48096000-48096FFF */ L4ID_MCBSP5,
 866     /* 48097000-48097FFF */ L4ID_MCBSP5_TA,
 867     /* 48098000-48098FFF */ L4ID_MCSPI1,
 868     /* 48099000-48099FFF */ L4ID_MCSPI1_TA,
 869     /* 4809A000-4809AFFF */ L4ID_MCSPI2,
 870     /* 4809B000-4809BFFF */ L4ID_MCSPI2_TA,
 871     /* 4809C000-4809CFFF */ L4ID_MMCSDIO1,
 872     /* 4809D000-4809DFFF */ L4ID_MMCSDIO1_TA,
 873     /* 4809E000-4809EFFF */ L4ID_MSPRO,
 874     /* 4809F000-4809FFFF */ L4ID_MSPRO_TA,
 875     /* 480A0000-480AAFFF */
 876     /* 480AB000-480ABFFF */ L4ID_HSUSBOTG,
 877     /* 480AC000-480ACFFF */ L4ID_HSUSBOTG_TA,
 878     /* 480AD000-480ADFFF */ L4ID_MMCSDIO3,
 879     /* 480AE000-480AEFFF */ L4ID_MMCSDIO3_TA,
 880     /* 480AF000-480AFFFF */
 881     /* 480B0000-480B0FFF */
 882     /* 480B1000-480B1FFF */
 883     /* 480B2000-480B2FFF */ L4ID_HDQ1WIRE,
 884     /* 480B3000-480B2FFF */ L4ID_HDQ1WIRE_TA,
 885     /* 480B4000-480B4FFF */ L4ID_MMCSDIO2,
 886     /* 480B5000-480B5FFF */ L4ID_MMCSDIO2_TA,
 887     /* 480B6000-480B6FFF */ L4ID_ICRMPU,
 888     /* 480B7000-480B7FFF */ L4ID_ICRMPU_TA,
 889     /* 480B8000-480B8FFF */ L4ID_MCSPI3,
 890     /* 480B9000-480B9FFF */ L4ID_MCSPI3_TA,
 891     /* 480BA000-480BAFFF */ L4ID_MCSPI4,
 892     /* 480BB000-480BBFFF */ L4ID_MCSPI4_TA,
 893     /* 480BC000-480BFFFF */ L4ID_CAMERAISP,
 894     /* 480C0000-480C0FFF */ L4ID_CAMERAISP_TA,
 895     /* 480C1000-480CCFFF */
 896     /* 480CD000-480CDFFF */ L4ID_ICRMODEM,
 897     /* 480CE000-480CEFFF */ L4ID_ICRMODEM_TA,
 898     /* 480CF000-482FFFFF */
 899     /* 48300000-48303FFF */
 900     /* 48304000-48304FFF */ L4ID_GPTIMER12,
 901     /* 48305000-48305FFF */ L4ID_GPTIMER12_TA,
 902     /* 48306000-48307FFF */ L4ID_PRM_A,
 903     /* 48308000-483087FF */ L4ID_PRM_B,
 904     /* 48308800-48308FFF */
 905     /* 48309000-48309FFF */ L4ID_PRM_TA,
 906     /* 4830A000-4830AFFF */ L4ID_TAP,
 907     /* 4830B000-4830BFFF */ L4ID_TAP_TA,
 908     /* 4830C000-4830FFFF */
 909     /* 48310000-48310FFF */ L4ID_GPIO1,
 910     /* 48311000-48311FFF */ L4ID_GPIO1_TA,
 911     /* 48312000-48313FFF */
 912     /* 48314000-48314FFF */ L4ID_WDTIMER2,
 913     /* 48315000-48315FFF */ L4ID_WDTIMER2_TA,
 914     /* 48316000-48317FFF */
 915     /* 48318000-48318FFF */ L4ID_GPTIMER1,
 916     /* 48319000-48319FFF */ L4ID_GPTIMER1_TA,
 917     /* 4831A000-4831FFFF */
 918     /* 48320000-48320FFF */ L4ID_32KTIMER,
 919     /* 48321000-48321FFF */ L4ID_32KTIMER_TA,
 920     /* 48322000-48327FFF */
 921     /* 48328000-483287FF */ L4ID_WAKEUP_AP,
 922     /* 48328800-48328FFF */ L4ID_WAKEUP_C_IP,
 923     /* 48329000-48329FFF */ L4ID_WAKEUP_LA,
 924     /* 4832A000-4832A7FF */ L4ID_WAKEUP_E_IP,
 925     /* 4832A800-4833FFFF */
 926     /* 48340000-48340FFF */
 927     /* 48341000-48FFFFFF */
 928     /* 49000000-490007FF */ L4ID_PER_AP,
 929     /* 49000800-49000FFF */ L4ID_PER_IP,
 930     /* 49001000-49001FFF */ L4ID_PER_LA,
 931     /* 49002000-4901FFFF */
 932     /* 49020000-49020FFF */ L4ID_UART3,
 933     /* 49021000-49021FFF */ L4ID_UART3_TA,
 934     /* 49022000-49022FFF */ L4ID_MCBSP2,
 935     /* 49023000-49023FFF */ L4ID_MCBSP2_TA,
 936     /* 49024000-49024FFF */ L4ID_MCBSP3,
 937     /* 49025000-49025FFF */ L4ID_MCBSP3_TA,
 938     /* 49026000-49026FFF */ L4ID_MCBSP4,
 939     /* 49027000-49027FFF */ L4ID_MCBSP4_TA,
 940     /* 49028000-49028FFF */ L4ID_MCBSP2S,
 941     /* 49029000-49029FFF */ L4ID_MCBSP2S_TA,
 942     /* 4902A000-4902AFFF */ L4ID_MCBSP3S,
 943     /* 4902B000-4902BFFF */ L4ID_MCBSP3S_TA,
 944     /* 4902C000-4902FFFF */
 945     /* 49030000-49030FFF */ L4ID_WDTIMER3,
 946     /* 49031000-49031FFF */ L4ID_WDTIMER3_TA,
 947     /* 49032000-49032FFF */ L4ID_GPTIMER2,
 948     /* 49033000-49033FFF */ L4ID_GPTIMER2_TA,
 949     /* 49034000-49034FFF */ L4ID_GPTIMER3,
 950     /* 49035000-49035FFF */ L4ID_GPTIMER3_TA,
 951     /* 49036000-49036FFF */ L4ID_GPTIMER4,
 952     /* 49037000-49037FFF */ L4ID_GPTIMER4_TA,
 953     /* 49038000-49038FFF */ L4ID_GPTIMER5,
 954     /* 49039000-49039FFF */ L4ID_GPTIMER5_TA,
 955     /* 4903A000-4903AFFF */ L4ID_GPTIMER6,
 956     /* 4903B000-4903BFFF */ L4ID_GPTIMER6_TA,
 957     /* 4903C000-4903CFFF */ L4ID_GPTIMER7,
 958     /* 4903D000-4903DFFF */ L4ID_GPTIMER7_TA,
 959     /* 4903E000-4903EFFF */ L4ID_GPTIMER8,
 960     /* 4903F000-4903FFFF */ L4ID_GPTIMER8_TA,
 961     /* 49040000-49040FFF */ L4ID_GPTIMER9,
 962     /* 49041000-49041FFF */ L4ID_GPTIMER9_TA,
 963     /* 49042000-4904FFFF */
 964     /* 49050000-49050FFF */ L4ID_GPIO2,
 965     /* 49051000-49051FFF */ L4ID_GPIO2_TA,
 966     /* 49052000-49052FFF */ L4ID_GPIO3,
 967     /* 49053000-49053FFF */ L4ID_GPIO3_TA,
 968     /* 49054000-49054FFF */ L4ID_GPIO4,
 969     /* 49055000-49055FFF */ L4ID_GPIO4_TA,
 970     /* 49056000-49056FFF */ L4ID_GPIO5,
 971     /* 49057000-49057FFF */ L4ID_GPIO5_TA,
 972     /* 49058000-49058FFF */ L4ID_GPIO6,
 973     /* 49059000-49059FFF */ L4ID_GPIO6_TA,
 974     /* 4905A000-490FFFFF */
 975     /* 54000000-54003FFF */
 976     /* 54004000-54005FFF */
 977     /* 54006000-540067FF */ L4ID_EMU_AP,
 978     /* 54006800-54006FFF */ L4ID_EMU_IP_C,
 979     /* 54007000-54007FFF */ L4ID_EMU_LA,
 980     /* 54008000-540087FF */ L4ID_EMU_IP_DAP,
 981     /* 54008800-5400FFFF */
 982     /* 54010000-54017FFF */ L4ID_MPUEMU,
 983     /* 54018000-54018FFF */ L4ID_MPUEMU_TA,
 984     /* 54019000-54019FFF */ L4ID_TPIU,
 985     /* 5401A000-5401AFFF */ L4ID_TPIU_TA,
 986     /* 5401B000-5401BFFF */ L4ID_ETB,
 987     /* 5401C000-5401CFFF */ L4ID_ETB_TA,
 988     /* 5401D000-5401DFFF */ L4ID_DAPCTL,
 989     /* 5401E000-5401EFFF */ L4ID_DAPCTL_TA,
 990     /* 5401F000-5401FFFF */ L4ID_SDTI_TA,
 991     /* 54020000-544FFFFF */
 992     /* 54500000-5450FFFF */ L4ID_SDTI_CFG,
 993     /* 54510000-545FFFFF */
 994     /* 54600000-546FFFFF */ L4ID_SDTI,
 995     /* 54700000-54705FFF */
 996     /* 54706000-54707FFF */ L4ID_EMU_PRM_A,
 997     /* 54708000-547087FF */ L4ID_EMU_PRM_B,
 998     /* 54708800-54708FFF */
 999     /* 54709000-54709FFF */ L4ID_EMU_PRM_TA,
1000     /* 5470A000-5470FFFF */
1001     /* 54710000-54710FFF */ L4ID_EMU_GPIO1,
1002     /* 54711000-54711FFF */ L4ID_EMU_GPIO1_TA,
1003     /* 54712000-54713FFF */
1004     /* 54714000-54714FFF */ L4ID_EMU_WDTM2,
1005     /* 54715000-54715FFF */ L4ID_EMU_WDTM2_TA,
1006     /* 54716000-54717FFF */
1007     /* 54718000-54718FFF */ L4ID_EMU_GPTM1,
1008     /* 54719000-54719FFF */ L4ID_EMU_GPTM1_TA,
1009     /* 5471A000-5471FFFF */
1010     /* 54720000-54720FFF */ L4ID_EMU_32KTM,
1011     /* 54721000-54721FFF */ L4ID_EMU_32KTM_TA,
1012     /* 54722000-54727FFF */
1013     /* 54728000-547287FF */ L4ID_EMU_WKUP_AP,
1014     /* 54728800-54728FFF */ L4ID_EMU_WKUP_IPC,
1015     /* 54729000-54729FFF */ L4ID_EMU_WKUP_LA,
1016     /* 5472A000-5472A7FF */ L4ID_EMU_WKUP_IPE,
1017     /* 5472A800-547FFFFF */
1018 } omap3_l4_region_id_t;
1019
1020 typedef enum {
1021     L4TYPE_GENERIC = 0, /* not mapped by default, must be mapped separately */
1022     L4TYPE_IA,          /* initiator agent */
1023     L4TYPE_TA,          /* target agent */
1024     L4TYPE_LA,          /* link register agent */
1025     L4TYPE_AP           /* address protection */
1026 } omap3_l4_region_type_t;
1027
1028 /* we reuse the "access" member for defining region type -- the original
1029    omap_l4_region_s "access" member is not used anywhere else anyway! */
1030 static struct omap_l4_region_s omap3_l4_region[] = {
1031     /* L4-Core */
1032     [L4ID_SCM         ] = {0x00002000, 0x1000, L4TYPE_GENERIC},
1033     [L4ID_SCM_TA      ] = {0x00003000, 0x1000, L4TYPE_TA},
1034     [L4ID_CM_A        ] = {0x00004000, 0x2000, L4TYPE_GENERIC},
1035     [L4ID_CM_B        ] = {0x00006000, 0x0800, L4TYPE_GENERIC},
1036     [L4ID_CM_TA       ] = {0x00007000, 0x1000, L4TYPE_TA},
1037     [L4ID_CORE_AP     ] = {0x00040000, 0x0800, L4TYPE_AP},
1038     [L4ID_CORE_IP     ] = {0x00040800, 0x0800, L4TYPE_IA},
1039     [L4ID_CORE_LA     ] = {0x00041000, 0x1000, L4TYPE_LA},
1040     [L4ID_DSI         ] = {0x0004fc00, 0x0400, L4TYPE_GENERIC},
1041     [L4ID_DSS         ] = {0x00050000, 0x0400, L4TYPE_GENERIC},
1042     [L4ID_DISPC       ] = {0x00050400, 0x0400, L4TYPE_GENERIC},
1043     [L4ID_RFBI        ] = {0x00050800, 0x0400, L4TYPE_GENERIC},
1044     [L4ID_VENC        ] = {0x00050c00, 0x0400, L4TYPE_GENERIC},
1045     [L4ID_DSS_TA      ] = {0x00051000, 0x1000, L4TYPE_TA},
1046     [L4ID_SDMA        ] = {0x00056000, 0x1000, L4TYPE_GENERIC},
1047     [L4ID_SDMA_TA     ] = {0x00057000, 0x1000, L4TYPE_TA},
1048     [L4ID_I2C3        ] = {0x00060000, 0x1000, L4TYPE_GENERIC},
1049     [L4ID_I2C3_TA     ] = {0x00061000, 0x1000, L4TYPE_TA},
1050     [L4ID_USBTLL      ] = {0x00062000, 0x1000, L4TYPE_GENERIC},
1051     [L4ID_USBTLL_TA   ] = {0x00063000, 0x1000, L4TYPE_TA},
1052     [L4ID_USBHOST     ] = {0x00064000, 0x0400, L4TYPE_GENERIC},
1053     [L4ID_USBHOST_OHCI] = {0x00064400, 0x0400, L4TYPE_GENERIC},
1054     [L4ID_USBHOST_EHCI] = {0x00064800, 0x0400, L4TYPE_GENERIC},
1055     [L4ID_USBHOST_TA  ] = {0x00065000, 0x1000, L4TYPE_TA},
1056     [L4ID_UART1       ] = {0x0006a000, 0x1000, L4TYPE_GENERIC},
1057     [L4ID_UART1_TA    ] = {0x0006b000, 0x1000, L4TYPE_TA},
1058     [L4ID_UART2       ] = {0x0006c000, 0x1000, L4TYPE_GENERIC},
1059     [L4ID_UART2_TA    ] = {0x0006d000, 0x1000, L4TYPE_TA},
1060     [L4ID_I2C1        ] = {0x00070000, 0x1000, L4TYPE_GENERIC},
1061     [L4ID_I2C1_TA     ] = {0x00071000, 0x1000, L4TYPE_TA},
1062     [L4ID_I2C2        ] = {0x00072000, 0x1000, L4TYPE_GENERIC},
1063     [L4ID_I2C2_TA     ] = {0x00073000, 0x1000, L4TYPE_TA},
1064     [L4ID_MCBSP1      ] = {0x00074000, 0x1000, L4TYPE_GENERIC},
1065     [L4ID_MCBSP1_TA   ] = {0x00075000, 0x1000, L4TYPE_TA},
1066     [L4ID_GPTIMER10   ] = {0x00086000, 0x1000, L4TYPE_GENERIC},
1067     [L4ID_GPTIMER10_TA] = {0x00087000, 0x1000, L4TYPE_TA},
1068     [L4ID_GPTIMER11   ] = {0x00088000, 0x1000, L4TYPE_GENERIC},
1069     [L4ID_GPTIMER11_TA] = {0x00089000, 0x1000, L4TYPE_TA},
1070     [L4ID_MAILBOX     ] = {0x00094000, 0x1000, L4TYPE_GENERIC},
1071     [L4ID_MAILBOX_TA  ] = {0x00095000, 0x1000, L4TYPE_TA},
1072     [L4ID_MCBSP5      ] = {0x00096000, 0x1000, L4TYPE_GENERIC},
1073     [L4ID_MCBSP5_TA   ] = {0x00097000, 0x1000, L4TYPE_TA},
1074     [L4ID_MCSPI1      ] = {0x00098000, 0x1000, L4TYPE_GENERIC},
1075     [L4ID_MCSPI1_TA   ] = {0x00099000, 0x1000, L4TYPE_TA},
1076     [L4ID_MCSPI2      ] = {0x0009a000, 0x1000, L4TYPE_GENERIC},
1077     [L4ID_MCSPI2_TA   ] = {0x0009b000, 0x1000, L4TYPE_TA},
1078     [L4ID_MMCSDIO1    ] = {0x0009c000, 0x1000, L4TYPE_GENERIC},
1079     [L4ID_MMCSDIO1_TA ] = {0x0009d000, 0x1000, L4TYPE_TA},
1080     [L4ID_MSPRO       ] = {0x0009e000, 0x1000, L4TYPE_GENERIC},
1081     [L4ID_MSPRO_TA    ] = {0x0009f000, 0x1000, L4TYPE_TA},
1082     [L4ID_HSUSBOTG    ] = {0x000ab000, 0x1000, L4TYPE_GENERIC},
1083     [L4ID_HSUSBOTG_TA ] = {0x000ac000, 0x1000, L4TYPE_TA},
1084     [L4ID_MMCSDIO3    ] = {0x000ad000, 0x1000, L4TYPE_GENERIC},
1085     [L4ID_MMCSDIO3_TA ] = {0x000ae000, 0x1000, L4TYPE_TA},
1086     [L4ID_HDQ1WIRE    ] = {0x000b2000, 0x1000, L4TYPE_GENERIC},
1087     [L4ID_HDQ1WIRE_TA ] = {0x000b3000, 0x1000, L4TYPE_TA},
1088     [L4ID_MMCSDIO2    ] = {0x000b4000, 0x1000, L4TYPE_GENERIC},
1089     [L4ID_MMCSDIO2_TA ] = {0x000b5000, 0x1000, L4TYPE_TA},
1090     [L4ID_ICRMPU      ] = {0x000b6000, 0x1000, L4TYPE_GENERIC},
1091     [L4ID_ICRMPU_TA   ] = {0x000b7000, 0x1000, L4TYPE_TA},
1092     [L4ID_MCSPI3      ] = {0x000b8000, 0x1000, L4TYPE_GENERIC},
1093     [L4ID_MCSPI3_TA   ] = {0x000b9000, 0x1000, L4TYPE_TA},
1094     [L4ID_MCSPI4      ] = {0x000ba000, 0x1000, L4TYPE_GENERIC},
1095     [L4ID_MCSPI4_TA   ] = {0x000bb000, 0x1000, L4TYPE_TA},
1096     [L4ID_CAMERAISP   ] = {0x000bc000, 0x4000, L4TYPE_GENERIC},
1097     [L4ID_CAMERAISP_TA] = {0x000c0000, 0x1000, L4TYPE_TA},
1098     [L4ID_ICRMODEM    ] = {0x000cd000, 0x1000, L4TYPE_GENERIC},
1099     [L4ID_ICRMODEM_TA ] = {0x000ce000, 0x1000, L4TYPE_TA},
1100     /* L4-Wakeup interconnect region A */
1101     [L4ID_GPTIMER12   ] = {0x00304000, 0x1000, L4TYPE_GENERIC},
1102     [L4ID_GPTIMER12_TA] = {0x00305000, 0x1000, L4TYPE_TA},
1103     [L4ID_PRM_A       ] = {0x00306000, 0x2000, L4TYPE_GENERIC},
1104     [L4ID_PRM_B       ] = {0x00308000, 0x0800, L4TYPE_GENERIC},
1105     [L4ID_PRM_TA      ] = {0x00309000, 0x1000, L4TYPE_TA},
1106     /* L4-Core */
1107     [L4ID_TAP         ] = {0x0030a000, 0x1000, L4TYPE_GENERIC},
1108     [L4ID_TAP_TA      ] = {0x0030b000, 0x1000, L4TYPE_TA},
1109     /* L4-Wakeup interconnect region B */
1110     [L4ID_GPIO1       ] = {0x00310000, 0x1000, L4TYPE_GENERIC},
1111     [L4ID_GPIO1_TA    ] = {0x00311000, 0x1000, L4TYPE_TA},
1112     [L4ID_WDTIMER2    ] = {0x00314000, 0x1000, L4TYPE_GENERIC},
1113     [L4ID_WDTIMER2_TA ] = {0x00315000, 0x1000, L4TYPE_TA},
1114     [L4ID_GPTIMER1    ] = {0x00318000, 0x1000, L4TYPE_GENERIC},
1115     [L4ID_GPTIMER1_TA ] = {0x00319000, 0x1000, L4TYPE_TA},
1116     [L4ID_32KTIMER    ] = {0x00320000, 0x1000, L4TYPE_GENERIC},
1117     [L4ID_32KTIMER_TA ] = {0x00321000, 0x1000, L4TYPE_TA},
1118     [L4ID_WAKEUP_AP   ] = {0x00328000, 0x0800, L4TYPE_AP},
1119     [L4ID_WAKEUP_C_IP ] = {0x00328800, 0x0800, L4TYPE_IA},
1120     [L4ID_WAKEUP_LA   ] = {0x00329000, 0x1000, L4TYPE_LA},
1121     [L4ID_WAKEUP_E_IP ] = {0x0032a000, 0x0800, L4TYPE_IA},
1122     /* L4-Per */
1123     [L4ID_PER_AP      ] = {0x01000000, 0x0800, L4TYPE_AP},
1124     [L4ID_PER_IP      ] = {0x01000800, 0x0800, L4TYPE_IA},
1125     [L4ID_PER_LA      ] = {0x01001000, 0x1000, L4TYPE_LA},
1126     [L4ID_UART3       ] = {0x01020000, 0x1000, L4TYPE_GENERIC},
1127     [L4ID_UART3_TA    ] = {0x01021000, 0x1000, L4TYPE_TA},
1128     [L4ID_MCBSP2      ] = {0x01022000, 0x1000, L4TYPE_GENERIC},
1129     [L4ID_MCBSP2_TA   ] = {0x01023000, 0x1000, L4TYPE_TA},
1130     [L4ID_MCBSP3      ] = {0x01024000, 0x1000, L4TYPE_GENERIC},
1131     [L4ID_MCBSP3_TA   ] = {0x01025000, 0x1000, L4TYPE_TA},
1132     [L4ID_MCBSP4      ] = {0x01026000, 0x1000, L4TYPE_GENERIC},
1133     [L4ID_MCBSP4_TA   ] = {0x01027000, 0x1000, L4TYPE_TA},
1134     [L4ID_MCBSP2S     ] = {0x01028000, 0x1000, L4TYPE_GENERIC},
1135     [L4ID_MCBSP2S_TA  ] = {0x01029000, 0x1000, L4TYPE_TA},
1136     [L4ID_MCBSP3S     ] = {0x0102a000, 0x1000, L4TYPE_GENERIC},
1137     [L4ID_MCBSP3S_TA  ] = {0x0102b000, 0x1000, L4TYPE_TA},
1138     [L4ID_WDTIMER3    ] = {0x01030000, 0x1000, L4TYPE_GENERIC},
1139     [L4ID_WDTIMER3_TA ] = {0x01031000, 0x1000, L4TYPE_TA},
1140     [L4ID_GPTIMER2    ] = {0x01032000, 0x1000, L4TYPE_GENERIC},
1141     [L4ID_GPTIMER2_TA ] = {0x01033000, 0x1000, L4TYPE_TA},
1142     [L4ID_GPTIMER3    ] = {0x01034000, 0x1000, L4TYPE_GENERIC},
1143     [L4ID_GPTIMER3_TA ] = {0x01035000, 0x1000, L4TYPE_TA},
1144     [L4ID_GPTIMER4    ] = {0x01036000, 0x1000, L4TYPE_GENERIC},
1145     [L4ID_GPTIMER4_TA ] = {0x01037000, 0x1000, L4TYPE_TA},
1146     [L4ID_GPTIMER5    ] = {0x01038000, 0x1000, L4TYPE_GENERIC},
1147     [L4ID_GPTIMER5_TA ] = {0x01039000, 0x1000, L4TYPE_TA},
1148     [L4ID_GPTIMER6    ] = {0x0103a000, 0x1000, L4TYPE_GENERIC},
1149     [L4ID_GPTIMER6_TA ] = {0x0103b000, 0x1000, L4TYPE_TA},
1150     [L4ID_GPTIMER7    ] = {0x0103c000, 0x1000, L4TYPE_GENERIC},
1151     [L4ID_GPTIMER7_TA ] = {0x0103d000, 0x1000, L4TYPE_TA},
1152     [L4ID_GPTIMER8    ] = {0x0103e000, 0x1000, L4TYPE_GENERIC},
1153     [L4ID_GPTIMER8_TA ] = {0x0103f000, 0x1000, L4TYPE_TA},
1154     [L4ID_GPTIMER9    ] = {0x01040000, 0x1000, L4TYPE_GENERIC},
1155     [L4ID_GPTIMER9_TA ] = {0x01041000, 0x1000, L4TYPE_TA},
1156     [L4ID_GPIO2       ] = {0x01050000, 0x1000, L4TYPE_GENERIC},
1157     [L4ID_GPIO2_TA    ] = {0x01051000, 0x1000, L4TYPE_TA},
1158     [L4ID_GPIO3       ] = {0x01052000, 0x1000, L4TYPE_GENERIC},
1159     [L4ID_GPIO3_TA    ] = {0x01053000, 0x1000, L4TYPE_TA},
1160     [L4ID_GPIO4       ] = {0x01054000, 0x1000, L4TYPE_GENERIC},
1161     [L4ID_GPIO4_TA    ] = {0x01055000, 0x1000, L4TYPE_TA},
1162     [L4ID_GPIO5       ] = {0x01056000, 0x1000, L4TYPE_GENERIC},
1163     [L4ID_GPIO5_TA    ] = {0x01057000, 0x1000, L4TYPE_TA},
1164     [L4ID_GPIO6       ] = {0x01058000, 0x1000, L4TYPE_GENERIC},
1165     [L4ID_GPIO6_TA    ] = {0x01059000, 0x1000, L4TYPE_TA},
1166     /* L4-Emu */
1167     [L4ID_EMU_AP      ] = {0x0c006000, 0x0800, L4TYPE_AP},
1168     [L4ID_EMU_IP_C    ] = {0x0c006800, 0x0800, L4TYPE_IA},
1169     [L4ID_EMU_LA      ] = {0x0c007000, 0x1000, L4TYPE_LA},
1170     [L4ID_EMU_IP_DAP  ] = {0x0c008000, 0x0800, L4TYPE_IA},
1171     [L4ID_MPUEMU      ] = {0x0c010000, 0x8000, L4TYPE_GENERIC},
1172     [L4ID_MPUEMU_TA   ] = {0x0c018000, 0x1000, L4TYPE_TA},
1173     [L4ID_TPIU        ] = {0x0c019000, 0x1000, L4TYPE_GENERIC},
1174     [L4ID_TPIU_TA     ] = {0x0c01a000, 0x1000, L4TYPE_TA},
1175     [L4ID_ETB         ] = {0x0c01b000, 0x1000, L4TYPE_GENERIC},
1176     [L4ID_ETB_TA      ] = {0x0c01c000, 0x1000, L4TYPE_TA},
1177     [L4ID_DAPCTL      ] = {0x0c01d000, 0x1000, L4TYPE_GENERIC},
1178     [L4ID_DAPCTL_TA   ] = {0x0c01e000, 0x1000, L4TYPE_TA},
1179     [L4ID_EMU_PRM_A   ] = {0x0c706000, 0x2000, L4TYPE_GENERIC},
1180     [L4ID_EMU_PRM_B   ] = {0x0c706800, 0x0800, L4TYPE_GENERIC},
1181     [L4ID_EMU_PRM_TA  ] = {0x0c709000, 0x1000, L4TYPE_TA},
1182     [L4ID_EMU_GPIO1   ] = {0x0c710000, 0x1000, L4TYPE_GENERIC},
1183     [L4ID_EMU_GPIO1_TA] = {0x0c711000, 0x1000, L4TYPE_TA},
1184     [L4ID_EMU_WDTM2   ] = {0x0c714000, 0x1000, L4TYPE_GENERIC},
1185     [L4ID_EMU_WDTM2_TA] = {0x0c715000, 0x1000, L4TYPE_TA},
1186     [L4ID_EMU_GPTM1   ] = {0x0c718000, 0x1000, L4TYPE_GENERIC},
1187     [L4ID_EMU_GPTM1_TA] = {0x0c719000, 0x1000, L4TYPE_TA},
1188     [L4ID_EMU_32KTM   ] = {0x0c720000, 0x1000, L4TYPE_GENERIC},
1189     [L4ID_EMU_32KTM_TA] = {0x0c721000, 0x1000, L4TYPE_TA},
1190     [L4ID_EMU_WKUP_AP ] = {0x0c728000, 0x0800, L4TYPE_AP},
1191     [L4ID_EMU_WKUP_IPC] = {0x0c728800, 0x0800, L4TYPE_IA},
1192     [L4ID_EMU_WKUP_LA ] = {0x0c729000, 0x1000, L4TYPE_LA},
1193     [L4ID_EMU_WKUP_IPE] = {0x0c72a000, 0x0800, L4TYPE_IA},
1194 };
1195
1196 typedef enum {
1197     L4A_SCM = 0,
1198     L4A_CM,
1199     L4A_PRM,
1200     L4A_GPTIMER1,
1201     L4A_GPTIMER2,
1202     L4A_GPTIMER3,
1203     L4A_GPTIMER4,
1204     L4A_GPTIMER5,
1205     L4A_GPTIMER6,
1206     L4A_GPTIMER7,
1207     L4A_GPTIMER8,
1208     L4A_GPTIMER9,
1209     L4A_GPTIMER10,
1210     L4A_GPTIMER11,
1211     L4A_GPTIMER12,
1212     L4A_WDTIMER2,
1213     L4A_32KTIMER,
1214     L4A_UART1,
1215     L4A_UART2,
1216     L4A_UART3,
1217     L4A_DSS,
1218     L4A_GPIO1,
1219     L4A_GPIO2,
1220     L4A_GPIO3,
1221     L4A_GPIO4,
1222     L4A_GPIO5,
1223     L4A_GPIO6,
1224     L4A_MMC1,
1225     L4A_MMC2,
1226     L4A_MMC3,
1227     L4A_I2C1,
1228     L4A_I2C2,
1229     L4A_I2C3,
1230     L4A_TAP,
1231     L4A_USBHS_OTG,
1232     L4A_USBHS_HOST,
1233     L4A_USBHS_TLL,
1234     L4A_MCSPI1,
1235     L4A_MCSPI2,
1236     L4A_MCSPI3,
1237     L4A_MCSPI4,
1238     L4A_SDMA
1239 } omap3_l4_agent_info_id_t;
1240
1241 struct omap3_l4_agent_info_s {
1242     omap3_l4_agent_info_id_t agent_id;
1243     omap3_l4_region_id_t     first_region_id;
1244     int                      region_count;
1245 };
1246
1247 static const struct omap3_l4_agent_info_s omap3_l4_agent_info[] = {
1248     /* L4-Core Agents */
1249     {L4A_DSS,        L4ID_DSI,       6},
1250     /* TODO: camera */
1251     {L4A_USBHS_OTG,  L4ID_HSUSBOTG,  2},
1252     {L4A_USBHS_HOST, L4ID_USBHOST,   4},
1253     {L4A_USBHS_TLL,  L4ID_USBTLL,    2},
1254     {L4A_UART1,      L4ID_UART1,     2},
1255     {L4A_UART2,      L4ID_UART2,     2},
1256     {L4A_I2C1,       L4ID_I2C1,      2},
1257     {L4A_I2C2,       L4ID_I2C2,      2},
1258     {L4A_I2C3,       L4ID_I2C3,      2},
1259     /* TODO: McBSP1 */
1260     /* TODO: McBSP5 */
1261     {L4A_GPTIMER10,  L4ID_GPTIMER10, 2},
1262     {L4A_GPTIMER11,  L4ID_GPTIMER11, 2},
1263     {L4A_MCSPI1,     L4ID_MCSPI1,    2},
1264     {L4A_MCSPI2,     L4ID_MCSPI2,    2},
1265     {L4A_MMC1,       L4ID_MMCSDIO1,  2},
1266     {L4A_MMC2,       L4ID_MMCSDIO2,  2},
1267     {L4A_MMC3,       L4ID_MMCSDIO3,  2},
1268     /* TODO: HDQ/1-Wire */
1269     /* TODO: Mailbox */
1270     {L4A_MCSPI3,     L4ID_MCSPI3,    2},
1271     {L4A_MCSPI4,     L4ID_MCSPI4,    2},
1272     {L4A_SDMA,       L4ID_SDMA,      2},
1273     {L4A_CM,         L4ID_CM_A,      3},
1274     {L4A_SCM,        L4ID_SCM,       2},
1275     {L4A_TAP,        L4ID_TAP,       2},
1276     /* L4-Wakeup Agents */
1277     {L4A_GPTIMER12,  L4ID_GPTIMER12, 2},
1278     {L4A_PRM,        L4ID_PRM_A,     3},
1279     {L4A_GPIO1,      L4ID_GPIO1,     2},
1280     {L4A_WDTIMER2,   L4ID_WDTIMER2,  2},
1281     {L4A_GPTIMER1,   L4ID_GPTIMER1,  2},
1282     {L4A_32KTIMER,   L4ID_32KTIMER,  2},
1283     /* L4-Per Agents */
1284     {L4A_UART3,      L4ID_UART3,     2},
1285     /* TODO: McBSP2 */
1286     /* TODO: McBSP3 */
1287     {L4A_GPTIMER2,   L4ID_GPTIMER2,  2},
1288     {L4A_GPTIMER3,   L4ID_GPTIMER3,  2},
1289     {L4A_GPTIMER4,   L4ID_GPTIMER4,  2},
1290     {L4A_GPTIMER5,   L4ID_GPTIMER5,  2},
1291     {L4A_GPTIMER6,   L4ID_GPTIMER6,  2},
1292     {L4A_GPTIMER7,   L4ID_GPTIMER7,  2},
1293     {L4A_GPTIMER8,   L4ID_GPTIMER8,  2},
1294     {L4A_GPTIMER9,   L4ID_GPTIMER9,  2},
1295     {L4A_GPIO2,      L4ID_GPIO2,     2},
1296     {L4A_GPIO3,      L4ID_GPIO3,     2},
1297     {L4A_GPIO4,      L4ID_GPIO4,     2},
1298     {L4A_GPIO5,      L4ID_GPIO5,     2},
1299     {L4A_GPIO6,      L4ID_GPIO6,     2},
1300 };
1301
1302 #ifndef OMAP3_REDUCE_IOREGIONS
1303 static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)
1304 {
1305     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1306
1307     switch (addr) {
1308         case 0x00: /* COMPONENT_L */
1309             return s->component;
1310         case 0x04: /* COMPONENT_H */
1311             return 0;
1312         case 0x18: /* CORE_L */
1313             return s->component;
1314         case 0x1c: /* CORE_H */
1315             return (s->component >> 16);
1316         case 0x20: /* AGENT_CONTROL_L */
1317             return s->control;
1318         case 0x24: /* AGENT_CONTROL_H */
1319             return s->control_h;
1320         case 0x28: /* AGENT_STATUS_L */
1321             return s->status;
1322         case 0x2c: /* AGENT_STATUS_H */
1323             return 0;
1324         default:
1325             break;
1326     }
1327
1328     OMAP_BAD_REG(s->base + addr);
1329     return 0;
1330 }
1331
1332 static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr,
1333                              uint32_t value)
1334 {
1335     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1336
1337     switch (addr) {
1338         case 0x00: /* COMPONENT_L */
1339         case 0x04: /* COMPONENT_H */
1340         case 0x18: /* CORE_L */
1341         case 0x1c: /* CORE_H */
1342             OMAP_RO_REG(s->base + addr);
1343             break;
1344         case 0x20: /* AGENT_CONTROL_L */
1345             s->control = value & 0x00000701;
1346             break;
1347         case 0x24: /* AGENT_CONTROL_H */
1348             s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */
1349             break;
1350         case 0x28: /* AGENT_STATUS_L */
1351             if (value & 0x100)
1352                 s->status &= ~0x100; /* REQ_TIMEOUT */
1353             break;
1354         case 0x2c: /* AGENT_STATUS_H */
1355             /* no writable bits although the register is listed as RW */
1356             break;
1357         default:
1358             OMAP_BAD_REG(s->base + addr);
1359             break;
1360     }
1361 }
1362
1363 static void omap3_l4ta_save_state(QEMUFile *f, void *opaque)
1364 {
1365     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1366
1367     qemu_put_be32(f, s->control);
1368     qemu_put_be32(f, s->control_h);
1369     qemu_put_be32(f, s->status);
1370 }
1371
1372 static int omap3_l4ta_load_state(QEMUFile *f, void *opaque, int version_id)
1373 {
1374     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1375
1376     if (version_id)
1377         return -EINVAL;
1378
1379     s->control = qemu_get_be32(f);
1380     s->control_h = qemu_get_be32(f);
1381     s->status = qemu_get_be32(f);
1382
1383     return 0;
1384 }
1385
1386 static CPUReadMemoryFunc *omap3_l4ta_readfn[] = {
1387     omap_badwidth_read32,
1388     omap_badwidth_read32,
1389     omap3_l4ta_read,
1390 };
1391
1392 static CPUWriteMemoryFunc *omap3_l4ta_writefn[] = {
1393     omap_badwidth_write32,
1394     omap_badwidth_write32,
1395     omap3_l4ta_write,
1396 };
1397 #endif
1398
1399 static struct omap_target_agent_s *omap3_l4ta_init(struct omap_l4_s *bus, int cs)
1400 {
1401 #ifndef OMAP3_REDUCE_IOREGIONS
1402     int iomemtype;
1403 #endif
1404     int i;
1405     struct omap_target_agent_s *ta = 0;
1406     const struct omap3_l4_agent_info_s *info = 0;
1407
1408     for (i = 0; i < bus->ta_num; i++)
1409         if (omap3_l4_agent_info[i].agent_id == cs) {
1410             ta = &bus->ta[i];
1411             info = &omap3_l4_agent_info[i];
1412             break;
1413         }
1414     if (!ta) {
1415         fprintf(stderr, "%s: invalid agent id (%i)\n", __FUNCTION__, cs);
1416         exit(-1);
1417     }
1418     if (ta->bus) {
1419         fprintf(stderr, "%s: target agent (%d) already initialized\n",
1420                 __FUNCTION__, cs);
1421         exit(-1);
1422     }
1423
1424     ta->bus = bus;
1425     ta->start = &omap3_l4_region[info->first_region_id];
1426     ta->regions = info->region_count;
1427
1428     ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1429     ta->status = 0x00000000;
1430     ta->control = 0x00000200;
1431
1432     for (i = 0; i < info->region_count; i++)
1433         if (omap3_l4_region[info->first_region_id + i].access == L4TYPE_TA)
1434             break;
1435     if (i >= info->region_count) {
1436         fprintf(stderr, "%s: specified agent (%d) has no TA region\n",
1437                 __FUNCTION__, cs);
1438         exit(-1);
1439     }
1440
1441 #ifndef OMAP3_REDUCE_IOREGIONS
1442     iomemtype = l4_register_io_memory(0, omap3_l4ta_readfn,
1443                                       omap3_l4ta_writefn, ta);
1444     ta->base = omap_l4_attach(ta, i, iomemtype);
1445
1446     register_savevm("omap3_l4ta", ta->base >> 8, 0,
1447                     omap3_l4ta_save_state, omap3_l4ta_load_state, ta);
1448 #else
1449     ta->base = ta->bus->base + ta->start[i].offset;
1450 #endif
1451
1452     return ta;
1453 }
1454
1455 /* common PRM domain registers */
1456 struct omap3_prm_domain_s {
1457     uint32_t rm_rstctrl;     /* 50 */
1458     uint32_t rm_rstst;       /* 58 */
1459     uint32_t pm_wken;        /* a0 */
1460     uint32_t pm_mpugrpsel;   /* a4 */
1461     uint32_t pm_ivagrpsel;   /* a8 */
1462     uint32_t pm_wkst;        /* b0 */
1463     uint32_t pm_wkst3;       /* b8 */
1464     uint32_t pm_wkdep;       /* c8 */
1465     uint32_t pm_evgenctrl;   /* d4 */
1466     uint32_t pm_evgenontim;  /* d8 */
1467     uint32_t pm_evgenofftim; /* dc */
1468     uint32_t pm_pwstctrl;    /* e0 */
1469     uint32_t pm_pwstst;      /* e4 */
1470     uint32_t pm_prepwstst;   /* e8 */
1471     uint32_t pm_wken3;       /* f0 */
1472 };
1473
1474 struct omap3_prm_s {
1475     qemu_irq mpu_irq;
1476     qemu_irq iva_irq;
1477     struct omap_mpu_state_s *omap;
1478
1479     struct omap3_prm_domain_s iva2;
1480     struct omap3_prm_domain_s mpu;
1481     struct omap3_prm_domain_s core;
1482     struct omap3_prm_domain_s sgx;
1483     struct omap3_prm_domain_s wkup;
1484     struct omap3_prm_domain_s dss;
1485     struct omap3_prm_domain_s cam;
1486     struct omap3_prm_domain_s per;
1487     struct omap3_prm_domain_s emu;
1488     struct omap3_prm_domain_s neon;
1489     struct omap3_prm_domain_s usbhost;
1490
1491     uint32_t prm_irqstatus_iva2;
1492     uint32_t prm_irqenable_iva2;
1493
1494     uint32_t pm_iva2grpsel3_core;
1495     uint32_t pm_mpugrpsel3_core;
1496
1497     struct {
1498         uint32_t prm_revision;
1499         uint32_t prm_sysconfig;
1500         uint32_t prm_irqstatus_mpu;
1501         uint32_t prm_irqenable_mpu;
1502     } ocp;
1503
1504     struct {
1505         uint32_t prm_clksel;
1506         uint32_t prm_clkout_ctrl;
1507     } ccr; /* clock_control_reg */
1508
1509     struct {
1510         uint32_t prm_vc_smps_sa;
1511         uint32_t prm_vc_smps_vol_ra;
1512         uint32_t prm_vc_smps_cmd_ra;
1513         uint32_t prm_vc_cmd_val_0;
1514         uint32_t prm_vc_cmd_val_1;
1515         uint32_t prm_vc_hc_conf;
1516         uint32_t prm_vc_i2c_cfg;
1517         uint32_t prm_vc_bypass_val;
1518         uint32_t prm_rstctrl;
1519         uint32_t prm_rsttimer;
1520         uint32_t prm_rstst;
1521         uint32_t prm_voltctrl;
1522         uint32_t prm_sram_pcharge;
1523         uint32_t prm_clksrc_ctrl;
1524         uint32_t prm_obs;
1525         uint32_t prm_voltsetup1;
1526         uint32_t prm_voltoffset;
1527         uint32_t prm_clksetup;
1528         uint32_t prm_polctrl;
1529         uint32_t prm_voltsetup2;
1530     } gr; /* global_reg */
1531 };
1532
1533 static void omap3_prm_int_update(struct omap3_prm_s *s)
1534 {
1535     qemu_set_irq(s->mpu_irq, s->ocp.prm_irqstatus_mpu & s->ocp.prm_irqenable_mpu);
1536     qemu_set_irq(s->iva_irq, s->prm_irqstatus_iva2 & s->prm_irqenable_iva2);
1537 }
1538
1539 static void omap3_prm_reset(struct omap3_prm_s *s)
1540 {
1541     bzero(&s->iva2, sizeof(s->iva2));
1542     s->iva2.rm_rstctrl    = 0x7;
1543     s->iva2.rm_rstst      = 0x1;
1544     s->iva2.pm_wkdep      = 0xb3;
1545     s->iva2.pm_pwstctrl   = 0xff0f07;
1546     s->iva2.pm_pwstst     = 0xff7;
1547     s->prm_irqstatus_iva2 = 0x0;
1548     s->prm_irqenable_iva2 = 0x0;
1549
1550     bzero(&s->ocp, sizeof(s->ocp));
1551     s->ocp.prm_revision      = 0x10;
1552     s->ocp.prm_sysconfig     = 0x1;
1553
1554     bzero(&s->mpu, sizeof(s->mpu));
1555     s->mpu.rm_rstst       = 0x1;
1556     s->mpu.pm_wkdep       = 0xa5;
1557     s->mpu.pm_pwstctrl    = 0x30107;
1558     s->mpu.pm_pwstst      = 0xc7;
1559     s->mpu.pm_evgenctrl   = 0x12;
1560
1561     bzero(&s->core, sizeof(s->core));
1562     s->core.rm_rstst       = 0x1;
1563     s->core.pm_wken        = 0xc33ffe18;
1564     s->core.pm_mpugrpsel   = 0xc33ffe18;
1565     s->core.pm_ivagrpsel   = 0xc33ffe18;
1566     s->core.pm_pwstctrl    = 0xf0307;
1567     s->core.pm_pwstst      = 0xf7;
1568     s->core.pm_wken3       = 0x4;
1569     s->pm_iva2grpsel3_core = 0x4;
1570     s->pm_mpugrpsel3_core  = 0x4;
1571
1572     bzero(&s->sgx, sizeof(s->sgx));
1573     s->sgx.rm_rstst     = 0x1;
1574     s->sgx.pm_wkdep     = 0x16;
1575     s->sgx.pm_pwstctrl  = 0x30107;
1576     s->sgx.pm_pwstst    = 0x3;
1577
1578     bzero(&s->wkup, sizeof(s->wkup));
1579     s->wkup.pm_wken      = 0x3cb;
1580     s->wkup.pm_mpugrpsel = 0x3cb;
1581     s->wkup.pm_pwstst    = 0x3; /* TODO: check on real hardware */
1582
1583     bzero(&s->ccr, sizeof(s->ccr));
1584     s->ccr.prm_clksel      = 0x3; /* TRM says 0x4, but on HW this is 0x3 */
1585     s->ccr.prm_clkout_ctrl = 0x80;
1586
1587     bzero(&s->dss, sizeof(s->dss));
1588     s->dss.rm_rstst     = 0x1;
1589     s->dss.pm_wken      = 0x1;
1590     s->dss.pm_wkdep     = 0x16;
1591     s->dss.pm_pwstctrl  = 0x30107;
1592     s->dss.pm_pwstst    = 0x3;
1593
1594     bzero(&s->cam, sizeof(s->cam));
1595     s->cam.rm_rstst     = 0x1;
1596     s->cam.pm_wkdep     = 0x16;
1597     s->cam.pm_pwstctrl  = 0x30107;
1598     s->cam.pm_pwstst    = 0x3;
1599
1600     bzero(&s->per, sizeof(s->per));
1601     s->per.rm_rstst     = 0x1;
1602     s->per.pm_wken      = 0x3efff;
1603     s->per.pm_mpugrpsel = 0x3efff;
1604     s->per.pm_ivagrpsel = 0x3efff;
1605     s->per.pm_wkdep     = 0x17;
1606     s->per.pm_pwstctrl  = 0x30107;
1607     s->per.pm_pwstst    = 0x7;
1608
1609     bzero(&s->emu, sizeof(s->emu));
1610     s->emu.rm_rstst  = 0x1;
1611     s->emu.pm_pwstst = 0x13;
1612
1613     bzero(&s->gr, sizeof(s->gr));
1614     s->gr.prm_vc_i2c_cfg     = 0x18;
1615     s->gr.prm_rsttimer       = 0x1006;
1616     s->gr.prm_rstst          = 0x1;
1617     s->gr.prm_sram_pcharge   = 0x50;
1618     s->gr.prm_clksrc_ctrl    = 0x43;
1619     s->gr.prm_polctrl        = 0xa;
1620
1621     bzero(&s->neon, sizeof(s->neon));
1622     s->neon.rm_rstst     = 0x1;
1623     s->neon.pm_wkdep     = 0x2;
1624     s->neon.pm_pwstctrl  = 0x7;
1625     s->neon.pm_pwstst    = 0x3;
1626
1627     bzero(&s->usbhost, sizeof(s->usbhost));
1628     s->usbhost.rm_rstst     = 0x1;
1629     s->usbhost.pm_wken      = 0x1;
1630     s->usbhost.pm_mpugrpsel = 0x1;
1631     s->usbhost.pm_ivagrpsel = 0x1;
1632     s->usbhost.pm_wkdep     = 0x17;
1633     s->usbhost.pm_pwstctrl  = 0x30107;
1634     s->usbhost.pm_pwstst    = 0x3;
1635
1636     omap3_prm_int_update(s);
1637 }
1638
1639 static uint32_t omap3_prm_read(void *opaque, target_phys_addr_t addr)
1640 {
1641     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1642     struct omap3_prm_domain_s *d = 0;
1643
1644     TRACE("%04x", addr);
1645
1646     /* handle common domain registers first - all domains may not
1647        have all common registers though but we're returning zeroes there */
1648     switch ((addr >> 8) & 0xff) {
1649         case 0x00: d = &s->iva2; break;
1650         case 0x09: d = &s->mpu; break;
1651         case 0x0a: d = &s->core; break;
1652         case 0x0b: d = &s->sgx; break;
1653         case 0x0c: d = &s->wkup; break;
1654         case 0x0e: d = &s->dss; break;
1655         case 0x0f: d = &s->cam; break;
1656         case 0x10: d = &s->per; break;
1657         case 0x11: d = &s->emu; break;
1658         case 0x13: d = &s->neon; break;
1659         case 0x14: d = &s->usbhost; break;
1660         default: break;
1661     }
1662     if (d)
1663         switch (addr & 0xff) {
1664             case 0x50: return d->rm_rstctrl;
1665             case 0x58: return d->rm_rstst;
1666             case 0xa0: return d->pm_wken;
1667             case 0xa4: return d->pm_mpugrpsel;
1668             case 0xa8: return d->pm_ivagrpsel;
1669             case 0xb0: return d->pm_wkst;
1670             case 0xb8: return d->pm_wkst3;
1671             case 0xc8: return d->pm_wkdep;
1672             case 0xd4: return d->pm_evgenctrl;
1673             case 0xd8: return d->pm_evgenontim;
1674             case 0xdc: return d->pm_evgenofftim;
1675             case 0xe0: return d->pm_pwstctrl;
1676             case 0xe4: return d->pm_pwstst;
1677             case 0xe8: return d->pm_prepwstst;
1678             case 0xf0: return d->pm_wken3;
1679             default: break;
1680         }
1681
1682     /* okay, not a common domain register so let's take a closer look */
1683     switch (addr) {
1684         case 0x00f8: return s->prm_irqstatus_iva2;
1685         case 0x00fc: return s->prm_irqenable_iva2;
1686         case 0x0804: return s->ocp.prm_revision;
1687         case 0x0814: return s->ocp.prm_sysconfig;
1688         case 0x0818: return s->ocp.prm_irqstatus_mpu;
1689         case 0x081c: return s->ocp.prm_irqenable_mpu;
1690         case 0x0af4: return s->pm_iva2grpsel3_core;
1691         case 0x0af8: return s->pm_mpugrpsel3_core;
1692         case 0x0d40: return s->ccr.prm_clksel;
1693         case 0x0d70: return s->ccr.prm_clkout_ctrl;
1694         case 0x0de4: return 0x3; /* TODO: check on real hardware */
1695         case 0x1220: return s->gr.prm_vc_smps_sa;
1696         case 0x1224: return s->gr.prm_vc_smps_vol_ra;
1697         case 0x1228: return s->gr.prm_vc_smps_cmd_ra;
1698         case 0x122c: return s->gr.prm_vc_cmd_val_0;
1699         case 0x1230: return s->gr.prm_vc_cmd_val_1;
1700         case 0x1234: return s->gr.prm_vc_hc_conf;
1701         case 0x1238: return s->gr.prm_vc_i2c_cfg;
1702         case 0x123c: return s->gr.prm_vc_bypass_val;
1703         case 0x1250: return s->gr.prm_rstctrl;
1704         case 0x1254: return s->gr.prm_rsttimer;
1705         case 0x1258: return s->gr.prm_rstst;
1706         case 0x1260: return s->gr.prm_voltctrl;
1707         case 0x1264: return s->gr.prm_sram_pcharge;
1708         case 0x1270: return s->gr.prm_clksrc_ctrl;
1709         case 0x1280: return s->gr.prm_obs;
1710         case 0x1290: return s->gr.prm_voltsetup1;
1711         case 0x1294: return s->gr.prm_voltoffset;
1712         case 0x1298: return s->gr.prm_clksetup;
1713         case 0x129c: return s->gr.prm_polctrl;
1714         case 0x12a0: return s->gr.prm_voltsetup2;
1715         default: break;
1716     }
1717
1718     OMAP_BAD_REG(addr);
1719     return 0;
1720 }
1721
1722 static inline void omap3_prm_clksrc_ctrl_update(struct omap3_prm_s *s)
1723 {
1724     uint32_t value = s->gr.prm_clksrc_ctrl;
1725
1726     if ((value & 0xd0) == 0x40)
1727         omap_clk_setrate(omap_findclk(s->omap, "omap3_sys_clk"), 1, 1);
1728     else if ((value & 0xd0) == 0x80)
1729         omap_clk_setrate(omap_findclk(s->omap, "omap3_sys_clk"), 2, 1);
1730 }
1731
1732 static void omap3_prm_clksel_update(struct omap3_prm_s *s)
1733 {
1734     omap_clk newparent = 0;
1735
1736     switch (s->ccr.prm_clksel & 7) {
1737         case 0: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk12"); break;
1738         case 1: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk13"); break;
1739         case 2: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk192"); break;
1740         case 3: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk26"); break;
1741         case 4: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk384"); break;
1742         case 5: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk168"); break;
1743         default:
1744             fprintf(stderr, "%s: invalid sys_clk input selection (%d) - ignored\n",
1745                     __FUNCTION__, s->ccr.prm_clksel & 7);
1746             break;
1747     }
1748     if (newparent) {
1749         omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clk"), newparent);
1750         omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clkout1"), newparent);
1751     }
1752 }
1753
1754 static void omap3_prm_write(void *opaque, target_phys_addr_t addr,
1755                             uint32_t value)
1756 {
1757     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1758
1759     TRACE("%04x = %08x", addr, value);
1760     switch (addr) {
1761         /* IVA2_PRM */
1762         case 0x0050: s->iva2.rm_rstctrl = value & 0x7; break;
1763         case 0x0058: s->iva2.rm_rstst &= ~(value & 0x3f0f); break;
1764         case 0x00c8: s->iva2.pm_wkdep = value & 0xb3; break;
1765         case 0x00e0: s->iva2.pm_pwstctrl = 0xcff000 | (value & 0x300f0f); break;
1766         case 0x00e4: OMAP_RO_REG(addr); break;
1767         case 0x00e8: s->iva2.pm_prepwstst = value & 0xff7;
1768         case 0x00f8:
1769             s->prm_irqstatus_iva2 &= ~(value & 0x7);
1770             omap3_prm_int_update(s);
1771             break;
1772         case 0x00fc:
1773             s->prm_irqenable_iva2 = value & 0x7;
1774             omap3_prm_int_update(s);
1775             break;
1776         /* OCP_System_Reg_PRM */
1777         case 0x0804: OMAP_RO_REG(addr); break;
1778         case 0x0814: s->ocp.prm_sysconfig = value & 0x1; break;
1779         case 0x0818:
1780             s->ocp.prm_irqstatus_mpu &= ~(value & 0x03c003fd);
1781             omap3_prm_int_update(s);
1782             break;
1783         case 0x081c:
1784             s->ocp.prm_irqenable_mpu = value & 0x03c003fd;
1785             omap3_prm_int_update(s);
1786             break;
1787         /* MPU_PRM */
1788         case 0x0958: s->mpu.rm_rstst &= ~(value & 0x080f); break;
1789         case 0x09c8: s->mpu.pm_wkdep = value & 0xa5; break;
1790         case 0x09d4: s->mpu.pm_evgenctrl = value & 0x1f; break;
1791         case 0x09d8: s->mpu.pm_evgenontim = value; break;
1792         case 0x09dc: s->mpu.pm_evgenofftim = value; break;
1793         case 0x09e0: s->mpu.pm_pwstctrl = value & 0x3010f; break;
1794         case 0x09e4: OMAP_RO_REG(addr); break;
1795         case 0x09e8: s->mpu.pm_prepwstst = value & 0xc7; break;
1796         /* CORE_PRM */
1797         case 0x0a50: s->core.rm_rstctrl = value & 0x3; break; /* TODO: check if available on real hw */
1798         case 0x0a58: s->core.rm_rstst &= ~(value & 0x7); break;
1799         case 0x0aa0: s->core.pm_wken = 0x80000008 | (value & 0x433ffe10); break;
1800         case 0x0aa4: s->core.pm_mpugrpsel = 0x80000008 | (value & 0x433ffe10); break;
1801         case 0x0aa8: s->core.pm_ivagrpsel = 0x80000008 | (value & 0x433ffe10); break;
1802         case 0x0ab0: s->core.pm_wkst = value & 0x433ffe10; break;
1803         case 0x0ab8: s->core.pm_wkst3 &= ~(value & 0x4); break;
1804         case 0x0ae0: s->core.pm_pwstctrl = (value & 0x0f031f); break;
1805         case 0x0ae4: OMAP_RO_REG(addr); break;
1806         case 0x0ae8: s->core.pm_prepwstst = value & 0xf7; break;
1807         case 0x0af0: s->core.pm_wken3 = value & 0x4; break;
1808         case 0x0af4: s->pm_iva2grpsel3_core = value & 0x4; break;
1809         case 0x0af8: s->pm_mpugrpsel3_core = value & 0x4; break;
1810         /* SGX_PRM */
1811         case 0x0b58: s->sgx.rm_rstst &= ~(value & 0xf); break;
1812         case 0x0bc8: s->sgx.pm_wkdep = value & 0x16; break;
1813         case 0x0be0: s->sgx.pm_pwstctrl = 0x030104 | (value & 0x3); break;
1814         case 0x0be4: OMAP_RO_REG(addr); break;
1815         case 0x0be8: s->sgx.pm_prepwstst = value & 0x3; break;
1816         /* WKUP_PRM */
1817         case 0x0ca0: s->wkup.pm_wken = 0x2 | (value & 0x0103c9); break;
1818         case 0x0ca4: s->wkup.pm_mpugrpsel = 0x0102 | (value & 0x02c9); break;
1819         case 0x0ca8: s->wkup.pm_ivagrpsel = value & 0x03cb; break;
1820         case 0x0cb0: s->wkup.pm_wkst &= ~(value & 0x0103cb); break;
1821         /* Clock_Control_Reg_PRM */
1822         case 0x0d40:
1823             s->ccr.prm_clksel = value & 0x7;
1824             omap3_prm_clksel_update(s);
1825             break;
1826         case 0x0d70:
1827             s->ccr.prm_clkout_ctrl = value & 0x80;
1828             omap_clk_onoff(omap_findclk(s->omap, "omap3_sys_clkout1"),
1829                            s->ccr.prm_clkout_ctrl & 0x80);
1830             break;
1831         /* DSS_PRM */
1832         case 0x0e58: s->dss.rm_rstst &= ~(value & 0xf); break;
1833         case 0x0ea0: s->dss.pm_wken = value & 1; break;
1834         case 0x0ec8: s->dss.pm_wkdep = value & 0x16; break;
1835         case 0x0ee0: s->dss.pm_pwstctrl = 0x030104 | (value & 3); break;
1836         case 0x0ee4: OMAP_RO_REG(addr); break;
1837         case 0x0ee8: s->dss.pm_prepwstst = value & 3; break;
1838         /* CAM_PRM */
1839         case 0x0f58: s->cam.rm_rstst &= (value & 0xf); break;
1840         case 0x0fc8: s->cam.pm_wkdep = value & 0x16; break;
1841         case 0x0fe0: s->cam.pm_pwstctrl = 0x030104 | (value & 3); break;
1842         case 0x0fe4: OMAP_RO_REG(addr); break;
1843         case 0x0fe8: s->cam.pm_prepwstst = value & 0x3; break;
1844         /* PER_PRM */
1845         case 0x1058: s->per.rm_rstst &= ~(value & 0xf); break;
1846         case 0x10a0: s->per.pm_wken = value & 0x03efff; break;
1847         case 0x10a4: s->per.pm_mpugrpsel = value & 0x03efff; break;
1848         case 0x10a8: s->per.pm_ivagrpsel = value & 0x03efff; break;
1849         case 0x10b0: s->per.pm_wkst &= ~(value & 0x03efff); break;
1850         case 0x10c8: s->per.pm_wkdep = value & 0x17; break;
1851         case 0x10e0: s->per.pm_pwstctrl = 0x030100 | (value & 7); break;
1852         case 0x10e4: OMAP_RO_REG(addr); break;
1853         case 0x10e8: s->per.pm_prepwstst = value & 0x7; break;
1854         /* EMU_PRM */
1855         case 0x1158: s->emu.rm_rstst &= ~(value & 7); break;
1856         case 0x11e4: OMAP_RO_REG(addr); break;
1857         /* Global_Reg_PRM */
1858         case 0x1220: s->gr.prm_vc_smps_sa = value & 0x7f007f; break;
1859         case 0x1224: s->gr.prm_vc_smps_vol_ra = value & 0xff00ff; break;
1860         case 0x1228: s->gr.prm_vc_smps_cmd_ra = value & 0xff00ff; break;
1861         case 0x122c: s->gr.prm_vc_cmd_val_0 = value; break;
1862         case 0x1230: s->gr.prm_vc_cmd_val_1 = value; break;
1863         case 0x1234: s->gr.prm_vc_hc_conf = value & 0x1f001f; break;
1864         case 0x1238: s->gr.prm_vc_i2c_cfg = value & 0x3f; break;
1865         case 0x123c: s->gr.prm_vc_bypass_val = value & 0x01ffff7f; break;
1866         case 0x1250: s->gr.prm_rstctrl = 0; break; /* TODO: resets */
1867         case 0x1254: s->gr.prm_rsttimer = value & 0x1fff; break;
1868         case 0x1258: s->gr.prm_rstst &= ~(value & 0x7fb); break;
1869         case 0x1260: s->gr.prm_voltctrl = value & 0x1f; break;
1870         case 0x1264: s->gr.prm_sram_pcharge = value & 0xff; break;
1871         case 0x1270:
1872             s->gr.prm_clksrc_ctrl = value & 0xd8; /* set osc bypass mode */
1873             omap3_prm_clksrc_ctrl_update(s);
1874             break;
1875         case 0x1280: OMAP_RO_REG(addr); break;
1876         case 0x1290: s->gr.prm_voltsetup1 = value; break;
1877         case 0x1294: s->gr.prm_voltoffset = value & 0xffff; break;
1878         case 0x1298: s->gr.prm_clksetup = value & 0xffff; break;
1879         case 0x129c: s->gr.prm_polctrl = value & 0xf; break;
1880         case 0x12a0: s->gr.prm_voltsetup2 = value & 0xffff; break;
1881         /* NEON_PRM */
1882         case 0x1358: s->neon.rm_rstst &= ~(value & 0xf); break;
1883         case 0x13c8: s->neon.pm_wkdep = value & 0x2; break;
1884         case 0x13e0: s->neon.pm_pwstctrl = 0x4 | (value & 3); break;
1885         case 0x13e4: OMAP_RO_REG(addr); break;
1886         case 0x13e8: s->neon.pm_prepwstst = value & 3; break;
1887         /* USBHOST_PRM */
1888         case 0x1458: s->usbhost.rm_rstst &= ~(value & 0xf); break;
1889         case 0x14a0: s->usbhost.pm_wken = value & 1; break;
1890         case 0x14a4: s->usbhost.pm_mpugrpsel = value & 1; break;
1891         case 0x14a8: s->usbhost.pm_ivagrpsel = value & 1; break;
1892         case 0x14b0: s->usbhost.pm_wkst &= ~(value & 1); break;
1893         case 0x14c8: s->usbhost.pm_wkdep = value & 0x17; break;
1894         case 0x14e0: s->usbhost.pm_pwstctrl = 0x030104 | (value & 0x13); break;
1895         case 0x14e4: OMAP_RO_REG(addr); break;
1896         case 0x14e8: s->usbhost.pm_prepwstst = value & 3; break;
1897         default:
1898             OMAP_BAD_REGV(addr, value);
1899             break;
1900     }
1901 }
1902
1903 static void omap3_prm_save_domain_state(QEMUFile *f,
1904                                         struct omap3_prm_domain_s *s)
1905 {
1906     qemu_put_be32(f, s->rm_rstctrl);
1907     qemu_put_be32(f, s->rm_rstst);
1908     qemu_put_be32(f, s->pm_wken);
1909     qemu_put_be32(f, s->pm_mpugrpsel);
1910     qemu_put_be32(f, s->pm_ivagrpsel);
1911     qemu_put_be32(f, s->pm_wkst);
1912     qemu_put_be32(f, s->pm_wkst3);
1913     qemu_put_be32(f, s->pm_wkdep);
1914     qemu_put_be32(f, s->pm_evgenctrl);
1915     qemu_put_be32(f, s->pm_evgenontim);
1916     qemu_put_be32(f, s->pm_evgenofftim);
1917     qemu_put_be32(f, s->pm_pwstctrl);
1918     qemu_put_be32(f, s->pm_pwstst);
1919     qemu_put_be32(f, s->pm_prepwstst);
1920     qemu_put_be32(f, s->pm_wken3);
1921 }
1922
1923 static void omap3_prm_load_domain_state(QEMUFile *f,
1924                                         struct omap3_prm_domain_s *s)
1925 {
1926     s->rm_rstctrl = qemu_get_be32(f);
1927     s->rm_rstst = qemu_get_be32(f);
1928     s->pm_wken = qemu_get_be32(f);
1929     s->pm_mpugrpsel = qemu_get_be32(f);
1930     s->pm_ivagrpsel = qemu_get_be32(f);
1931     s->pm_wkst = qemu_get_be32(f);
1932     s->pm_wkst3 = qemu_get_be32(f);
1933     s->pm_wkdep = qemu_get_be32(f);
1934     s->pm_evgenctrl = qemu_get_be32(f);
1935     s->pm_evgenontim = qemu_get_be32(f);
1936     s->pm_evgenofftim = qemu_get_be32(f);
1937     s->pm_pwstctrl = qemu_get_be32(f);
1938     s->pm_pwstst = qemu_get_be32(f);
1939     s->pm_prepwstst = qemu_get_be32(f);
1940     s->pm_wken3 = qemu_get_be32(f);
1941 }
1942
1943 static void omap3_prm_save_state(QEMUFile *f, void *opaque)
1944 {
1945     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1946
1947     omap3_prm_save_domain_state(f, &s->iva2);
1948     omap3_prm_save_domain_state(f, &s->mpu);
1949     omap3_prm_save_domain_state(f, &s->core);
1950     omap3_prm_save_domain_state(f, &s->sgx);
1951     omap3_prm_save_domain_state(f, &s->wkup);
1952     omap3_prm_save_domain_state(f, &s->dss);
1953     omap3_prm_save_domain_state(f, &s->cam);
1954     omap3_prm_save_domain_state(f, &s->per);
1955     omap3_prm_save_domain_state(f, &s->emu);
1956     omap3_prm_save_domain_state(f, &s->neon);
1957     omap3_prm_save_domain_state(f, &s->usbhost);
1958
1959     qemu_put_be32(f, s->prm_irqstatus_iva2);
1960     qemu_put_be32(f, s->prm_irqenable_iva2);
1961     qemu_put_be32(f, s->pm_iva2grpsel3_core);
1962     qemu_put_be32(f, s->pm_mpugrpsel3_core);
1963
1964     qemu_put_be32(f, s->ocp.prm_revision);
1965     qemu_put_be32(f, s->ocp.prm_sysconfig);
1966     qemu_put_be32(f, s->ocp.prm_irqstatus_mpu);
1967     qemu_put_be32(f, s->ocp.prm_irqenable_mpu);
1968
1969     qemu_put_be32(f, s->ccr.prm_clksel);
1970     qemu_put_be32(f, s->ccr.prm_clkout_ctrl);
1971
1972     qemu_put_be32(f, s->gr.prm_vc_smps_sa);
1973     qemu_put_be32(f, s->gr.prm_vc_smps_vol_ra);
1974     qemu_put_be32(f, s->gr.prm_vc_smps_cmd_ra);
1975     qemu_put_be32(f, s->gr.prm_vc_cmd_val_0);
1976     qemu_put_be32(f, s->gr.prm_vc_cmd_val_1);
1977     qemu_put_be32(f, s->gr.prm_vc_hc_conf);
1978     qemu_put_be32(f, s->gr.prm_vc_i2c_cfg);
1979     qemu_put_be32(f, s->gr.prm_vc_bypass_val);
1980     qemu_put_be32(f, s->gr.prm_rstctrl);
1981     qemu_put_be32(f, s->gr.prm_rsttimer);
1982     qemu_put_be32(f, s->gr.prm_rstst);
1983     qemu_put_be32(f, s->gr.prm_voltctrl);
1984     qemu_put_be32(f, s->gr.prm_sram_pcharge);
1985     qemu_put_be32(f, s->gr.prm_clksrc_ctrl);
1986     qemu_put_be32(f, s->gr.prm_obs);
1987     qemu_put_be32(f, s->gr.prm_voltsetup1);
1988     qemu_put_be32(f, s->gr.prm_voltoffset);
1989     qemu_put_be32(f, s->gr.prm_clksetup);
1990     qemu_put_be32(f, s->gr.prm_polctrl);
1991     qemu_put_be32(f, s->gr.prm_voltsetup2);
1992 }
1993
1994 static int omap3_prm_load_state(QEMUFile *f, void *opaque, int version_id)
1995 {
1996     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1997
1998     if (version_id)
1999         return -EINVAL;
2000
2001     omap3_prm_load_domain_state(f, &s->iva2);
2002     omap3_prm_load_domain_state(f, &s->mpu);
2003     omap3_prm_load_domain_state(f, &s->core);
2004     omap3_prm_load_domain_state(f, &s->sgx);
2005     omap3_prm_load_domain_state(f, &s->wkup);
2006     omap3_prm_load_domain_state(f, &s->dss);
2007     omap3_prm_load_domain_state(f, &s->cam);
2008     omap3_prm_load_domain_state(f, &s->per);
2009     omap3_prm_load_domain_state(f, &s->emu);
2010     omap3_prm_load_domain_state(f, &s->neon);
2011     omap3_prm_load_domain_state(f, &s->usbhost);
2012
2013     s->prm_irqstatus_iva2 = qemu_get_be32(f);
2014     s->prm_irqenable_iva2 = qemu_get_be32(f);
2015     s->pm_iva2grpsel3_core = qemu_get_be32(f);
2016     s->pm_mpugrpsel3_core = qemu_get_be32(f);
2017
2018     s->ocp.prm_revision = qemu_get_be32(f);
2019     s->ocp.prm_sysconfig = qemu_get_be32(f);
2020     s->ocp.prm_irqstatus_mpu = qemu_get_be32(f);
2021     s->ocp.prm_irqenable_mpu = qemu_get_be32(f);
2022
2023     s->ccr.prm_clksel = qemu_get_be32(f);
2024     s->ccr.prm_clkout_ctrl = qemu_get_be32(f);
2025
2026     s->gr.prm_vc_smps_sa = qemu_get_be32(f);
2027     s->gr.prm_vc_smps_vol_ra = qemu_get_be32(f);
2028     s->gr.prm_vc_smps_cmd_ra = qemu_get_be32(f);
2029     s->gr.prm_vc_cmd_val_0 = qemu_get_be32(f);
2030     s->gr.prm_vc_cmd_val_1 = qemu_get_be32(f);
2031     s->gr.prm_vc_hc_conf = qemu_get_be32(f);
2032     s->gr.prm_vc_i2c_cfg = qemu_get_be32(f);
2033     s->gr.prm_vc_bypass_val = qemu_get_be32(f);
2034     s->gr.prm_rstctrl = qemu_get_be32(f);
2035     s->gr.prm_rsttimer = qemu_get_be32(f);
2036     s->gr.prm_rstst = qemu_get_be32(f);
2037     s->gr.prm_voltctrl = qemu_get_be32(f);
2038     s->gr.prm_sram_pcharge = qemu_get_be32(f);
2039     s->gr.prm_clksrc_ctrl = qemu_get_be32(f);
2040     s->gr.prm_obs = qemu_get_be32(f);
2041     s->gr.prm_voltsetup1 = qemu_get_be32(f);
2042     s->gr.prm_voltoffset = qemu_get_be32(f);
2043     s->gr.prm_clksetup = qemu_get_be32(f);
2044     s->gr.prm_polctrl = qemu_get_be32(f);
2045     s->gr.prm_voltsetup2 = qemu_get_be32(f);
2046
2047     omap3_prm_int_update(s);
2048     omap3_prm_clksrc_ctrl_update(s);
2049     omap3_prm_clksel_update(s);
2050     omap_clk_onoff(omap_findclk(s->omap, "omap3_sys_clkout1"),
2051                    s->ccr.prm_clkout_ctrl & 0x80);
2052
2053     return 0;
2054 }
2055
2056 static CPUReadMemoryFunc *omap3_prm_readfn[] = {
2057     omap_badwidth_read32,
2058     omap_badwidth_read32,
2059     omap3_prm_read,
2060 };
2061
2062 static CPUWriteMemoryFunc *omap3_prm_writefn[] = {
2063     omap_badwidth_write32,
2064     omap_badwidth_write32,
2065     omap3_prm_write,
2066 };
2067
2068 static struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
2069                                           qemu_irq mpu_int, qemu_irq iva_int,
2070                                           struct omap_mpu_state_s *mpu)
2071 {
2072     int iomemtype;
2073     struct omap3_prm_s *s = (struct omap3_prm_s *) qemu_mallocz(sizeof(*s));
2074
2075     s->mpu_irq = mpu_int;
2076     s->iva_irq = iva_int;
2077     s->omap = mpu;
2078     omap3_prm_reset(s);
2079
2080     iomemtype = l4_register_io_memory(0, omap3_prm_readfn,
2081                                       omap3_prm_writefn, s);
2082     omap_l4_attach(ta, 0, iomemtype);
2083     omap_l4_attach(ta, 1, iomemtype);
2084
2085     register_savevm("omap3_prm", -1, 0,
2086                     omap3_prm_save_state, omap3_prm_load_state, s);
2087
2088     return s;
2089 }
2090
2091 struct omap3_cm_s {
2092     qemu_irq irq[3];
2093     struct omap_mpu_state_s *mpu;
2094
2095     /* IVA2_CM: base + 0x0000 */
2096     uint32_t cm_fclken_iva2;       /* 00 */
2097     uint32_t cm_clken_pll_iva2;    /* 04 */
2098     uint32_t cm_idlest_iva2;       /* 20 */
2099     uint32_t cm_idlest_pll_iva2;   /* 24 */
2100     uint32_t cm_autoidle_pll_iva2; /* 34 */
2101     uint32_t cm_clksel1_pll_iva2;  /* 40 */
2102     uint32_t cm_clksel2_pll_iva2;  /* 44 */
2103     uint32_t cm_clkstctrl_iva2;    /* 48 */
2104     uint32_t cm_clkstst_iva2;      /* 4c */
2105
2106     /* OCP_System_Reg_CM: base + 0x0800 */
2107     uint32_t cm_revision;  /* 00 */
2108     uint32_t cm_sysconfig; /* 10 */
2109
2110     /* MPU_CM: base + 0x0900 */
2111     uint32_t cm_clken_pll_mpu;    /* 04 */
2112     uint32_t cm_idlest_mpu;       /* 20 */
2113     uint32_t cm_idlest_pll_mpu;   /* 24 */
2114     uint32_t cm_autoidle_pll_mpu; /* 34 */
2115     uint32_t cm_clksel1_pll_mpu;  /* 40 */
2116     uint32_t cm_clksel2_pll_mpu;  /* 44 */
2117     uint32_t cm_clkstctrl_mpu;    /* 48 */
2118     uint32_t cm_clkstst_mpu;      /* 4c */
2119
2120     /* CORE_CM: base + 0x0a00 */
2121     uint32_t cm_fclken1_core;   /* 0a00 */
2122     uint32_t cm_fclken3_core;   /* 0a08 */
2123     uint32_t cm_iclken1_core;   /* 0a10 */
2124     uint32_t cm_iclken2_core;   /* 0a14 */
2125     uint32_t cm_iclken3_core;   /* 0a18 */
2126     uint32_t cm_idlest1_core;   /* 0a20 */
2127     uint32_t cm_idlest2_core;   /* 0a24 */
2128     uint32_t cm_idlest3_core;   /* 0a28 */
2129     uint32_t cm_autoidle1_core; /* 0a30 */
2130     uint32_t cm_autoidle2_core; /* 0a34 */
2131     uint32_t cm_autoidle3_core; /* 0a38 */
2132     uint32_t cm_clksel_core;    /* 0a40 */
2133     uint32_t cm_clkstctrl_core; /* 0a48 */
2134     uint32_t cm_clkstst_core;   /* 0a4c */
2135
2136     /* SGX_CM: base + 0x0b00 */
2137     uint32_t cm_fclken_sgx;    /* 00 */
2138     uint32_t cm_iclken_sgx;    /* 10 */
2139     uint32_t cm_idlest_sgx;    /* 20 */
2140     uint32_t cm_clksel_sgx;    /* 40 */
2141     uint32_t cm_sleepdep_sgx;  /* 44 */
2142     uint32_t cm_clkstctrl_sgx; /* 48 */
2143     uint32_t cm_clkstst_sgx;   /* 4c */
2144
2145     /* WKUP_CM: base + 0x0c00 */
2146     uint32_t cm_fclken_wkup;   /* 00 */
2147     uint32_t cm_iclken_wkup;   /* 10 */
2148     uint32_t cm_idlest_wkup;   /* 20 */
2149     uint32_t cm_autoidle_wkup; /* 30 */
2150     uint32_t cm_clksel_wkup;   /* 40 */
2151     uint32_t cm_c48;           /* 48 */
2152
2153     /* Clock_Control_Reg_CM: base + 0x0d00 */
2154     uint32_t cm_clken_pll;     /* 00 */
2155     uint32_t cm_clken2_pll;    /* 04 */
2156     uint32_t cm_idlest_ckgen;  /* 20 */
2157     uint32_t cm_idlest2_ckgen; /* 24 */
2158     uint32_t cm_autoidle_pll;  /* 30 */
2159     uint32_t cm_autoidle2_pll; /* 34 */
2160     uint32_t cm_clksel1_pll;   /* 40 */
2161     uint32_t cm_clksel2_pll;   /* 44 */
2162     uint32_t cm_clksel3_pll;   /* 48 */
2163     uint32_t cm_clksel4_pll;   /* 4c */
2164     uint32_t cm_clksel5_pll;   /* 50 */
2165     uint32_t cm_clkout_ctrl;   /* 70 */
2166
2167     /* DSS_CM: base + 0x0e00 */
2168     uint32_t cm_fclken_dss;    /* 00 */
2169     uint32_t cm_iclken_dss;    /* 10 */
2170     uint32_t cm_idlest_dss;    /* 20 */
2171     uint32_t cm_autoidle_dss;  /* 30 */
2172     uint32_t cm_clksel_dss;    /* 40 */
2173     uint32_t cm_sleepdep_dss;  /* 44 */
2174     uint32_t cm_clkstctrl_dss; /* 48 */
2175     uint32_t cm_clkstst_dss;   /* 4c */
2176
2177    /* CAM_CM: base + 0x0f00 */
2178     uint32_t cm_fclken_cam;    /* 00 */
2179     uint32_t cm_iclken_cam;    /* 10 */
2180     uint32_t cm_idlest_cam;    /* 20 */
2181     uint32_t cm_autoidle_cam;  /* 30 */
2182     uint32_t cm_clksel_cam;    /* 40 */
2183     uint32_t cm_sleepdep_cam;  /* 44 */
2184     uint32_t cm_clkstctrl_cam; /* 48 */
2185     uint32_t cm_clkstst_cam;   /* 4c */
2186
2187     /* PER_CM: base + 0x1000 */
2188     uint32_t cm_fclken_per;    /* 00 */
2189     uint32_t cm_iclken_per;    /* 10 */
2190     uint32_t cm_idlest_per;    /* 20 */
2191     uint32_t cm_autoidle_per;  /* 30 */
2192     uint32_t cm_clksel_per;    /* 40 */
2193     uint32_t cm_sleepdep_per;  /* 44 */
2194     uint32_t cm_clkstctrl_per; /* 48 */
2195     uint32_t cm_clkstst_per;   /* 4c */
2196
2197     /* EMU_CM: base + 0x1100 */
2198     uint32_t cm_clksel1_emu;   /* 40 */
2199     uint32_t cm_clkstctrl_emu; /* 48 */
2200     uint32_t cm_clkstst_emu;   /* 4c */
2201     uint32_t cm_clksel2_emu;   /* 50 */
2202     uint32_t cm_clksel3_emu;   /* 54 */
2203
2204     /* Global_Reg_CM: base + 0x1200 */
2205     uint32_t cm_polctrl; /* 9c */
2206
2207     /* NEON_CM: base + 0x1300 */
2208     uint32_t cm_idlest_neon;    /* 20 */
2209     uint32_t cm_clkstctrl_neon; /* 48 */
2210
2211     /* USBHOST_CM: base + 0x1400 */
2212     uint32_t cm_fclken_usbhost;    /* 00 */
2213     uint32_t cm_iclken_usbhost;    /* 10 */
2214     uint32_t cm_idlest_usbhost;    /* 20 */
2215     uint32_t cm_autoidle_usbhost;  /* 30 */
2216     uint32_t cm_sleepdep_usbhost;  /* 44 */
2217     uint32_t cm_clkstctrl_usbhost; /* 48 */
2218     uint32_t cm_clkstst_usbhost;   /* 4c */
2219 };
2220
2221 static inline void omap3_cm_clksel_wkup_update(struct omap3_cm_s *s)
2222 {
2223     omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp1_fclk"),
2224                       omap_findclk(s->mpu,
2225                                    (s->cm_clksel_wkup & 1) /* CLKSEL_GPT1 */
2226                                    ? "omap3_sys_clk"
2227                                    : "omap3_32k_fclk"));
2228     omap_clk_setrate(omap_findclk(s->mpu, "omap3_rm_iclk"),
2229                      (s->cm_clksel_wkup >> 1) & 3, /* CLKSEL_RM */
2230                      1);
2231
2232     /* Tell GPTIMER to generate new clk rate */
2233     omap_gp_timer_change_clk(s->mpu->gptimer[0]);
2234
2235     TRACE("gptimer1 fclk=%lld",
2236           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp1_fclk")));
2237
2238     /* TODO: CM_USIM_CLK */
2239 }
2240
2241 static inline void omap3_cm_iva2_update(struct omap3_cm_s *s)
2242 {
2243     uint32_t iva2_dpll_mul = ((s->cm_clksel1_pll_iva2 >> 8) & 0x7ff);
2244     uint32_t iva2_dpll_div, iva2_dpll_clkout_div, iva2_clk_src;
2245     omap_clk iva2_clk = omap_findclk(s->mpu, "omap3_iva2_clk");
2246
2247     omap_clk_onoff(iva2_clk, s->cm_fclken_iva2 & 1);
2248
2249     switch ((s->cm_clken_pll_iva2 & 0x7)) {
2250         case 0x01: /* low power stop mode */
2251         case 0x05: /* low power bypass mode */
2252             s->cm_idlest_pll_iva2 &= ~1;
2253             break;
2254         case 0x07: /* locked */
2255             if (iva2_dpll_mul < 2)
2256                 s->cm_idlest_pll_iva2 &= ~1;
2257             else
2258                 s->cm_idlest_pll_iva2 |= 1;
2259             break;
2260         default:
2261             break;
2262     }
2263
2264     if (s->cm_idlest_pll_iva2 & 1) {
2265         iva2_dpll_div = s->cm_clksel1_pll_iva2 & 0x7f;
2266         iva2_dpll_clkout_div = s->cm_clksel2_pll_iva2 & 0x1f;
2267         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
2268         omap_clk_setrate(iva2_clk,
2269                          (iva2_dpll_div + 1) * iva2_dpll_clkout_div,
2270                          iva2_dpll_mul);
2271     } else {
2272         /* bypass mode */
2273         iva2_clk_src = (s->cm_clksel1_pll_iva2 >> 19) & 0x07;
2274         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_core_clk"));
2275         omap_clk_setrate(iva2_clk, iva2_clk_src, 1);
2276     }
2277 }
2278
2279 static inline void omap3_cm_mpu_update(struct omap3_cm_s *s)
2280 {
2281     uint32_t mpu_dpll_mul = ((s->cm_clksel1_pll_mpu >> 8) & 0x7ff);
2282     uint32_t mpu_dpll_div, mpu_dpll_clkout_div, mpu_clk_src;
2283     omap_clk mpu_clk = omap_findclk(s->mpu, "omap3_mpu_clk");
2284
2285     switch ((s->cm_clken_pll_mpu & 0x7)) {
2286         case 0x05: /* low power bypass mode */
2287             s->cm_idlest_pll_mpu &= ~1;
2288             break;
2289         case 0x07: /* locked */
2290             if (mpu_dpll_mul < 2)
2291                 s->cm_idlest_pll_mpu &= ~1;
2292             else
2293                 s->cm_idlest_pll_mpu |= 1;
2294             break;
2295         default:
2296             break;
2297     }
2298
2299     if (s->cm_idlest_pll_mpu & 1) {
2300         mpu_dpll_div = s->cm_clksel1_pll_mpu & 0x7f;
2301         mpu_dpll_clkout_div = s->cm_clksel2_pll_mpu & 0x1f;
2302         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
2303         omap_clk_setrate(mpu_clk,
2304                          (mpu_dpll_div + 1) * mpu_dpll_clkout_div,
2305                          mpu_dpll_mul);
2306     } else {
2307         /* bypass mode */
2308         mpu_clk_src = (s->cm_clksel1_pll_mpu >> 19) & 0x07;
2309         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_core_clk"));
2310         omap_clk_setrate(mpu_clk, mpu_clk_src, 1);
2311     }
2312 }
2313
2314 static inline void omap3_cm_dpll3_update(struct omap3_cm_s *s)
2315 {
2316     uint32_t core_dpll_mul = ((s->cm_clksel1_pll >> 16) & 0x7ff);
2317     uint32_t core_dpll_div, core_dpll_clkout_div, div_dpll3;
2318
2319     switch ((s->cm_clken_pll & 0x7)) {
2320         case 0x05: /* low power bypass */
2321         case 0x06: /* fast relock bypass */
2322             s->cm_idlest_ckgen &= ~1;
2323             break;
2324         case 0x07: /* locked */
2325             if (core_dpll_mul < 2)
2326                 s->cm_idlest_ckgen &= ~1;
2327             else
2328                 s->cm_idlest_ckgen |= 1;
2329             break;
2330         default:
2331             break;
2332     }
2333
2334     if (s->cm_idlest_ckgen & 1) {
2335         core_dpll_div = (s->cm_clksel1_pll >> 8) & 0x7f;
2336         core_dpll_clkout_div = (s->cm_clksel1_pll >> 27) & 0x1f;
2337         div_dpll3 = (s->cm_clksel1_emu >> 16) & 0x1f;
2338
2339         if (s->cm_clksel2_emu & 0x80000) { /* OVERRIDE_ENABLE */
2340                 core_dpll_mul = (s->cm_clksel2_emu >> 8) & 0x7ff;
2341                 core_dpll_div = s->cm_clksel2_emu & 0x7f;
2342         }
2343
2344         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"),
2345                          (core_dpll_div + 1) * core_dpll_clkout_div,
2346                          core_dpll_mul);
2347         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"),
2348                          (core_dpll_div + 1) * core_dpll_clkout_div,
2349                          core_dpll_mul * 2);
2350         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"),
2351                          (core_dpll_div + 1) * div_dpll3,
2352                          core_dpll_mul * 2);
2353     } else {
2354         /* bypass mode */
2355         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), 1, 1);
2356         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), 1, 1);
2357         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"), 1, 1);
2358     }
2359 }
2360
2361 static inline void omap3_cm_dpll4_update(struct omap3_cm_s *s)
2362 {
2363     uint32_t per_dpll_mul = ((s->cm_clksel2_pll >> 8) & 0x7ff);
2364     uint32_t per_dpll_div, div_96m, clksel_tv, clksel_dss1, clksel_cam, div_dpll4;
2365
2366     switch (((s->cm_clken_pll >> 16) & 0x7)) {
2367         case 0x01: /* lower power stop mode */
2368             s->cm_idlest_ckgen &= ~2;
2369             break;
2370         case 0x07: /* locked */
2371             if (per_dpll_mul < 2)
2372                 s->cm_idlest_ckgen &= ~2;
2373             else
2374                 s->cm_idlest_ckgen |= 2;
2375             break;
2376         default:
2377             break;
2378     }
2379
2380     if (s->cm_idlest_ckgen & 2) {
2381         per_dpll_div = s->cm_clksel2_pll & 0x7f;
2382         div_96m = s->cm_clksel3_pll & 0x1f;
2383         clksel_tv = (s->cm_clksel_dss >> 8) & 0x1f;
2384         clksel_dss1 = s->cm_clksel_dss & 0x1f;
2385         clksel_cam = s->cm_clksel_cam & 0x1f;
2386         div_dpll4 = (s->cm_clksel1_emu >> 24) & 0x1f;
2387
2388         if (s->cm_clksel3_emu & 0x80000) { /* OVERRIDE_ENABLE */
2389                 per_dpll_mul = (s->cm_clksel3_emu >> 8) & 0x7ff;
2390                 per_dpll_div =  s->cm_clksel3_emu & 0x7f;
2391         }
2392
2393         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"),
2394                          (per_dpll_div + 1) * div_96m,
2395                          per_dpll_mul * 2);
2396         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"),
2397                          (per_dpll_div + 1) * clksel_tv,
2398                          per_dpll_mul * 2);
2399         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"),
2400                          (per_dpll_div + 1) * clksel_dss1,
2401                          per_dpll_mul * 2);
2402         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"),
2403                          (per_dpll_div + 1) * clksel_cam,
2404                          per_dpll_mul * 2);
2405         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"),
2406                          (per_dpll_div + 1) * div_dpll4,
2407                          per_dpll_mul * 2);
2408     } else {
2409         /* bypass mode */
2410         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), 1, 1);
2411         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), 1, 1);
2412         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"), 1, 1);
2413         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), 1, 1);
2414         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"), 1, 1);
2415     }
2416 }
2417
2418 static inline void omap3_cm_dpll5_update(struct omap3_cm_s *s)
2419 {
2420     uint32_t per2_dpll_mul = ((s->cm_clksel4_pll >> 8) & 0x7ff);
2421     uint32_t per2_dpll_div, div_120m;
2422
2423     switch ((s->cm_clken2_pll & 0x7)) {
2424         case 0x01: /* low power stop mode */
2425             s->cm_idlest2_ckgen &= ~1;
2426             break;
2427         case 0x07: /* locked */
2428             if (per2_dpll_mul < 2)
2429                 s->cm_idlest2_ckgen &= ~1;
2430             else
2431                 s->cm_idlest2_ckgen |= 1;
2432             break;
2433         default:
2434             break;
2435     }
2436
2437     if (s->cm_idlest2_ckgen & 1) {
2438         per2_dpll_div = s->cm_clksel4_pll & 0x7f;
2439         div_120m = s->cm_clksel5_pll & 0x1f;
2440
2441         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"),
2442                          (per2_dpll_div + 1) * div_120m,
2443                          per2_dpll_mul);
2444     } else {
2445         /* bypass mode */
2446         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), 1, 1);
2447     }
2448 }
2449
2450 static inline void omap3_cm_48m_update(struct omap3_cm_s *s)
2451 {
2452     omap_clk pclk = omap_findclk(s->mpu,
2453                                  (s->cm_clksel1_pll & 0x8) /* SOURCE_48M */
2454                                  ? "omap3_sys_altclk"
2455                                  : "omap3_96m_fclk");
2456
2457     omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"), pclk);
2458     omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"), pclk);
2459 }
2460
2461 static inline void omap3_cm_gp10gp11_update(struct omap3_cm_s *s)
2462 {
2463     omap_clk gp10 = omap_findclk(s->mpu, "omap3_gp10_fclk");
2464     omap_clk gp11 = omap_findclk(s->mpu, "omap3_gp11_fclk");
2465     omap_clk sys  = omap_findclk(s->mpu, "omap3_sys_clk");
2466     omap_clk f32k = omap_findclk(s->mpu, "omap3_32k_fclk");
2467
2468     omap_clk_reparent(gp10, (s->cm_clksel_core & 0x40) ? sys : f32k);
2469     omap_clk_reparent(gp11, (s->cm_clksel_core & 0x80) ? sys : f32k);
2470     omap_gp_timer_change_clk(s->mpu->gptimer[9]);
2471     omap_gp_timer_change_clk(s->mpu->gptimer[10]);
2472
2473     TRACE("gptimer10 fclk = %lld", omap_clk_getrate(gp10));
2474     TRACE("gptimer11 fclk = %lld", omap_clk_getrate(gp11));
2475 }
2476
2477 static inline void omap3_cm_per_gptimer_update(struct omap3_cm_s *s)
2478 {
2479     omap_clk sys = omap_findclk(s->mpu, "omap3_sys_clk");
2480     omap_clk f32k = omap_findclk(s->mpu, "omap3_32k_fclk");
2481     uint32_t cm_clksel_per = s->cm_clksel_per;
2482     uint32_t n;
2483     char clkname[] = "omap3_gp#_fclk";
2484
2485     for (n = 1; n < 9; n++, cm_clksel_per >>= 1) {
2486         clkname[8] = '1' + n; /* 2 - 9 */
2487         omap_clk_reparent(omap_findclk(s->mpu, clkname),
2488                           (cm_clksel_per & 1) ? sys : f32k);
2489         omap_gp_timer_change_clk(s->mpu->gptimer[n]);
2490         TRACE("gptimer%d fclk = %lld", n + 1,
2491               omap_clk_getrate(omap_findclk(s->mpu, clkname)));
2492     }
2493 }
2494
2495 static inline void omap3_cm_clkout2_update(struct omap3_cm_s *s)
2496 {
2497     omap_clk c = omap_findclk(s->mpu, "omap3_sys_clkout2");
2498
2499     omap_clk_onoff(c, (s->cm_clkout_ctrl >> 7) & 1);
2500     switch (s->cm_clkout_ctrl & 0x3) {
2501         case 0:
2502             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_core_clk"));
2503             break;
2504         case 1:
2505             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_sys_clk"));
2506             break;
2507         case 2:
2508             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_96m_fclk"));
2509             break;
2510         case 3:
2511             omap_clk_reparent(c, omap_findclk(s->mpu, "omap3_54m_fclk"));
2512             break;
2513         default:
2514             break;
2515     }
2516     omap_clk_setrate(c, 1 << ((s->cm_clkout_ctrl >> 3) & 7), 1);
2517 }
2518
2519 static inline void omap3_cm_fclken1_core_update(struct omap3_cm_s *s)
2520 {
2521     uint32_t v = s->cm_fclken1_core;
2522
2523     /* TODO: EN_MCBSP1,5 */
2524     omap_clk_onoff(omap_findclk(s->mpu, "omap3_gp10_fclk"),  (v >> 11) & 1);
2525     omap_clk_onoff(omap_findclk(s->mpu, "omap3_gp11_fclk"),  (v >> 12) & 1);
2526     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart1_fclk"), (v >> 13) & 1);
2527     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart2_fclk"), (v >> 14) & 1);
2528     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c1_fclk"),  (v >> 15) & 1);
2529     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c2_fclk"),  (v >> 16) & 1);
2530     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c3_fclk"),  (v >> 17) & 1);
2531     /* TODO: EN_HDQ, EN_SPI1-4 */
2532     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc1_fclk"),  (v >> 24) & 1);
2533     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc2_fclk"),  (v >> 25) & 1);
2534     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc3_fclk"),  (v >> 30) & 1);
2535 }
2536
2537 static inline void omap3_cm_iclken1_core_update(struct omap3_cm_s *s)
2538 {
2539     uint32_t v = s->cm_iclken1_core;
2540
2541     /* TODO: EN_SDRC, EN_HSOTGUSB, EN_OMAPCTRL, EN_MAILBOXES, EN_MCBSP1,5 */
2542     /* TODO: EN_GPT10, EN_GPT11 */
2543     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart1_iclk"), (v >> 13) & 1);
2544     omap_clk_onoff(omap_findclk(s->mpu, "omap3_uart2_iclk"), (v >> 14) & 1);
2545     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c1_iclk"),  (v >> 15) & 1);
2546     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c2_iclk"),  (v >> 16) & 1);
2547     omap_clk_onoff(omap_findclk(s->mpu, "omap3_i2c3_iclk"),  (v >> 17) & 1);
2548     /* TODO: EN_HDQ, EN_SPI1-4 */
2549     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc1_iclk"),  (v >> 24) & 1);
2550     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc2_iclk"),  (v >> 25) & 1);
2551     omap_clk_onoff(omap_findclk(s->mpu, "omap3_mmc3_iclk"),  (v >> 30) & 1);
2552     /* set USB OTG idle if iclk is enabled and SDMA always in standby */
2553     v &= ~0x24;
2554     v |= (v & 0x10) << 1;
2555     s->cm_idlest1_core = ~v;
2556 }
2557
2558 static inline void omap3_cm_l3l4iclk_update(struct omap3_cm_s *s)
2559 {
2560     omap_clk_setrate(omap_findclk(s->mpu, "omap3_l3_iclk"),
2561                      s->cm_clksel_core & 0x3, 1);
2562     omap_clk_setrate(omap_findclk(s->mpu, "omap3_l4_iclk"),
2563                      (s->cm_clksel_core >> 2) & 0x3, 1);
2564 }
2565
2566 static void omap3_cm_reset(struct omap3_cm_s *s)
2567 {
2568     s->cm_fclken_iva2 = 0x0;
2569     s->cm_clken_pll_iva2 = 0x11;
2570     s->cm_idlest_iva2 = 0x1;
2571     s->cm_idlest_pll_iva2 = 0;
2572     s->cm_autoidle_pll_iva2 = 0x0;
2573     s->cm_clksel1_pll_iva2 = 0x80000;
2574     s->cm_clksel2_pll_iva2 = 0x1;
2575     s->cm_clkstctrl_iva2 = 0x0;
2576     s->cm_clkstst_iva2 = 0x0;
2577
2578     s->cm_revision = 0x10;
2579     s->cm_sysconfig = 0x1;
2580
2581     s->cm_clken_pll_mpu = 0x15;
2582     s->cm_idlest_mpu = 0x1;
2583     s->cm_idlest_pll_mpu = 0;
2584     s->cm_autoidle_pll_mpu = 0x0;
2585     s->cm_clksel1_pll_mpu = 0x80000;
2586     s->cm_clksel2_pll_mpu = 0x1;
2587     s->cm_clkstctrl_mpu = 0x0;
2588     s->cm_clkstst_mpu = 0x0;
2589
2590     s->cm_fclken1_core = 0x0;
2591     s->cm_fclken3_core = 0x0;
2592     s->cm_iclken1_core = 0x42;
2593     s->cm_iclken2_core = 0x0;
2594     s->cm_iclken3_core = 0x0;
2595     /*allow access to devices*/
2596     s->cm_idlest1_core = 0x0;
2597     s->cm_idlest2_core = 0x0;
2598     /*ide status =0 */
2599     s->cm_idlest3_core = 0xa;
2600     s->cm_autoidle1_core = 0x0;
2601     s->cm_autoidle2_core = 0x0;
2602     s->cm_autoidle3_core = 0x0;
2603     s->cm_clksel_core = 0x105;
2604     s->cm_clkstctrl_core = 0x0;
2605     s->cm_clkstst_core = 0x0;
2606
2607     s->cm_fclken_sgx = 0x0;
2608     s->cm_iclken_sgx = 0x0;
2609     s->cm_idlest_sgx = 0x1;
2610     s->cm_clksel_sgx = 0x0;
2611     s->cm_sleepdep_sgx = 0x0;
2612     s->cm_clkstctrl_sgx = 0x0;
2613     s->cm_clkstst_sgx = 0x0;
2614
2615     s->cm_fclken_wkup = 0x0;
2616     s->cm_iclken_wkup = 0x0;
2617     /*assume all clock can be accessed*/
2618     s->cm_idlest_wkup = 0x0;
2619     s->cm_autoidle_wkup = 0x0;
2620     s->cm_clksel_wkup = 0x12;
2621
2622     s->cm_clken_pll = 0x110015;
2623     s->cm_clken2_pll = 0x11;
2624     s->cm_idlest_ckgen = 0x3f3c; /* FIXME: provide real clock statuses */
2625     s->cm_idlest2_ckgen = 0xa; /* FIXME: provide real clock statuses */
2626     s->cm_autoidle_pll = 0x0;
2627     s->cm_autoidle2_pll = 0x0;
2628     s->cm_clksel1_pll = 0x8000040;
2629     s->cm_clksel2_pll = 0x0;
2630     s->cm_clksel3_pll = 0x1;
2631     s->cm_clksel4_pll = 0x0;
2632     s->cm_clksel5_pll = 0x1;
2633     s->cm_clkout_ctrl = 0x3;
2634
2635
2636     s->cm_fclken_dss = 0x0;
2637     s->cm_iclken_dss = 0x0;
2638     /*dss can be accessed*/
2639     s->cm_idlest_dss = 0x0;
2640     s->cm_autoidle_dss = 0x0;
2641     s->cm_clksel_dss = 0x1010;
2642     s->cm_sleepdep_dss = 0x0;
2643     s->cm_clkstctrl_dss = 0x0;
2644     s->cm_clkstst_dss = 0x0;
2645
2646     s->cm_fclken_cam = 0x0;
2647     s->cm_iclken_cam = 0x0;
2648     s->cm_idlest_cam = 0x1;
2649     s->cm_autoidle_cam = 0x0;
2650     s->cm_clksel_cam = 0x10;
2651     s->cm_sleepdep_cam = 0x0;
2652     s->cm_clkstctrl_cam = 0x0;
2653     s->cm_clkstst_cam = 0x0;
2654
2655     s->cm_fclken_per = 0x0;
2656     s->cm_iclken_per = 0x0;
2657     //s->cm_idlest_per = 0x3ffff;
2658     s->cm_idlest_per = 0x0; //enable GPIO access
2659     s->cm_autoidle_per = 0x0;
2660     s->cm_clksel_per = 0x0;
2661     s->cm_sleepdep_per = 0x0;
2662     s->cm_clkstctrl_per = 0x0;
2663     s->cm_clkstst_per = 0x0;
2664
2665     s->cm_clksel1_emu = 0x10100a50;
2666     s->cm_clkstctrl_emu = 0x2;
2667     s->cm_clkstst_emu = 0x0;
2668     s->cm_clksel2_emu = 0x0;
2669     s->cm_clksel3_emu = 0x0;
2670
2671     s->cm_polctrl = 0x0;
2672
2673     s->cm_idlest_neon = 0x1;
2674     s->cm_clkstctrl_neon = 0x0;
2675
2676     s->cm_fclken_usbhost = 0x0;
2677     s->cm_iclken_usbhost = 0x0;
2678     s->cm_idlest_usbhost = 0x3;
2679     s->cm_autoidle_usbhost = 0x0;
2680     s->cm_sleepdep_usbhost = 0x0;
2681     s->cm_clkstctrl_usbhost = 0x0;
2682     s->cm_clkstst_usbhost = 0x0;
2683 }
2684
2685 static uint32_t omap3_cm_read(void *opaque, target_phys_addr_t addr)
2686 {
2687     struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;
2688
2689     switch (addr) {
2690         /* IVA2_CM */
2691         case 0x0000: return s->cm_fclken_iva2;
2692         case 0x0004: return s->cm_clken_pll_iva2;
2693         case 0x0020: return s->cm_idlest_iva2;
2694         case 0x0024: return s->cm_idlest_pll_iva2;
2695         case 0x0034: return s->cm_autoidle_pll_iva2;
2696         case 0x0040: return s->cm_clksel1_pll_iva2;
2697         case 0x0044: return s->cm_clksel2_pll_iva2;
2698         case 0x0048: return s->cm_clkstctrl_iva2;
2699         case 0x004c: return s->cm_clkstst_iva2;
2700         /* OCP_System_Reg_CM */
2701         case 0x0800: return s->cm_revision;
2702         case 0x0810: return s->cm_sysconfig;
2703         /* MPU_CM */
2704         case 0x0904: return s->cm_clken_pll_mpu;
2705         case 0x0920: return s->cm_idlest_mpu & 0x0; /*MPU is active*/
2706         case 0x0924: return s->cm_idlest_pll_mpu;
2707         case 0x0934: return s->cm_autoidle_pll_mpu;
2708         case 0x0940: return s->cm_clksel1_pll_mpu;
2709         case 0x0944: return s->cm_clksel2_pll_mpu;
2710         case 0x0948: return s->cm_clkstctrl_mpu;
2711         case 0x094c: return s->cm_clkstst_mpu;
2712         /* CORE_CM */
2713         case 0x0a00: return s->cm_fclken1_core;
2714         case 0x0a08: return s->cm_fclken3_core;
2715         case 0x0a10: return s->cm_iclken1_core;
2716         case 0x0a14: return s->cm_iclken2_core;
2717         case 0x0a20: return s->cm_idlest1_core;
2718         case 0x0a24: return s->cm_idlest2_core;
2719         case 0x0a28: return s->cm_idlest3_core;
2720         case 0x0a30: return s->cm_autoidle1_core;
2721         case 0x0a34: return s->cm_autoidle2_core;
2722         case 0x0a38: return s->cm_autoidle3_core;
2723         case 0x0a40: return s->cm_clksel_core;
2724         case 0x0a48: return s->cm_clkstctrl_core;
2725         case 0x0a4c: return s->cm_clkstst_core;
2726         /* SGX_CM */
2727         case 0x0b00: return s->cm_fclken_sgx;
2728         case 0x0b10: return s->cm_iclken_sgx;
2729         case 0x0b20: return s->cm_idlest_sgx & 0x0;
2730         case 0x0b40: return s->cm_clksel_sgx;
2731         case 0x0b48: return s->cm_clkstctrl_sgx;
2732         case 0x0b4c: return s->cm_clkstst_sgx;
2733         /* WKUP_CM */
2734         case 0x0c00: return s->cm_fclken_wkup;
2735         case 0x0c10: return s->cm_iclken_wkup;
2736         case 0x0c20: return 0; /* TODO: Check if the timer can be accessed. */
2737         case 0x0c30: return s->cm_idlest_wkup;
2738         case 0x0c40: return s->cm_clksel_wkup;
2739         case 0x0c48: return s->cm_c48;
2740         /* Clock_Control_Reg_CM */
2741         case 0x0d00: return s->cm_clken_pll;
2742         case 0x0d04: return s->cm_clken2_pll;
2743         case 0x0d20: return s->cm_idlest_ckgen;
2744         case 0x0d24: return s->cm_idlest2_ckgen;
2745         case 0x0d30: return s->cm_autoidle_pll;
2746         case 0x0d34: return s->cm_autoidle2_pll;
2747         case 0x0d40: return s->cm_clksel1_pll;
2748         case 0x0d44: return s->cm_clksel2_pll;
2749         case 0x0d48: return s->cm_clksel3_pll;
2750         case 0x0d4c: return s->cm_clksel4_pll;
2751         case 0x0d50: return s->cm_clksel5_pll;
2752         case 0x0d70: return s->cm_clkout_ctrl;
2753         /* DSS_CM */
2754         case 0x0e00: return s->cm_fclken_dss;
2755         case 0x0e10: return s->cm_iclken_dss;
2756         case 0x0e20: return s->cm_idlest_dss;
2757         case 0x0e30: return s->cm_autoidle_dss;
2758         case 0x0e40: return s->cm_clksel_dss;
2759         case 0x0e44: return s->cm_sleepdep_dss;
2760         case 0x0e48: return s->cm_clkstctrl_dss;
2761         case 0x0e4c: return s->cm_clkstst_dss;
2762         /* CAM_CM */
2763         case 0x0f00: return s->cm_fclken_cam;
2764         case 0x0f10: return s->cm_iclken_cam;
2765         case 0x0f20: return s->cm_idlest_cam & 0x0;
2766         case 0x0f30: return s->cm_autoidle_cam;
2767         case 0x0f40: return s->cm_clksel_cam;
2768         case 0x0f44: return s->cm_sleepdep_cam;
2769         case 0x0f48: return s->cm_clkstctrl_cam;
2770         case 0x0f4c: return s->cm_clkstst_cam;
2771         /* PER_CM */
2772         case 0x1000: return s->cm_fclken_per;
2773         case 0x1010: return s->cm_iclken_per;
2774         case 0x1020: return s->cm_idlest_per ;
2775         case 0x1030: return s->cm_autoidle_per;
2776         case 0x1040: return s->cm_clksel_per;
2777         case 0x1044: return s->cm_sleepdep_per;
2778         case 0x1048: return s->cm_clkstctrl_per;
2779         case 0x104c: return s->cm_clkstst_per;
2780         /* EMU_CM */
2781         case 0x1140: return s->cm_clksel1_emu;
2782         case 0x1148: return s->cm_clkstctrl_emu;
2783         case 0x114c: return s->cm_clkstst_emu & 0x0;
2784         case 0x1150: return s->cm_clksel2_emu;
2785         case 0x1154: return s->cm_clksel3_emu;
2786         /* Global_Reg_CM */
2787         case 0x129c: return s->cm_polctrl;
2788         /* NEON_CM */
2789         case 0x1320: return s->cm_idlest_neon & 0x0;
2790         case 0x1348: return s->cm_clkstctrl_neon;
2791         /* USBHOST_CM */
2792         case 0x1400: return s->cm_fclken_usbhost;
2793         case 0x1410: return s->cm_iclken_usbhost;
2794         case 0x1420: return s->cm_idlest_usbhost & 0x0;
2795         case 0x1430: return s->cm_autoidle_usbhost;
2796         case 0x1444: return s->cm_sleepdep_usbhost;
2797         case 0x1448: return s->cm_clkstctrl_usbhost;
2798         case 0x144c: return s->cm_clkstst_usbhost;
2799         /* unknown */
2800         default: break;
2801     }
2802     OMAP_BAD_REG(addr);
2803     return 0;
2804 }
2805
2806 static void omap3_cm_write(void *opaque,
2807                            target_phys_addr_t addr,
2808                            uint32_t value)
2809 {
2810     struct omap3_cm_s *s = (struct omap3_cm_s *)opaque;
2811
2812     switch (addr) {
2813         case 0x0020:
2814         case 0x0024:
2815         case 0x004c:
2816         case 0x0800:
2817         case 0x0920:
2818         case 0x0924:
2819         case 0x094c:
2820         case 0x0a20:
2821         case 0x0a24:
2822         case 0x0a28:
2823         case 0x0a4c:
2824         case 0x0b20:
2825         case 0x0b4c:
2826         case 0x0c20:
2827         case 0x0d20:
2828         case 0x0d24:
2829         case 0x0e20:
2830         case 0x0e4c:
2831         case 0x0f20:
2832         case 0x0f4c:
2833         case 0x1020:
2834         case 0x104c:
2835         case 0x114c:
2836         case 0x1320:
2837         case 0x1420:
2838         case 0x144c:
2839             OMAP_RO_REGV(addr, value);
2840             break;
2841         /* IVA2_CM */
2842         case 0x0000:
2843             s->cm_fclken_iva2 = value & 0x1;
2844             omap3_cm_iva2_update(s);
2845             break;
2846         case 0x0004:
2847             s->cm_clken_pll_iva2 = value & 0x7ff;
2848             omap3_cm_iva2_update(s);
2849             break;
2850         case 0x0034:
2851             s->cm_autoidle_pll_iva2 = value & 0x7;
2852             break;
2853         case 0x0040:
2854             s->cm_clksel1_pll_iva2 = value & 0x3fff7f;
2855             omap3_cm_iva2_update(s);
2856             break;
2857         case 0x0044:
2858             s->cm_clksel2_pll_iva2 = value & 0x1f;
2859             omap3_cm_iva2_update(s);
2860             break;
2861         case 0x0048:
2862             s->cm_clkstctrl_iva2 = value & 0x3;
2863             break;
2864         /* OCP_System_Reg_CM */
2865         case 0x0810:
2866             s->cm_sysconfig = value & 0x1;
2867             break;
2868         /* MPU_CM */
2869         case 0x0904:
2870             s->cm_clken_pll_mpu = value & 0x7ff;
2871             omap3_cm_mpu_update(s);
2872             break;
2873         case 0x0934:
2874             s->cm_autoidle_pll_mpu = value & 0x7;
2875             break;
2876         case 0x0940:
2877             s->cm_clksel1_pll_mpu = value & 0x3fff7f;
2878             omap3_cm_mpu_update(s);
2879             break;
2880         case 0x0944:
2881             s->cm_clksel2_pll_mpu = value & 0x1f;
2882             omap3_cm_mpu_update(s);
2883             break;
2884         case 0x0948:
2885             s->cm_clkstctrl_mpu = value & 0x3;
2886             break;
2887         /* CORE_CM */
2888         case 0xa00:
2889             s->cm_fclken1_core = value & 0x43fffe00;
2890             omap3_cm_fclken1_core_update(s);
2891             break;
2892         case 0xa08:
2893             s->cm_fclken3_core = value & 0x7;
2894             /* TODO: EN_USBTLL, EN_TS */
2895             break;
2896         case 0xa10:
2897             s->cm_iclken1_core = value & 0x637ffed2;
2898             omap3_cm_iclken1_core_update(s);
2899             break;
2900         case 0xa14:
2901             s->cm_iclken2_core = value & 0x1f;
2902             break;
2903         case 0xa18:
2904             s->cm_iclken3_core = value & 0x4;
2905             s->cm_idlest3_core = 0xd & ~(s->cm_iclken3_core & 4);
2906             break;
2907         case 0xa30:
2908             s->cm_autoidle1_core = value & 0x7ffffed0;
2909             break;
2910         case 0xa34:
2911             s->cm_autoidle2_core = value & 0x1f;
2912             break;
2913         case 0xa38:
2914             s->cm_autoidle3_core = value & 0x2;
2915             break;
2916         case 0xa40:
2917             s->cm_clksel_core = (value & 0xff) | 0x100;
2918             omap3_cm_gp10gp11_update(s);
2919             omap3_cm_l3l4iclk_update(s);
2920             break;
2921         case 0xa48:
2922             s->cm_clkstctrl_core = value & 0xf;
2923             break;
2924         /* SGX_CM */
2925         case 0xb00: s->cm_fclken_sgx = value & 0x2; break;
2926         case 0xb10: s->cm_iclken_sgx = value & 0x1; break;
2927         case 0xb40: s->cm_clksel_sgx = value; break; /* TODO: SGX clock */
2928         case 0xb44: s->cm_sleepdep_sgx = value &0x2; break;
2929         case 0xb48: s->cm_clkstctrl_sgx = value & 0x3; break;
2930         /* WKUP_CM */
2931         case 0xc00:
2932             s->cm_fclken_wkup = value & 0x2e9;
2933             omap_clk_onoff(omap_findclk(s->mpu, "omap3_gp1_fclk"),
2934                            s->cm_fclken_wkup & 1);
2935             /* TODO: EN_GPIO1 */
2936             /* TODO: EN_WDT2 */
2937             break;
2938         case 0xc10:
2939             s->cm_iclken_wkup = value & 0x23f;
2940             omap_clk_onoff(omap_findclk(s->mpu, "omap3_wkup_l4_iclk"),
2941                            s->cm_iclken_wkup ? 1 : 0);
2942             break;
2943         case 0xc30: s->cm_autoidle_wkup = value & 0x23f; break;
2944         case 0xc40:
2945             s->cm_clksel_wkup = value & 0x7f;
2946             omap3_cm_clksel_wkup_update(s);
2947             break;
2948         /* Clock_Control_Reg_CM */
2949         case 0xd00:
2950             s->cm_clken_pll = value & 0xffff17ff;
2951             omap3_cm_dpll3_update(s);
2952             omap3_cm_dpll4_update(s);
2953             break;
2954         case 0xd04:
2955             s->cm_clken2_pll = value & 0x7ff;
2956             omap3_cm_dpll5_update(s);
2957             break;
2958         case 0xd30: s->cm_autoidle_pll = value & 0x3f; break;
2959         case 0xd34: s->cm_autoidle2_pll = value & 0x7; break;
2960         case 0xd40:
2961             s->cm_clksel1_pll = value & 0xffffbffc;
2962             omap3_cm_dpll3_update(s);
2963             omap3_cm_48m_update(s);
2964             /* TODO: 96m and 54m update */
2965             break;
2966         case 0xd44:
2967             s->cm_clksel2_pll = value & 0x7ff7f;
2968             omap3_cm_dpll4_update(s);
2969             break;
2970         case 0xd48:
2971             s->cm_clksel3_pll = value & 0x1f;
2972             omap3_cm_dpll4_update(s);
2973             break;
2974         case 0xd4c:
2975             s->cm_clksel4_pll = value & 0x7ff7f;
2976             omap3_cm_dpll5_update(s);
2977             break;
2978         case 0xd50:
2979             s->cm_clksel5_pll = value & 0x1f;
2980             omap3_cm_dpll5_update(s);
2981             break;
2982         case 0xd70:
2983             s->cm_clkout_ctrl = value & 0xbb;
2984             omap3_cm_clkout2_update(s);
2985             break;
2986         /* DSS_CM */
2987         case 0xe00: s->cm_fclken_dss = value & 0x7; break;
2988         case 0xe10: s->cm_iclken_dss = value & 0x1; break;
2989         case 0xe30: s->cm_autoidle_dss = value & 0x1; break;
2990         case 0xe40:
2991             s->cm_clksel_dss = value & 0x1f1f;
2992             omap3_cm_dpll4_update(s);
2993             break;
2994         case 0xe44: s->cm_sleepdep_dss = value & 0x7; break;
2995         case 0xe48: s->cm_clkstctrl_dss = value & 0x3; break;
2996         /* CAM_CM */
2997         case 0xf00: s->cm_fclken_cam = value & 0x3; break;
2998         case 0xf10: s->cm_iclken_cam = value & 0x1; break;
2999         case 0xf30: s->cm_autoidle_cam = value & 0x1; break;
3000         case 0xf40:
3001             s->cm_clksel_cam = value & 0x1f;
3002             omap3_cm_dpll4_update(s);
3003             break;
3004         case 0xf44: s->cm_sleepdep_cam = value & 0x2; break;
3005         case 0xf48: s->cm_clkstctrl_cam = value & 0x3; break;
3006         /* PER_CM */
3007         case 0x1000: s->cm_fclken_per = value & 0x3ffff; break;
3008         case 0x1010: s->cm_iclken_per = value & 0x3ffff; break;
3009         case 0x1030: s->cm_autoidle_per = value &0x3ffff; break;
3010         case 0x1040:
3011             s->cm_clksel_per = value & 0xff;
3012             omap3_cm_per_gptimer_update(s);
3013             break;
3014         case 0x1044: s->cm_sleepdep_per = value & 0x6; break;
3015         case 0x1048: s->cm_clkstctrl_per = value &0x7; break;
3016         /* EMU_CM */
3017         case 0x1140:
3018             s->cm_clksel1_emu = value & 0x1f1f3fff;
3019             omap3_cm_dpll3_update(s);
3020             omap3_cm_dpll4_update(s);
3021             break;
3022         case 0x1148: s->cm_clkstctrl_emu = value & 0x3; break;
3023         case 0x1150:
3024             s->cm_clksel2_emu = value & 0xfff7f;
3025             omap3_cm_dpll3_update(s);
3026             break;
3027         case 0x1154:
3028             s->cm_clksel3_emu = value & 0xfff7f;
3029             omap3_cm_dpll4_update(s);
3030             break;
3031         /* Global_Reg_CM */
3032         case 0x129c: s->cm_polctrl = value & 0x1; break;
3033         /* NEON_CM */
3034         case 0x1348: s->cm_clkstctrl_neon = value & 0x3; break;
3035         /* USBHOST_CM */
3036         case 0x1400: s->cm_fclken_usbhost = value & 0x3; break;
3037         case 0x1410: s->cm_iclken_usbhost = value & 0x1; break;
3038         case 0x1430: s->cm_autoidle_usbhost = value & 0x1; break;
3039         case 0x1444: s->cm_sleepdep_usbhost = value & 0x6; break;
3040         case 0x1448: s->cm_clkstctrl_usbhost = value & 0x3; break;
3041         /* unknown */
3042         default:
3043             OMAP_BAD_REGV(addr, value);
3044             break;
3045     }
3046 }
3047
3048 static void omap3_cm_save_state(QEMUFile *f, void *opaque)
3049 {
3050     struct omap3_cm_s *s = (struct omap3_cm_s *)opaque;
3051
3052     qemu_put_be32(f, s->cm_fclken_iva2);
3053     qemu_put_be32(f, s->cm_clken_pll_iva2);
3054     qemu_put_be32(f, s->cm_idlest_iva2);
3055     qemu_put_be32(f, s->cm_idlest_pll_iva2);
3056     qemu_put_be32(f, s->cm_autoidle_pll_iva2);
3057     qemu_put_be32(f, s->cm_clksel1_pll_iva2);
3058     qemu_put_be32(f, s->cm_clksel2_pll_iva2);
3059     qemu_put_be32(f, s->cm_clkstctrl_iva2);
3060     qemu_put_be32(f, s->cm_clkstst_iva2);
3061
3062     qemu_put_be32(f, s->cm_revision);
3063     qemu_put_be32(f, s->cm_sysconfig);
3064
3065     qemu_put_be32(f, s->cm_clken_pll_mpu);
3066     qemu_put_be32(f, s->cm_idlest_mpu);
3067     qemu_put_be32(f, s->cm_idlest_pll_mpu);
3068     qemu_put_be32(f, s->cm_autoidle_pll_mpu);
3069     qemu_put_be32(f, s->cm_clksel1_pll_mpu);
3070     qemu_put_be32(f, s->cm_clksel2_pll_mpu);
3071     qemu_put_be32(f, s->cm_clkstctrl_mpu);
3072     qemu_put_be32(f, s->cm_clkstst_mpu);
3073
3074     qemu_put_be32(f, s->cm_fclken1_core);
3075     qemu_put_be32(f, s->cm_fclken3_core);
3076     qemu_put_be32(f, s->cm_iclken1_core);
3077     qemu_put_be32(f, s->cm_iclken2_core);
3078     qemu_put_be32(f, s->cm_iclken3_core);
3079     qemu_put_be32(f, s->cm_idlest1_core);
3080     qemu_put_be32(f, s->cm_idlest2_core);
3081     qemu_put_be32(f, s->cm_idlest3_core);
3082     qemu_put_be32(f, s->cm_autoidle1_core);
3083     qemu_put_be32(f, s->cm_autoidle2_core);
3084     qemu_put_be32(f, s->cm_autoidle3_core);
3085     qemu_put_be32(f, s->cm_clksel_core);
3086     qemu_put_be32(f, s->cm_clkstctrl_core);
3087     qemu_put_be32(f, s->cm_clkstst_core);
3088
3089     qemu_put_be32(f, s->cm_fclken_sgx);
3090     qemu_put_be32(f, s->cm_iclken_sgx);
3091     qemu_put_be32(f, s->cm_idlest_sgx);
3092     qemu_put_be32(f, s->cm_clksel_sgx);
3093     qemu_put_be32(f, s->cm_sleepdep_sgx);
3094     qemu_put_be32(f, s->cm_clkstctrl_sgx);
3095     qemu_put_be32(f, s->cm_clkstst_sgx);
3096
3097     qemu_put_be32(f, s->cm_fclken_wkup);
3098     qemu_put_be32(f, s->cm_iclken_wkup);
3099     qemu_put_be32(f, s->cm_idlest_wkup);
3100     qemu_put_be32(f, s->cm_autoidle_wkup);
3101     qemu_put_be32(f, s->cm_clksel_wkup);
3102     qemu_put_be32(f, s->cm_c48);
3103
3104     qemu_put_be32(f, s->cm_clken_pll);
3105     qemu_put_be32(f, s->cm_clken2_pll);
3106     qemu_put_be32(f, s->cm_idlest_ckgen);
3107     qemu_put_be32(f, s->cm_idlest2_ckgen);
3108     qemu_put_be32(f, s->cm_autoidle_pll);
3109     qemu_put_be32(f, s->cm_autoidle2_pll);
3110     qemu_put_be32(f, s->cm_clksel1_pll);
3111     qemu_put_be32(f, s->cm_clksel2_pll);
3112     qemu_put_be32(f, s->cm_clksel3_pll);
3113     qemu_put_be32(f, s->cm_clksel4_pll);
3114     qemu_put_be32(f, s->cm_clksel5_pll);
3115     qemu_put_be32(f, s->cm_clkout_ctrl);
3116
3117     qemu_put_be32(f, s->cm_fclken_dss);
3118     qemu_put_be32(f, s->cm_iclken_dss);
3119     qemu_put_be32(f, s->cm_idlest_dss);
3120     qemu_put_be32(f, s->cm_autoidle_dss);
3121     qemu_put_be32(f, s->cm_clksel_dss);
3122     qemu_put_be32(f, s->cm_sleepdep_dss);
3123     qemu_put_be32(f, s->cm_clkstctrl_dss);
3124     qemu_put_be32(f, s->cm_clkstst_dss);
3125
3126     qemu_put_be32(f, s->cm_fclken_cam);
3127     qemu_put_be32(f, s->cm_iclken_cam);
3128     qemu_put_be32(f, s->cm_idlest_cam);
3129     qemu_put_be32(f, s->cm_autoidle_cam);
3130     qemu_put_be32(f, s->cm_clksel_cam);
3131     qemu_put_be32(f, s->cm_sleepdep_cam);
3132     qemu_put_be32(f, s->cm_clkstctrl_cam);
3133     qemu_put_be32(f, s->cm_clkstst_cam);
3134
3135     qemu_put_be32(f, s->cm_fclken_per);
3136     qemu_put_be32(f, s->cm_iclken_per);
3137     qemu_put_be32(f, s->cm_idlest_per);
3138     qemu_put_be32(f, s->cm_autoidle_per);
3139     qemu_put_be32(f, s->cm_clksel_per);
3140     qemu_put_be32(f, s->cm_sleepdep_per);
3141     qemu_put_be32(f, s->cm_clkstctrl_per);
3142     qemu_put_be32(f, s->cm_clkstst_per);
3143
3144     qemu_put_be32(f, s->cm_clksel1_emu);
3145     qemu_put_be32(f, s->cm_clkstctrl_emu);
3146     qemu_put_be32(f, s->cm_clkstst_emu);
3147     qemu_put_be32(f, s->cm_clksel2_emu);
3148     qemu_put_be32(f, s->cm_clksel3_emu);
3149
3150     qemu_put_be32(f, s->cm_polctrl);
3151
3152     qemu_put_be32(f, s->cm_idlest_neon);
3153     qemu_put_be32(f, s->cm_clkstctrl_neon);
3154
3155     qemu_put_be32(f, s->cm_fclken_usbhost);
3156     qemu_put_be32(f, s->cm_iclken_usbhost);
3157     qemu_put_be32(f, s->cm_idlest_usbhost);
3158     qemu_put_be32(f, s->cm_autoidle_usbhost);
3159     qemu_put_be32(f, s->cm_sleepdep_usbhost);
3160     qemu_put_be32(f, s->cm_clkstctrl_usbhost);
3161     qemu_put_be32(f, s->cm_clkstst_usbhost);
3162 }
3163
3164 static int omap3_cm_load_state(QEMUFile *f, void *opaque, int version_id)
3165 {
3166     struct omap3_cm_s *s = (struct omap3_cm_s *)opaque;
3167
3168     if (version_id)
3169         return -EINVAL;
3170
3171     s->cm_fclken_iva2 = qemu_get_be32(f);
3172     s->cm_clken_pll_iva2 = qemu_get_be32(f);
3173     s->cm_idlest_iva2 = qemu_get_be32(f);
3174     s->cm_idlest_pll_iva2 = qemu_get_be32(f);
3175     s->cm_autoidle_pll_iva2 = qemu_get_be32(f);
3176     s->cm_clksel1_pll_iva2 = qemu_get_be32(f);
3177     s->cm_clksel2_pll_iva2 = qemu_get_be32(f);
3178     s->cm_clkstctrl_iva2 = qemu_get_be32(f);
3179     s->cm_clkstst_iva2 = qemu_get_be32(f);
3180
3181     s->cm_revision = qemu_get_be32(f);
3182     s->cm_sysconfig = qemu_get_be32(f);
3183
3184     s->cm_clken_pll_mpu = qemu_get_be32(f);
3185     s->cm_idlest_mpu = qemu_get_be32(f);
3186     s->cm_idlest_pll_mpu = qemu_get_be32(f);
3187     s->cm_autoidle_pll_mpu = qemu_get_be32(f);
3188     s->cm_clksel1_pll_mpu = qemu_get_be32(f);
3189     s->cm_clksel2_pll_mpu = qemu_get_be32(f);
3190     s->cm_clkstctrl_mpu = qemu_get_be32(f);
3191     s->cm_clkstst_mpu = qemu_get_be32(f);
3192
3193     s->cm_fclken1_core = qemu_get_be32(f);
3194     s->cm_fclken3_core = qemu_get_be32(f);
3195     s->cm_iclken1_core = qemu_get_be32(f);
3196     s->cm_iclken2_core = qemu_get_be32(f);
3197     s->cm_iclken3_core = qemu_get_be32(f);
3198     s->cm_idlest1_core = qemu_get_be32(f);
3199     s->cm_idlest2_core = qemu_get_be32(f);
3200     s->cm_idlest3_core = qemu_get_be32(f);
3201     s->cm_autoidle1_core = qemu_get_be32(f);
3202     s->cm_autoidle2_core = qemu_get_be32(f);
3203     s->cm_autoidle3_core = qemu_get_be32(f);
3204     s->cm_clksel_core = qemu_get_be32(f);
3205     s->cm_clkstctrl_core = qemu_get_be32(f);
3206     s->cm_clkstst_core = qemu_get_be32(f);
3207
3208     s->cm_fclken_sgx = qemu_get_be32(f);
3209     s->cm_iclken_sgx = qemu_get_be32(f);
3210     s->cm_idlest_sgx = qemu_get_be32(f);
3211     s->cm_clksel_sgx = qemu_get_be32(f);
3212     s->cm_sleepdep_sgx = qemu_get_be32(f);
3213     s->cm_clkstctrl_sgx = qemu_get_be32(f);
3214     s->cm_clkstst_sgx = qemu_get_be32(f);
3215
3216     s->cm_fclken_wkup = qemu_get_be32(f);
3217     s->cm_iclken_wkup = qemu_get_be32(f);
3218     s->cm_idlest_wkup = qemu_get_be32(f);
3219     s->cm_autoidle_wkup = qemu_get_be32(f);
3220     s->cm_clksel_wkup = qemu_get_be32(f);
3221     s->cm_c48 = qemu_get_be32(f);
3222
3223     s->cm_clken_pll = qemu_get_be32(f);
3224     s->cm_clken2_pll = qemu_get_be32(f);
3225     s->cm_idlest_ckgen = qemu_get_be32(f);
3226     s->cm_idlest2_ckgen = qemu_get_be32(f);
3227     s->cm_autoidle_pll = qemu_get_be32(f);
3228     s->cm_autoidle2_pll = qemu_get_be32(f);
3229     s->cm_clksel1_pll = qemu_get_be32(f);
3230     s->cm_clksel2_pll = qemu_get_be32(f);
3231     s->cm_clksel3_pll = qemu_get_be32(f);
3232     s->cm_clksel4_pll = qemu_get_be32(f);
3233     s->cm_clksel5_pll = qemu_get_be32(f);
3234     s->cm_clkout_ctrl = qemu_get_be32(f);
3235
3236     s->cm_fclken_dss = qemu_get_be32(f);
3237     s->cm_iclken_dss = qemu_get_be32(f);
3238     s->cm_idlest_dss = qemu_get_be32(f);
3239     s->cm_autoidle_dss = qemu_get_be32(f);
3240     s->cm_clksel_dss = qemu_get_be32(f);
3241     s->cm_sleepdep_dss = qemu_get_be32(f);
3242     s->cm_clkstctrl_dss = qemu_get_be32(f);
3243     s->cm_clkstst_dss = qemu_get_be32(f);
3244
3245     s->cm_fclken_cam = qemu_get_be32(f);
3246     s->cm_iclken_cam = qemu_get_be32(f);
3247     s->cm_idlest_cam = qemu_get_be32(f);
3248     s->cm_autoidle_cam = qemu_get_be32(f);
3249     s->cm_clksel_cam = qemu_get_be32(f);
3250     s->cm_sleepdep_cam = qemu_get_be32(f);
3251     s->cm_clkstctrl_cam = qemu_get_be32(f);
3252     s->cm_clkstst_cam = qemu_get_be32(f);
3253
3254     s->cm_fclken_per = qemu_get_be32(f);
3255     s->cm_iclken_per = qemu_get_be32(f);
3256     s->cm_idlest_per = qemu_get_be32(f);
3257     s->cm_autoidle_per = qemu_get_be32(f);
3258     s->cm_clksel_per = qemu_get_be32(f);
3259     s->cm_sleepdep_per = qemu_get_be32(f);
3260     s->cm_clkstctrl_per = qemu_get_be32(f);
3261     s->cm_clkstst_per = qemu_get_be32(f);
3262
3263     s->cm_clksel1_emu = qemu_get_be32(f);
3264     s->cm_clkstctrl_emu = qemu_get_be32(f);
3265     s->cm_clkstst_emu = qemu_get_be32(f);
3266     s->cm_clksel2_emu = qemu_get_be32(f);
3267     s->cm_clksel3_emu = qemu_get_be32(f);
3268
3269     s->cm_polctrl = qemu_get_be32(f);
3270
3271     s->cm_idlest_neon = qemu_get_be32(f);
3272     s->cm_clkstctrl_neon = qemu_get_be32(f);
3273
3274     s->cm_fclken_usbhost = qemu_get_be32(f);
3275     s->cm_iclken_usbhost = qemu_get_be32(f);
3276     s->cm_idlest_usbhost = qemu_get_be32(f);
3277     s->cm_autoidle_usbhost = qemu_get_be32(f);
3278     s->cm_sleepdep_usbhost = qemu_get_be32(f);
3279     s->cm_clkstctrl_usbhost = qemu_get_be32(f);
3280     s->cm_clkstst_usbhost = qemu_get_be32(f);
3281
3282     omap3_cm_iva2_update(s);
3283     omap3_cm_mpu_update(s);
3284     omap3_cm_fclken1_core_update(s);
3285     omap3_cm_iclken1_core_update(s);
3286     omap3_cm_gp10gp11_update(s);
3287     omap3_cm_l3l4iclk_update(s);
3288     omap_clk_onoff(omap_findclk(s->mpu, "omap3_gp1_fclk"),
3289                    s->cm_fclken_wkup & 1);
3290     omap_clk_onoff(omap_findclk(s->mpu, "omap3_wkup_l4_iclk"),
3291                    s->cm_iclken_wkup ? 1 : 0);
3292     omap3_cm_clksel_wkup_update(s);
3293     omap3_cm_dpll3_update(s);
3294     omap3_cm_dpll4_update(s);
3295     omap3_cm_dpll5_update(s);
3296     omap3_cm_48m_update(s);
3297     omap3_cm_clkout2_update(s);
3298     omap3_cm_per_gptimer_update(s);
3299
3300     return 0;
3301 }
3302
3303 static CPUReadMemoryFunc *omap3_cm_readfn[] = {
3304     omap_badwidth_read32,
3305     omap_badwidth_read32,
3306     omap3_cm_read,
3307 };
3308
3309 static CPUWriteMemoryFunc *omap3_cm_writefn[] = {
3310     omap_badwidth_write32,
3311     omap_badwidth_write32,
3312     omap3_cm_write,
3313 };
3314
3315 static struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
3316                                         qemu_irq mpu_int, qemu_irq dsp_int,
3317                                         qemu_irq iva_int,
3318                                         struct omap_mpu_state_s *mpu)
3319 {
3320     int iomemtype;
3321     struct omap3_cm_s *s = (struct omap3_cm_s *) qemu_mallocz(sizeof(*s));
3322
3323     s->irq[0] = mpu_int;
3324     s->irq[1] = dsp_int;
3325     s->irq[2] = iva_int;
3326     s->mpu = mpu;
3327     omap3_cm_reset(s);
3328
3329     iomemtype = l4_register_io_memory(0, omap3_cm_readfn, omap3_cm_writefn, s);
3330     omap_l4_attach(ta, 0, iomemtype);
3331     omap_l4_attach(ta, 1, iomemtype);
3332
3333     register_savevm("omap3_cm", -1, 0,
3334                     omap3_cm_save_state, omap3_cm_load_state, s);
3335     return s;
3336 }
3337
3338 #define OMAP3_SEC_WDT          1
3339 #define OMAP3_MPU_WDT         2
3340 #define OMAP3_IVA2_WDT        3
3341 /*omap3 watchdog timer*/
3342 struct omap3_wdt_s
3343 {
3344     qemu_irq irq;               /*IVA2 IRQ */
3345     struct omap_mpu_state_s *mpu;
3346     omap_clk clk;
3347     QEMUTimer *timer;
3348
3349     int active;
3350     int64_t rate;
3351     int64_t time;
3352     //int64_t ticks_per_sec;
3353
3354     uint32_t wd_sysconfig;
3355     uint32_t wd_sysstatus;
3356     uint32_t wisr;
3357     uint32_t wier;
3358     uint32_t wclr;
3359     uint32_t wcrr;
3360     uint32_t wldr;
3361     uint32_t wtgr;
3362     uint32_t wwps;
3363     uint32_t wspr;
3364
3365     /*pre and ptv in wclr */
3366     uint32_t pre;
3367     uint32_t ptv;
3368     //uint32_t val;
3369
3370     uint16_t writeh;            /* LSB */
3371     uint16_t readh;             /* MSB */
3372 };
3373
3374 static inline void omap3_wdt_timer_update(struct omap3_wdt_s *wdt_timer)
3375 {
3376     int64_t expires;
3377     if (wdt_timer->active) {
3378         expires = muldiv64(0xffffffffll - wdt_timer->wcrr,
3379                            ticks_per_sec, wdt_timer->rate);
3380         qemu_mod_timer(wdt_timer->timer, wdt_timer->time + expires);
3381     } else
3382         qemu_del_timer(wdt_timer->timer);
3383 }
3384
3385 static void omap3_wdt_clk_setup(struct omap3_wdt_s *timer)
3386 {
3387     /*TODO: Add irq as user to clk */
3388 }
3389
3390 static inline uint32_t omap3_wdt_timer_read(struct omap3_wdt_s *timer)
3391 {
3392     uint64_t distance;
3393
3394     if (timer->active) {
3395         distance = qemu_get_clock(vm_clock) - timer->time;
3396         distance = muldiv64(distance, timer->rate, ticks_per_sec);
3397
3398         if (distance >= 0xffffffff - timer->wcrr)
3399             return 0xffffffff;
3400         else
3401             return timer->wcrr + distance;
3402     } else
3403         return timer->wcrr;
3404 }
3405
3406 /*
3407 static inline void omap3_wdt_timer_sync(struct omap3_wdt_s *timer)
3408 {
3409     if (timer->active) {
3410         timer->val = omap3_wdt_timer_read(timer);
3411         timer->time = qemu_get_clock(vm_clock);
3412     }
3413 }*/
3414
3415 static void omap3_wdt_reset(struct omap3_wdt_s *s, int wdt_index)
3416 {
3417     s->wd_sysconfig = 0x0;
3418     s->wd_sysstatus = 0x0;
3419     s->wisr = 0x0;
3420     s->wier = 0x0;
3421     s->wclr = 0x20;
3422     s->wcrr = 0x0;
3423     switch (wdt_index) {
3424         case OMAP3_MPU_WDT:
3425         case OMAP3_IVA2_WDT:
3426             s->wldr = 0xfffb0000;
3427             break;
3428         case OMAP3_SEC_WDT:
3429             s->wldr = 0xffa60000;
3430             break;
3431         default:
3432             break;
3433     }
3434     s->wtgr = 0x0;
3435     s->wwps = 0x0;
3436     s->wspr = 0x0;
3437
3438     switch (wdt_index) {
3439         case OMAP3_SEC_WDT:
3440         case OMAP3_MPU_WDT:
3441             s->active = 1;
3442             break;
3443         case OMAP3_IVA2_WDT:
3444             s->active = 0;
3445             break;
3446         default:
3447             break;
3448     }
3449     s->pre = s->wclr & (1 << 5);
3450     s->ptv = (s->wclr & 0x1c) >> 2;
3451     s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
3452
3453     s->active = 1;
3454     s->time = qemu_get_clock(vm_clock);
3455     omap3_wdt_timer_update(s);
3456 }
3457
3458 static uint32_t omap3_wdt_read32(void *opaque, target_phys_addr_t addr,
3459                                  int wdt_index)
3460 {
3461     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
3462
3463     switch (addr) {
3464         case 0x10: return s->wd_sysconfig;
3465         case 0x14: return s->wd_sysstatus;
3466         case 0x18: return s->wisr & 0x1;
3467         case 0x1c: return s->wier & 0x1;
3468         case 0x24: return s->wclr & 0x3c;
3469         case 0x28: /* WCRR */
3470             s->wcrr = omap3_wdt_timer_read(s);
3471             s->time = qemu_get_clock(vm_clock);
3472             return s->wcrr;
3473         case 0x2c: return s->wldr;
3474         case 0x30: return s->wtgr;
3475         case 0x34: return s->wwps;
3476         case 0x48: return s->wspr;
3477         default: break;
3478     }
3479     OMAP_BAD_REG(addr);
3480     return 0;
3481 }
3482
3483 static uint32_t omap3_mpu_wdt_read16(void *opaque, target_phys_addr_t addr)
3484 {
3485     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
3486     uint32_t ret;
3487
3488     if (addr & 2)
3489         return s->readh;
3490
3491     ret = omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
3492     s->readh = ret >> 16;
3493     return ret & 0xffff;
3494 }
3495
3496 static uint32_t omap3_mpu_wdt_read32(void *opaque, target_phys_addr_t addr)
3497 {
3498     return omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
3499 }
3500
3501 static void omap3_wdt_write32(void *opaque, target_phys_addr_t addr,
3502                               uint32_t value, int wdt_index)
3503 {
3504     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
3505
3506     switch (addr) {
3507     case 0x14: /* WD_SYSSTATUS */
3508     case 0x34: /* WWPS */
3509         OMAP_RO_REGV(addr, value);
3510         break;
3511     case 0x10: /*WD_SYSCONFIG */
3512         s->wd_sysconfig = value & 0x33f;
3513         break;
3514     case 0x18: /* WISR */
3515          s->wisr = value & 0x1;
3516         break;
3517     case 0x1c: /* WIER */
3518         s->wier = value & 0x1;
3519         break;
3520     case 0x24: /* WCLR */
3521         s->wclr = value & 0x3c;
3522         break;
3523     case 0x28: /* WCRR */
3524         s->wcrr = value;
3525         s->time = qemu_get_clock(vm_clock);
3526         omap3_wdt_timer_update(s);
3527         break;
3528     case 0x2c: /* WLDR */
3529         s->wldr = value; /* It will take effect after next overflow */
3530         break;
3531     case 0x30: /* WTGR */
3532         if (value != s->wtgr) {
3533             s->wcrr = s->wldr;
3534             s->pre = s->wclr & (1 << 5);
3535             s->ptv = (s->wclr & 0x1c) >> 2;
3536             s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
3537             s->time = qemu_get_clock(vm_clock);
3538             omap3_wdt_timer_update(s);
3539         }
3540         s->wtgr = value;
3541         break;
3542     case 0x48: /* WSPR */
3543         if (((value & 0xffff) == 0x5555) && ((s->wspr & 0xffff) == 0xaaaa)) {
3544             s->active = 0;
3545             s->wcrr = omap3_wdt_timer_read(s);
3546             omap3_wdt_timer_update(s);
3547         }
3548         if (((value & 0xffff) == 0x4444) && ((s->wspr & 0xffff) == 0xbbbb)) {
3549             s->active = 1;
3550             s->time = qemu_get_clock(vm_clock);
3551             omap3_wdt_timer_update(s);
3552         }
3553         s->wspr = value;
3554         break;
3555     default:
3556         OMAP_BAD_REGV(addr, value);
3557         break;
3558     }
3559 }
3560
3561 static void omap3_mpu_wdt_write16(void *opaque, target_phys_addr_t addr,
3562                                   uint32_t value)
3563 {
3564     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
3565
3566     if (addr & 2)
3567         return omap3_wdt_write32(opaque, addr, (value << 16) | s->writeh,
3568                                  OMAP3_MPU_WDT);
3569     else
3570         s->writeh = (uint16_t) value;
3571 }
3572
3573 static void omap3_mpu_wdt_write32(void *opaque, target_phys_addr_t addr,
3574                                   uint32_t value)
3575 {
3576     omap3_wdt_write32(opaque, addr, value, OMAP3_MPU_WDT);
3577 }
3578
3579 static CPUReadMemoryFunc *omap3_mpu_wdt_readfn[] = {
3580     omap_badwidth_read32,
3581     omap3_mpu_wdt_read16,
3582     omap3_mpu_wdt_read32,
3583 };
3584
3585 static CPUWriteMemoryFunc *omap3_mpu_wdt_writefn[] = {
3586     omap_badwidth_write32,
3587     omap3_mpu_wdt_write16,
3588     omap3_mpu_wdt_write32,
3589 };
3590
3591 static void omap3_mpu_wdt_timer_tick(void *opaque)
3592 {
3593     struct omap3_wdt_s *wdt_timer = (struct omap3_wdt_s *) opaque;
3594
3595     /*TODO:Sent reset pulse to PRCM */
3596     wdt_timer->wcrr = wdt_timer->wldr;
3597
3598     /*after overflow, generate the new wdt_timer->rate */
3599     wdt_timer->pre = wdt_timer->wclr & (1 << 5);
3600     wdt_timer->ptv = (wdt_timer->wclr & 0x1c) >> 2;
3601     wdt_timer->rate =
3602         omap_clk_getrate(wdt_timer->clk) >> (wdt_timer->pre ? wdt_timer->
3603                                              ptv : 0);
3604
3605     wdt_timer->time = qemu_get_clock(vm_clock);
3606     omap3_wdt_timer_update(wdt_timer);
3607 }
3608
3609 static void omap3_mpu_wdt_save_state(QEMUFile *f, void *opaque)
3610 {
3611     struct omap3_wdt_s *s = (struct omap3_wdt_s *)opaque;
3612
3613     qemu_put_timer(f, s->timer);
3614     qemu_put_sbe32(f, s->active);
3615     qemu_put_be64(f, s->rate);
3616     qemu_put_be64(f, s->time);
3617     qemu_put_be32(f, s->wd_sysconfig);
3618     qemu_put_be32(f, s->wd_sysstatus);
3619     qemu_put_be32(f, s->wisr);
3620     qemu_put_be32(f, s->wier);
3621     qemu_put_be32(f, s->wclr);
3622     qemu_put_be32(f, s->wcrr);
3623     qemu_put_be32(f, s->wldr);
3624     qemu_put_be32(f, s->wtgr);
3625     qemu_put_be32(f, s->wwps);
3626     qemu_put_be32(f, s->wspr);
3627     qemu_put_be32(f, s->pre);
3628     qemu_put_be32(f, s->ptv);
3629     qemu_put_be16(f, s->writeh);
3630     qemu_put_be16(f, s->readh);
3631 }
3632
3633 static int omap3_mpu_wdt_load_state(QEMUFile *f, void *opaque, int version_id)
3634 {
3635     struct omap3_wdt_s *s = (struct omap3_wdt_s *)opaque;
3636
3637     if (version_id)
3638         return -EINVAL;
3639
3640     qemu_get_timer(f, s->timer);
3641     s->active = qemu_get_sbe32(f);
3642     s->rate = qemu_get_be64(f);
3643     s->time = qemu_get_be64(f);
3644     s->wd_sysconfig = qemu_get_be32(f);
3645     s->wd_sysstatus = qemu_get_be32(f);
3646     s->wisr = qemu_get_be32(f);
3647     s->wier = qemu_get_be32(f);
3648     s->wclr = qemu_get_be32(f);
3649     s->wcrr = qemu_get_be32(f);
3650     s->wldr = qemu_get_be32(f);
3651     s->wtgr = qemu_get_be32(f);
3652     s->wwps = qemu_get_be32(f);
3653     s->wspr = qemu_get_be32(f);
3654     s->pre = qemu_get_be32(f);
3655     s->ptv = qemu_get_be32(f);
3656     s->writeh = qemu_get_be16(f);
3657     s->readh = qemu_get_be16(f);
3658
3659     return 0;
3660 }
3661
3662 static struct omap3_wdt_s *omap3_mpu_wdt_init(struct omap_target_agent_s *ta,
3663                                               qemu_irq irq, omap_clk fclk,
3664                                               omap_clk iclk,
3665                                               struct omap_mpu_state_s *mpu)
3666 {
3667     int iomemtype;
3668     struct omap3_wdt_s *s = (struct omap3_wdt_s *) qemu_mallocz(sizeof(*s));
3669
3670     s->irq = irq;
3671     s->clk = fclk;
3672     s->timer = qemu_new_timer(vm_clock, omap3_mpu_wdt_timer_tick, s);
3673
3674     omap3_wdt_reset(s, OMAP3_MPU_WDT);
3675     if (irq != NULL)
3676         omap3_wdt_clk_setup(s);
3677
3678     iomemtype = l4_register_io_memory(0, omap3_mpu_wdt_readfn,
3679                                       omap3_mpu_wdt_writefn, s);
3680     omap_l4_attach(ta, 0, iomemtype);
3681
3682     register_savevm("omap3_mpu_wdt", -1, 0,
3683                     omap3_mpu_wdt_save_state, omap3_mpu_wdt_load_state, s);
3684     return s;
3685 }
3686
3687 struct omap3_scm_s {
3688     struct omap_mpu_state_s *mpu;
3689
3690         uint8 interface[48];     /*0x4800 2000*/
3691         uint8 padconfs[576];     /*0x4800 2030*/
3692         uint32 general[228];     /*0x4800 2270*/
3693         uint8 mem_wkup[1024];    /*0x4800 2600*/
3694         uint8 padconfs_wkup[84]; /*0x4800 2a00*/
3695         uint32 general_wkup[8];  /*0x4800 2a60*/
3696 };
3697
3698 static void omap3_scm_save_state(QEMUFile *f, void *opaque)
3699 {
3700     struct omap3_scm_s *s = (struct omap3_scm_s *)opaque;
3701     int i;
3702
3703     qemu_put_buffer(f, s->interface, sizeof(s->interface));
3704     qemu_put_buffer(f, s->padconfs, sizeof(s->padconfs));
3705     for (i = 0; i < sizeof(s->general)/sizeof(uint32); i++)
3706         qemu_put_be32(f, s->general[i]);
3707     qemu_put_buffer(f, s->mem_wkup, sizeof(s->mem_wkup));
3708     qemu_put_buffer(f, s->padconfs_wkup, sizeof(s->padconfs_wkup));
3709     for (i = 0; i < sizeof(s->general_wkup)/sizeof(uint32); i++)
3710         qemu_put_be32(f, s->general_wkup[i]);
3711 }
3712
3713 static int omap3_scm_load_state(QEMUFile *f, void *opaque, int version_id)
3714 {
3715     struct omap3_scm_s *s = (struct omap3_scm_s *)opaque;
3716     int i;
3717
3718     if (version_id)
3719         return -EINVAL;
3720
3721     qemu_get_buffer(f, s->interface, sizeof(s->interface));
3722     qemu_get_buffer(f, s->padconfs, sizeof(s->padconfs));
3723     for (i = 0; i < sizeof(s->general)/sizeof(uint32); i++)
3724         s->general[i] = qemu_get_be32(f);
3725     qemu_get_buffer(f, s->mem_wkup, sizeof(s->mem_wkup));
3726     qemu_get_buffer(f, s->padconfs_wkup, sizeof(s->padconfs_wkup));
3727     for (i = 0; i < sizeof(s->general_wkup)/sizeof(uint32); i++)
3728         s->general_wkup[i] = qemu_get_be32(f);
3729
3730     return 0;
3731 }
3732
3733 #define PADCONFS_VALUE(wakeup0,wakeup1,offmode0,offmode1, \
3734                                                 inputenable0,inputenable1,pupd0,pupd1,muxmode0,muxmode1,offset) \
3735         do { \
3736                  *(padconfs+offset/4) = (wakeup0 <<14)|(offmode0<<9)|(inputenable0<<8)|(pupd0<<3)|(muxmode0); \
3737                  *(padconfs+offset/4) |= (wakeup1 <<30)|(offmode1<<25)|(inputenable1<<24)|(pupd1<<19)|(muxmode1<<16); \
3738 } while (0)
3739
3740
3741 static void omap3_scm_reset(struct omap3_scm_s *s)
3742 {
3743     uint32 * padconfs;
3744     padconfs = (uint32 *)(s->padconfs);
3745     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x0);
3746     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
3747     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x8);
3748     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
3749     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
3750     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
3751     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x18);
3752     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x1c);
3753     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x20);
3754     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x24);
3755     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x28);
3756     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x2c);
3757     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x30);
3758     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x34);
3759     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x38);
3760     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x3c);
3761     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x40);
3762     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x44);
3763     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,7,0x48);
3764     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x4c);
3765     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x50);
3766     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x54);
3767     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x58);
3768     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,0,0x5c);
3769     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x60);
3770     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x64);
3771     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x68);
3772     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x6c);
3773     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x70);
3774     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x74);
3775     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x78);
3776     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x7c);
3777     PADCONFS_VALUE(0,0,0,0,1,1,0,3,0,7,0x80);
3778     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x84);
3779     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x88);
3780     PADCONFS_VALUE(0,0,0,0,1,1,3,0,7,0,0x8c);
3781     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x90);
3782     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x94);
3783     PADCONFS_VALUE(0,0,0,0,1,1,1,0,7,0,0x98);
3784     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,7,0x9c);
3785     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa0);
3786     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa4);
3787     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0xa8);
3788     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xac);
3789     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb0);
3790     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb4);
3791     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb8);
3792     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xbc);
3793     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc0);
3794     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc4);
3795     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc8);
3796     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xcc);
3797     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd0);
3798     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd4);
3799     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd8);
3800     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xdc);
3801     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe0);
3802     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe4);
3803     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe8);
3804     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xec);
3805     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf0);
3806     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf4);
3807     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf8);
3808     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xfc);
3809     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x100);
3810     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x104);
3811     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x108);
3812     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x10c);
3813     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x110);
3814     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x114);
3815     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x118);
3816     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x11c);
3817     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x120);
3818     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x124);
3819     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x128);
3820     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x12c);
3821     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x130);
3822     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x134);
3823     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x138);
3824     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x13c);
3825     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x140);
3826     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x144);
3827     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x148);
3828     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x14c);
3829     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x150);
3830     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x154);
3831     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x158);
3832     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x15c);
3833     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x160);
3834     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x164);
3835     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x168);
3836     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x16c);
3837     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x170);
3838     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x174);
3839     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x178);
3840     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x17c);
3841     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x180);
3842     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x184);
3843     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x188);
3844     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x18c);
3845     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x190);
3846     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x194);
3847     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x198);
3848     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x19c);
3849     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x1a0);
3850     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1a4);
3851     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x1a8);
3852     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1ac);
3853     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1b0);
3854     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b4);
3855     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b8);
3856     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1bc);
3857     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c0);
3858     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c4);
3859     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c8);
3860     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1cc);
3861     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d0);
3862     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d4);
3863     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d8);
3864     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1dc);
3865     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e0);
3866     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e4);
3867     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e8);
3868     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1ec);
3869     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f0);
3870     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f4);
3871     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f8);
3872     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1fc);
3873     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x200);
3874     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x204);
3875     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x208);
3876     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x20c);
3877     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x210);
3878     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x214);
3879     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x218);
3880     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x21c);
3881     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x220);
3882     PADCONFS_VALUE(0,0,0,0,1,1,3,1,0,0,0x224);
3883     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x228);
3884     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x22c);
3885     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x230);
3886     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x234);
3887
3888         padconfs = (uint32 *)(s->general);
3889     memset(s->general, 0, sizeof(s->general));
3890         s->general[0x01] = 0x4000000;  /* CONTROL_DEVCONF_0 */
3891         s->general[0x1c] = 0x1;        /* 0x480022e0?? */
3892     s->general[0x20] = 0x30f;      /* CONTROL_STATUS:
3893                                     * - device type  = GP Device
3894                                     * - sys_boot:6   = oscillator bypass mode
3895                                     * - sys_boot:0-5 = NAND, USB, UART3, MMC1*/
3896         s->general[0x75] = 0x7fc0;     /* CONTROL_PROG_IO0 */
3897         s->general[0x76] = 0xaa;       /* CONTROL_PROG_IO1 */
3898         s->general[0x7c] = 0x2700;     /* CONTROL_SDRC_SHARING */
3899         s->general[0x7d] = 0x300000;   /* CONTROL_SDRC_MCFG0 */
3900         s->general[0x7e] = 0x300000;   /* CONTROL_SDRC_MCFG1 */
3901         s->general[0x81] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_REQ_INFO */
3902         s->general[0x82] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_RD */
3903         s->general[0x83] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_WR */
3904         s->general[0x84] = 0x6;        /* CONTROL_MODEM_GPMC_BOOT_CODE */
3905         s->general[0x85] = 0xffffffff; /* CONTROL_MODEM_SMS_RG_ATT1 */
3906         s->general[0x86] = 0xffff;     /* CONTROL_MODEM_SMS_RG_RDPERM1 */
3907         s->general[0x87] = 0xffff;     /* CONTROL_MODEM_SMS_RG_WRPERM1 */
3908         s->general[0x88] = 0x1;        /* CONTROL_MODEM_D2D_FW_DEBUG_MODE */
3909         s->general[0x8b] = 0xffffffff; /* CONTROL_DPF_OCM_RAM_FW_REQINFO */
3910         s->general[0x8c] = 0xffff;     /* CONTROL_DPF_OCM_RAM_FW_WR */
3911         s->general[0x8e] = 0xffff;     /* CONTROL_DPF_REGION4_GPMC_FW_REQINFO */
3912         s->general[0x8f] = 0xffff;     /* CONTROL_DPF_REGION4_GPMC_FW_WR */
3913         s->general[0x91] = 0xffff;     /* CONTROL_DPF_REGION1_IVA2_FW_REQINFO */
3914         s->general[0x92] = 0xffff;     /* CONTROL_DPF_REGION1_IVA2_FW_WR */
3915         s->general[0xac] = 0x109;      /* CONTROL_PBIAS_LITE */
3916         s->general[0xb2] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_ADDR_MATCH */
3917         s->general[0xb3] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_REQINFO */
3918         s->general[0xb4] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_WR */
3919         PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x368); /* PADCONF_ETK_CLK */
3920     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x36c); /* PADCONF_ETK_D0 */
3921     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x370); /* PADCONF_ETK_D2 */
3922     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x374); /* PADCONF_ETK_D4 */
3923     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x378); /* PADCONF_ETK_D6 */
3924     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x37c); /* PADCONF_ETK_D8 */
3925     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x380); /* PADCONF_ETK_D10 */
3926     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x384); /* PADCONF_ETK_D12 */
3927     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x388); /* PADCONF_ETK_D14 */
3928
3929         padconfs = (uint32 *)(s->padconfs_wkup);
3930         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x0);
3931         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
3932         PADCONFS_VALUE(0,0,0,0,1,1,3,0,0,0,0x8);
3933         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
3934         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
3935         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
3936         PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x18);
3937         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c);
3938         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x20);
3939         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x24);
3940         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x2c);
3941
3942         s->general_wkup[0] = 0x66ff; /* 0x48002A60?? */
3943 }
3944
3945 static uint32_t omap3_scm_read8(void *opaque, target_phys_addr_t addr)
3946 {
3947     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3948     uint8_t* temp;
3949
3950     switch (addr) {
3951         case 0x000 ... 0x02f: return s->interface[addr];
3952         case 0x030 ... 0x26f: return s->padconfs[addr - 0x30];
3953         case 0x270 ... 0x5ff: temp = (uint8_t *)s->general; return temp[addr - 0x270];
3954         case 0x600 ... 0x9ff: return s->mem_wkup[addr - 0x600];
3955         case 0xa00 ... 0xa5f: return s->padconfs_wkup[addr - 0xa00];
3956         case 0xa60 ... 0xa7f: temp = (uint8_t *)s->general_wkup; return temp[addr - 0xa60];
3957         default: break;
3958     }
3959     OMAP_BAD_REG(addr);
3960     return 0;
3961 }
3962
3963 static uint32_t omap3_scm_read16(void *opaque, target_phys_addr_t addr)
3964 {
3965     uint32_t v;
3966     v = omap3_scm_read8(opaque, addr);
3967     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3968     return v;
3969 }
3970
3971 static uint32_t omap3_scm_read32(void *opaque, target_phys_addr_t addr)
3972 {
3973     uint32_t v;
3974     v = omap3_scm_read8(opaque, addr);
3975     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3976     v |= omap3_scm_read8(opaque, addr + 2) << 16;
3977     v |= omap3_scm_read8(opaque, addr + 3) << 24;
3978     return v;
3979 }
3980
3981 static void omap3_scm_write8(void *opaque, target_phys_addr_t addr,
3982                              uint32_t value)
3983 {
3984     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3985     uint8_t* temp;
3986
3987     switch (addr) {
3988         case 0x000 ... 0x02f: s->interface[addr] = value; break;
3989         case 0x030 ... 0x26f: s->padconfs[addr-0x30] = value; break;
3990         case 0x270 ... 0x5ff: temp = (uint8_t *)s->general; temp[addr-0x270] = value; break;
3991         case 0x600 ... 0x9ff: s->mem_wkup[addr-0x600] = value; break;
3992         case 0xa00 ... 0xa5f: s->padconfs_wkup[addr-0xa00] = value; break;
3993         case 0xa60 ... 0xa7f: temp = (uint8_t *)s->general_wkup; temp[addr-0xa60] = value; break;
3994         default: OMAP_BAD_REGV(addr, value); break;
3995     }
3996 }
3997
3998 static void omap3_scm_write16(void *opaque, target_phys_addr_t addr,
3999                               uint32_t value)
4000 {
4001     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
4002     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
4003 }
4004
4005 static void omap3_scm_write32(void *opaque, target_phys_addr_t addr,
4006                               uint32_t value)
4007 {
4008     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
4009     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
4010     omap3_scm_write8(opaque, addr + 2, (value >> 16) & 0xff);
4011     omap3_scm_write8(opaque, addr + 3, (value >> 24) & 0xff);
4012 }
4013
4014 static CPUReadMemoryFunc *omap3_scm_readfn[] = {
4015     omap3_scm_read8,
4016     omap3_scm_read16,
4017     omap3_scm_read32,
4018 };
4019
4020 static CPUWriteMemoryFunc *omap3_scm_writefn[] = {
4021     omap3_scm_write8,
4022     omap3_scm_write16,
4023     omap3_scm_write32,
4024 };
4025
4026 static struct omap3_scm_s *omap3_scm_init(struct omap_target_agent_s *ta,
4027                                           struct omap_mpu_state_s *mpu)
4028 {
4029     int iomemtype;
4030     struct omap3_scm_s *s = (struct omap3_scm_s *) qemu_mallocz(sizeof(*s));
4031
4032     s->mpu = mpu;
4033
4034     omap3_scm_reset(s);
4035
4036     iomemtype = l4_register_io_memory(0, omap3_scm_readfn,
4037                                       omap3_scm_writefn, s);
4038     omap_l4_attach(ta, 0, iomemtype);
4039
4040     register_savevm("omap3_scm", -1, 0,
4041                     omap3_scm_save_state, omap3_scm_load_state, s);
4042     return s;
4043 }
4044
4045 /*dummy SDRAM Memory Scheduler emulation*/
4046 struct omap3_sms_s
4047 {
4048     struct omap_mpu_state_s *mpu;
4049
4050     uint32 sms_sysconfig;
4051     uint32 sms_sysstatus;
4052     uint32 sms_rg_att[8];
4053     uint32 sms_rg_rdperm[8];
4054     uint32 sms_rg_wrperm[8];
4055     uint32 sms_rg_start[7];
4056     uint32 sms_rg_end[7];
4057     uint32 sms_security_control;
4058     uint32 sms_class_arbiter0;
4059     uint32 sms_class_arbiter1;
4060     uint32 sms_class_arbiter2;
4061     uint32 sms_interclass_arbiter;
4062     uint32 sms_class_rotation[3];
4063     uint32 sms_err_addr;
4064     uint32 sms_err_type;
4065     uint32 sms_pow_ctrl;
4066     uint32 sms_rot_control[12];
4067     uint32 sms_rot_size[12];
4068     uint32 sms_rot_physical_ba[12];
4069 };
4070
4071 static void omap3_sms_save_state(QEMUFile *f, void *opaque)
4072 {
4073     struct omap3_sms_s *s = (struct omap3_sms_s *)opaque;
4074     int i;
4075
4076     qemu_put_be32(f, s->sms_sysconfig);
4077     qemu_put_be32(f, s->sms_sysstatus);
4078     for (i = 0; i < 8; i++) {
4079         qemu_put_be32(f, s->sms_rg_att[i]);
4080         qemu_put_be32(f, s->sms_rg_rdperm[i]);
4081         qemu_put_be32(f, s->sms_rg_wrperm[i]);
4082         if (i < 7) {
4083             qemu_put_be32(f, s->sms_rg_start[i]);
4084             qemu_put_be32(f, s->sms_rg_end[i]);
4085         }
4086     }
4087     qemu_put_be32(f, s->sms_security_control);
4088     qemu_put_be32(f, s->sms_class_arbiter0);
4089     qemu_put_be32(f, s->sms_class_arbiter1);
4090     qemu_put_be32(f, s->sms_class_arbiter2);
4091     qemu_put_be32(f, s->sms_interclass_arbiter);
4092     qemu_put_be32(f, s->sms_class_rotation[0]);
4093     qemu_put_be32(f, s->sms_class_rotation[1]);
4094     qemu_put_be32(f, s->sms_class_rotation[2]);
4095     qemu_put_be32(f, s->sms_err_addr);
4096     qemu_put_be32(f, s->sms_err_type);
4097     qemu_put_be32(f, s->sms_pow_ctrl);
4098     for (i = 0; i< 12; i++) {
4099         qemu_put_be32(f, s->sms_rot_control[i]);
4100         qemu_put_be32(f, s->sms_rot_size[i]);
4101         qemu_put_be32(f, s->sms_rot_physical_ba[i]);
4102     }
4103 }
4104
4105 static int omap3_sms_load_state(QEMUFile *f, void *opaque, int version_id)
4106 {
4107     struct omap3_sms_s *s = (struct omap3_sms_s *)opaque;
4108     int i;
4109
4110     if (version_id)
4111         return -EINVAL;
4112
4113     s->sms_sysconfig = qemu_get_be32(f);
4114     s->sms_sysstatus = qemu_get_be32(f);
4115     for (i = 0; i < 8; i++) {
4116         s->sms_rg_att[i] = qemu_get_be32(f);
4117         s->sms_rg_rdperm[i] = qemu_get_be32(f);
4118         s->sms_rg_wrperm[i] = qemu_get_be32(f);
4119         if (i < 7) {
4120             s->sms_rg_start[i] = qemu_get_be32(f);
4121             s->sms_rg_end[i] = qemu_get_be32(f);
4122         }
4123     }
4124     s->sms_security_control = qemu_get_be32(f);
4125     s->sms_class_arbiter0 = qemu_get_be32(f);
4126     s->sms_class_arbiter1 = qemu_get_be32(f);
4127     s->sms_class_arbiter2 = qemu_get_be32(f);
4128     s->sms_interclass_arbiter = qemu_get_be32(f);
4129     s->sms_class_rotation[0] = qemu_get_be32(f);
4130     s->sms_class_rotation[1] = qemu_get_be32(f);
4131     s->sms_class_rotation[2] = qemu_get_be32(f);
4132     s->sms_err_addr = qemu_get_be32(f);
4133     s->sms_err_type = qemu_get_be32(f);
4134     s->sms_pow_ctrl = qemu_get_be32(f);
4135     for (i = 0; i< 12; i++) {
4136         s->sms_rot_control[i] = qemu_get_be32(f);
4137         s->sms_rot_size[i] = qemu_get_be32(f);
4138         s->sms_rot_physical_ba[i] = qemu_get_be32(f);
4139     }
4140
4141     return 0;
4142 }
4143
4144 static uint32_t omap3_sms_read32(void *opaque, target_phys_addr_t addr)
4145 {
4146     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
4147
4148     switch (addr)
4149     {
4150     case 0x10:
4151         return s->sms_sysconfig;
4152     case 0x14:
4153         return s->sms_sysstatus;
4154     case 0x48:
4155     case 0x68:
4156     case 0x88:
4157     case 0xa8:
4158     case 0xc8:
4159     case 0xe8:
4160     case 0x108:
4161     case 0x128:
4162         return s->sms_rg_att[(addr-0x48)/0x20];
4163     case 0x50:
4164     case 0x70:
4165     case 0x90:
4166     case 0xb0:
4167     case 0xd0:
4168     case 0xf0:
4169     case 0x110:
4170     case 0x130:
4171         return s->sms_rg_rdperm[(addr-0x50)/0x20];
4172     case 0x58:
4173     case 0x78:
4174     case 0x98:
4175     case 0xb8:
4176     case 0xd8:
4177     case 0xf8:
4178     case 0x118:
4179         return s->sms_rg_wrperm[(addr-0x58)/0x20];
4180     case 0x60:
4181     case 0x80:
4182     case 0xa0:
4183     case 0xc0:
4184     case 0xe0:
4185     case 0x100:
4186     case 0x120:
4187         return s->sms_rg_start[(addr-0x60)/0x20];
4188
4189     case 0x64:
4190     case 0x84:
4191     case 0xa4:
4192     case 0xc4:
4193     case 0xe4:
4194     case 0x104:
4195     case 0x124:
4196         return s->sms_rg_end[(addr-0x64)/0x20];
4197     case 0x140:
4198         return s->sms_security_control;
4199     case 0x150:
4200         return s->sms_class_arbiter0;
4201         case 0x154:
4202                 return s->sms_class_arbiter1;
4203         case 0x158:
4204                 return s->sms_class_arbiter2;
4205         case 0x160:
4206                 return s->sms_interclass_arbiter;
4207         case 0x164:
4208         case 0x168:
4209         case 0x16c:
4210                 return s->sms_class_rotation[(addr-0x164)/4];
4211         case 0x170:
4212                 return s->sms_err_addr;
4213         case 0x174:
4214                 return s->sms_err_type;
4215         case 0x178:
4216                 return s->sms_pow_ctrl;
4217         case 0x180:
4218         case 0x190:
4219         case 0x1a0:
4220         case 0x1b0:
4221         case 0x1c0:
4222         case 0x1d0:
4223         case 0x1e0:
4224         case 0x1f0:
4225         case 0x200:
4226         case 0x210:
4227         case 0x220:
4228         case 0x230:
4229                 return s->sms_rot_control[(addr-0x180)/0x10];
4230         case 0x184:
4231         case 0x194:
4232         case 0x1a4:
4233         case 0x1b4:
4234         case 0x1c4:
4235         case 0x1d4:
4236         case 0x1e4:
4237         case 0x1f4:
4238         case 0x204:
4239         case 0x214:
4240         case 0x224:
4241         case 0x234:
4242                 return s->sms_rot_size[(addr-0x184)/0x10];
4243
4244         case 0x188:
4245         case 0x198:
4246         case 0x1a8:
4247         case 0x1b8:
4248         case 0x1c8:
4249         case 0x1d8:
4250         case 0x1e8:
4251         case 0x1f8:
4252         case 0x208:
4253         case 0x218:
4254         case 0x228:
4255         case 0x238:
4256                 return s->sms_rot_size[(addr-0x188)/0x10];
4257
4258     default:
4259         break;
4260     }
4261     OMAP_BAD_REG(addr);
4262     return 0;
4263 }
4264
4265 static void omap3_sms_write32(void *opaque, target_phys_addr_t addr,
4266                               uint32_t value)
4267 {
4268     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
4269     //int i;
4270
4271     switch (addr)
4272     {
4273     case 0x14:
4274         OMAP_RO_REG(addr);
4275         return;
4276     case 0x10:
4277         s->sms_sysconfig = value & 0x1f;
4278         break;
4279
4280     case 0x48:
4281     case 0x68:
4282     case 0x88:
4283     case 0xa8:
4284     case 0xc8:
4285     case 0xe8:
4286     case 0x108:
4287     case 0x128:
4288         s->sms_rg_att[(addr-0x48)/0x20] = value;
4289         break;
4290     case 0x50:
4291     case 0x70:
4292     case 0x90:
4293     case 0xb0:
4294     case 0xd0:
4295     case 0xf0:
4296     case 0x110:
4297     case 0x130:
4298         s->sms_rg_rdperm[(addr-0x50)/0x20] = value&0xffff;
4299         break;
4300     case 0x58:
4301     case 0x78:
4302     case 0x98:
4303     case 0xb8:
4304     case 0xd8:
4305     case 0xf8:
4306     case 0x118:
4307         s->sms_rg_wrperm[(addr-0x58)/0x20] = value&0xffff;
4308         break;
4309     case 0x60:
4310     case 0x80:
4311     case 0xa0:
4312     case 0xc0:
4313     case 0xe0:
4314     case 0x100:
4315     case 0x120:
4316         s->sms_rg_start[(addr-0x60)/0x20] = value;
4317         break;
4318     case 0x64:
4319     case 0x84:
4320     case 0xa4:
4321     case 0xc4:
4322     case 0xe4:
4323     case 0x104:
4324     case 0x124:
4325         s->sms_rg_end[(addr-0x64)/0x20] = value;
4326         break;
4327     case 0x140:
4328         s->sms_security_control = value &0xfffffff;
4329         break;
4330     case 0x150:
4331         s->sms_class_arbiter0 = value;
4332         break;
4333         case 0x154:
4334                 s->sms_class_arbiter1 = value;
4335                 break;
4336         case 0x158:
4337                 s->sms_class_arbiter2 = value;
4338                 break;
4339         case 0x160:
4340                 s->sms_interclass_arbiter = value;
4341                 break;
4342         case 0x164:
4343         case 0x168:
4344         case 0x16c:
4345                 s->sms_class_rotation[(addr-0x164)/4] = value;
4346                 break;
4347         case 0x170:
4348                 s->sms_err_addr = value;
4349                 break;
4350         case 0x174:
4351                 s->sms_err_type = value;
4352                 break;
4353         case 0x178:
4354                 s->sms_pow_ctrl = value;
4355                 break;
4356         case 0x180:
4357         case 0x190:
4358         case 0x1a0:
4359         case 0x1b0:
4360         case 0x1c0:
4361         case 0x1d0:
4362         case 0x1e0:
4363         case 0x1f0:
4364         case 0x200:
4365         case 0x210:
4366         case 0x220:
4367         case 0x230:
4368                 s->sms_rot_control[(addr-0x180)/0x10] = value;
4369                 break;
4370         case 0x184:
4371         case 0x194:
4372         case 0x1a4:
4373         case 0x1b4:
4374         case 0x1c4:
4375         case 0x1d4:
4376         case 0x1e4:
4377         case 0x1f4:
4378         case 0x204:
4379         case 0x214:
4380         case 0x224:
4381         case 0x234:
4382                 s->sms_rot_size[(addr-0x184)/0x10] = value;
4383                 break;
4384
4385         case 0x188:
4386         case 0x198:
4387         case 0x1a8:
4388         case 0x1b8:
4389         case 0x1c8:
4390         case 0x1d8:
4391         case 0x1e8:
4392         case 0x1f8:
4393         case 0x208:
4394         case 0x218:
4395         case 0x228:
4396         case 0x238:
4397                 s->sms_rot_size[(addr-0x188)/0x10] = value;
4398                 break;
4399         default:
4400         OMAP_BAD_REGV(addr, value);
4401         break;
4402     }
4403 }
4404
4405 static CPUReadMemoryFunc *omap3_sms_readfn[] = {
4406     omap_badwidth_read32,
4407     omap_badwidth_read32,
4408     omap3_sms_read32,
4409 };
4410
4411 static CPUWriteMemoryFunc *omap3_sms_writefn[] = {
4412     omap_badwidth_write32,
4413     omap_badwidth_write32,
4414     omap3_sms_write32,
4415 };
4416
4417 static void omap3_sms_reset(struct omap3_sms_s *s)
4418 {
4419         s->sms_sysconfig = 0x1;
4420         s->sms_class_arbiter0 = 0x500000;
4421         s->sms_class_arbiter1 = 0x500;
4422         s->sms_class_arbiter2 = 0x55000;
4423         s->sms_interclass_arbiter = 0x400040;
4424         s->sms_class_rotation[0] = 0x1;
4425         s->sms_class_rotation[1] = 0x1;
4426         s->sms_class_rotation[2] = 0x1;
4427         s->sms_pow_ctrl = 0x80;
4428 }
4429
4430 static struct omap3_sms_s *omap3_sms_init(struct omap_mpu_state_s *mpu)
4431 {
4432     int iomemtype;
4433     struct omap3_sms_s *s = (struct omap3_sms_s *) qemu_mallocz(sizeof(*s));
4434
4435     s->mpu = mpu;
4436
4437     omap3_sms_reset(s);
4438
4439     iomemtype = cpu_register_io_memory(0, omap3_sms_readfn,
4440                                        omap3_sms_writefn, s);
4441     cpu_register_physical_memory(0x6c000000, 0x10000, iomemtype);
4442
4443     register_savevm("omap3_sms", -1, 0,
4444                     omap3_sms_save_state, omap3_sms_load_state, s);
4445     return s;
4446 }
4447
4448 static const struct dma_irq_map omap3_dma_irq_map[] = {
4449     {0, OMAP_INT_3XXX_SDMA_IRQ0},
4450     {0, OMAP_INT_3XXX_SDMA_IRQ1},
4451     {0, OMAP_INT_3XXX_SDMA_IRQ2},
4452     {0, OMAP_INT_3XXX_SDMA_IRQ3},
4453 };
4454
4455 static int omap3_validate_addr(struct omap_mpu_state_s *s,
4456                                target_phys_addr_t addr)
4457 {
4458     return 1;
4459 }
4460
4461 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
4462                                            CharDriverState *chr_uart1,
4463                                            CharDriverState *chr_uart2,
4464                                            CharDriverState *chr_uart3)
4465 {
4466     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4467         qemu_mallocz(sizeof(struct omap_mpu_state_s));
4468     ram_addr_t sram_base, q2_base;
4469     qemu_irq *cpu_irq;
4470     qemu_irq drqs[4];
4471     int i;
4472
4473     s->mpu_model = omap3530;
4474     s->env = cpu_init("cortex-a8-r2");
4475     if (!s->env) {
4476         fprintf(stderr, "Unable to find CPU definition\n");
4477         exit(1);
4478     }
4479     s->sdram_size = sdram_size;
4480     s->sram_size = OMAP3XXX_SRAM_SIZE;
4481
4482     /* Clocks */
4483     omap_clk_init(s);
4484
4485     /* Memory-mapped stuff */
4486     q2_base = qemu_ram_alloc(s->sdram_size);
4487     cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,
4488                                  q2_base | IO_MEM_RAM);
4489     sram_base = qemu_ram_alloc(s->sram_size);
4490     cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,
4491                                  sram_base | IO_MEM_RAM);
4492
4493     s->l4 = omap_l4_init(OMAP3_L4_BASE,
4494                          sizeof(omap3_l4_agent_info)
4495                          / sizeof(struct omap3_l4_agent_info_s));
4496
4497     cpu_irq = arm_pic_init_cpu(s->env);
4498     s->ih[0] = omap2_inth_init(s, 0x48200000, 0x1000, 3, &s->irq[0],
4499                                cpu_irq[ARM_PIC_CPU_IRQ],
4500                                cpu_irq[ARM_PIC_CPU_FIQ],
4501                                omap_findclk(s, "omap3_mpu_intc_fclk"),
4502                                omap_findclk(s, "omap3_mpu_intc_iclk"));
4503
4504     for (i = 0; i < 4; i++)
4505         drqs[i] = s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];
4506     s->dma = omap3_dma4_init(omap3_l4ta_init(s->l4, L4A_SDMA), s, drqs, 32,
4507                              omap_findclk(s, "omap3_sdma_fclk"),
4508                              omap_findclk(s, "omap3_sdma_iclk"));
4509     s->port->addr_valid = omap3_validate_addr;
4510     soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
4511     soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
4512
4513
4514     s->omap3_cm = omap3_cm_init(omap3_l4ta_init(s->l4, L4A_CM), NULL, NULL, NULL, s);
4515
4516     s->omap3_prm = omap3_prm_init(omap3_l4ta_init(s->l4, L4A_PRM),
4517                                   s->irq[0][OMAP_INT_3XXX_PRCM_MPU_IRQ],
4518                                   NULL, s);
4519
4520     s->omap3_mpu_wdt = omap3_mpu_wdt_init(omap3_l4ta_init(s->l4, L4A_WDTIMER2),
4521                                           NULL,
4522                                           omap_findclk(s, "omap3_wkup_32k_fclk"),
4523                                           omap_findclk(s, "omap3_wkup_l4_iclk"),
4524                                           s);
4525
4526     s->omap3_l3 = omap3_l3_init(OMAP3_L3_BASE,
4527                                 omap3_l3_region,
4528                                 sizeof(omap3_l3_region)
4529                                 / sizeof(struct omap_l3_region_s));
4530     s->omap3_scm = omap3_scm_init(omap3_l4ta_init(s->l4, L4A_SCM), s);
4531
4532     s->omap3_sms = omap3_sms_init(s);
4533
4534     s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER1),
4535                                        s->irq[0][OMAP_INT_3XXX_GPT1_IRQ],
4536                                        omap_findclk(s, "omap3_gp1_fclk"),
4537                                        omap_findclk(s, "omap3_wkup_l4_iclk"));
4538     s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER2),
4539                                        s->irq[0][OMAP_INT_3XXX_GPT2_IRQ],
4540                                        omap_findclk(s, "omap3_gp2_fclk"),
4541                                        omap_findclk(s, "omap3_per_l4_iclk"));
4542     s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER3),
4543                                        s->irq[0][OMAP_INT_3XXX_GPT3_IRQ],
4544                                        omap_findclk(s, "omap3_gp3_fclk"),
4545                                        omap_findclk(s, "omap3_per_l4_iclk"));
4546     s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER4),
4547                                        s->irq[0][OMAP_INT_3XXX_GPT4_IRQ],
4548                                        omap_findclk(s, "omap3_gp4_fclk"),
4549                                        omap_findclk(s, "omap3_per_l4_iclk"));
4550     s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER5),
4551                                        s->irq[0][OMAP_INT_3XXX_GPT5_IRQ],
4552                                        omap_findclk(s, "omap3_gp5_fclk"),
4553                                        omap_findclk(s, "omap3_per_l4_iclk"));
4554     s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER6),
4555                                        s->irq[0][OMAP_INT_3XXX_GPT6_IRQ],
4556                                        omap_findclk(s, "omap3_gp6_fclk"),
4557                                        omap_findclk(s, "omap3_per_l4_iclk"));
4558     s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER7),
4559                                        s->irq[0][OMAP_INT_3XXX_GPT7_IRQ],
4560                                        omap_findclk(s, "omap3_gp7_fclk"),
4561                                        omap_findclk(s, "omap3_per_l4_iclk"));
4562     s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER8),
4563                                        s->irq[0][OMAP_INT_3XXX_GPT8_IRQ],
4564                                        omap_findclk(s, "omap3_gp8_fclk"),
4565                                        omap_findclk(s, "omap3_per_l4_iclk"));
4566     s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER9),
4567                                        s->irq[0][OMAP_INT_3XXX_GPT9_IRQ],
4568                                        omap_findclk(s, "omap3_gp9_fclk"),
4569                                        omap_findclk(s, "omap3_per_l4_iclk"));
4570     s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER10),
4571                                        s->irq[0][OMAP_INT_3XXX_GPT10_IRQ],
4572                                        omap_findclk(s, "omap3_gp10_fclk"),
4573                                        omap_findclk(s, "omap3_core_l4_iclk"));
4574     s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER11),
4575                                        s->irq[0][OMAP_INT_3XXX_GPT11_IRQ],
4576                                        omap_findclk(s, "omap3_gp12_fclk"),
4577                                        omap_findclk(s, "omap3_core_l4_iclk"));
4578     s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER12),
4579                                         s->irq[0][OMAP_INT_3XXX_GPT12_IRQ],
4580                                         omap_findclk(s, "omap3_gp12_fclk"),
4581                                         omap_findclk(s, "omap3_wkup_l4_iclk"));
4582
4583
4584     omap_synctimer_init(omap3_l4ta_init(s->l4, L4A_32KTIMER), s,
4585                         omap_findclk(s, "omap3_sys_32k"), NULL);
4586
4587     s->sdrc = omap_sdrc_init(0x6d000000);
4588
4589     s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_3XXX_GPMC_IRQ]);
4590
4591
4592     s->uart[0] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART1),
4593                                  s->irq[0][OMAP_INT_3XXX_UART1_IRQ],
4594                                  omap_findclk(s, "omap3_uart1_fclk"),
4595                                  omap_findclk(s, "omap3_uart1_iclk"),
4596                                  s->drq[OMAP3XXX_DMA_UART1_TX],
4597                                  s->drq[OMAP3XXX_DMA_UART1_RX],
4598                                  chr_uart1);
4599     s->uart[1] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART2),
4600                                  s->irq[0][OMAP_INT_3XXX_UART2_IRQ],
4601                                  omap_findclk(s, "omap3_uart2_fclk"),
4602                                  omap_findclk(s, "omap3_uart2_iclk"),
4603                                  s->drq[OMAP3XXX_DMA_UART2_TX],
4604                                  s->drq[OMAP3XXX_DMA_UART2_RX],
4605                                  chr_uart2);
4606     s->uart[2] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART3),
4607                                  s->irq[0][OMAP_INT_3XXX_UART3_IRQ],
4608                                  omap_findclk(s, "omap3_uart2_fclk"),
4609                                  omap_findclk(s, "omap3_uart3_iclk"),
4610                                  s->drq[OMAP3XXX_DMA_UART3_TX],
4611                                  s->drq[OMAP3XXX_DMA_UART3_RX],
4612                                  chr_uart3);
4613
4614     s->dss = omap_dss_init(s, omap3_l4ta_init(s->l4, L4A_DSS),
4615                     s->irq[0][OMAP_INT_3XXX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
4616                    NULL,NULL,NULL,NULL,NULL);
4617
4618     s->gpif = omap3_gpif_init();
4619     omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO1),
4620                     s->irq[0][OMAP_INT_3XXX_GPIO1_MPU_IRQ],
4621                     NULL,NULL,0);
4622     omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO2),
4623                     s->irq[0][OMAP_INT_3XXX_GPIO2_MPU_IRQ],
4624                     NULL,NULL,1);
4625     omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO3),
4626                     s->irq[0][OMAP_INT_3XXX_GPIO3_MPU_IRQ],
4627                     NULL,NULL,2);
4628     omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO4),
4629                     s->irq[0][OMAP_INT_3XXX_GPIO4_MPU_IRQ],
4630                     NULL,NULL,3);
4631     omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO5),
4632                     s->irq[0][OMAP_INT_3XXX_GPIO5_MPU_IRQ],
4633                     NULL,NULL,4);
4634     omap3_gpio_init(s, s->gpif, omap3_l4ta_init(s->l4, L4A_GPIO6),
4635                     s->irq[0][OMAP_INT_3XXX_GPIO6_MPU_IRQ],
4636                     NULL,NULL,5);
4637
4638     omap_tap_init(omap3_l4ta_init(s->l4, L4A_TAP), s);
4639
4640     s->omap3_mmc[0] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC1),
4641                                      s->irq[0][OMAP_INT_3XXX_MMC1_IRQ],
4642                                      &s->drq[OMAP3XXX_DMA_MMC1_TX],
4643                                      omap_findclk(s, "omap3_mmc1_fclk"),
4644                                      omap_findclk(s, "omap3_mmc1_iclk"));
4645
4646     s->omap3_mmc[1] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC2),
4647                                      s->irq[0][OMAP_INT_3XXX_MMC2_IRQ],
4648                                      &s->drq[OMAP3XXX_DMA_MMC2_TX],
4649                                      omap_findclk(s, "omap3_mmc2_fclk"),
4650                                      omap_findclk(s, "omap3_mmc2_iclk"));
4651
4652     s->omap3_mmc[2] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC3),
4653                                      s->irq[0][OMAP_INT_3XXX_MMC3_IRQ],
4654                                      &s->drq[OMAP3XXX_DMA_MMC3_TX],
4655                                      omap_findclk(s, "omap3_mmc3_fclk"),
4656                                      omap_findclk(s, "omap3_mmc3_iclk"));
4657
4658     s->i2c[0] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C1),
4659                                s->irq[0][OMAP_INT_3XXX_I2C1_IRQ],
4660                                &s->drq[OMAP3XXX_DMA_I2C1_TX],
4661                                omap_findclk(s, "omap3_i2c1_fclk"),
4662                                omap_findclk(s, "omap3_i2c1_iclk"),
4663                                8);
4664     s->i2c[1] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C2),
4665                                s->irq[0][OMAP_INT_3XXX_I2C2_IRQ],
4666                                &s->drq[OMAP3XXX_DMA_I2C2_TX],
4667                                omap_findclk(s, "omap3_i2c2_fclk"),
4668                                omap_findclk(s, "omap3_i2c2_iclk"),
4669                                8);
4670     s->i2c[2] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C3),
4671                                s->irq[0][OMAP_INT_3XXX_I2C3_IRQ],
4672                                &s->drq[OMAP3XXX_DMA_I2C3_TX],
4673                                omap_findclk(s, "omap3_i2c3_fclk"),
4674                                omap_findclk(s, "omap3_i2c3_iclk"),
4675                                64);
4676
4677     s->omap3_usb = omap3_hsusb_init(omap3_l4ta_init(s->l4, L4A_USBHS_OTG),
4678                                     omap3_l4ta_init(s->l4, L4A_USBHS_HOST),
4679                                     omap3_l4ta_init(s->l4, L4A_USBHS_TLL),
4680                                     s->irq[0][OMAP_INT_3XXX_HSUSB_MC],
4681                                     s->irq[0][OMAP_INT_3XXX_HSUSB_DMA],
4682                                     s->irq[0][OMAP_INT_3XXX_OHCI_IRQ],
4683                                     s->irq[0][OMAP_INT_3XXX_EHCI_IRQ],
4684                                     s->irq[0][OMAP_INT_3XXX_TLL_IRQ]);
4685
4686     s->mcspi[0] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI1), s, 4,
4687                                   s->irq[0][OMAP_INT_3XXX_MCSPI1_IRQ],
4688                                   &s->drq[OMAP3XXX_DMA_SPI1_TX0],
4689                                   omap_findclk(s, "omap3_spi1_fclk"),
4690                                   omap_findclk(s, "omap3_spi1_iclk"));
4691     s->mcspi[1] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI2), s, 2,
4692                                   s->irq[0][OMAP_INT_3XXX_MCSPI2_IRQ],
4693                                   &s->drq[OMAP3XXX_DMA_SPI2_TX0],
4694                                   omap_findclk(s, "omap3_spi2_fclk"),
4695                                   omap_findclk(s, "omap3_spi2_iclk"));
4696     drqs[0] = s->drq[OMAP3XXX_DMA_SPI3_TX0];
4697     drqs[1] = s->drq[OMAP3XXX_DMA_SPI3_RX0];
4698     drqs[2] = s->drq[OMAP3XXX_DMA_SPI3_TX1];
4699     drqs[3] = s->drq[OMAP3XXX_DMA_SPI3_RX1];
4700     s->mcspi[2] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI3), s, 2,
4701                                   s->irq[0][OMAP_INT_3XXX_MCSPI3_IRQ],
4702                                   drqs,
4703                                   omap_findclk(s, "omap3_spi3_fclk"),
4704                                   omap_findclk(s, "omap3_spi3_iclk"));
4705     s->mcspi[3] = omap_mcspi_init(omap3_l4ta_init(s->l4, L4A_MCSPI4), s, 1,
4706                                   s->irq[0][OMAP_INT_3XXX_MCSPI4_IRQ],
4707                                   &s->drq[OMAP3XXX_DMA_SPI4_TX0],
4708                                   omap_findclk(s, "omap3_spi4_fclk"),
4709                                   omap_findclk(s, "omap3_spi4_iclk"));
4710
4711     return s;
4712 }