4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34 pci_set_irq_fn set_irq;
35 pci_map_irq_fn map_irq;
36 uint32_t config_reg; /* XXX: suppress */
38 SetIRQFunc *low_set_irq;
40 PCIDevice *devices[256];
41 PCIDevice *parent_dev;
43 /* The bus IRQ state is the logical OR of the connected devices.
44 Keep a count of the number of devices with raised IRQs. */
48 static void pci_update_mappings(PCIDevice *d);
49 static void pci_set_irq(void *opaque, int irq_num, int level);
51 target_phys_addr_t pci_mem_base;
52 static int pci_irq_index;
53 static PCIBus *first_bus;
55 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
56 qemu_irq *pic, int devfn_min, int nirq)
59 bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
60 bus->set_irq = set_irq;
61 bus->map_irq = map_irq;
62 bus->irq_opaque = pic;
63 bus->devfn_min = devfn_min;
68 PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
71 bus = qemu_mallocz(sizeof(PCIBus));
72 bus->map_irq = map_irq;
73 bus->parent_dev = dev;
74 bus->next = dev->bus->next;
79 int pci_bus_num(PCIBus *s)
84 void pci_device_save(PCIDevice *s, QEMUFile *f)
86 qemu_put_be32(f, 1); /* PCI device version */
87 qemu_put_buffer(f, s->config, 256);
90 int pci_device_load(PCIDevice *s, QEMUFile *f)
93 version_id = qemu_get_be32(f);
96 qemu_get_buffer(f, s->config, 256);
97 pci_update_mappings(s);
101 /* -1 for devfn means auto assign */
102 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
103 int instance_size, int devfn,
104 PCIConfigReadFunc *config_read,
105 PCIConfigWriteFunc *config_write)
109 if (pci_irq_index >= PCI_DEVICES_MAX)
113 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
114 if (!bus->devices[devfn])
120 pci_dev = qemu_mallocz(instance_size);
124 pci_dev->devfn = devfn;
125 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
126 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
129 config_read = pci_default_read_config;
131 config_write = pci_default_write_config;
132 pci_dev->config_read = config_read;
133 pci_dev->config_write = config_write;
134 pci_dev->irq_index = pci_irq_index++;
135 bus->devices[devfn] = pci_dev;
136 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
140 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
141 uint32_t size, int type,
142 PCIMapIORegionFunc *map_func)
147 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
149 r = &pci_dev->io_regions[region_num];
153 r->map_func = map_func;
154 if (region_num == PCI_ROM_SLOT) {
157 addr = 0x10 + region_num * 4;
159 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
162 target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
164 return addr + pci_mem_base;
167 static void pci_update_mappings(PCIDevice *d)
171 uint32_t last_addr, new_addr, config_ofs;
173 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
174 for(i = 0; i < PCI_NUM_REGIONS; i++) {
175 r = &d->io_regions[i];
176 if (i == PCI_ROM_SLOT) {
179 config_ofs = 0x10 + i * 4;
182 if (r->type & PCI_ADDRESS_SPACE_IO) {
183 if (cmd & PCI_COMMAND_IO) {
184 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
186 new_addr = new_addr & ~(r->size - 1);
187 last_addr = new_addr + r->size - 1;
188 /* NOTE: we have only 64K ioports on PC */
189 if (last_addr <= new_addr || new_addr == 0 ||
190 last_addr >= 0x10000) {
197 if (cmd & PCI_COMMAND_MEMORY) {
198 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
200 /* the ROM slot has a specific enable bit */
201 if (i == PCI_ROM_SLOT && !(new_addr & 1))
203 new_addr = new_addr & ~(r->size - 1);
204 last_addr = new_addr + r->size - 1;
205 /* NOTE: we do not support wrapping */
206 /* XXX: as we cannot support really dynamic
207 mappings, we handle specific values as invalid
209 if (last_addr <= new_addr || new_addr == 0 ||
218 /* now do the real mapping */
219 if (new_addr != r->addr) {
221 if (r->type & PCI_ADDRESS_SPACE_IO) {
223 /* NOTE: specific hack for IDE in PC case:
224 only one byte must be mapped. */
225 class = d->config[0x0a] | (d->config[0x0b] << 8);
226 if (class == 0x0101 && r->size == 4) {
227 isa_unassign_ioport(r->addr + 2, 1);
229 isa_unassign_ioport(r->addr, r->size);
232 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
239 r->map_func(d, i, r->addr, r->size, r->type);
246 uint32_t pci_default_read_config(PCIDevice *d,
247 uint32_t address, int len)
254 if (address <= 0xfc) {
255 val = le32_to_cpu(*(uint32_t *)(d->config + address));
260 if (address <= 0xfe) {
261 val = le16_to_cpu(*(uint16_t *)(d->config + address));
266 val = d->config[address];
272 void pci_default_write_config(PCIDevice *d,
273 uint32_t address, uint32_t val, int len)
278 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
279 (address >= 0x30 && address < 0x34))) {
283 if ( address >= 0x30 ) {
286 reg = (address - 0x10) >> 2;
288 r = &d->io_regions[reg];
291 /* compute the stored value */
292 if (reg == PCI_ROM_SLOT) {
293 /* keep ROM enable bit */
294 val &= (~(r->size - 1)) | 1;
296 val &= ~(r->size - 1);
299 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
300 pci_update_mappings(d);
304 /* not efficient, but simple */
306 for(i = 0; i < len; i++) {
307 /* default read/write accesses */
308 switch(d->config[0x0e]) {
321 case 0x10 ... 0x27: /* base */
322 case 0x30 ... 0x33: /* rom */
343 case 0x38 ... 0x3b: /* rom */
354 d->config[addr] = val;
362 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
363 /* if the command register is modified, we must modify the mappings */
364 pci_update_mappings(d);
368 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
372 int config_addr, bus_num;
374 #if defined(DEBUG_PCI) && 0
375 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
378 bus_num = (addr >> 16) & 0xff;
379 while (s && s->bus_num != bus_num)
383 pci_dev = s->devices[(addr >> 8) & 0xff];
386 config_addr = addr & 0xff;
387 #if defined(DEBUG_PCI)
388 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
389 pci_dev->name, config_addr, val, len);
391 pci_dev->config_write(pci_dev, config_addr, val, len);
394 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
398 int config_addr, bus_num;
401 bus_num = (addr >> 16) & 0xff;
402 while (s && s->bus_num != bus_num)
406 pci_dev = s->devices[(addr >> 8) & 0xff];
423 config_addr = addr & 0xff;
424 val = pci_dev->config_read(pci_dev, config_addr, len);
425 #if defined(DEBUG_PCI)
426 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
427 pci_dev->name, config_addr, val, len);
430 #if defined(DEBUG_PCI) && 0
431 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
437 /***********************************************************/
438 /* generic PCI irq support */
440 /* 0 <= irq_num <= 3. level must be 0 or 1 */
441 static void pci_set_irq(void *opaque, int irq_num, int level)
443 PCIDevice *pci_dev = (PCIDevice *)opaque;
447 change = level - pci_dev->irq_state[irq_num];
451 pci_dev->irq_state[irq_num] = level;
454 irq_num = bus->map_irq(pci_dev, irq_num);
457 pci_dev = bus->parent_dev;
459 bus->irq_count[irq_num] += change;
460 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
463 /***********************************************************/
464 /* monitor info on PCI */
471 static pci_class_desc pci_class_descriptions[] =
473 { 0x0100, "SCSI controller"},
474 { 0x0101, "IDE controller"},
475 { 0x0102, "Floppy controller"},
476 { 0x0103, "IPI controller"},
477 { 0x0104, "RAID controller"},
478 { 0x0106, "SATA controller"},
479 { 0x0107, "SAS controller"},
480 { 0x0180, "Storage controller"},
481 { 0x0200, "Ethernet controller"},
482 { 0x0201, "Token Ring controller"},
483 { 0x0202, "FDDI controller"},
484 { 0x0203, "ATM controller"},
485 { 0x0280, "Network controller"},
486 { 0x0300, "VGA controller"},
487 { 0x0301, "XGA controller"},
488 { 0x0302, "3D controller"},
489 { 0x0380, "Display controller"},
490 { 0x0400, "Video controller"},
491 { 0x0401, "Audio controller"},
493 { 0x0480, "Multimedia controller"},
494 { 0x0500, "RAM controller"},
495 { 0x0501, "Flash controller"},
496 { 0x0580, "Memory controller"},
497 { 0x0600, "Host bridge"},
498 { 0x0601, "ISA bridge"},
499 { 0x0602, "EISA bridge"},
500 { 0x0603, "MC bridge"},
501 { 0x0604, "PCI bridge"},
502 { 0x0605, "PCMCIA bridge"},
503 { 0x0606, "NUBUS bridge"},
504 { 0x0607, "CARDBUS bridge"},
505 { 0x0608, "RACEWAY bridge"},
507 { 0x0c03, "USB controller"},
511 static void pci_info_device(PCIDevice *d)
515 pci_class_desc *desc;
517 term_printf(" Bus %2d, device %3d, function %d:\n",
518 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
519 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
521 desc = pci_class_descriptions;
522 while (desc->desc && class != desc->class)
525 term_printf("%s", desc->desc);
527 term_printf("Class %04x", class);
529 term_printf(": PCI device %04x:%04x\n",
530 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
531 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
533 if (d->config[PCI_INTERRUPT_PIN] != 0) {
534 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
536 if (class == 0x0604) {
537 term_printf(" BUS %d.\n", d->config[0x19]);
539 for(i = 0;i < PCI_NUM_REGIONS; i++) {
540 r = &d->io_regions[i];
542 term_printf(" BAR%d: ", i);
543 if (r->type & PCI_ADDRESS_SPACE_IO) {
544 term_printf("I/O at 0x%04x [0x%04x].\n",
545 r->addr, r->addr + r->size - 1);
547 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
548 r->addr, r->addr + r->size - 1);
552 if (class == 0x0604 && d->config[0x19] != 0) {
553 pci_for_each_device(d->config[0x19], pci_info_device);
557 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
559 PCIBus *bus = first_bus;
563 while (bus && bus->bus_num != bus_num)
566 for(devfn = 0; devfn < 256; devfn++) {
567 d = bus->devices[devfn];
576 pci_for_each_device(0, pci_info_device);
579 /* Initialize a PCI NIC. */
580 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
582 if (strcmp(nd->model, "ne2k_pci") == 0) {
583 pci_ne2000_init(bus, nd, devfn);
584 } else if (strcmp(nd->model, "i82551") == 0) {
585 pci_i82551_init(bus, nd, devfn);
586 } else if (strcmp(nd->model, "i82557b") == 0) {
587 pci_i82557b_init(bus, nd, devfn);
588 } else if (strcmp(nd->model, "i82559er") == 0) {
589 pci_i82559er_init(bus, nd, devfn);
590 } else if (strcmp(nd->model, "rtl8139") == 0) {
591 pci_rtl8139_init(bus, nd, devfn);
592 } else if (strcmp(nd->model, "pcnet") == 0) {
593 pci_pcnet_init(bus, nd, devfn);
594 } else if (strcmp(nd->model, "?") == 0) {
595 fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
596 " ne2k_pci pcnet rtl8139\n");
599 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
609 void pci_bridge_write_config(PCIDevice *d,
610 uint32_t address, uint32_t val, int len)
612 PCIBridge *s = (PCIBridge *)d;
614 if (address == 0x19 || (address == 0x18 && len > 1)) {
616 s->bus->bus_num = val & 0xff;
618 s->bus->bus_num = (val >> 8) & 0xff;
619 #if defined(DEBUG_PCI)
620 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
623 pci_default_write_config(d, address, val, len);
626 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
627 pci_map_irq_fn map_irq, const char *name)
630 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
631 devfn, NULL, pci_bridge_write_config);
632 s->dev.config[0x00] = id >> 16;
633 s->dev.config[0x01] = id >> 24;
634 s->dev.config[0x02] = id; // device_id
635 s->dev.config[0x03] = id >> 8;
636 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
637 s->dev.config[0x05] = 0x00;
638 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
639 s->dev.config[0x07] = 0x00; // status = fast devsel
640 s->dev.config[0x08] = 0x00; // revision
641 s->dev.config[0x09] = 0x00; // programming i/f
642 s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
643 s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
644 s->dev.config[0x0D] = 0x10; // latency_timer
645 s->dev.config[0x0E] = 0x81; // header_type
646 s->dev.config[0x1E] = 0xa0; // secondary status
648 s->bus = pci_register_secondary_bus(&s->dev, map_irq);