2 * ARM AMBA PrimeCell PL031 RTC
4 * Copyright (c) 2007 CodeSourcery
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #include "primecell.h"
14 #include "qemu-timer.h"
20 #define DPRINTF(fmt, args...) \
21 do { printf("pl031: " fmt , ##args); } while (0)
23 #define DPRINTF(fmt, args...) do {} while(0)
26 #define RTC_DR 0x00 /* Data read register */
27 #define RTC_MR 0x04 /* Match register */
28 #define RTC_LR 0x08 /* Data load register */
29 #define RTC_CR 0x0c /* Control register */
30 #define RTC_IMSC 0x10 /* Interrupt mask and set register */
31 #define RTC_RIS 0x14 /* Raw interrupt status register */
32 #define RTC_MIS 0x18 /* Masked interrupt status register */
33 #define RTC_ICR 0x1c /* Interrupt clear register */
48 static const unsigned char pl031_id[] = {
49 0x31, 0x10, 0x14, 0x00, /* Device ID */
50 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
53 static void pl031_update(pl031_state *s)
55 qemu_set_irq(s->irq, s->is & s->im);
58 static void pl031_interrupt(void * opaque)
60 pl031_state *s = (pl031_state *)opaque;
63 DPRINTF("Alarm raised\n");
67 static uint32_t pl031_get_count(pl031_state *s)
69 /* This assumes qemu_get_clock returns the time since the machine was
71 return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec;
74 static void pl031_set_alarm(pl031_state *s)
79 now = qemu_get_clock(vm_clock);
80 ticks = s->tick_offset + now / ticks_per_sec;
82 /* The timer wraps around. This subtraction also wraps in the same way,
83 and gives correct results when alarm < now_ticks. */
84 ticks = s->mr - ticks;
85 DPRINTF("Alarm set in %ud ticks\n", ticks);
87 qemu_del_timer(s->timer);
90 qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec);
94 static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
96 pl031_state *s = (pl031_state *)opaque;
98 if (offset >= 0xfe0 && offset < 0x1000)
99 return pl031_id[(offset - 0xfe0) >> 2];
103 return pl031_get_count(s);
113 /* RTC is permanently enabled. */
116 return s->is & s->im;
118 fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
122 cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
130 static void pl031_write(void * opaque, target_phys_addr_t offset,
133 pl031_state *s = (pl031_state *)opaque;
138 s->tick_offset += value - pl031_get_count(s);
147 DPRINTF("Interrupt mask %d\n", s->im);
151 /* The PL031 documentation (DDI0224B) states that the interupt is
152 cleared when bit 0 of the written value is set. However the
153 arm926e documentation (DDI0287B) states that the interrupt is
154 cleared when any value is written. */
155 DPRINTF("Interrupt cleared");
160 /* Written value is ignored. */
166 fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
171 cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
177 static CPUWriteMemoryFunc * pl031_writefn[] = {
183 static CPUReadMemoryFunc * pl031_readfn[] = {
189 void pl031_init(uint32_t base, qemu_irq irq)
195 s = qemu_mallocz(sizeof(pl031_state));
197 iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
199 cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
201 cpu_register_physical_memory(base, 0x00001000, iomemtype);
204 /* ??? We assume vm_clock is zero at this point. */
205 qemu_get_timedate(&tm, 0);
206 s->tick_offset = mktimegm(&tm);
208 s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s);