2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
41 //#define DEBUG_UNASSIGNED
43 /*****************************************************************************/
44 /* Generic PowerPC 405 processor instanciation */
45 CPUState *ppc405_init (const unsigned char *cpu_model,
46 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
54 qemu_register_reset(&cpu_ppc_reset, env);
55 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
56 ppc_find_by_name(cpu_model, &def);
58 cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",
61 cpu_ppc_register(env, def);
62 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
63 cpu_clk->opaque = env;
64 /* Set time-base frequency to sysclk */
65 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
67 ppc_dcr_init(env, NULL, NULL);
72 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd)
77 /* We put the bd structure at the top of memory */
78 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
79 stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
80 stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
81 stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
82 stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
83 stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
84 stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
85 stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
86 stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
87 stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
88 for (i = 0; i < 6; i++)
89 stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
90 stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
91 stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
92 stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
93 stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
94 for (i = 0; i < 4; i++)
95 stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
96 for (i = 0; i < 32; i++)
97 stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
98 stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
99 stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
100 for (i = 0; i < 6; i++)
101 stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
103 if (env->spr[SPR_PVR] == CPU_PPC_405EP) {
104 for (i = 0; i < 6; i++)
105 stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
107 stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
109 for (i = 0; i < 2; i++) {
110 stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
117 /*****************************************************************************/
118 /* Shared peripherals */
120 /*****************************************************************************/
121 /* Fake device used to map multiple devices in a single memory page */
122 #define MMIO_AREA_BITS 8
123 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
124 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
125 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
126 struct ppc4xx_mmio_t {
127 target_phys_addr_t base;
128 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
129 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
130 void *opaque[MMIO_AREA_NB];
133 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
135 #ifdef DEBUG_UNASSIGNED
139 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
146 static void unassigned_mmio_writeb (void *opaque,
147 target_phys_addr_t addr, uint32_t val)
149 #ifdef DEBUG_UNASSIGNED
153 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
154 addr, val, mmio->base);
158 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
159 unassigned_mmio_readb,
160 unassigned_mmio_readb,
161 unassigned_mmio_readb,
164 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
165 unassigned_mmio_writeb,
166 unassigned_mmio_writeb,
167 unassigned_mmio_writeb,
170 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
171 target_phys_addr_t addr, int len)
173 CPUReadMemoryFunc **mem_read;
177 idx = MMIO_IDX(addr - mmio->base);
178 #if defined(DEBUG_MMIO)
179 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
180 mmio, len, addr, idx);
182 mem_read = mmio->mem_read[idx];
183 ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
188 static void mmio_writelen (ppc4xx_mmio_t *mmio,
189 target_phys_addr_t addr, uint32_t value, int len)
191 CPUWriteMemoryFunc **mem_write;
194 idx = MMIO_IDX(addr - mmio->base);
195 #if defined(DEBUG_MMIO)
196 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
197 mmio, len, addr, idx, value);
199 mem_write = mmio->mem_write[idx];
200 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
203 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
205 #if defined(DEBUG_MMIO)
206 printf("%s: addr " PADDRX "\n", __func__, addr);
209 return mmio_readlen(opaque, addr, 0);
212 static void mmio_writeb (void *opaque,
213 target_phys_addr_t addr, uint32_t value)
215 #if defined(DEBUG_MMIO)
216 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
218 mmio_writelen(opaque, addr, value, 0);
221 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
223 #if defined(DEBUG_MMIO)
224 printf("%s: addr " PADDRX "\n", __func__, addr);
227 return mmio_readlen(opaque, addr, 1);
230 static void mmio_writew (void *opaque,
231 target_phys_addr_t addr, uint32_t value)
233 #if defined(DEBUG_MMIO)
234 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
236 mmio_writelen(opaque, addr, value, 1);
239 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
241 #if defined(DEBUG_MMIO)
242 printf("%s: addr " PADDRX "\n", __func__, addr);
245 return mmio_readlen(opaque, addr, 2);
248 static void mmio_writel (void *opaque,
249 target_phys_addr_t addr, uint32_t value)
251 #if defined(DEBUG_MMIO)
252 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
254 mmio_writelen(opaque, addr, value, 2);
257 static CPUReadMemoryFunc *mmio_read[] = {
263 static CPUWriteMemoryFunc *mmio_write[] = {
269 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
270 target_phys_addr_t offset, uint32_t len,
271 CPUReadMemoryFunc **mem_read,
272 CPUWriteMemoryFunc **mem_write, void *opaque)
277 if ((offset + len) > TARGET_PAGE_SIZE)
279 idx = MMIO_IDX(offset);
280 end = offset + len - 1;
281 eidx = MMIO_IDX(end);
282 #if defined(DEBUG_MMIO)
283 printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
286 for (; idx <= eidx; idx++) {
287 mmio->mem_read[idx] = mem_read;
288 mmio->mem_write[idx] = mem_write;
289 mmio->opaque[idx] = opaque;
295 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
300 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
303 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
304 #if defined(DEBUG_MMIO)
305 printf("%s: %p base %08x len %08x %d\n", __func__,
306 mmio, base, TARGET_PAGE_SIZE, mmio_memory);
308 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
309 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
310 unassigned_mmio_read, unassigned_mmio_write,
317 /*****************************************************************************/
318 /* Peripheral local bus arbitrer */
325 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
326 struct ppc4xx_plb_t {
332 static target_ulong dcr_read_plb (void *opaque, int dcrn)
349 /* Avoid gcc warning */
357 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
364 /* We don't care about the actual parameters written as
365 * we don't manage any priorities on the bus
367 plb->acr = val & 0xF8000000;
379 static void ppc4xx_plb_reset (void *opaque)
384 plb->acr = 0x00000000;
385 plb->bear = 0x00000000;
386 plb->besr = 0x00000000;
389 void ppc4xx_plb_init (CPUState *env)
393 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
395 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
396 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
397 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
398 ppc4xx_plb_reset(plb);
399 qemu_register_reset(ppc4xx_plb_reset, plb);
403 /*****************************************************************************/
404 /* PLB to OPB bridge */
411 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
412 struct ppc4xx_pob_t {
417 static target_ulong dcr_read_pob (void *opaque, int dcrn)
429 ret = pob->besr[dcrn - POB0_BESR0];
432 /* Avoid gcc warning */
440 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
452 pob->besr[dcrn - POB0_BESR0] &= ~val;
457 static void ppc4xx_pob_reset (void *opaque)
463 pob->bear = 0x00000000;
464 pob->besr[0] = 0x0000000;
465 pob->besr[1] = 0x0000000;
468 void ppc4xx_pob_init (CPUState *env)
472 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
474 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
475 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
476 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
477 qemu_register_reset(ppc4xx_pob_reset, pob);
478 ppc4xx_pob_reset(env);
482 /*****************************************************************************/
484 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
485 struct ppc4xx_opba_t {
486 target_phys_addr_t base;
491 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
497 printf("%s: addr " PADDRX "\n", __func__, addr);
500 switch (addr - opba->base) {
515 static void opba_writeb (void *opaque,
516 target_phys_addr_t addr, uint32_t value)
521 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
524 switch (addr - opba->base) {
526 opba->cr = value & 0xF8;
529 opba->pr = value & 0xFF;
536 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
541 printf("%s: addr " PADDRX "\n", __func__, addr);
543 ret = opba_readb(opaque, addr) << 8;
544 ret |= opba_readb(opaque, addr + 1);
549 static void opba_writew (void *opaque,
550 target_phys_addr_t addr, uint32_t value)
553 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
555 opba_writeb(opaque, addr, value >> 8);
556 opba_writeb(opaque, addr + 1, value);
559 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
564 printf("%s: addr " PADDRX "\n", __func__, addr);
566 ret = opba_readb(opaque, addr) << 24;
567 ret |= opba_readb(opaque, addr + 1) << 16;
572 static void opba_writel (void *opaque,
573 target_phys_addr_t addr, uint32_t value)
576 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
578 opba_writeb(opaque, addr, value >> 24);
579 opba_writeb(opaque, addr + 1, value >> 16);
582 static CPUReadMemoryFunc *opba_read[] = {
588 static CPUWriteMemoryFunc *opba_write[] = {
594 static void ppc4xx_opba_reset (void *opaque)
599 opba->cr = 0x00; /* No dynamic priorities - park disabled */
603 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
604 target_phys_addr_t offset)
608 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
612 printf("%s: offset=" PADDRX "\n", __func__, offset);
614 ppc4xx_mmio_register(env, mmio, offset, 0x002,
615 opba_read, opba_write, opba);
616 qemu_register_reset(ppc4xx_opba_reset, opba);
617 ppc4xx_opba_reset(opba);
621 /*****************************************************************************/
622 /* "Universal" Interrupt controller */
636 #define UIC_MAX_IRQ 32
637 typedef struct ppcuic_t ppcuic_t;
641 uint32_t uicsr; /* Status register */
642 uint32_t uicer; /* Enable register */
643 uint32_t uiccr; /* Critical register */
644 uint32_t uicpr; /* Polarity register */
645 uint32_t uictr; /* Triggering register */
646 uint32_t uicvcr; /* Vector configuration register */
651 static void ppcuic_trigger_irq (ppcuic_t *uic)
654 int start, end, inc, i;
656 /* Trigger interrupt if any is pending */
657 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
658 cr = uic->uicsr & uic->uicer & uic->uiccr;
660 if (loglevel & CPU_LOG_INT) {
661 fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
662 " %08x ir %08x cr %08x\n", __func__,
663 uic->uicsr, uic->uicer, uic->uiccr,
664 uic->uicsr & uic->uicer, ir, cr);
667 if (ir != 0x0000000) {
669 if (loglevel & CPU_LOG_INT) {
670 fprintf(logfile, "Raise UIC interrupt\n");
673 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
676 if (loglevel & CPU_LOG_INT) {
677 fprintf(logfile, "Lower UIC interrupt\n");
680 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
682 /* Trigger critical interrupt if any is pending and update vector */
683 if (cr != 0x0000000) {
684 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
685 if (uic->use_vectors) {
686 /* Compute critical IRQ vector */
687 if (uic->uicvcr & 1) {
696 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
697 for (i = start; i <= end; i += inc) {
699 uic->uicvr += (i - start) * 512 * inc;
705 if (loglevel & CPU_LOG_INT) {
706 fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
712 if (loglevel & CPU_LOG_INT) {
713 fprintf(logfile, "Lower UIC critical interrupt\n");
716 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
717 uic->uicvr = 0x00000000;
721 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
729 if (loglevel & CPU_LOG_INT) {
730 fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
731 "%08x\n", __func__, irq_num, level,
732 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
735 if (irq_num < 0 || irq_num > 31)
738 if (!(uic->uicpr & mask)) {
739 /* Negatively asserted IRQ */
740 level = level == 0 ? 1 : 0;
742 /* Update status register */
743 if (uic->uictr & mask) {
744 /* Edge sensitive interrupt */
748 /* Level sensitive interrupt */
755 if (loglevel & CPU_LOG_INT) {
756 fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
757 irq_num, level, uic->uicsr, sr);
760 if (sr != uic->uicsr)
761 ppcuic_trigger_irq(uic);
764 static target_ulong dcr_read_uic (void *opaque, int dcrn)
770 dcrn -= uic->dcr_base;
789 ret = uic->uicsr & uic->uicer;
792 if (!uic->use_vectors)
797 if (!uic->use_vectors)
810 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
815 dcrn -= uic->dcr_base;
817 if (loglevel & CPU_LOG_INT) {
818 fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
824 ppcuic_trigger_irq(uic);
828 ppcuic_trigger_irq(uic);
832 ppcuic_trigger_irq(uic);
836 ppcuic_trigger_irq(uic);
840 ppcuic_trigger_irq(uic);
844 ppcuic_trigger_irq(uic);
851 uic->uicvcr = val & 0xFFFFFFFD;
852 ppcuic_trigger_irq(uic);
857 static void ppcuic_reset (void *opaque)
862 uic->uiccr = 0x00000000;
863 uic->uicer = 0x00000000;
864 uic->uicpr = 0x00000000;
865 uic->uicsr = 0x00000000;
866 uic->uictr = 0x00000000;
867 if (uic->use_vectors) {
868 uic->uicvcr = 0x00000000;
869 uic->uicvr = 0x0000000;
873 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
874 uint32_t dcr_base, int has_ssr, int has_vr)
879 uic = qemu_mallocz(sizeof(ppcuic_t));
881 uic->dcr_base = dcr_base;
884 uic->use_vectors = 1;
885 for (i = 0; i < DCR_UICMAX; i++) {
886 ppc_dcr_register(env, dcr_base + i, uic,
887 &dcr_read_uic, &dcr_write_uic);
889 qemu_register_reset(ppcuic_reset, uic);
893 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
896 /*****************************************************************************/
897 /* Code decompression controller */
900 /*****************************************************************************/
901 /* SDRAM controller */
902 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
903 struct ppc4xx_sdram_t {
906 target_phys_addr_t ram_bases[4];
907 target_phys_addr_t ram_sizes[4];
923 SDRAM0_CFGADDR = 0x010,
924 SDRAM0_CFGDATA = 0x011,
927 static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size)
932 case (4 * 1024 * 1024):
935 case (8 * 1024 * 1024):
938 case (16 * 1024 * 1024):
941 case (32 * 1024 * 1024):
944 case (64 * 1024 * 1024):
947 case (128 * 1024 * 1024):
950 case (256 * 1024 * 1024):
954 printf("%s: invalid RAM size " TARGET_FMT_ld "\n", __func__, ram_size);
957 bcr |= ram_base & 0xFF800000;
963 static inline target_phys_addr_t sdram_base (uint32_t bcr)
965 return bcr & 0xFF800000;
968 static target_ulong sdram_size (uint32_t bcr)
973 sh = (bcr >> 17) & 0x7;
977 size = (4 * 1024 * 1024) << sh;
982 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
984 if (*bcrp & 0x00000001) {
987 printf("%s: unmap RAM area " ADDRX " " ADDRX "\n", __func__,
988 sdram_base(*bcrp), sdram_size(*bcrp));
990 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
993 *bcrp = bcr & 0xFFDEE001;
994 if (enabled && (bcr & 0x00000001)) {
996 printf("%s: Map RAM area " ADDRX " " ADDRX "\n", __func__,
997 sdram_base(bcr), sdram_size(bcr));
999 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
1000 sdram_base(bcr) | IO_MEM_RAM);
1004 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
1008 for (i = 0; i < sdram->nbanks; i++) {
1009 if (sdram->ram_sizes[i] != 0) {
1010 sdram_set_bcr(&sdram->bcr[i],
1011 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1014 sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
1019 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
1023 for (i = 0; i < sdram->nbanks; i++) {
1025 printf("%s: Unmap RAM area " ADDRX " " ADDRX "\n", __func__,
1026 sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
1028 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
1029 sdram_size(sdram->bcr[i]),
1034 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
1036 ppc4xx_sdram_t *sdram;
1041 case SDRAM0_CFGADDR:
1044 case SDRAM0_CFGDATA:
1045 switch (sdram->addr) {
1046 case 0x00: /* SDRAM_BESR0 */
1049 case 0x08: /* SDRAM_BESR1 */
1052 case 0x10: /* SDRAM_BEAR */
1055 case 0x20: /* SDRAM_CFG */
1058 case 0x24: /* SDRAM_STATUS */
1059 ret = sdram->status;
1061 case 0x30: /* SDRAM_RTR */
1064 case 0x34: /* SDRAM_PMIT */
1067 case 0x40: /* SDRAM_B0CR */
1068 ret = sdram->bcr[0];
1070 case 0x44: /* SDRAM_B1CR */
1071 ret = sdram->bcr[1];
1073 case 0x48: /* SDRAM_B2CR */
1074 ret = sdram->bcr[2];
1076 case 0x4C: /* SDRAM_B3CR */
1077 ret = sdram->bcr[3];
1079 case 0x80: /* SDRAM_TR */
1082 case 0x94: /* SDRAM_ECCCFG */
1083 ret = sdram->ecccfg;
1085 case 0x98: /* SDRAM_ECCESR */
1086 ret = sdram->eccesr;
1088 default: /* Error */
1094 /* Avoid gcc warning */
1102 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
1104 ppc4xx_sdram_t *sdram;
1108 case SDRAM0_CFGADDR:
1111 case SDRAM0_CFGDATA:
1112 switch (sdram->addr) {
1113 case 0x00: /* SDRAM_BESR0 */
1114 sdram->besr0 &= ~val;
1116 case 0x08: /* SDRAM_BESR1 */
1117 sdram->besr1 &= ~val;
1119 case 0x10: /* SDRAM_BEAR */
1122 case 0x20: /* SDRAM_CFG */
1124 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
1126 printf("%s: enable SDRAM controller\n", __func__);
1128 /* validate all RAM mappings */
1129 sdram_map_bcr(sdram);
1130 sdram->status &= ~0x80000000;
1131 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
1133 printf("%s: disable SDRAM controller\n", __func__);
1135 /* invalidate all RAM mappings */
1136 sdram_unmap_bcr(sdram);
1137 sdram->status |= 0x80000000;
1139 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
1140 sdram->status |= 0x40000000;
1141 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
1142 sdram->status &= ~0x40000000;
1145 case 0x24: /* SDRAM_STATUS */
1146 /* Read-only register */
1148 case 0x30: /* SDRAM_RTR */
1149 sdram->rtr = val & 0x3FF80000;
1151 case 0x34: /* SDRAM_PMIT */
1152 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
1154 case 0x40: /* SDRAM_B0CR */
1155 sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
1157 case 0x44: /* SDRAM_B1CR */
1158 sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
1160 case 0x48: /* SDRAM_B2CR */
1161 sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
1163 case 0x4C: /* SDRAM_B3CR */
1164 sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
1166 case 0x80: /* SDRAM_TR */
1167 sdram->tr = val & 0x018FC01F;
1169 case 0x94: /* SDRAM_ECCCFG */
1170 sdram->ecccfg = val & 0x00F00000;
1172 case 0x98: /* SDRAM_ECCESR */
1174 if (sdram->eccesr == 0 && val != 0)
1175 qemu_irq_raise(sdram->irq);
1176 else if (sdram->eccesr != 0 && val == 0)
1177 qemu_irq_lower(sdram->irq);
1178 sdram->eccesr = val;
1180 default: /* Error */
1187 static void sdram_reset (void *opaque)
1189 ppc4xx_sdram_t *sdram;
1192 sdram->addr = 0x00000000;
1193 sdram->bear = 0x00000000;
1194 sdram->besr0 = 0x00000000; /* No error */
1195 sdram->besr1 = 0x00000000; /* No error */
1196 sdram->cfg = 0x00000000;
1197 sdram->ecccfg = 0x00000000; /* No ECC */
1198 sdram->eccesr = 0x00000000; /* No error */
1199 sdram->pmit = 0x07C00000;
1200 sdram->rtr = 0x05F00000;
1201 sdram->tr = 0x00854009;
1202 /* We pre-initialize RAM banks */
1203 sdram->status = 0x00000000;
1204 sdram->cfg = 0x00800000;
1205 sdram_unmap_bcr(sdram);
1208 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1209 target_phys_addr_t *ram_bases,
1210 target_phys_addr_t *ram_sizes,
1213 ppc4xx_sdram_t *sdram;
1215 sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
1216 if (sdram != NULL) {
1218 sdram->nbanks = nbanks;
1219 memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
1220 memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t));
1221 memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
1222 memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t));
1224 qemu_register_reset(&sdram_reset, sdram);
1225 ppc_dcr_register(env, SDRAM0_CFGADDR,
1226 sdram, &dcr_read_sdram, &dcr_write_sdram);
1227 ppc_dcr_register(env, SDRAM0_CFGDATA,
1228 sdram, &dcr_read_sdram, &dcr_write_sdram);
1230 sdram_map_bcr(sdram);
1234 /*****************************************************************************/
1235 /* Peripheral controller */
1236 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
1237 struct ppc4xx_ebc_t {
1248 EBC0_CFGADDR = 0x012,
1249 EBC0_CFGDATA = 0x013,
1252 static target_ulong dcr_read_ebc (void *opaque, int dcrn)
1263 switch (ebc->addr) {
1264 case 0x00: /* B0CR */
1267 case 0x01: /* B1CR */
1270 case 0x02: /* B2CR */
1273 case 0x03: /* B3CR */
1276 case 0x04: /* B4CR */
1279 case 0x05: /* B5CR */
1282 case 0x06: /* B6CR */
1285 case 0x07: /* B7CR */
1288 case 0x10: /* B0AP */
1291 case 0x11: /* B1AP */
1294 case 0x12: /* B2AP */
1297 case 0x13: /* B3AP */
1300 case 0x14: /* B4AP */
1303 case 0x15: /* B5AP */
1306 case 0x16: /* B6AP */
1309 case 0x17: /* B7AP */
1312 case 0x20: /* BEAR */
1315 case 0x21: /* BESR0 */
1318 case 0x22: /* BESR1 */
1321 case 0x23: /* CFG */
1336 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
1346 switch (ebc->addr) {
1347 case 0x00: /* B0CR */
1349 case 0x01: /* B1CR */
1351 case 0x02: /* B2CR */
1353 case 0x03: /* B3CR */
1355 case 0x04: /* B4CR */
1357 case 0x05: /* B5CR */
1359 case 0x06: /* B6CR */
1361 case 0x07: /* B7CR */
1363 case 0x10: /* B0AP */
1365 case 0x11: /* B1AP */
1367 case 0x12: /* B2AP */
1369 case 0x13: /* B3AP */
1371 case 0x14: /* B4AP */
1373 case 0x15: /* B5AP */
1375 case 0x16: /* B6AP */
1377 case 0x17: /* B7AP */
1379 case 0x20: /* BEAR */
1381 case 0x21: /* BESR0 */
1383 case 0x22: /* BESR1 */
1385 case 0x23: /* CFG */
1396 static void ebc_reset (void *opaque)
1402 ebc->addr = 0x00000000;
1403 ebc->bap[0] = 0x7F8FFE80;
1404 ebc->bcr[0] = 0xFFE28000;
1405 for (i = 0; i < 8; i++) {
1406 ebc->bap[i] = 0x00000000;
1407 ebc->bcr[i] = 0x00000000;
1409 ebc->besr0 = 0x00000000;
1410 ebc->besr1 = 0x00000000;
1411 ebc->cfg = 0x80400000;
1414 void ppc405_ebc_init (CPUState *env)
1418 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
1421 qemu_register_reset(&ebc_reset, ebc);
1422 ppc_dcr_register(env, EBC0_CFGADDR,
1423 ebc, &dcr_read_ebc, &dcr_write_ebc);
1424 ppc_dcr_register(env, EBC0_CFGDATA,
1425 ebc, &dcr_read_ebc, &dcr_write_ebc);
1429 /*****************************************************************************/
1430 /* DMA controller */
1458 typedef struct ppc405_dma_t ppc405_dma_t;
1459 struct ppc405_dma_t {
1472 static target_ulong dcr_read_dma (void *opaque, int dcrn)
1481 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
1488 static void ppc405_dma_reset (void *opaque)
1494 for (i = 0; i < 4; i++) {
1495 dma->cr[i] = 0x00000000;
1496 dma->ct[i] = 0x00000000;
1497 dma->da[i] = 0x00000000;
1498 dma->sa[i] = 0x00000000;
1499 dma->sg[i] = 0x00000000;
1501 dma->sr = 0x00000000;
1502 dma->sgc = 0x00000000;
1503 dma->slp = 0x7C000000;
1504 dma->pol = 0x00000000;
1507 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
1511 dma = qemu_mallocz(sizeof(ppc405_dma_t));
1513 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
1514 ppc405_dma_reset(dma);
1515 qemu_register_reset(&ppc405_dma_reset, dma);
1516 ppc_dcr_register(env, DMA0_CR0,
1517 dma, &dcr_read_dma, &dcr_write_dma);
1518 ppc_dcr_register(env, DMA0_CT0,
1519 dma, &dcr_read_dma, &dcr_write_dma);
1520 ppc_dcr_register(env, DMA0_DA0,
1521 dma, &dcr_read_dma, &dcr_write_dma);
1522 ppc_dcr_register(env, DMA0_SA0,
1523 dma, &dcr_read_dma, &dcr_write_dma);
1524 ppc_dcr_register(env, DMA0_SG0,
1525 dma, &dcr_read_dma, &dcr_write_dma);
1526 ppc_dcr_register(env, DMA0_CR1,
1527 dma, &dcr_read_dma, &dcr_write_dma);
1528 ppc_dcr_register(env, DMA0_CT1,
1529 dma, &dcr_read_dma, &dcr_write_dma);
1530 ppc_dcr_register(env, DMA0_DA1,
1531 dma, &dcr_read_dma, &dcr_write_dma);
1532 ppc_dcr_register(env, DMA0_SA1,
1533 dma, &dcr_read_dma, &dcr_write_dma);
1534 ppc_dcr_register(env, DMA0_SG1,
1535 dma, &dcr_read_dma, &dcr_write_dma);
1536 ppc_dcr_register(env, DMA0_CR2,
1537 dma, &dcr_read_dma, &dcr_write_dma);
1538 ppc_dcr_register(env, DMA0_CT2,
1539 dma, &dcr_read_dma, &dcr_write_dma);
1540 ppc_dcr_register(env, DMA0_DA2,
1541 dma, &dcr_read_dma, &dcr_write_dma);
1542 ppc_dcr_register(env, DMA0_SA2,
1543 dma, &dcr_read_dma, &dcr_write_dma);
1544 ppc_dcr_register(env, DMA0_SG2,
1545 dma, &dcr_read_dma, &dcr_write_dma);
1546 ppc_dcr_register(env, DMA0_CR3,
1547 dma, &dcr_read_dma, &dcr_write_dma);
1548 ppc_dcr_register(env, DMA0_CT3,
1549 dma, &dcr_read_dma, &dcr_write_dma);
1550 ppc_dcr_register(env, DMA0_DA3,
1551 dma, &dcr_read_dma, &dcr_write_dma);
1552 ppc_dcr_register(env, DMA0_SA3,
1553 dma, &dcr_read_dma, &dcr_write_dma);
1554 ppc_dcr_register(env, DMA0_SG3,
1555 dma, &dcr_read_dma, &dcr_write_dma);
1556 ppc_dcr_register(env, DMA0_SR,
1557 dma, &dcr_read_dma, &dcr_write_dma);
1558 ppc_dcr_register(env, DMA0_SGC,
1559 dma, &dcr_read_dma, &dcr_write_dma);
1560 ppc_dcr_register(env, DMA0_SLP,
1561 dma, &dcr_read_dma, &dcr_write_dma);
1562 ppc_dcr_register(env, DMA0_POL,
1563 dma, &dcr_read_dma, &dcr_write_dma);
1567 /*****************************************************************************/
1569 typedef struct ppc405_gpio_t ppc405_gpio_t;
1570 struct ppc405_gpio_t {
1571 target_phys_addr_t base;
1585 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
1587 ppc405_gpio_t *gpio;
1591 printf("%s: addr " PADDRX "\n", __func__, addr);
1597 static void ppc405_gpio_writeb (void *opaque,
1598 target_phys_addr_t addr, uint32_t value)
1600 ppc405_gpio_t *gpio;
1604 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1608 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
1610 ppc405_gpio_t *gpio;
1614 printf("%s: addr " PADDRX "\n", __func__, addr);
1620 static void ppc405_gpio_writew (void *opaque,
1621 target_phys_addr_t addr, uint32_t value)
1623 ppc405_gpio_t *gpio;
1627 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1631 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
1633 ppc405_gpio_t *gpio;
1637 printf("%s: addr " PADDRX "\n", __func__, addr);
1643 static void ppc405_gpio_writel (void *opaque,
1644 target_phys_addr_t addr, uint32_t value)
1646 ppc405_gpio_t *gpio;
1650 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1654 static CPUReadMemoryFunc *ppc405_gpio_read[] = {
1660 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
1661 &ppc405_gpio_writeb,
1662 &ppc405_gpio_writew,
1663 &ppc405_gpio_writel,
1666 static void ppc405_gpio_reset (void *opaque)
1668 ppc405_gpio_t *gpio;
1673 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
1674 target_phys_addr_t offset)
1676 ppc405_gpio_t *gpio;
1678 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
1680 gpio->base = offset;
1681 ppc405_gpio_reset(gpio);
1682 qemu_register_reset(&ppc405_gpio_reset, gpio);
1684 printf("%s: offset=" PADDRX "\n", __func__, offset);
1686 ppc4xx_mmio_register(env, mmio, offset, 0x038,
1687 ppc405_gpio_read, ppc405_gpio_write, gpio);
1691 /*****************************************************************************/
1693 static CPUReadMemoryFunc *serial_mm_read[] = {
1699 static CPUWriteMemoryFunc *serial_mm_write[] = {
1705 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1706 target_phys_addr_t offset, qemu_irq irq,
1707 CharDriverState *chr)
1712 printf("%s: offset=" PADDRX "\n", __func__, offset);
1714 serial = serial_mm_init(offset, 0, irq, chr, 0);
1715 ppc4xx_mmio_register(env, mmio, offset, 0x008,
1716 serial_mm_read, serial_mm_write, serial);
1719 /*****************************************************************************/
1720 /* On Chip Memory */
1723 OCM0_ISACNTL = 0x019,
1725 OCM0_DSACNTL = 0x01B,
1728 typedef struct ppc405_ocm_t ppc405_ocm_t;
1729 struct ppc405_ocm_t {
1730 target_ulong offset;
1737 static void ocm_update_mappings (ppc405_ocm_t *ocm,
1738 uint32_t isarc, uint32_t isacntl,
1739 uint32_t dsarc, uint32_t dsacntl)
1742 printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
1743 isarc, isacntl, dsarc, dsacntl,
1744 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
1746 if (ocm->isarc != isarc ||
1747 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
1748 if (ocm->isacntl & 0x80000000) {
1749 /* Unmap previously assigned memory region */
1750 printf("OCM unmap ISA %08x\n", ocm->isarc);
1751 cpu_register_physical_memory(ocm->isarc, 0x04000000,
1754 if (isacntl & 0x80000000) {
1755 /* Map new instruction memory region */
1757 printf("OCM map ISA %08x\n", isarc);
1759 cpu_register_physical_memory(isarc, 0x04000000,
1760 ocm->offset | IO_MEM_RAM);
1763 if (ocm->dsarc != dsarc ||
1764 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
1765 if (ocm->dsacntl & 0x80000000) {
1766 /* Beware not to unmap the region we just mapped */
1767 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
1768 /* Unmap previously assigned memory region */
1770 printf("OCM unmap DSA %08x\n", ocm->dsarc);
1772 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
1776 if (dsacntl & 0x80000000) {
1777 /* Beware not to remap the region we just mapped */
1778 if (!(isacntl & 0x80000000) || dsarc != isarc) {
1779 /* Map new data memory region */
1781 printf("OCM map DSA %08x\n", dsarc);
1783 cpu_register_physical_memory(dsarc, 0x04000000,
1784 ocm->offset | IO_MEM_RAM);
1790 static target_ulong dcr_read_ocm (void *opaque, int dcrn)
1817 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
1820 uint32_t isarc, dsarc, isacntl, dsacntl;
1825 isacntl = ocm->isacntl;
1826 dsacntl = ocm->dsacntl;
1829 isarc = val & 0xFC000000;
1832 isacntl = val & 0xC0000000;
1835 isarc = val & 0xFC000000;
1838 isacntl = val & 0xC0000000;
1841 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1844 ocm->isacntl = isacntl;
1845 ocm->dsacntl = dsacntl;
1848 static void ocm_reset (void *opaque)
1851 uint32_t isarc, dsarc, isacntl, dsacntl;
1855 isacntl = 0x00000000;
1857 dsacntl = 0x00000000;
1858 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1861 ocm->isacntl = isacntl;
1862 ocm->dsacntl = dsacntl;
1865 void ppc405_ocm_init (CPUState *env, unsigned long offset)
1869 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1871 ocm->offset = offset;
1873 qemu_register_reset(&ocm_reset, ocm);
1874 ppc_dcr_register(env, OCM0_ISARC,
1875 ocm, &dcr_read_ocm, &dcr_write_ocm);
1876 ppc_dcr_register(env, OCM0_ISACNTL,
1877 ocm, &dcr_read_ocm, &dcr_write_ocm);
1878 ppc_dcr_register(env, OCM0_DSARC,
1879 ocm, &dcr_read_ocm, &dcr_write_ocm);
1880 ppc_dcr_register(env, OCM0_DSACNTL,
1881 ocm, &dcr_read_ocm, &dcr_write_ocm);
1885 /*****************************************************************************/
1886 /* I2C controller */
1887 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1888 struct ppc4xx_i2c_t {
1889 target_phys_addr_t base;
1908 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1914 printf("%s: addr " PADDRX "\n", __func__, addr);
1917 switch (addr - i2c->base) {
1919 // i2c_readbyte(&i2c->mdata);
1959 ret = i2c->xtcntlss;
1962 ret = i2c->directcntl;
1969 printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret);
1975 static void ppc4xx_i2c_writeb (void *opaque,
1976 target_phys_addr_t addr, uint32_t value)
1981 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1984 switch (addr - i2c->base) {
1987 // i2c_sendbyte(&i2c->mdata);
2002 i2c->mdcntl = value & 0xDF;
2005 i2c->sts &= ~(value & 0x0A);
2008 i2c->extsts &= ~(value & 0x8F);
2017 i2c->clkdiv = value;
2020 i2c->intrmsk = value;
2023 i2c->xfrcnt = value & 0x77;
2026 i2c->xtcntlss = value;
2029 i2c->directcntl = value & 0x7;
2034 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
2039 printf("%s: addr " PADDRX "\n", __func__, addr);
2041 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
2042 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
2047 static void ppc4xx_i2c_writew (void *opaque,
2048 target_phys_addr_t addr, uint32_t value)
2051 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2053 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
2054 ppc4xx_i2c_writeb(opaque, addr + 1, value);
2057 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
2062 printf("%s: addr " PADDRX "\n", __func__, addr);
2064 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
2065 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
2066 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
2067 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
2072 static void ppc4xx_i2c_writel (void *opaque,
2073 target_phys_addr_t addr, uint32_t value)
2076 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2078 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
2079 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
2080 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
2081 ppc4xx_i2c_writeb(opaque, addr + 3, value);
2084 static CPUReadMemoryFunc *i2c_read[] = {
2090 static CPUWriteMemoryFunc *i2c_write[] = {
2096 static void ppc4xx_i2c_reset (void *opaque)
2109 i2c->directcntl = 0x0F;
2112 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
2113 target_phys_addr_t offset, qemu_irq irq)
2117 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
2121 ppc4xx_i2c_reset(i2c);
2123 printf("%s: offset=" PADDRX "\n", __func__, offset);
2125 ppc4xx_mmio_register(env, mmio, offset, 0x011,
2126 i2c_read, i2c_write, i2c);
2127 qemu_register_reset(ppc4xx_i2c_reset, i2c);
2131 /*****************************************************************************/
2132 /* General purpose timers */
2133 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
2134 struct ppc4xx_gpt_t {
2135 target_phys_addr_t base;
2138 struct QEMUTimer *timer;
2149 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
2152 printf("%s: addr " PADDRX "\n", __func__, addr);
2154 /* XXX: generate a bus fault */
2158 static void ppc4xx_gpt_writeb (void *opaque,
2159 target_phys_addr_t addr, uint32_t value)
2162 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2164 /* XXX: generate a bus fault */
2167 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
2170 printf("%s: addr " PADDRX "\n", __func__, addr);
2172 /* XXX: generate a bus fault */
2176 static void ppc4xx_gpt_writew (void *opaque,
2177 target_phys_addr_t addr, uint32_t value)
2180 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2182 /* XXX: generate a bus fault */
2185 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
2191 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
2196 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
2202 for (i = 0; i < 5; i++) {
2203 if (gpt->oe & mask) {
2204 /* Output is enabled */
2205 if (ppc4xx_gpt_compare(gpt, i)) {
2206 /* Comparison is OK */
2207 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
2209 /* Comparison is KO */
2210 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
2218 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
2224 for (i = 0; i < 5; i++) {
2225 if (gpt->is & gpt->im & mask)
2226 qemu_irq_raise(gpt->irqs[i]);
2228 qemu_irq_lower(gpt->irqs[i]);
2234 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
2239 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
2246 printf("%s: addr " PADDRX "\n", __func__, addr);
2249 switch (addr - gpt->base) {
2251 /* Time base counter */
2252 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
2253 gpt->tb_freq, ticks_per_sec);
2264 /* Interrupt mask */
2269 /* Interrupt status */
2273 /* Interrupt enable */
2278 idx = ((addr - gpt->base) - 0x80) >> 2;
2279 ret = gpt->comp[idx];
2283 idx = ((addr - gpt->base) - 0xC0) >> 2;
2284 ret = gpt->mask[idx];
2294 static void ppc4xx_gpt_writel (void *opaque,
2295 target_phys_addr_t addr, uint32_t value)
2301 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2304 switch (addr - gpt->base) {
2306 /* Time base counter */
2307 gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
2308 - qemu_get_clock(vm_clock);
2309 ppc4xx_gpt_compute_timer(gpt);
2313 gpt->oe = value & 0xF8000000;
2314 ppc4xx_gpt_set_outputs(gpt);
2318 gpt->ol = value & 0xF8000000;
2319 ppc4xx_gpt_set_outputs(gpt);
2322 /* Interrupt mask */
2323 gpt->im = value & 0x0000F800;
2326 /* Interrupt status set */
2327 gpt->is |= value & 0x0000F800;
2328 ppc4xx_gpt_set_irqs(gpt);
2331 /* Interrupt status clear */
2332 gpt->is &= ~(value & 0x0000F800);
2333 ppc4xx_gpt_set_irqs(gpt);
2336 /* Interrupt enable */
2337 gpt->ie = value & 0x0000F800;
2338 ppc4xx_gpt_set_irqs(gpt);
2342 idx = ((addr - gpt->base) - 0x80) >> 2;
2343 gpt->comp[idx] = value & 0xF8000000;
2344 ppc4xx_gpt_compute_timer(gpt);
2348 idx = ((addr - gpt->base) - 0xC0) >> 2;
2349 gpt->mask[idx] = value & 0xF8000000;
2350 ppc4xx_gpt_compute_timer(gpt);
2355 static CPUReadMemoryFunc *gpt_read[] = {
2361 static CPUWriteMemoryFunc *gpt_write[] = {
2367 static void ppc4xx_gpt_cb (void *opaque)
2372 ppc4xx_gpt_set_irqs(gpt);
2373 ppc4xx_gpt_set_outputs(gpt);
2374 ppc4xx_gpt_compute_timer(gpt);
2377 static void ppc4xx_gpt_reset (void *opaque)
2383 qemu_del_timer(gpt->timer);
2384 gpt->oe = 0x00000000;
2385 gpt->ol = 0x00000000;
2386 gpt->im = 0x00000000;
2387 gpt->is = 0x00000000;
2388 gpt->ie = 0x00000000;
2389 for (i = 0; i < 5; i++) {
2390 gpt->comp[i] = 0x00000000;
2391 gpt->mask[i] = 0x00000000;
2395 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
2396 target_phys_addr_t offset, qemu_irq irqs[5])
2401 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
2404 for (i = 0; i < 5; i++)
2405 gpt->irqs[i] = irqs[i];
2406 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
2407 ppc4xx_gpt_reset(gpt);
2409 printf("%s: offset=" PADDRX "\n", __func__, offset);
2411 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
2412 gpt_read, gpt_write, gpt);
2413 qemu_register_reset(ppc4xx_gpt_reset, gpt);
2417 /*****************************************************************************/
2423 MAL0_TXCASR = 0x184,
2424 MAL0_TXCARR = 0x185,
2425 MAL0_TXEOBISR = 0x186,
2426 MAL0_TXDEIR = 0x187,
2427 MAL0_RXCASR = 0x190,
2428 MAL0_RXCARR = 0x191,
2429 MAL0_RXEOBISR = 0x192,
2430 MAL0_RXDEIR = 0x193,
2431 MAL0_TXCTP0R = 0x1A0,
2432 MAL0_TXCTP1R = 0x1A1,
2433 MAL0_TXCTP2R = 0x1A2,
2434 MAL0_TXCTP3R = 0x1A3,
2435 MAL0_RXCTP0R = 0x1C0,
2436 MAL0_RXCTP1R = 0x1C1,
2441 typedef struct ppc40x_mal_t ppc40x_mal_t;
2442 struct ppc40x_mal_t {
2460 static void ppc40x_mal_reset (void *opaque);
2462 static target_ulong dcr_read_mal (void *opaque, int dcrn)
2485 ret = mal->txeobisr;
2497 ret = mal->rxeobisr;
2503 ret = mal->txctpr[0];
2506 ret = mal->txctpr[1];
2509 ret = mal->txctpr[2];
2512 ret = mal->txctpr[3];
2515 ret = mal->rxctpr[0];
2518 ret = mal->rxctpr[1];
2534 static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
2542 if (val & 0x80000000)
2543 ppc40x_mal_reset(mal);
2544 mal->cfg = val & 0x00FFC087;
2551 mal->ier = val & 0x0000001F;
2554 mal->txcasr = val & 0xF0000000;
2557 mal->txcarr = val & 0xF0000000;
2561 mal->txeobisr &= ~val;
2565 mal->txdeir &= ~val;
2568 mal->rxcasr = val & 0xC0000000;
2571 mal->rxcarr = val & 0xC0000000;
2575 mal->rxeobisr &= ~val;
2579 mal->rxdeir &= ~val;
2593 mal->txctpr[idx] = val;
2601 mal->rxctpr[idx] = val;
2605 goto update_rx_size;
2609 mal->rcbs[idx] = val & 0x000000FF;
2614 static void ppc40x_mal_reset (void *opaque)
2619 mal->cfg = 0x0007C000;
2620 mal->esr = 0x00000000;
2621 mal->ier = 0x00000000;
2622 mal->rxcasr = 0x00000000;
2623 mal->rxdeir = 0x00000000;
2624 mal->rxeobisr = 0x00000000;
2625 mal->txcasr = 0x00000000;
2626 mal->txdeir = 0x00000000;
2627 mal->txeobisr = 0x00000000;
2630 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
2635 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
2637 for (i = 0; i < 4; i++)
2638 mal->irqs[i] = irqs[i];
2639 ppc40x_mal_reset(mal);
2640 qemu_register_reset(&ppc40x_mal_reset, mal);
2641 ppc_dcr_register(env, MAL0_CFG,
2642 mal, &dcr_read_mal, &dcr_write_mal);
2643 ppc_dcr_register(env, MAL0_ESR,
2644 mal, &dcr_read_mal, &dcr_write_mal);
2645 ppc_dcr_register(env, MAL0_IER,
2646 mal, &dcr_read_mal, &dcr_write_mal);
2647 ppc_dcr_register(env, MAL0_TXCASR,
2648 mal, &dcr_read_mal, &dcr_write_mal);
2649 ppc_dcr_register(env, MAL0_TXCARR,
2650 mal, &dcr_read_mal, &dcr_write_mal);
2651 ppc_dcr_register(env, MAL0_TXEOBISR,
2652 mal, &dcr_read_mal, &dcr_write_mal);
2653 ppc_dcr_register(env, MAL0_TXDEIR,
2654 mal, &dcr_read_mal, &dcr_write_mal);
2655 ppc_dcr_register(env, MAL0_RXCASR,
2656 mal, &dcr_read_mal, &dcr_write_mal);
2657 ppc_dcr_register(env, MAL0_RXCARR,
2658 mal, &dcr_read_mal, &dcr_write_mal);
2659 ppc_dcr_register(env, MAL0_RXEOBISR,
2660 mal, &dcr_read_mal, &dcr_write_mal);
2661 ppc_dcr_register(env, MAL0_RXDEIR,
2662 mal, &dcr_read_mal, &dcr_write_mal);
2663 ppc_dcr_register(env, MAL0_TXCTP0R,
2664 mal, &dcr_read_mal, &dcr_write_mal);
2665 ppc_dcr_register(env, MAL0_TXCTP1R,
2666 mal, &dcr_read_mal, &dcr_write_mal);
2667 ppc_dcr_register(env, MAL0_TXCTP2R,
2668 mal, &dcr_read_mal, &dcr_write_mal);
2669 ppc_dcr_register(env, MAL0_TXCTP3R,
2670 mal, &dcr_read_mal, &dcr_write_mal);
2671 ppc_dcr_register(env, MAL0_RXCTP0R,
2672 mal, &dcr_read_mal, &dcr_write_mal);
2673 ppc_dcr_register(env, MAL0_RXCTP1R,
2674 mal, &dcr_read_mal, &dcr_write_mal);
2675 ppc_dcr_register(env, MAL0_RCBS0,
2676 mal, &dcr_read_mal, &dcr_write_mal);
2677 ppc_dcr_register(env, MAL0_RCBS1,
2678 mal, &dcr_read_mal, &dcr_write_mal);
2682 /*****************************************************************************/
2684 void ppc40x_core_reset (CPUState *env)
2688 printf("Reset PowerPC core\n");
2690 dbsr = env->spr[SPR_40x_DBSR];
2691 dbsr &= ~0x00000300;
2693 env->spr[SPR_40x_DBSR] = dbsr;
2697 void ppc40x_chip_reset (CPUState *env)
2701 printf("Reset PowerPC chip\n");
2703 /* XXX: TODO reset all internal peripherals */
2704 dbsr = env->spr[SPR_40x_DBSR];
2705 dbsr &= ~0x00000300;
2707 env->spr[SPR_40x_DBSR] = dbsr;
2711 void ppc40x_system_reset (CPUState *env)
2713 printf("Reset PowerPC system\n");
2714 qemu_system_reset_request();
2717 void store_40x_dbcr0 (CPUState *env, uint32_t val)
2719 switch ((val >> 28) & 0x3) {
2725 ppc40x_core_reset(env);
2729 ppc40x_chip_reset(env);
2733 ppc40x_system_reset(env);
2738 /*****************************************************************************/
2741 PPC405CR_CPC0_PLLMR = 0x0B0,
2742 PPC405CR_CPC0_CR0 = 0x0B1,
2743 PPC405CR_CPC0_CR1 = 0x0B2,
2744 PPC405CR_CPC0_PSR = 0x0B4,
2745 PPC405CR_CPC0_JTAGID = 0x0B5,
2746 PPC405CR_CPC0_ER = 0x0B9,
2747 PPC405CR_CPC0_FR = 0x0BA,
2748 PPC405CR_CPC0_SR = 0x0BB,
2752 PPC405CR_CPU_CLK = 0,
2753 PPC405CR_TMR_CLK = 1,
2754 PPC405CR_PLB_CLK = 2,
2755 PPC405CR_SDRAM_CLK = 3,
2756 PPC405CR_OPB_CLK = 4,
2757 PPC405CR_EXT_CLK = 5,
2758 PPC405CR_UART_CLK = 6,
2759 PPC405CR_CLK_NB = 7,
2762 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
2763 struct ppc405cr_cpc_t {
2764 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2775 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
2777 uint64_t VCO_out, PLL_out;
2778 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
2781 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
2782 if (cpc->pllmr & 0x80000000) {
2783 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
2784 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
2786 VCO_out = cpc->sysclk * M;
2787 if (VCO_out < 400000000 || VCO_out > 800000000) {
2788 /* PLL cannot lock */
2789 cpc->pllmr &= ~0x80000000;
2792 PLL_out = VCO_out / D2;
2797 PLL_out = cpc->sysclk * M;
2800 if (cpc->cr1 & 0x00800000)
2801 TMR_clk = cpc->sysclk; /* Should have a separate clock */
2804 PLB_clk = CPU_clk / D0;
2805 SDRAM_clk = PLB_clk;
2806 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
2807 OPB_clk = PLB_clk / D0;
2808 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
2809 EXT_clk = PLB_clk / D0;
2810 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
2811 UART_clk = CPU_clk / D0;
2812 /* Setup CPU clocks */
2813 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
2814 /* Setup time-base clock */
2815 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
2816 /* Setup PLB clock */
2817 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
2818 /* Setup SDRAM clock */
2819 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
2820 /* Setup OPB clock */
2821 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
2822 /* Setup external clock */
2823 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
2824 /* Setup UART clock */
2825 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
2828 static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
2830 ppc405cr_cpc_t *cpc;
2835 case PPC405CR_CPC0_PLLMR:
2838 case PPC405CR_CPC0_CR0:
2841 case PPC405CR_CPC0_CR1:
2844 case PPC405CR_CPC0_PSR:
2847 case PPC405CR_CPC0_JTAGID:
2850 case PPC405CR_CPC0_ER:
2853 case PPC405CR_CPC0_FR:
2856 case PPC405CR_CPC0_SR:
2857 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
2860 /* Avoid gcc warning */
2868 static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
2870 ppc405cr_cpc_t *cpc;
2874 case PPC405CR_CPC0_PLLMR:
2875 cpc->pllmr = val & 0xFFF77C3F;
2877 case PPC405CR_CPC0_CR0:
2878 cpc->cr0 = val & 0x0FFFFFFE;
2880 case PPC405CR_CPC0_CR1:
2881 cpc->cr1 = val & 0x00800000;
2883 case PPC405CR_CPC0_PSR:
2886 case PPC405CR_CPC0_JTAGID:
2889 case PPC405CR_CPC0_ER:
2890 cpc->er = val & 0xBFFC0000;
2892 case PPC405CR_CPC0_FR:
2893 cpc->fr = val & 0xBFFC0000;
2895 case PPC405CR_CPC0_SR:
2901 static void ppc405cr_cpc_reset (void *opaque)
2903 ppc405cr_cpc_t *cpc;
2907 /* Compute PLLMR value from PSR settings */
2908 cpc->pllmr = 0x80000000;
2910 switch ((cpc->psr >> 30) & 3) {
2913 cpc->pllmr &= ~0x80000000;
2917 cpc->pllmr |= 5 << 16;
2921 cpc->pllmr |= 4 << 16;
2925 cpc->pllmr |= 2 << 16;
2929 D = (cpc->psr >> 28) & 3;
2930 cpc->pllmr |= (D + 1) << 20;
2932 D = (cpc->psr >> 25) & 7;
2947 D = (cpc->psr >> 23) & 3;
2948 cpc->pllmr |= D << 26;
2950 D = (cpc->psr >> 21) & 3;
2951 cpc->pllmr |= D << 10;
2953 D = (cpc->psr >> 17) & 3;
2954 cpc->pllmr |= D << 24;
2955 cpc->cr0 = 0x0000003C;
2956 cpc->cr1 = 0x2B0D8800;
2957 cpc->er = 0x00000000;
2958 cpc->fr = 0x00000000;
2959 ppc405cr_clk_setup(cpc);
2962 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2966 /* XXX: this should be read from IO pins */
2967 cpc->psr = 0x00000000; /* 8 bits ROM */
2969 D = 0x2; /* Divide by 4 */
2970 cpc->psr |= D << 30;
2972 D = 0x1; /* Divide by 2 */
2973 cpc->psr |= D << 28;
2975 D = 0x1; /* Divide by 2 */
2976 cpc->psr |= D << 23;
2978 D = 0x5; /* M = 16 */
2979 cpc->psr |= D << 25;
2981 D = 0x1; /* Divide by 2 */
2982 cpc->psr |= D << 21;
2984 D = 0x2; /* Divide by 4 */
2985 cpc->psr |= D << 17;
2988 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2991 ppc405cr_cpc_t *cpc;
2993 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2995 memcpy(cpc->clk_setup, clk_setup,
2996 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2997 cpc->sysclk = sysclk;
2998 cpc->jtagid = 0x42051049;
2999 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
3000 &dcr_read_crcpc, &dcr_write_crcpc);
3001 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
3002 &dcr_read_crcpc, &dcr_write_crcpc);
3003 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
3004 &dcr_read_crcpc, &dcr_write_crcpc);
3005 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
3006 &dcr_read_crcpc, &dcr_write_crcpc);
3007 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
3008 &dcr_read_crcpc, &dcr_write_crcpc);
3009 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
3010 &dcr_read_crcpc, &dcr_write_crcpc);
3011 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
3012 &dcr_read_crcpc, &dcr_write_crcpc);
3013 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
3014 &dcr_read_crcpc, &dcr_write_crcpc);
3015 ppc405cr_clk_init(cpc);
3016 qemu_register_reset(ppc405cr_cpc_reset, cpc);
3017 ppc405cr_cpc_reset(cpc);
3021 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
3022 target_phys_addr_t ram_sizes[4],
3023 uint32_t sysclk, qemu_irq **picp,
3024 ram_addr_t *offsetp, int do_init)
3026 clk_setup_t clk_setup[PPC405CR_CLK_NB];
3027 qemu_irq dma_irqs[4];
3029 ppc4xx_mmio_t *mmio;
3030 qemu_irq *pic, *irqs;
3034 memset(clk_setup, 0, sizeof(clk_setup));
3035 env = ppc405_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
3036 &clk_setup[PPC405CR_TMR_CLK], sysclk);
3037 /* Memory mapped devices registers */
3038 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3040 ppc4xx_plb_init(env);
3041 /* PLB to OPB bridge */
3042 ppc4xx_pob_init(env);
3044 ppc4xx_opba_init(env, mmio, 0x600);
3045 /* Universal interrupt controller */
3046 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3047 irqs[PPCUIC_OUTPUT_INT] =
3048 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
3049 irqs[PPCUIC_OUTPUT_CINT] =
3050 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
3051 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3053 /* SDRAM controller */
3054 ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
3056 for (i = 0; i < 4; i++)
3057 offset += ram_sizes[i];
3058 /* External bus controller */
3059 ppc405_ebc_init(env);
3060 /* DMA controller */
3061 dma_irqs[0] = pic[26];
3062 dma_irqs[1] = pic[25];
3063 dma_irqs[2] = pic[24];
3064 dma_irqs[3] = pic[23];
3065 ppc405_dma_init(env, dma_irqs);
3067 if (serial_hds[0] != NULL) {
3068 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3070 if (serial_hds[1] != NULL) {
3071 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3073 /* IIC controller */
3074 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3076 ppc405_gpio_init(env, mmio, 0x700);
3078 ppc405cr_cpc_init(env, clk_setup, sysclk);
3084 /*****************************************************************************/
3088 PPC405EP_CPC0_PLLMR0 = 0x0F0,
3089 PPC405EP_CPC0_BOOT = 0x0F1,
3090 PPC405EP_CPC0_EPCTL = 0x0F3,
3091 PPC405EP_CPC0_PLLMR1 = 0x0F4,
3092 PPC405EP_CPC0_UCR = 0x0F5,
3093 PPC405EP_CPC0_SRR = 0x0F6,
3094 PPC405EP_CPC0_JTAGID = 0x0F7,
3095 PPC405EP_CPC0_PCI = 0x0F9,
3097 PPC405EP_CPC0_ER = xxx,
3098 PPC405EP_CPC0_FR = xxx,
3099 PPC405EP_CPC0_SR = xxx,
3104 PPC405EP_CPU_CLK = 0,
3105 PPC405EP_PLB_CLK = 1,
3106 PPC405EP_OPB_CLK = 2,
3107 PPC405EP_EBC_CLK = 3,
3108 PPC405EP_MAL_CLK = 4,
3109 PPC405EP_PCI_CLK = 5,
3110 PPC405EP_UART0_CLK = 6,
3111 PPC405EP_UART1_CLK = 7,
3112 PPC405EP_CLK_NB = 8,
3115 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
3116 struct ppc405ep_cpc_t {
3118 clk_setup_t clk_setup[PPC405EP_CLK_NB];
3126 /* Clock and power management */
3132 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
3134 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
3135 uint32_t UART0_clk, UART1_clk;
3136 uint64_t VCO_out, PLL_out;
3140 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
3141 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
3142 // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
3143 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
3144 // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
3145 VCO_out = cpc->sysclk * M * D;
3146 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
3147 /* Error - unlock the PLL */
3148 printf("VCO out of range %" PRIu64 "\n", VCO_out);
3150 cpc->pllmr[1] &= ~0x80000000;
3154 PLL_out = VCO_out / D;
3155 /* Pretend the PLL is locked */
3156 cpc->boot |= 0x00000001;
3161 PLL_out = cpc->sysclk;
3162 if (cpc->pllmr[1] & 0x40000000) {
3163 /* Pretend the PLL is not locked */
3164 cpc->boot &= ~0x00000001;
3167 /* Now, compute all other clocks */
3168 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
3170 // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
3172 CPU_clk = PLL_out / D;
3173 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
3175 // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
3177 PLB_clk = CPU_clk / D;
3178 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
3180 // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
3182 OPB_clk = PLB_clk / D;
3183 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
3185 // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
3187 EBC_clk = PLB_clk / D;
3188 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
3190 // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
3192 MAL_clk = PLB_clk / D;
3193 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
3195 // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
3197 PCI_clk = PLB_clk / D;
3198 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
3200 // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
3202 UART0_clk = PLL_out / D;
3203 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
3205 // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
3207 UART1_clk = PLL_out / D;
3209 printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
3210 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
3211 printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
3212 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
3213 UART0_clk, UART1_clk);
3214 printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
3215 cpc->clk_setup[PPC405EP_CPU_CLK].opaque);
3217 /* Setup CPU clocks */
3218 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
3219 /* Setup PLB clock */
3220 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
3221 /* Setup OPB clock */
3222 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
3223 /* Setup external clock */
3224 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
3225 /* Setup MAL clock */
3226 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
3227 /* Setup PCI clock */
3228 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
3229 /* Setup UART0 clock */
3230 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
3231 /* Setup UART1 clock */
3232 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
3235 static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
3237 ppc405ep_cpc_t *cpc;
3242 case PPC405EP_CPC0_BOOT:
3245 case PPC405EP_CPC0_EPCTL:
3248 case PPC405EP_CPC0_PLLMR0:
3249 ret = cpc->pllmr[0];
3251 case PPC405EP_CPC0_PLLMR1:
3252 ret = cpc->pllmr[1];
3254 case PPC405EP_CPC0_UCR:
3257 case PPC405EP_CPC0_SRR:
3260 case PPC405EP_CPC0_JTAGID:
3263 case PPC405EP_CPC0_PCI:
3267 /* Avoid gcc warning */
3275 static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
3277 ppc405ep_cpc_t *cpc;
3281 case PPC405EP_CPC0_BOOT:
3282 /* Read-only register */
3284 case PPC405EP_CPC0_EPCTL:
3285 /* Don't care for now */
3286 cpc->epctl = val & 0xC00000F3;
3288 case PPC405EP_CPC0_PLLMR0:
3289 cpc->pllmr[0] = val & 0x00633333;
3290 ppc405ep_compute_clocks(cpc);
3292 case PPC405EP_CPC0_PLLMR1:
3293 cpc->pllmr[1] = val & 0xC0F73FFF;
3294 ppc405ep_compute_clocks(cpc);
3296 case PPC405EP_CPC0_UCR:
3297 /* UART control - don't care for now */
3298 cpc->ucr = val & 0x003F7F7F;
3300 case PPC405EP_CPC0_SRR:
3303 case PPC405EP_CPC0_JTAGID:
3306 case PPC405EP_CPC0_PCI:
3312 static void ppc405ep_cpc_reset (void *opaque)
3314 ppc405ep_cpc_t *cpc = opaque;
3316 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
3317 cpc->epctl = 0x00000000;
3318 cpc->pllmr[0] = 0x00011010;
3319 cpc->pllmr[1] = 0x40000000;
3320 cpc->ucr = 0x00000000;
3321 cpc->srr = 0x00040000;
3322 cpc->pci = 0x00000000;
3323 cpc->er = 0x00000000;
3324 cpc->fr = 0x00000000;
3325 cpc->sr = 0x00000000;
3326 ppc405ep_compute_clocks(cpc);
3329 /* XXX: sysclk should be between 25 and 100 MHz */
3330 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
3333 ppc405ep_cpc_t *cpc;
3335 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
3337 memcpy(cpc->clk_setup, clk_setup,
3338 PPC405EP_CLK_NB * sizeof(clk_setup_t));
3339 cpc->jtagid = 0x20267049;
3340 cpc->sysclk = sysclk;
3341 ppc405ep_cpc_reset(cpc);
3342 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
3343 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
3344 &dcr_read_epcpc, &dcr_write_epcpc);
3345 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
3346 &dcr_read_epcpc, &dcr_write_epcpc);
3347 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
3348 &dcr_read_epcpc, &dcr_write_epcpc);
3349 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
3350 &dcr_read_epcpc, &dcr_write_epcpc);
3351 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
3352 &dcr_read_epcpc, &dcr_write_epcpc);
3353 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
3354 &dcr_read_epcpc, &dcr_write_epcpc);
3355 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
3356 &dcr_read_epcpc, &dcr_write_epcpc);
3357 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
3358 &dcr_read_epcpc, &dcr_write_epcpc);
3360 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
3361 &dcr_read_epcpc, &dcr_write_epcpc);
3362 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
3363 &dcr_read_epcpc, &dcr_write_epcpc);
3364 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
3365 &dcr_read_epcpc, &dcr_write_epcpc);
3370 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
3371 target_phys_addr_t ram_sizes[2],
3372 uint32_t sysclk, qemu_irq **picp,
3373 ram_addr_t *offsetp, int do_init)
3375 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
3376 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
3378 ppc4xx_mmio_t *mmio;
3379 qemu_irq *pic, *irqs;
3383 memset(clk_setup, 0, sizeof(clk_setup));
3385 env = ppc405_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
3386 &tlb_clk_setup, sysclk);
3387 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
3388 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
3389 /* Internal devices init */
3390 /* Memory mapped devices registers */
3391 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3393 ppc4xx_plb_init(env);
3394 /* PLB to OPB bridge */
3395 ppc4xx_pob_init(env);
3397 ppc4xx_opba_init(env, mmio, 0x600);
3398 /* Universal interrupt controller */
3399 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3400 irqs[PPCUIC_OUTPUT_INT] =
3401 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
3402 irqs[PPCUIC_OUTPUT_CINT] =
3403 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
3404 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3406 /* SDRAM controller */
3407 ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
3409 for (i = 0; i < 2; i++)
3410 offset += ram_sizes[i];
3411 /* External bus controller */
3412 ppc405_ebc_init(env);
3413 /* DMA controller */
3414 dma_irqs[0] = pic[26];
3415 dma_irqs[1] = pic[25];
3416 dma_irqs[2] = pic[24];
3417 dma_irqs[3] = pic[23];
3418 ppc405_dma_init(env, dma_irqs);
3419 /* IIC controller */
3420 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3422 ppc405_gpio_init(env, mmio, 0x700);
3424 if (serial_hds[0] != NULL) {
3425 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3427 if (serial_hds[1] != NULL) {
3428 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3431 ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
3434 gpt_irqs[0] = pic[12];
3435 gpt_irqs[1] = pic[11];
3436 gpt_irqs[2] = pic[10];
3437 gpt_irqs[3] = pic[9];
3438 gpt_irqs[4] = pic[8];
3439 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
3441 /* Uses pic[28], pic[15], pic[13] */
3443 mal_irqs[0] = pic[20];
3444 mal_irqs[1] = pic[19];
3445 mal_irqs[2] = pic[18];
3446 mal_irqs[3] = pic[17];
3447 ppc405_mal_init(env, mal_irqs);
3449 /* Uses pic[22], pic[16], pic[14] */
3451 ppc405ep_cpc_init(env, clk_setup, sysclk);