2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 //#define HARD_DEBUG_PPC_IO
37 //#define DEBUG_PPC_IO
39 /* SMP is not enabled, for now */
44 #define BIOS_SIZE (1024 * 1024)
45 #define BIOS_FILENAME "ppc_rom.bin"
46 #define KERNEL_LOAD_ADDR 0x01000000
47 #define INITRD_LOAD_ADDR 0x01800000
49 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
53 #if defined (HARD_DEBUG_PPC_IO)
54 #define PPC_IO_DPRINTF(fmt, ...) \
56 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
57 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
59 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
62 #elif defined (DEBUG_PPC_IO)
63 #define PPC_IO_DPRINTF(fmt, ...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
65 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
68 /* Constants for devices init */
69 static const int ide_iobase[2] = { 0x1f0, 0x170 };
70 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
71 static const int ide_irq[2] = { 13, 13 };
73 #define NE2000_NB_MAX 6
75 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
76 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
78 //static PITState *pit;
80 /* ISA IO ports bridge */
81 #define PPC_IO_BASE 0x80000000
84 /* Speaker port 0x61 */
85 static int speaker_data_on;
86 static int dummy_refresh_clock;
89 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
92 speaker_data_on = (val >> 1) & 1;
93 pit_set_gate(pit, 2, val & 1);
97 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
101 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
102 dummy_refresh_clock ^= 1;
103 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
104 (dummy_refresh_clock << 4);
109 /* PCI intack register */
110 /* Read-only register (?) */
111 static void _PPC_intack_write (void *opaque,
112 target_phys_addr_t addr, uint32_t value)
114 // printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
117 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
121 if ((addr & 0xf) == 0)
122 retval = pic_intack_read(isa_pic);
123 // printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
128 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
130 return _PPC_intack_read(addr);
133 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
135 #ifdef TARGET_WORDS_BIGENDIAN
136 return bswap16(_PPC_intack_read(addr));
138 return _PPC_intack_read(addr);
142 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
144 #ifdef TARGET_WORDS_BIGENDIAN
145 return bswap32(_PPC_intack_read(addr));
147 return _PPC_intack_read(addr);
151 static CPUWriteMemoryFunc *PPC_intack_write[] = {
157 static CPUReadMemoryFunc *PPC_intack_read[] = {
163 /* PowerPC control and status registers */
169 /* Control and status */
174 /* General purpose registers */
187 /* Error diagnostic */
190 static void PPC_XCSR_writeb (void *opaque,
191 target_phys_addr_t addr, uint32_t value)
193 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
196 static void PPC_XCSR_writew (void *opaque,
197 target_phys_addr_t addr, uint32_t value)
199 #ifdef TARGET_WORDS_BIGENDIAN
200 value = bswap16(value);
202 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
205 static void PPC_XCSR_writel (void *opaque,
206 target_phys_addr_t addr, uint32_t value)
208 #ifdef TARGET_WORDS_BIGENDIAN
209 value = bswap32(value);
211 printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
214 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
218 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
223 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
227 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
228 #ifdef TARGET_WORDS_BIGENDIAN
229 retval = bswap16(retval);
235 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
239 printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
240 #ifdef TARGET_WORDS_BIGENDIAN
241 retval = bswap32(retval);
247 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
253 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
260 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
261 typedef struct sysctrl_t {
272 STATE_HARDFILE = 0x01,
275 static sysctrl_t *sysctrl;
277 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
279 sysctrl_t *sysctrl = opaque;
281 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
283 sysctrl->fake_io[addr - 0x0398] = val;
286 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
288 sysctrl_t *sysctrl = opaque;
290 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
291 sysctrl->fake_io[addr - 0x0398]);
292 return sysctrl->fake_io[addr - 0x0398];
295 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
297 sysctrl_t *sysctrl = opaque;
299 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
300 addr - PPC_IO_BASE, val);
303 /* Special port 92 */
304 /* Check soft reset asked */
306 qemu_irq_raise(sysctrl->reset_irq);
308 qemu_irq_lower(sysctrl->reset_irq);
318 /* Motorola CPU configuration register : read-only */
321 /* Motorola base module feature register : read-only */
324 /* Motorola base module status register : read-only */
327 /* Hardfile light register */
329 sysctrl->state |= STATE_HARDFILE;
331 sysctrl->state &= ~STATE_HARDFILE;
334 /* Password protect 1 register */
335 if (sysctrl->nvram != NULL)
336 m48t59_toggle_lock(sysctrl->nvram, 1);
339 /* Password protect 2 register */
340 if (sysctrl->nvram != NULL)
341 m48t59_toggle_lock(sysctrl->nvram, 2);
344 /* L2 invalidate register */
345 // tlb_flush(first_cpu, 1);
348 /* system control register */
349 sysctrl->syscontrol = val & 0x0F;
352 /* I/O map type register */
353 sysctrl->contiguous_map = val & 0x01;
356 printf("ERROR: unaffected IO port write: %04" PRIx32
357 " => %02" PRIx32"\n", addr, val);
362 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
364 sysctrl_t *sysctrl = opaque;
365 uint32_t retval = 0xFF;
369 /* Special port 92 */
373 /* Motorola CPU configuration register */
374 retval = 0xEF; /* MPC750 */
377 /* Motorola Base module feature register */
378 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
381 /* Motorola base module status register */
382 retval = 0xE0; /* Standard MPC750 */
385 /* Equipment present register:
387 * no upgrade processor
388 * no cards in PCI slots
394 /* Motorola base module extended feature register */
395 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
398 /* L2 invalidate: don't care */
405 /* system control register
406 * 7 - 6 / 1 - 0: L2 cache enable
408 retval = sysctrl->syscontrol;
412 retval = 0x03; /* no L2 cache */
415 /* I/O map type register */
416 retval = sysctrl->contiguous_map;
419 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
422 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
423 addr - PPC_IO_BASE, retval);
428 static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
432 if (sysctrl->contiguous_map == 0) {
433 /* 64 KB contiguous space for IOs */
436 /* 8 MB non-contiguous space for IOs */
437 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
443 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
446 sysctrl_t *sysctrl = opaque;
448 addr = prep_IO_address(sysctrl, addr);
449 cpu_outb(NULL, addr, value);
452 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
454 sysctrl_t *sysctrl = opaque;
457 addr = prep_IO_address(sysctrl, addr);
458 ret = cpu_inb(NULL, addr);
463 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
466 sysctrl_t *sysctrl = opaque;
468 addr = prep_IO_address(sysctrl, addr);
469 #ifdef TARGET_WORDS_BIGENDIAN
470 value = bswap16(value);
472 PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
473 cpu_outw(NULL, addr, value);
476 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
478 sysctrl_t *sysctrl = opaque;
481 addr = prep_IO_address(sysctrl, addr);
482 ret = cpu_inw(NULL, addr);
483 #ifdef TARGET_WORDS_BIGENDIAN
486 PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
491 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
494 sysctrl_t *sysctrl = opaque;
496 addr = prep_IO_address(sysctrl, addr);
497 #ifdef TARGET_WORDS_BIGENDIAN
498 value = bswap32(value);
500 PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
501 cpu_outl(NULL, addr, value);
504 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
506 sysctrl_t *sysctrl = opaque;
509 addr = prep_IO_address(sysctrl, addr);
510 ret = cpu_inl(NULL, addr);
511 #ifdef TARGET_WORDS_BIGENDIAN
514 PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
519 static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
525 static CPUReadMemoryFunc *PPC_prep_io_read[] = {
531 #define NVRAM_SIZE 0x2000
533 /* PowerPC PREP hardware initialisation */
534 static void ppc_prep_init (ram_addr_t ram_size,
535 const char *boot_device,
536 const char *kernel_filename,
537 const char *kernel_cmdline,
538 const char *initrd_filename,
539 const char *cpu_model)
541 CPUState *env = NULL, *envs[MAX_CPUS];
546 int linux_boot, i, nb_nics1, bios_size;
547 ram_addr_t ram_offset, bios_offset;
548 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
553 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
554 BlockDriverState *fd[MAX_FD];
556 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
558 linux_boot = (kernel_filename != NULL);
561 if (cpu_model == NULL)
562 cpu_model = "default";
563 for (i = 0; i < smp_cpus; i++) {
564 env = cpu_init(cpu_model);
566 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
569 if (env->flags & POWERPC_FLAG_RTC_CLK) {
570 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
571 cpu_ppc_tb_init(env, 7812500UL);
573 /* Set time-base frequency to 100 Mhz */
574 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
576 qemu_register_reset(&cpu_ppc_reset, 0, env);
581 ram_offset = qemu_ram_alloc(ram_size);
582 cpu_register_physical_memory(0, ram_size, ram_offset);
584 /* allocate and load BIOS */
585 bios_offset = qemu_ram_alloc(BIOS_SIZE);
586 if (bios_name == NULL)
587 bios_name = BIOS_FILENAME;
588 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
589 bios_size = get_image_size(buf);
590 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
591 target_phys_addr_t bios_addr;
592 bios_size = (bios_size + 0xfff) & ~0xfff;
593 bios_addr = (uint32_t)(-bios_size);
594 cpu_register_physical_memory(bios_addr, bios_size,
595 bios_offset | IO_MEM_ROM);
596 bios_size = load_image_targphys(buf, bios_addr, bios_size);
598 if (bios_size < 0 || bios_size > BIOS_SIZE) {
599 hw_error("qemu: could not load PPC PREP bios '%s'\n", buf);
601 if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
602 hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
606 kernel_base = KERNEL_LOAD_ADDR;
607 /* now we can load the kernel */
608 kernel_size = load_image_targphys(kernel_filename, kernel_base,
609 ram_size - kernel_base);
610 if (kernel_size < 0) {
611 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
615 if (initrd_filename) {
616 initrd_base = INITRD_LOAD_ADDR;
617 initrd_size = load_image_targphys(initrd_filename, initrd_base,
618 ram_size - initrd_base);
619 if (initrd_size < 0) {
620 hw_error("qemu: could not load initial ram disk '%s'\n",
627 ppc_boot_device = 'm';
633 ppc_boot_device = '\0';
634 /* For now, OHW cannot boot from the network. */
635 for (i = 0; boot_device[i] != '\0'; i++) {
636 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
637 ppc_boot_device = boot_device[i];
641 if (ppc_boot_device == '\0') {
642 fprintf(stderr, "No valid boot device for Mac99 machine\n");
647 isa_mem_base = 0xc0000000;
648 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
649 hw_error("Only 6xx bus is supported on PREP machine\n");
651 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
652 pci_bus = pci_prep_init(i8259);
653 // pci_bus = i440fx_init();
654 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
655 PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
656 PPC_prep_io_write, sysctrl);
657 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
659 /* init basic PC hardware */
660 pci_vga_init(pci_bus, 0, 0);
661 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
662 // pit = pit_init(0x40, i8259[0]);
663 rtc_init(0x70, i8259[8], 2000);
665 serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
667 if (nb_nics1 > NE2000_NB_MAX)
668 nb_nics1 = NE2000_NB_MAX;
669 for(i = 0; i < nb_nics1; i++) {
670 if (nd_table[i].model == NULL) {
671 nd_table[i].model = "ne2k_isa";
673 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
674 isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
676 pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
680 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
681 fprintf(stderr, "qemu: too many IDE bus\n");
685 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
686 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
688 hd[i] = drives_table[index].bdrv;
693 for(i = 0; i < MAX_IDE_BUS; i++) {
694 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
698 i8042_init(i8259[1], i8259[12], 0x60);
702 for(i = 0; i < MAX_FD; i++) {
703 index = drive_get_index(IF_FLOPPY, 0, i);
705 fd[i] = drives_table[index].bdrv;
709 fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
711 /* Register speaker port */
712 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
713 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
714 /* Register fake IO ports for PREP */
715 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
716 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
717 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
718 /* System control ports */
719 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
720 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
721 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
722 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
723 /* PCI intack location */
724 PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
725 PPC_intack_write, NULL);
726 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
727 /* PowerPC control and status register group */
729 PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
731 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
735 usb_ohci_init_pci(pci_bus, 3, -1);
738 m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
741 sysctrl->nvram = m48t59;
743 /* Initialise NVRAM */
744 nvram.opaque = m48t59;
745 nvram.read_fn = &m48t59_read;
746 nvram.write_fn = &m48t59_write;
747 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
748 kernel_base, kernel_size,
750 initrd_base, initrd_size,
751 /* XXX: need an option to load a NVRAM image */
753 graphic_width, graphic_height, graphic_depth);
755 /* Special port to get debug messages from Open-Firmware */
756 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
759 static QEMUMachine prep_machine = {
761 .desc = "PowerPC PREP platform",
762 .init = ppc_prep_init,
763 .max_cpus = MAX_CPUS,
766 static void prep_machine_init(void)
768 qemu_register_machine(&prep_machine);
771 machine_init(prep_machine_init);