2 * QEMU JAZZ RC4030 chipset
4 * Copyright (c) 2007-2008 Hervé Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu-timer.h"
29 //#define DEBUG_RC4030
32 static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
33 "network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
36 typedef struct rc4030State
38 uint32_t config; /* 0x0000: RC4030 config register */
39 uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
42 uint32_t dma_regs[8][4];
43 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
44 uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
47 uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
48 uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
49 uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
50 uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
51 uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
52 uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
56 uint32_t nvram_protect; /* 0x0220: NV ram protect register */
58 uint32_t rem_speed[15];
59 uint32_t imr_jazz; /* Local bus int enable mask */
60 uint32_t isr_jazz; /* Local bus int source */
63 QEMUTimer *periodic_timer;
64 uint32_t itr; /* Interval timer reload */
68 qemu_irq jazz_bus_irq;
71 static void set_next_tick(rc4030State *s)
73 qemu_irq_lower(s->timer_irq);
76 tm_hz = 1000 / (s->itr + 1);
78 qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / tm_hz);
81 /* called for accesses to rc4030 */
82 static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
84 rc4030State *s = opaque;
88 switch (addr & ~0x3) {
89 /* Global config register */
93 /* Invalid Address register */
95 val = s->invalid_address_register;
97 /* DMA transl. table base */
101 /* DMA transl. table limit */
103 val = s->dma_tl_limit;
105 /* Remote Failed Address */
107 val = s->remote_failed_address;
109 /* Memory Failed Address */
111 val = s->memory_failed_address;
113 /* I/O Cache Byte Mask */
115 val = s->cache_bmask;
117 if (s->cache_bmask == (uint32_t)-1)
120 /* Remote Speed Registers */
136 val = s->rem_speed[(addr - 0x0070) >> 3];
138 /* DMA channel base address */
172 int entry = (addr - 0x0100) >> 5;
173 int idx = (addr & 0x1f) >> 3;
174 val = s->dma_regs[entry][idx];
185 /* NV ram protect register */
187 val = s->nvram_protect;
189 /* Interval timer count */
192 qemu_irq_lower(s->timer_irq);
200 printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr);
207 if ((addr & ~3) != 0x230)
208 printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
214 static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
216 uint32_t v = rc4030_readl(opaque, addr & ~0x3);
223 static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
225 uint32_t v = rc4030_readl(opaque, addr & ~0x3);
226 return (v >> (8 * (addr & 0x3))) & 0xff;
229 static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
231 rc4030State *s = opaque;
235 printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
238 switch (addr & ~0x3) {
239 /* Global config register */
243 /* DMA transl. table base */
245 s->dma_tl_base = val;
247 /* DMA transl. table limit */
249 s->dma_tl_limit = val;
251 /* I/O Cache Physical Tag */
255 /* I/O Cache Logical Tag */
259 /* I/O Cache Byte Mask */
261 s->cache_bmask |= val; /* HACK */
263 /* I/O Cache Buffer Window */
267 if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
268 target_phys_addr_t dests[] = { 4, 0, 8, 0x10 };
269 static int current = 0;
270 target_phys_addr_t dest = 0 + dests[current];
272 current = (current + 1) % (sizeof(dests)/sizeof(dests[0]));
273 buf = s->cache_bwin - 1;
274 cpu_physical_memory_rw(dest, &buf, 1, 1);
277 /* Remote Speed Registers */
293 s->rem_speed[(addr - 0x0070) >> 3] = val;
295 /* DMA channel base address */
329 int entry = (addr - 0x0100) >> 5;
330 int idx = (addr & 0x1f) >> 3;
331 s->dma_regs[entry][idx] = val;
338 /* Interval timer reload */
341 qemu_irq_lower(s->timer_irq);
346 printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
352 static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
354 uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
357 val = (val << 16) | (old_val & 0x0000ffff);
359 val = val | (old_val & 0xffff0000);
360 rc4030_writel(opaque, addr & ~0x3, val);
363 static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
365 uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
369 val = val | (old_val & 0xffffff00);
372 val = (val << 8) | (old_val & 0xffff00ff);
375 val = (val << 16) | (old_val & 0xff00ffff);
378 val = (val << 24) | (old_val & 0x00ffffff);
381 rc4030_writel(opaque, addr & ~0x3, val);
384 static CPUReadMemoryFunc *rc4030_read[3] = {
390 static CPUWriteMemoryFunc *rc4030_write[3] = {
396 static void update_jazz_irq(rc4030State *s)
400 pending = s->isr_jazz & s->imr_jazz;
403 if (s->isr_jazz != 0) {
405 printf("jazz pending:");
406 for (irq = 0; irq < sizeof(irq_names)/sizeof(irq_names[0]); irq++) {
407 if (s->isr_jazz & (1 << irq)) {
408 printf(" %s", irq_names[irq]);
409 if (!(s->imr_jazz & (1 << irq))) {
419 qemu_irq_raise(s->jazz_bus_irq);
421 qemu_irq_lower(s->jazz_bus_irq);
424 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
426 rc4030State *s = opaque;
429 s->isr_jazz |= 1 << irq;
431 s->isr_jazz &= ~(1 << irq);
437 static void rc4030_periodic_timer(void *opaque)
439 rc4030State *s = opaque;
442 qemu_irq_raise(s->timer_irq);
445 static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
447 rc4030State *s = opaque;
454 /* Local bus int source */
455 uint32_t pending = s->isr_jazz & s->imr_jazz;
460 //printf("returning irq %s\n", irq_names[irq]);
461 val = (irq + 1) << 2;
471 printf("rc4030: (interrupt controller) invalid read [" TARGET_FMT_lx "]\n", addr);
477 printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
483 static uint32_t int_readw(void *opaque, target_phys_addr_t addr)
486 v = int_readb(opaque, addr);
487 v |= int_readb(opaque, addr + 1) << 8;
491 static uint32_t int_readl(void *opaque, target_phys_addr_t addr)
494 v = int_readb(opaque, addr);
495 v |= int_readb(opaque, addr + 1) << 8;
496 v |= int_readb(opaque, addr + 2) << 16;
497 v |= int_readb(opaque, addr + 3) << 24;
501 static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
503 rc4030State *s = opaque;
507 printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
511 /* Local bus int enable mask */
513 s->imr_jazz = (s->imr_jazz & 0xff00) | (val << 0); update_jazz_irq(s);
516 s->imr_jazz = (s->imr_jazz & 0x00ff) | (val << 8); update_jazz_irq(s);
520 printf("rc4030: (interrupt controller) invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
526 static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
528 int_writeb(opaque, addr, val & 0xff);
529 int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
532 static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
534 int_writeb(opaque, addr, val & 0xff);
535 int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
536 int_writeb(opaque, addr + 2, (val >> 16) & 0xff);
537 int_writeb(opaque, addr + 3, (val >> 24) & 0xff);
540 static CPUReadMemoryFunc *int_read[3] = {
546 static CPUWriteMemoryFunc *int_write[3] = {
552 #define G364_512KB_RAM (0x0)
553 #define G364_2MB_RAM (0x1)
554 #define G364_8MB_RAM (0x2)
555 #define G364_32MB_RAM (0x3)
557 static void rc4030_reset(void *opaque)
559 rc4030State *s = opaque;
562 s->config = (G364_2MB_RAM << 8) | 0x04;
563 s->invalid_address_register = 0;
565 memset(s->dma_regs, 0, sizeof(s->dma_regs));
566 s->dma_tl_base = s->dma_tl_limit = 0;
568 s->remote_failed_address = s->memory_failed_address = 0;
569 s->cache_ptag = s->cache_ltag = 0;
570 s->cache_bmask = s->cache_bwin = 0;
573 s->offset210 = 0x18186;
574 s->nvram_protect = 7;
576 for (i = 0; i < 15; i++)
578 s->imr_jazz = s->isr_jazz = 0;
583 qemu_irq_lower(s->timer_irq);
584 qemu_irq_lower(s->jazz_bus_irq);
587 qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
590 int s_chipset, s_int;
592 s = qemu_mallocz(sizeof(rc4030State));
596 s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
597 s->timer_irq = timer;
598 s->jazz_bus_irq = jazz_bus;
600 qemu_register_reset(rc4030_reset, s);
603 s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
604 cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
605 s_int = cpu_register_io_memory(0, int_read, int_write, s);
606 cpu_register_physical_memory(0xf0000000, 0x00001000, s_int);
608 return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);