2 * QEMU JAZZ RC4030 chipset
4 * Copyright (c) 2007-2009 Herve Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu-timer.h"
29 /********************************************************/
32 //#define DEBUG_RC4030
33 //#define DEBUG_RC4030_DMA
36 #define DPRINTF(fmt, ...) \
37 do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0)
38 static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
39 "network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
41 #define DPRINTF(fmt, ...)
44 #define RC4030_ERROR(fmt, ...) \
45 do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
47 /********************************************************/
48 /* rc4030 emulation */
50 typedef struct dma_pagetable_entry {
53 } __attribute__((packed)) dma_pagetable_entry;
55 #define DMA_PAGESIZE 4096
56 #define DMA_REG_ENABLE 1
57 #define DMA_REG_COUNT 2
58 #define DMA_REG_ADDRESS 3
60 #define DMA_FLAG_ENABLE 0x0001
61 #define DMA_FLAG_MEM_TO_DEV 0x0002
62 #define DMA_FLAG_TC_INTR 0x0100
63 #define DMA_FLAG_MEM_INTR 0x0200
64 #define DMA_FLAG_ADDR_INTR 0x0400
66 typedef struct rc4030State
68 uint32_t config; /* 0x0000: RC4030 config register */
69 uint32_t revision; /* 0x0008: RC4030 Revision register */
70 uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
73 uint32_t dma_regs[8][4];
74 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
75 uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
78 uint32_t cache_maint; /* 0x0030: Cache Maintenance */
79 uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
80 uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
81 uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
82 uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
83 uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
85 uint32_t nmi_interrupt; /* 0x0200: interrupt source */
87 uint32_t nvram_protect; /* 0x0220: NV ram protect register */
88 uint32_t rem_speed[16];
89 uint32_t imr_jazz; /* Local bus int enable mask */
90 uint32_t isr_jazz; /* Local bus int source */
93 QEMUTimer *periodic_timer;
94 uint32_t itr; /* Interval timer reload */
97 qemu_irq jazz_bus_irq;
100 static void set_next_tick(rc4030State *s)
102 qemu_irq_lower(s->timer_irq);
105 tm_hz = 1000 / (s->itr + 1);
107 qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / tm_hz);
110 /* called for accesses to rc4030 */
111 static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
113 rc4030State *s = opaque;
117 switch (addr & ~0x3) {
118 /* Global config register */
122 /* Revision register */
126 /* Invalid Address register */
128 val = s->invalid_address_register;
130 /* DMA transl. table base */
132 val = s->dma_tl_base;
134 /* DMA transl. table limit */
136 val = s->dma_tl_limit;
138 /* Remote Failed Address */
140 val = s->remote_failed_address;
142 /* Memory Failed Address */
144 val = s->memory_failed_address;
146 /* I/O Cache Byte Mask */
148 val = s->cache_bmask;
150 if (s->cache_bmask == (uint32_t)-1)
153 /* Remote Speed Registers */
170 val = s->rem_speed[(addr - 0x0070) >> 3];
172 /* DMA channel base address */
206 int entry = (addr - 0x0100) >> 5;
207 int idx = (addr & 0x1f) >> 3;
208 val = s->dma_regs[entry][idx];
211 /* Interrupt source */
213 val = s->nmi_interrupt;
223 /* NV ram protect register */
225 val = s->nvram_protect;
227 /* Interval timer count */
230 qemu_irq_lower(s->timer_irq);
234 val = 7; /* FIXME: should be read from EISA controller */
237 RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
242 if ((addr & ~3) != 0x230)
243 DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
248 static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
250 uint32_t v = rc4030_readl(opaque, addr & ~0x3);
257 static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
259 uint32_t v = rc4030_readl(opaque, addr & ~0x3);
260 return (v >> (8 * (addr & 0x3))) & 0xff;
263 static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
265 rc4030State *s = opaque;
268 DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
270 switch (addr & ~0x3) {
271 /* Global config register */
275 /* DMA transl. table base */
277 s->dma_tl_base = val;
279 /* DMA transl. table limit */
281 s->dma_tl_limit = val;
283 /* DMA transl. table invalidated */
286 /* Cache Maintenance */
288 s->cache_maint = val;
290 /* I/O Cache Physical Tag */
294 /* I/O Cache Logical Tag */
298 /* I/O Cache Byte Mask */
300 s->cache_bmask |= val; /* HACK */
302 /* I/O Cache Buffer Window */
305 if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
306 target_phys_addr_t dest = s->cache_ptag & ~0x1;
307 dest += (s->cache_maint & 0x3) << 3;
308 cpu_physical_memory_rw(dest, (uint8_t*)&val, 4, 1);
311 /* Remote Speed Registers */
328 s->rem_speed[(addr - 0x0070) >> 3] = val;
330 /* DMA channel base address */
364 int entry = (addr - 0x0100) >> 5;
365 int idx = (addr & 0x1f) >> 3;
366 s->dma_regs[entry][idx] = val;
373 /* Interval timer reload */
376 qemu_irq_lower(s->timer_irq);
383 RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
388 static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
390 uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
393 val = (val << 16) | (old_val & 0x0000ffff);
395 val = val | (old_val & 0xffff0000);
396 rc4030_writel(opaque, addr & ~0x3, val);
399 static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
401 uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
405 val = val | (old_val & 0xffffff00);
408 val = (val << 8) | (old_val & 0xffff00ff);
411 val = (val << 16) | (old_val & 0xff00ffff);
414 val = (val << 24) | (old_val & 0x00ffffff);
417 rc4030_writel(opaque, addr & ~0x3, val);
420 static CPUReadMemoryFunc *rc4030_read[3] = {
426 static CPUWriteMemoryFunc *rc4030_write[3] = {
432 static void update_jazz_irq(rc4030State *s)
436 pending = s->isr_jazz & s->imr_jazz;
439 if (s->isr_jazz != 0) {
441 DPRINTF("pending irqs:");
442 for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
443 if (s->isr_jazz & (1 << irq)) {
444 printf(" %s", irq_names[irq]);
445 if (!(s->imr_jazz & (1 << irq))) {
455 qemu_irq_raise(s->jazz_bus_irq);
457 qemu_irq_lower(s->jazz_bus_irq);
460 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
462 rc4030State *s = opaque;
465 s->isr_jazz |= 1 << irq;
467 s->isr_jazz &= ~(1 << irq);
473 static void rc4030_periodic_timer(void *opaque)
475 rc4030State *s = opaque;
478 qemu_irq_raise(s->timer_irq);
481 static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
483 rc4030State *s = opaque;
489 /* Local bus int source */
491 uint32_t pending = s->isr_jazz & s->imr_jazz;
496 DPRINTF("returning irq %s\n", irq_names[irq]);
497 val = (irq + 1) << 2;
505 /* Local bus int enable mask */
510 RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
514 DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
519 static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
522 v = jazzio_readw(opaque, addr & ~0x1);
523 return (v >> (8 * (addr & 0x1))) & 0xff;
526 static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
529 v = jazzio_readw(opaque, addr);
530 v |= jazzio_readw(opaque, addr + 2) << 16;
534 static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
536 rc4030State *s = opaque;
539 DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
542 /* Local bus int enable mask */
548 RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
553 static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
555 uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
559 val = val | (old_val & 0xff00);
562 val = (val << 8) | (old_val & 0x00ff);
565 jazzio_writew(opaque, addr & ~0x1, val);
568 static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
570 jazzio_writew(opaque, addr, val & 0xffff);
571 jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
574 static CPUReadMemoryFunc *jazzio_read[3] = {
580 static CPUWriteMemoryFunc *jazzio_write[3] = {
586 static void rc4030_reset(void *opaque)
588 rc4030State *s = opaque;
591 s->config = 0x410; /* some boards seem to accept 0x104 too */
593 s->invalid_address_register = 0;
595 memset(s->dma_regs, 0, sizeof(s->dma_regs));
596 s->dma_tl_base = s->dma_tl_limit = 0;
598 s->remote_failed_address = s->memory_failed_address = 0;
600 s->cache_ptag = s->cache_ltag = 0;
603 s->offset210 = 0x18186;
604 s->nvram_protect = 7;
605 for (i = 0; i < 15; i++)
607 s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
612 qemu_irq_lower(s->timer_irq);
613 qemu_irq_lower(s->jazz_bus_irq);
616 static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
618 rc4030State* s = opaque;
624 s->config = qemu_get_be32(f);
625 s->invalid_address_register = qemu_get_be32(f);
626 for (i = 0; i < 8; i++)
627 for (j = 0; j < 4; j++)
628 s->dma_regs[i][j] = qemu_get_be32(f);
629 s->dma_tl_base = qemu_get_be32(f);
630 s->dma_tl_limit = qemu_get_be32(f);
631 s->cache_maint = qemu_get_be32(f);
632 s->remote_failed_address = qemu_get_be32(f);
633 s->memory_failed_address = qemu_get_be32(f);
634 s->cache_ptag = qemu_get_be32(f);
635 s->cache_ltag = qemu_get_be32(f);
636 s->cache_bmask = qemu_get_be32(f);
637 s->offset210 = qemu_get_be32(f);
638 s->nvram_protect = qemu_get_be32(f);
639 for (i = 0; i < 15; i++)
640 s->rem_speed[i] = qemu_get_be32(f);
641 s->imr_jazz = qemu_get_be32(f);
642 s->isr_jazz = qemu_get_be32(f);
643 s->itr = qemu_get_be32(f);
651 static void rc4030_save(QEMUFile *f, void *opaque)
653 rc4030State* s = opaque;
656 qemu_put_be32(f, s->config);
657 qemu_put_be32(f, s->invalid_address_register);
658 for (i = 0; i < 8; i++)
659 for (j = 0; j < 4; j++)
660 qemu_put_be32(f, s->dma_regs[i][j]);
661 qemu_put_be32(f, s->dma_tl_base);
662 qemu_put_be32(f, s->dma_tl_limit);
663 qemu_put_be32(f, s->cache_maint);
664 qemu_put_be32(f, s->remote_failed_address);
665 qemu_put_be32(f, s->memory_failed_address);
666 qemu_put_be32(f, s->cache_ptag);
667 qemu_put_be32(f, s->cache_ltag);
668 qemu_put_be32(f, s->cache_bmask);
669 qemu_put_be32(f, s->offset210);
670 qemu_put_be32(f, s->nvram_protect);
671 for (i = 0; i < 15; i++)
672 qemu_put_be32(f, s->rem_speed[i]);
673 qemu_put_be32(f, s->imr_jazz);
674 qemu_put_be32(f, s->isr_jazz);
675 qemu_put_be32(f, s->itr);
678 void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
680 rc4030State *s = opaque;
681 target_phys_addr_t entry_addr;
682 target_phys_addr_t phys_addr;
683 dma_pagetable_entry entry;
693 ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
697 /* Get DMA translation table entry */
698 index = addr / DMA_PAGESIZE;
699 if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
702 entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
703 /* XXX: not sure. should we really use only lowest bits? */
704 entry_addr &= 0x7fffffff;
705 cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0);
707 /* Read/write data at right place */
708 phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
709 cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
716 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
718 rc4030State *s = opaque;
719 target_phys_addr_t dma_addr;
722 s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
724 /* Check DMA channel consistency */
725 dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
726 if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
727 (is_write != dev_to_mem)) {
728 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
729 s->nmi_interrupt |= 1 << n;
733 /* Get start address and len */
734 if (len > s->dma_regs[n][DMA_REG_COUNT])
735 len = s->dma_regs[n][DMA_REG_COUNT];
736 dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
738 /* Read/write data at right place */
739 rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
741 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
742 s->dma_regs[n][DMA_REG_COUNT] -= len;
744 #ifdef DEBUG_RC4030_DMA
747 printf("rc4030 dma: Copying %d bytes %s host %p\n",
748 len, is_write ? "from" : "to", buf);
749 for (i = 0; i < len; i += 16) {
750 int n = min(16, len - i);
751 for (j = 0; j < n; j++)
752 printf("%02x ", buf[i + j]);
756 for (j = 0; j < n; j++)
757 printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
764 struct rc4030DMAState {
769 void rc4030_dma_read(void *dma, uint8_t *buf, int len)
772 rc4030_do_dma(s->opaque, s->n, buf, len, 0);
775 void rc4030_dma_write(void *dma, uint8_t *buf, int len)
778 rc4030_do_dma(s->opaque, s->n, buf, len, 1);
781 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
784 struct rc4030DMAState *p;
787 s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
788 p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n);
789 for (i = 0; i < n; i++) {
798 void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
799 qemu_irq **irqs, rc4030_dma **dmas)
802 int s_chipset, s_jazzio;
804 s = qemu_mallocz(sizeof(rc4030State));
806 *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
807 *dmas = rc4030_allocate_dmas(s, 4);
809 s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
810 s->timer_irq = timer;
811 s->jazz_bus_irq = jazz_bus;
813 qemu_register_reset(rc4030_reset, 0, s);
814 register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
817 s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
818 cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
819 s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
820 cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);