git.maemo.org Git - qemu/blob - hw/unin_pci.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc_mac.h"
  26 #include "pci.h"
  27
  28 /* debug UniNorth */
  29 //#define DEBUG_UNIN
  30
  31 #ifdef DEBUG_UNIN
  32 #define UNIN_DPRINTF(fmt, ...)                                  \
  33     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define UNIN_DPRINTF(fmt, ...)
  36 #endif
  37
  38 typedef target_phys_addr_t pci_addr_t;
  39 #include "pci_host.h"
  40
  41 typedef PCIHostState UNINState;
  42
  43 static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
  44                                          uint32_t val)
  45 {
  46     UNINState *s = opaque;
  47
  48     UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
  49 #ifdef TARGET_WORDS_BIGENDIAN
  50     val = bswap32(val);
  51 #endif
  52
  53     s->config_reg = val;
  54 }
  55
  56 static uint32_t pci_unin_main_config_readl (void *opaque,
  57                                             target_phys_addr_t addr)
  58 {
  59     UNINState *s = opaque;
  60     uint32_t val;
  61
  62     val = s->config_reg;
  63 #ifdef TARGET_WORDS_BIGENDIAN
  64     val = bswap32(val);
  65 #endif
  66     UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
  67
  68     return val;
  69 }
  70
  71 static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
  72     &pci_unin_main_config_writel,
  73     &pci_unin_main_config_writel,
  74     &pci_unin_main_config_writel,
  75 };
  76
  77 static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
  78     &pci_unin_main_config_readl,
  79     &pci_unin_main_config_readl,
  80     &pci_unin_main_config_readl,
  81 };
  82
  83 static CPUWriteMemoryFunc *pci_unin_main_write[] = {
  84     &pci_host_data_writeb,
  85     &pci_host_data_writew,
  86     &pci_host_data_writel,
  87 };
  88
  89 static CPUReadMemoryFunc *pci_unin_main_read[] = {
  90     &pci_host_data_readb,
  91     &pci_host_data_readw,
  92     &pci_host_data_readl,
  93 };
  94
  95 static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
  96                                     uint32_t val)
  97 {
  98     UNINState *s = opaque;
  99
 100     s->config_reg = val;
 101 }
 102
 103 static uint32_t pci_unin_config_readl (void *opaque,
 104                                        target_phys_addr_t addr)
 105 {
 106     UNINState *s = opaque;
 107
 108     return s->config_reg;
 109 }
 110
 111 static CPUWriteMemoryFunc *pci_unin_config_write[] = {
 112     &pci_unin_config_writel,
 113     &pci_unin_config_writel,
 114     &pci_unin_config_writel,
 115 };
 116
 117 static CPUReadMemoryFunc *pci_unin_config_read[] = {
 118     &pci_unin_config_readl,
 119     &pci_unin_config_readl,
 120     &pci_unin_config_readl,
 121 };
 122
 123 #if 0
 124 static CPUWriteMemoryFunc *pci_unin_write[] = {
 125     &pci_host_pci_writeb,
 126     &pci_host_pci_writew,
 127     &pci_host_pci_writel,
 128 };
 129
 130 static CPUReadMemoryFunc *pci_unin_read[] = {
 131     &pci_host_pci_readb,
 132     &pci_host_pci_readw,
 133     &pci_host_pci_readl,
 134 };
 135 #endif
 136
 137 /* Don't know if this matches real hardware, but it agrees with OHW.  */
 138 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
 139 {
 140     return (irq_num + (pci_dev->devfn >> 3)) & 3;
 141 }
 142
 143 static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
 144 {
 145     qemu_set_irq(pic[irq_num + 8], level);
 146 }
 147
 148 static void pci_unin_save(QEMUFile* f, void *opaque)
 149 {
 150     PCIDevice *d = opaque;
 151
 152     pci_device_save(d, f);
 153 }
 154
 155 static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
 156 {
 157     PCIDevice *d = opaque;
 158
 159     if (version_id != 1)
 160         return -EINVAL;
 161
 162     return pci_device_load(d, f);
 163 }
 164
 165 static void pci_unin_reset(void *opaque)
 166 {
 167 }
 168
 169 PCIBus *pci_pmac_init(qemu_irq *pic)
 170 {
 171     UNINState *s;
 172     PCIDevice *d;
 173     int pci_mem_config, pci_mem_data;
 174
 175     /* Use values found on a real PowerMac */
 176     /* Uninorth main bus */
 177     s = qemu_mallocz(sizeof(UNINState));
 178     s->bus = pci_register_bus(NULL, "pci",
 179                               pci_unin_set_irq, pci_unin_map_irq,
 180                               pic, 11 << 3, 4);
 181
 182     pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
 183                                             pci_unin_main_config_write, s);
 184     pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
 185                                           pci_unin_main_write, s);
 186     cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
 187     cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
 188     d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
 189                             11 << 3, NULL, NULL);
 190     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 191     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
 192     d->config[0x08] = 0x00; // revision
 193     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 194     d->config[0x0C] = 0x08; // cache_line_size
 195     d->config[0x0D] = 0x10; // latency_timer
 196     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 197     d->config[0x34] = 0x00; // capabilities_pointer
 198
 199 #if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
 200     /* pci-to-pci bridge */
 201     d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
 202                             NULL, NULL);
 203     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
 204     pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
 205     d->config[0x08] = 0x05; // revision
 206     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
 207     d->config[0x0C] = 0x08; // cache_line_size
 208     d->config[0x0D] = 0x20; // latency_timer
 209     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
 210
 211     d->config[0x18] = 0x01; // primary_bus
 212     d->config[0x19] = 0x02; // secondary_bus
 213     d->config[0x1A] = 0x02; // subordinate_bus
 214     d->config[0x1B] = 0x20; // secondary_latency_timer
 215     d->config[0x1C] = 0x11; // io_base
 216     d->config[0x1D] = 0x01; // io_limit
 217     d->config[0x20] = 0x00; // memory_base
 218     d->config[0x21] = 0x80;
 219     d->config[0x22] = 0x00; // memory_limit
 220     d->config[0x23] = 0x80;
 221     d->config[0x24] = 0x01; // prefetchable_memory_base
 222     d->config[0x25] = 0x80;
 223     d->config[0x26] = 0xF1; // prefectchable_memory_limit
 224     d->config[0x27] = 0x7F;
 225     // d->config[0x34] = 0xdc // capabilities_pointer
 226 #endif
 227
 228     /* Uninorth AGP bus */
 229     pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
 230                                             pci_unin_config_write, s);
 231     pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
 232                                           pci_unin_main_write, s);
 233     cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
 234     cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
 235
 236     d = pci_register_device(s->bus, "Uni-north AGP", sizeof(PCIDevice),
 237                             11 << 3, NULL, NULL);
 238     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 239     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
 240     d->config[0x08] = 0x00; // revision
 241     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 242     d->config[0x0C] = 0x08; // cache_line_size
 243     d->config[0x0D] = 0x10; // latency_timer
 244     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 245     //    d->config[0x34] = 0x80; // capabilities_pointer
 246
 247 #if 0 // XXX: not needed for now
 248     /* Uninorth internal bus */
 249     s = &pci_bridge[2];
 250     pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
 251                                             pci_unin_config_write, s);
 252     pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
 253                                           pci_unin_write, s);
 254     cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
 255     cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
 256
 257     d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
 258                             3, 11 << 3, NULL, NULL);
 259     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 260     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
 261     d->config[0x08] = 0x00; // revision
 262     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 263     d->config[0x0C] = 0x08; // cache_line_size
 264     d->config[0x0D] = 0x10; // latency_timer
 265     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 266     d->config[0x34] = 0x00; // capabilities_pointer
 267 #endif
 268     register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
 269     qemu_register_reset(pci_unin_reset, 0, d);
 270     pci_unin_reset(d);
 271
 272     return s->bus;
 273 }