2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
22 * o Isochronous transfers
23 * o Allocate bandwidth in frames properly
24 * o Disable timers when nothing needs to be done, or remove timer usage
26 * o Handle unrecoverable errors properly
27 * o BIOS work to boot from USB storage
31 #include "qemu-timer.h"
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
45 #define dprintf printf
50 /* Number of Downstream Ports on the root hub. */
52 #define OHCI_MAX_PORTS 15
54 static int64_t usb_frame_time;
55 static int64_t usb_bit_time;
57 typedef struct OHCIPort {
79 /* Control partition */
84 /* memory pointer partition */
86 uint32_t ctrl_head, ctrl_cur;
87 uint32_t bulk_head, bulk_cur;
92 /* Frame counter partition */
97 uint16_t frame_number;
102 /* Root Hub partition */
103 uint32_t rhdesc_a, rhdesc_b;
105 OHCIPort rhport[OHCI_MAX_PORTS];
107 /* PXA27x Non-OHCI events */
113 /* Active packets. */
115 USBPacket usb_packet;
116 uint8_t usb_buf[8192];
122 /* Host Controller Communications Area */
129 static void ohci_bus_stop(OHCIState *ohci);
131 /* Bitfields for the first word of an Endpoint Desciptor. */
132 #define OHCI_ED_FA_SHIFT 0
133 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
134 #define OHCI_ED_EN_SHIFT 7
135 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
136 #define OHCI_ED_D_SHIFT 11
137 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
138 #define OHCI_ED_S (1<<13)
139 #define OHCI_ED_K (1<<14)
140 #define OHCI_ED_F (1<<15)
141 #define OHCI_ED_MPS_SHIFT 16
142 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
144 /* Flags in the head field of an Endpoint Desciptor. */
148 /* Bitfields for the first word of a Transfer Desciptor. */
149 #define OHCI_TD_R (1<<18)
150 #define OHCI_TD_DP_SHIFT 19
151 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
152 #define OHCI_TD_DI_SHIFT 21
153 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
154 #define OHCI_TD_T0 (1<<24)
155 #define OHCI_TD_T1 (1<<24)
156 #define OHCI_TD_EC_SHIFT 26
157 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
158 #define OHCI_TD_CC_SHIFT 28
159 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
161 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
162 /* CC & DI - same as in the General Transfer Desciptor */
163 #define OHCI_TD_SF_SHIFT 0
164 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
165 #define OHCI_TD_FC_SHIFT 24
166 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
168 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
169 #define OHCI_TD_PSW_CC_SHIFT 12
170 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
171 #define OHCI_TD_PSW_SIZE_SHIFT 0
172 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
174 #define OHCI_PAGE_MASK 0xfffff000
175 #define OHCI_OFFSET_MASK 0xfff
177 #define OHCI_DPTR_MASK 0xfffffff0
179 #define OHCI_BM(val, field) \
180 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
182 #define OHCI_SET_BM(val, field, newval) do { \
183 val &= ~OHCI_##field##_MASK; \
184 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
187 /* endpoint descriptor */
195 /* General transfer descriptor */
203 /* Isochronous transfer descriptor */
212 #define USB_HZ 12000000
214 /* OHCI Local stuff */
215 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
216 #define OHCI_CTL_PLE (1<<2)
217 #define OHCI_CTL_IE (1<<3)
218 #define OHCI_CTL_CLE (1<<4)
219 #define OHCI_CTL_BLE (1<<5)
220 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
221 #define OHCI_USB_RESET 0x00
222 #define OHCI_USB_RESUME 0x40
223 #define OHCI_USB_OPERATIONAL 0x80
224 #define OHCI_USB_SUSPEND 0xc0
225 #define OHCI_CTL_IR (1<<8)
226 #define OHCI_CTL_RWC (1<<9)
227 #define OHCI_CTL_RWE (1<<10)
229 #define OHCI_STATUS_HCR (1<<0)
230 #define OHCI_STATUS_CLF (1<<1)
231 #define OHCI_STATUS_BLF (1<<2)
232 #define OHCI_STATUS_OCR (1<<3)
233 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
235 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
236 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
237 #define OHCI_INTR_SF (1<<2) /* Start of frame */
238 #define OHCI_INTR_RD (1<<3) /* Resume detect */
239 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
240 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
241 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
242 #define OHCI_INTR_OC (1<<30) /* Ownership change */
243 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
245 #define OHCI_HCCA_SIZE 0x100
246 #define OHCI_HCCA_MASK 0xffffff00
248 #define OHCI_EDPTR_MASK 0xfffffff0
250 #define OHCI_FMI_FI 0x00003fff
251 #define OHCI_FMI_FSMPS 0xffff0000
252 #define OHCI_FMI_FIT 0x80000000
254 #define OHCI_FR_RT (1<<31)
256 #define OHCI_LS_THRESH 0x628
258 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
259 #define OHCI_RHA_PSM (1<<8)
260 #define OHCI_RHA_NPS (1<<9)
261 #define OHCI_RHA_DT (1<<10)
262 #define OHCI_RHA_OCPM (1<<11)
263 #define OHCI_RHA_NOCP (1<<12)
264 #define OHCI_RHA_POTPGT_MASK 0xff000000
266 #define OHCI_RHS_LPS (1<<0)
267 #define OHCI_RHS_OCI (1<<1)
268 #define OHCI_RHS_DRWE (1<<15)
269 #define OHCI_RHS_LPSC (1<<16)
270 #define OHCI_RHS_OCIC (1<<17)
271 #define OHCI_RHS_CRWE (1<<31)
273 #define OHCI_PORT_CCS (1<<0)
274 #define OHCI_PORT_PES (1<<1)
275 #define OHCI_PORT_PSS (1<<2)
276 #define OHCI_PORT_POCI (1<<3)
277 #define OHCI_PORT_PRS (1<<4)
278 #define OHCI_PORT_PPS (1<<8)
279 #define OHCI_PORT_LSDA (1<<9)
280 #define OHCI_PORT_CSC (1<<16)
281 #define OHCI_PORT_PESC (1<<17)
282 #define OHCI_PORT_PSSC (1<<18)
283 #define OHCI_PORT_OCIC (1<<19)
284 #define OHCI_PORT_PRSC (1<<20)
285 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
286 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
288 #define OHCI_TD_DIR_SETUP 0x0
289 #define OHCI_TD_DIR_OUT 0x1
290 #define OHCI_TD_DIR_IN 0x2
291 #define OHCI_TD_DIR_RESERVED 0x3
293 #define OHCI_CC_NOERROR 0x0
294 #define OHCI_CC_CRC 0x1
295 #define OHCI_CC_BITSTUFFING 0x2
296 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
297 #define OHCI_CC_STALL 0x4
298 #define OHCI_CC_DEVICENOTRESPONDING 0x5
299 #define OHCI_CC_PIDCHECKFAILURE 0x6
300 #define OHCI_CC_UNDEXPETEDPID 0x7
301 #define OHCI_CC_DATAOVERRUN 0x8
302 #define OHCI_CC_DATAUNDERRUN 0x9
303 #define OHCI_CC_BUFFEROVERRUN 0xc
304 #define OHCI_CC_BUFFERUNDERRUN 0xd
306 #define OHCI_HRESET_FSBIR (1 << 0)
308 /* Update IRQ levels */
309 static inline void ohci_intr_update(OHCIState *ohci)
313 if ((ohci->intr & OHCI_INTR_MIE) &&
314 (ohci->intr_status & ohci->intr))
317 qemu_set_irq(ohci->irq, level);
320 /* Set an interrupt */
321 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
323 ohci->intr_status |= intr;
324 ohci_intr_update(ohci);
327 /* Attach or detach a device on a root hub port. */
328 static void ohci_attach(USBPort *port1, USBDevice *dev)
330 OHCIState *s = port1->opaque;
331 OHCIPort *port = &s->rhport[port1->index];
332 uint32_t old_state = port->ctrl;
335 if (port->port.dev) {
336 usb_attach(port1, NULL);
338 /* set connect status */
339 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
342 if (dev->speed == USB_SPEED_LOW)
343 port->ctrl |= OHCI_PORT_LSDA;
345 port->ctrl &= ~OHCI_PORT_LSDA;
346 port->port.dev = dev;
348 /* notify of remote-wakeup */
349 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
350 ohci_set_interrupt(s, OHCI_INTR_RD);
352 /* send the attach message */
353 usb_send_msg(dev, USB_MSG_ATTACH);
354 dprintf("usb-ohci: Attached port %d\n", port1->index);
356 /* set connect status */
357 if (port->ctrl & OHCI_PORT_CCS) {
358 port->ctrl &= ~OHCI_PORT_CCS;
359 port->ctrl |= OHCI_PORT_CSC;
362 if (port->ctrl & OHCI_PORT_PES) {
363 port->ctrl &= ~OHCI_PORT_PES;
364 port->ctrl |= OHCI_PORT_PESC;
366 dev = port->port.dev;
368 /* send the detach message */
369 usb_send_msg(dev, USB_MSG_DETACH);
371 port->port.dev = NULL;
372 dprintf("usb-ohci: Detached port %d\n", port1->index);
375 if (old_state != port->ctrl)
376 ohci_set_interrupt(s, OHCI_INTR_RHSC);
379 /* Reset the controller */
380 static void ohci_reset(void *opaque)
382 OHCIState *ohci = opaque;
390 ohci->intr_status = 0;
391 ohci->intr = OHCI_INTR_MIE;
394 ohci->ctrl_head = ohci->ctrl_cur = 0;
395 ohci->bulk_head = ohci->bulk_cur = 0;
398 ohci->done_count = 7;
400 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
401 * I took the value linux sets ...
403 ohci->fsmps = 0x2778;
407 ohci->frame_number = 0;
409 ohci->lst = OHCI_LS_THRESH;
411 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
412 ohci->rhdesc_b = 0x0; /* Impl. specific */
415 for (i = 0; i < ohci->num_ports; i++)
417 port = &ohci->rhport[i];
420 ohci_attach(&port->port, port->port.dev);
422 if (ohci->async_td) {
423 usb_cancel_packet(&ohci->usb_packet);
426 dprintf("usb-ohci: Reset %s\n", ohci->name);
429 /* Get an array of dwords from main memory */
430 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
434 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
435 cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
436 *buf = le32_to_cpu(*buf);
442 /* Put an array of dwords in to main memory */
443 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
447 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
448 uint32_t tmp = cpu_to_le32(*buf);
449 cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
455 /* Get an array of words from main memory */
456 static inline int get_words(uint32_t addr, uint16_t *buf, int num)
460 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
461 cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
462 *buf = le16_to_cpu(*buf);
468 /* Put an array of words in to main memory */
469 static inline int put_words(uint32_t addr, uint16_t *buf, int num)
473 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
474 uint16_t tmp = cpu_to_le16(*buf);
475 cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
481 static inline int ohci_read_ed(uint32_t addr, struct ohci_ed *ed)
483 return get_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
486 static inline int ohci_read_td(uint32_t addr, struct ohci_td *td)
488 return get_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
491 static inline int ohci_read_iso_td(uint32_t addr, struct ohci_iso_td *td)
493 return (get_dwords(addr, (uint32_t *)td, 4) &&
494 get_words(addr + 16, td->offset, 8));
497 static inline int ohci_put_ed(uint32_t addr, struct ohci_ed *ed)
499 return put_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
502 static inline int ohci_put_td(uint32_t addr, struct ohci_td *td)
504 return put_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
507 static inline int ohci_put_iso_td(uint32_t addr, struct ohci_iso_td *td)
509 return (put_dwords(addr, (uint32_t *)td, 4) &&
510 put_words(addr + 16, td->offset, 8));
513 /* Read/Write the contents of a TD from/to main memory. */
514 static void ohci_copy_td(struct ohci_td *td, uint8_t *buf, int len, int write)
520 n = 0x1000 - (ptr & 0xfff);
523 cpu_physical_memory_rw(ptr, buf, n, write);
526 ptr = td->be & ~0xfffu;
528 cpu_physical_memory_rw(ptr, buf, len - n, write);
531 /* Read/Write the contents of an ISO TD from/to main memory. */
532 static void ohci_copy_iso_td(uint32_t start_addr, uint32_t end_addr,
533 uint8_t *buf, int len, int write)
539 n = 0x1000 - (ptr & 0xfff);
542 cpu_physical_memory_rw(ptr, buf, n, write);
545 ptr = end_addr & ~0xfffu;
547 cpu_physical_memory_rw(ptr, buf, len - n, write);
550 static void ohci_process_lists(OHCIState *ohci, int completion);
552 static void ohci_async_complete_packet(USBPacket *packet, void *opaque)
554 OHCIState *ohci = opaque;
556 dprintf("Async packet complete\n");
558 ohci->async_complete = 1;
559 ohci_process_lists(ohci, 1);
562 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
564 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
569 const char *str = NULL;
574 struct ohci_iso_td iso_td;
576 uint16_t starting_frame;
577 int16_t relative_frame_number;
579 uint32_t start_offset, next_offset, end_offset = 0;
580 uint32_t start_addr, end_addr;
582 addr = ed->head & OHCI_DPTR_MASK;
584 if (!ohci_read_iso_td(addr, &iso_td)) {
585 printf("usb-ohci: ISO_TD read error at %x\n", addr);
589 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
590 frame_count = OHCI_BM(iso_td.flags, TD_FC);
591 relative_frame_number = USUB(ohci->frame_number, starting_frame);
594 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
595 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
596 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
597 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
598 "frame_number 0x%.8x starting_frame 0x%.8x\n"
599 "frame_count 0x%.8x relative %d\n"
600 "di 0x%.8x cc 0x%.8x\n",
601 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
602 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
603 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
604 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
605 ohci->frame_number, starting_frame,
606 frame_count, relative_frame_number,
607 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
610 if (relative_frame_number < 0) {
611 dprintf("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
613 } else if (relative_frame_number > frame_count) {
614 /* ISO TD expired - retire the TD to the Done Queue and continue with
615 the next ISO TD of the same ED */
616 dprintf("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
618 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
619 ed->head &= ~OHCI_DPTR_MASK;
620 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
621 iso_td.next = ohci->done;
623 i = OHCI_BM(iso_td.flags, TD_DI);
624 if (i < ohci->done_count)
625 ohci->done_count = i;
626 ohci_put_iso_td(addr, &iso_td);
630 dir = OHCI_BM(ed->flags, ED_D);
636 case OHCI_TD_DIR_OUT:
640 case OHCI_TD_DIR_SETUP:
642 pid = USB_TOKEN_SETUP;
645 printf("usb-ohci: Bad direction %d\n", dir);
649 if (!iso_td.bp || !iso_td.be) {
650 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
654 start_offset = iso_td.offset[relative_frame_number];
655 next_offset = iso_td.offset[relative_frame_number + 1];
657 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
658 ((relative_frame_number < frame_count) &&
659 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
660 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
661 start_offset, next_offset);
665 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
666 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
667 start_offset, next_offset);
671 if ((start_offset & 0x1000) == 0) {
672 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
673 (start_offset & OHCI_OFFSET_MASK);
675 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
676 (start_offset & OHCI_OFFSET_MASK);
679 if (relative_frame_number < frame_count) {
680 end_offset = next_offset - 1;
681 if ((end_offset & 0x1000) == 0) {
682 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
683 (end_offset & OHCI_OFFSET_MASK);
685 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
686 (end_offset & OHCI_OFFSET_MASK);
689 /* Last packet in the ISO TD */
690 end_addr = iso_td.be;
693 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
694 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
695 - (start_addr & OHCI_OFFSET_MASK);
697 len = end_addr - start_addr + 1;
700 if (len && dir != OHCI_TD_DIR_IN) {
701 ohci_copy_iso_td(start_addr, end_addr, ohci->usb_buf, len, 0);
705 ret = ohci->usb_packet.len;
708 for (i = 0; i < ohci->num_ports; i++) {
709 dev = ohci->rhport[i].port.dev;
710 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
712 ohci->usb_packet.pid = pid;
713 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
714 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
715 ohci->usb_packet.data = ohci->usb_buf;
716 ohci->usb_packet.len = len;
717 ohci->usb_packet.complete_cb = ohci_async_complete_packet;
718 ohci->usb_packet.complete_opaque = ohci;
719 ret = dev->handle_packet(dev, &ohci->usb_packet);
720 if (ret != USB_RET_NODEV)
724 if (ret == USB_RET_ASYNC) {
730 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
731 start_offset, end_offset, start_addr, end_addr, str, len, ret);
735 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
736 /* IN transfer succeeded */
737 ohci_copy_iso_td(start_addr, end_addr, ohci->usb_buf, ret, 1);
738 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
740 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
741 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
742 /* OUT transfer succeeded */
743 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
745 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
747 if (ret > (ssize_t) len) {
748 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
749 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
750 OHCI_CC_DATAOVERRUN);
751 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
753 } else if (ret >= 0) {
754 printf("usb-ohci: DataUnderrun %d\n", ret);
755 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
756 OHCI_CC_DATAUNDERRUN);
760 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
761 OHCI_CC_DEVICENOTRESPONDING);
762 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
767 printf("usb-ohci: got NAK/STALL %d\n", ret);
768 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
770 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
774 printf("usb-ohci: Bad device response %d\n", ret);
775 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
776 OHCI_CC_UNDEXPETEDPID);
782 if (relative_frame_number == frame_count) {
783 /* Last data packet of ISO TD - retire the TD to the Done Queue */
784 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
785 ed->head &= ~OHCI_DPTR_MASK;
786 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
787 iso_td.next = ohci->done;
789 i = OHCI_BM(iso_td.flags, TD_DI);
790 if (i < ohci->done_count)
791 ohci->done_count = i;
793 ohci_put_iso_td(addr, &iso_td);
797 /* Service a transport descriptor.
798 Returns nonzero to terminate processing of this endpoint. */
800 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
804 const char *str = NULL;
814 addr = ed->head & OHCI_DPTR_MASK;
815 /* See if this TD has already been submitted to the device. */
816 completion = (addr == ohci->async_td);
817 if (completion && !ohci->async_complete) {
819 dprintf("Skipping async TD\n");
823 if (!ohci_read_td(addr, &td)) {
824 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
828 dir = OHCI_BM(ed->flags, ED_D);
830 case OHCI_TD_DIR_OUT:
835 dir = OHCI_BM(td.flags, TD_DP);
844 case OHCI_TD_DIR_OUT:
848 case OHCI_TD_DIR_SETUP:
850 pid = USB_TOKEN_SETUP;
853 fprintf(stderr, "usb-ohci: Bad direction\n");
856 if (td.cbp && td.be) {
857 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
858 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
860 len = (td.be - td.cbp) + 1;
863 if (len && dir != OHCI_TD_DIR_IN && !completion) {
864 ohci_copy_td(&td, ohci->usb_buf, len, 0);
868 flag_r = (td.flags & OHCI_TD_R) != 0;
870 dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
871 addr, len, str, flag_r, td.cbp, td.be);
873 if (len > 0 && dir != OHCI_TD_DIR_IN) {
875 for (i = 0; i < len; i++)
876 printf(" %.2x", ohci->usb_buf[i]);
881 ret = ohci->usb_packet.len;
883 ohci->async_complete = 0;
886 for (i = 0; i < ohci->num_ports; i++) {
887 dev = ohci->rhport[i].port.dev;
888 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
891 if (ohci->async_td) {
892 /* ??? The hardware should allow one active packet per
893 endpoint. We only allow one active packet per controller.
894 This should be sufficient as long as devices respond in a
898 dprintf("Too many pending packets\n");
902 ohci->usb_packet.pid = pid;
903 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
904 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
905 ohci->usb_packet.data = ohci->usb_buf;
906 ohci->usb_packet.len = len;
907 ohci->usb_packet.complete_cb = ohci_async_complete_packet;
908 ohci->usb_packet.complete_opaque = ohci;
909 ret = dev->handle_packet(dev, &ohci->usb_packet);
910 if (ret != USB_RET_NODEV)
914 dprintf("ret=%d\n", ret);
916 if (ret == USB_RET_ASYNC) {
917 ohci->async_td = addr;
922 if (dir == OHCI_TD_DIR_IN) {
923 ohci_copy_td(&td, ohci->usb_buf, ret, 1);
926 for (i = 0; i < ret; i++)
927 printf(" %.2x", ohci->usb_buf[i]);
936 if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
937 /* Transmission succeeded. */
942 if ((td.cbp & 0xfff) + ret > 0xfff) {
944 td.cbp |= td.be & ~0xfff;
947 td.flags |= OHCI_TD_T1;
948 td.flags ^= OHCI_TD_T0;
949 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
950 OHCI_SET_BM(td.flags, TD_EC, 0);
952 ed->head &= ~OHCI_ED_C;
953 if (td.flags & OHCI_TD_T0)
954 ed->head |= OHCI_ED_C;
957 dprintf("usb-ohci: Underrun\n");
958 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
962 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
964 dprintf("usb-ohci: got NAK\n");
967 dprintf("usb-ohci: got STALL\n");
968 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
971 dprintf("usb-ohci: got BABBLE\n");
972 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
975 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
976 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
977 OHCI_SET_BM(td.flags, TD_EC, 3);
981 ed->head |= OHCI_ED_H;
985 ed->head &= ~OHCI_DPTR_MASK;
986 ed->head |= td.next & OHCI_DPTR_MASK;
987 td.next = ohci->done;
989 i = OHCI_BM(td.flags, TD_DI);
990 if (i < ohci->done_count)
991 ohci->done_count = i;
992 ohci_put_td(addr, &td);
993 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
996 /* Service an endpoint list. Returns nonzero if active TD were found. */
997 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1009 for (cur = head; cur; cur = next_ed) {
1010 if (!ohci_read_ed(cur, &ed)) {
1011 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1015 next_ed = ed.next & OHCI_DPTR_MASK;
1017 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1019 /* Cancel pending packets for ED that have been paused. */
1020 addr = ed.head & OHCI_DPTR_MASK;
1021 if (ohci->async_td && addr == ohci->async_td) {
1022 usb_cancel_packet(&ohci->usb_packet);
1028 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1030 dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1031 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1032 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1033 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1034 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1035 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1036 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1037 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1041 if ((ed.flags & OHCI_ED_F) == 0) {
1042 if (ohci_service_td(ohci, &ed))
1045 /* Handle isochronous endpoints */
1046 if (ohci_service_iso_td(ohci, &ed, completion))
1051 ohci_put_ed(cur, &ed);
1057 /* Generate a SOF event, and set a timer for EOF */
1058 static void ohci_sof(OHCIState *ohci)
1060 ohci->sof_time = qemu_get_clock(vm_clock);
1061 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1062 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1065 /* Process Control and Bulk lists. */
1066 static void ohci_process_lists(OHCIState *ohci, int completion)
1068 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1069 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
1070 dprintf("usb-ohci: head %x, cur %x\n",
1071 ohci->ctrl_head, ohci->ctrl_cur);
1072 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1074 ohci->status &= ~OHCI_STATUS_CLF;
1078 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1079 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1081 ohci->status &= ~OHCI_STATUS_BLF;
1086 /* Do frame processing on frame boundary */
1087 static void ohci_frame_boundary(void *opaque)
1089 OHCIState *ohci = opaque;
1090 struct ohci_hcca hcca;
1092 cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 0);
1094 /* Process all the lists at the end of the frame */
1095 if (ohci->ctl & OHCI_CTL_PLE) {
1098 n = ohci->frame_number & 0x1f;
1099 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1102 /* Cancel all pending packets if either of the lists has been disabled. */
1103 if (ohci->async_td &&
1104 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1105 usb_cancel_packet(&ohci->usb_packet);
1108 ohci->old_ctl = ohci->ctl;
1109 ohci_process_lists(ohci, 0);
1111 /* Frame boundary, so do EOF stuf here */
1112 ohci->frt = ohci->fit;
1114 /* XXX: endianness */
1115 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1116 hcca.frame = cpu_to_le32(ohci->frame_number);
1118 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1121 if (ohci->intr & ohci->intr_status)
1123 hcca.done = cpu_to_le32(ohci->done);
1125 ohci->done_count = 7;
1126 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1129 if (ohci->done_count != 7 && ohci->done_count != 0)
1132 /* Do SOF stuff here */
1135 /* Writeback HCCA */
1136 cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 1);
1139 /* Start sending SOF tokens across the USB bus, lists are processed in
1142 static int ohci_bus_start(OHCIState *ohci)
1144 ohci->eof_timer = qemu_new_timer(vm_clock,
1145 ohci_frame_boundary,
1148 if (ohci->eof_timer == NULL) {
1149 fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
1150 /* TODO: Signal unrecoverable error */
1154 dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
1161 /* Stop sending SOF tokens on the bus */
1162 static void ohci_bus_stop(OHCIState *ohci)
1164 if (ohci->eof_timer)
1165 qemu_del_timer(ohci->eof_timer);
1166 ohci->eof_timer = NULL;
1169 /* Sets a flag in a port status register but only set it if the port is
1170 * connected, if not set ConnectStatusChange flag. If flag is enabled
1173 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1177 /* writing a 0 has no effect */
1181 /* If CurrentConnectStatus is cleared we set
1182 * ConnectStatusChange
1184 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1185 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1186 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1187 /* TODO: CSC is a wakeup event */
1192 if (ohci->rhport[i].ctrl & val)
1196 ohci->rhport[i].ctrl |= val;
1201 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1202 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1206 if (val != ohci->fi) {
1207 dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1208 ohci->name, ohci->fi, ohci->fi);
1214 static void ohci_port_power(OHCIState *ohci, int i, int p)
1217 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1219 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1226 /* Set HcControlRegister */
1227 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1232 old_state = ohci->ctl & OHCI_CTL_HCFS;
1234 new_state = ohci->ctl & OHCI_CTL_HCFS;
1236 /* no state change */
1237 if (old_state == new_state)
1240 switch (new_state) {
1241 case OHCI_USB_OPERATIONAL:
1242 ohci_bus_start(ohci);
1244 case OHCI_USB_SUSPEND:
1245 ohci_bus_stop(ohci);
1246 dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
1248 case OHCI_USB_RESUME:
1249 dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
1251 case OHCI_USB_RESET:
1253 dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
1258 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1263 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1264 return (ohci->frt << 31);
1266 /* Being in USB operational state guarnatees sof_time was
1269 tks = qemu_get_clock(vm_clock) - ohci->sof_time;
1271 /* avoid muldiv if possible */
1272 if (tks >= usb_frame_time)
1273 return (ohci->frt << 31);
1275 tks = muldiv64(1, tks, usb_bit_time);
1276 fr = (uint16_t)(ohci->fi - tks);
1278 return (ohci->frt << 31) | fr;
1282 /* Set root hub status */
1283 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1287 old_state = ohci->rhstatus;
1289 /* write 1 to clear OCIC */
1290 if (val & OHCI_RHS_OCIC)
1291 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1293 if (val & OHCI_RHS_LPS) {
1296 for (i = 0; i < ohci->num_ports; i++)
1297 ohci_port_power(ohci, i, 0);
1298 dprintf("usb-ohci: powered down all ports\n");
1301 if (val & OHCI_RHS_LPSC) {
1304 for (i = 0; i < ohci->num_ports; i++)
1305 ohci_port_power(ohci, i, 1);
1306 dprintf("usb-ohci: powered up all ports\n");
1309 if (val & OHCI_RHS_DRWE)
1310 ohci->rhstatus |= OHCI_RHS_DRWE;
1312 if (val & OHCI_RHS_CRWE)
1313 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1315 if (old_state != ohci->rhstatus)
1316 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1319 /* Set root hub port status */
1320 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1325 port = &ohci->rhport[portnum];
1326 old_state = port->ctrl;
1328 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1329 if (val & OHCI_PORT_WTC)
1330 port->ctrl &= ~(val & OHCI_PORT_WTC);
1332 if (val & OHCI_PORT_CCS)
1333 port->ctrl &= ~OHCI_PORT_PES;
1335 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1337 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
1338 dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
1340 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1341 dprintf("usb-ohci: port %d: RESET\n", portnum);
1342 usb_send_msg(port->port.dev, USB_MSG_RESET);
1343 port->ctrl &= ~OHCI_PORT_PRS;
1344 /* ??? Should this also set OHCI_PORT_PESC. */
1345 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1348 /* Invert order here to ensure in ambiguous case, device is
1351 if (val & OHCI_PORT_LSDA)
1352 ohci_port_power(ohci, portnum, 0);
1353 if (val & OHCI_PORT_PPS)
1354 ohci_port_power(ohci, portnum, 1);
1356 if (old_state != port->ctrl)
1357 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1362 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1364 OHCIState *ohci = ptr;
1367 /* Only aligned reads are allowed on OHCI */
1369 fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1371 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1372 /* HcRhPortStatus */
1373 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1375 switch (addr >> 2) {
1376 case 0: /* HcRevision */
1380 case 1: /* HcControl */
1384 case 2: /* HcCommandStatus */
1385 retval = ohci->status;
1388 case 3: /* HcInterruptStatus */
1389 retval = ohci->intr_status;
1392 case 4: /* HcInterruptEnable */
1393 case 5: /* HcInterruptDisable */
1394 retval = ohci->intr;
1397 case 6: /* HcHCCA */
1398 retval = ohci->hcca;
1401 case 7: /* HcPeriodCurrentED */
1402 retval = ohci->per_cur;
1405 case 8: /* HcControlHeadED */
1406 retval = ohci->ctrl_head;
1409 case 9: /* HcControlCurrentED */
1410 retval = ohci->ctrl_cur;
1413 case 10: /* HcBulkHeadED */
1414 retval = ohci->bulk_head;
1417 case 11: /* HcBulkCurrentED */
1418 retval = ohci->bulk_cur;
1421 case 12: /* HcDoneHead */
1422 retval = ohci->done;
1425 case 13: /* HcFmInterretval */
1426 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1429 case 14: /* HcFmRemaining */
1430 retval = ohci_get_frame_remaining(ohci);
1433 case 15: /* HcFmNumber */
1434 retval = ohci->frame_number;
1437 case 16: /* HcPeriodicStart */
1438 retval = ohci->pstart;
1441 case 17: /* HcLSThreshold */
1445 case 18: /* HcRhDescriptorA */
1446 retval = ohci->rhdesc_a;
1449 case 19: /* HcRhDescriptorB */
1450 retval = ohci->rhdesc_b;
1453 case 20: /* HcRhStatus */
1454 retval = ohci->rhstatus;
1457 /* PXA27x specific registers */
1458 case 24: /* HcStatus */
1459 retval = ohci->hstatus & ohci->hmask;
1462 case 25: /* HcHReset */
1463 retval = ohci->hreset;
1466 case 26: /* HcHInterruptEnable */
1467 retval = ohci->hmask;
1470 case 27: /* HcHInterruptTest */
1471 retval = ohci->htest;
1475 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1476 retval = 0xffffffff;
1480 #ifdef TARGET_WORDS_BIGENDIAN
1481 retval = bswap32(retval);
1486 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1488 OHCIState *ohci = ptr;
1490 #ifdef TARGET_WORDS_BIGENDIAN
1494 /* Only aligned reads are allowed on OHCI */
1496 fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1500 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1501 /* HcRhPortStatus */
1502 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1506 switch (addr >> 2) {
1507 case 1: /* HcControl */
1508 ohci_set_ctl(ohci, val);
1511 case 2: /* HcCommandStatus */
1512 /* SOC is read-only */
1513 val = (val & ~OHCI_STATUS_SOC);
1515 /* Bits written as '0' remain unchanged in the register */
1516 ohci->status |= val;
1518 if (ohci->status & OHCI_STATUS_HCR)
1522 case 3: /* HcInterruptStatus */
1523 ohci->intr_status &= ~val;
1524 ohci_intr_update(ohci);
1527 case 4: /* HcInterruptEnable */
1529 ohci_intr_update(ohci);
1532 case 5: /* HcInterruptDisable */
1534 ohci_intr_update(ohci);
1537 case 6: /* HcHCCA */
1538 ohci->hcca = val & OHCI_HCCA_MASK;
1541 case 8: /* HcControlHeadED */
1542 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1545 case 9: /* HcControlCurrentED */
1546 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1549 case 10: /* HcBulkHeadED */
1550 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1553 case 11: /* HcBulkCurrentED */
1554 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1557 case 13: /* HcFmInterval */
1558 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1559 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1560 ohci_set_frame_interval(ohci, val);
1563 case 15: /* HcFmNumber */
1566 case 16: /* HcPeriodicStart */
1567 ohci->pstart = val & 0xffff;
1570 case 17: /* HcLSThreshold */
1571 ohci->lst = val & 0xffff;
1574 case 18: /* HcRhDescriptorA */
1575 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1576 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1579 case 19: /* HcRhDescriptorB */
1582 case 20: /* HcRhStatus */
1583 ohci_set_hub_status(ohci, val);
1586 /* PXA27x specific registers */
1587 case 24: /* HcStatus */
1588 ohci->hstatus &= ~(val & ohci->hmask);
1590 case 25: /* HcHReset */
1591 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1592 if (val & OHCI_HRESET_FSBIR)
1596 case 26: /* HcHInterruptEnable */
1600 case 27: /* HcHInterruptTest */
1605 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1610 /* Only dword reads are defined on OHCI register space */
1611 static CPUReadMemoryFunc *ohci_readfn[3]={
1617 /* Only dword writes are defined on OHCI register space */
1618 static CPUWriteMemoryFunc *ohci_writefn[3]={
1624 static void usb_ohci_init(OHCIState *ohci, int num_ports, int devfn,
1625 qemu_irq irq, enum ohci_type type, const char *name)
1629 if (usb_frame_time == 0) {
1630 #ifdef OHCI_TIME_WARP
1631 usb_frame_time = ticks_per_sec;
1632 usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000);
1634 usb_frame_time = muldiv64(1, ticks_per_sec, 1000);
1635 if (ticks_per_sec >= USB_HZ) {
1636 usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ);
1641 dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1642 usb_frame_time, usb_bit_time);
1645 ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
1651 ohci->num_ports = num_ports;
1652 for (i = 0; i < num_ports; i++) {
1653 qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach);
1657 qemu_register_reset(ohci_reset, ohci);
1666 static void ohci_mapfunc(PCIDevice *pci_dev, int i,
1667 uint32_t addr, uint32_t size, int type)
1669 OHCIPCIState *ohci = (OHCIPCIState *)pci_dev;
1670 cpu_register_physical_memory(addr, size, ohci->state.mem);
1673 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn)
1677 ohci = (OHCIPCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci),
1680 fprintf(stderr, "usb-ohci: Failed to register PCI device\n");
1684 pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
1685 pci_config_set_device_id(ohci->pci_dev.config,
1686 PCI_DEVICE_ID_APPLE_IPID_USB);
1687 ohci->pci_dev.config[0x09] = 0x10; /* OHCI */
1688 pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
1689 ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1691 usb_ohci_init(&ohci->state, num_ports, devfn, ohci->pci_dev.irq[0],
1692 OHCI_TYPE_PCI, ohci->pci_dev.name);
1694 pci_register_io_region((struct PCIDevice *)ohci, 0, 256,
1695 PCI_ADDRESS_SPACE_MEM, ohci_mapfunc);
1698 void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
1701 OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
1703 usb_ohci_init(ohci, num_ports, devfn, irq,
1704 OHCI_TYPE_PXA, "OHCI USB");
1706 cpu_register_physical_memory(base, 0x1000, ohci->mem);
1709 int usb_ohci_init_omap(target_phys_addr_t base, uint32_t region_size,
1710 int num_ports, qemu_irq irq)
1712 OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
1714 usb_ohci_init(ohci, num_ports, -1, irq, OHCI_TYPE_OMAP, "OHCI USB");