4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #define PCI_VENDOR_ID 0x00 /* 16 bits */
29 #define PCI_DEVICE_ID 0x02 /* 16 bits */
30 #define PCI_COMMAND 0x04 /* 16 bits */
31 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
32 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
33 #define PCI_CLASS_DEVICE 0x0a /* Device class */
34 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
35 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
36 #define PCI_MIN_GNT 0x3e /* 8 bits */
37 #define PCI_MAX_LAT 0x3f /* 8 bits */
39 /* just used for simpler irq handling. */
40 #define PCI_DEVICES_MAX 64
41 #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
46 void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
47 uint32_t config_reg; /* XXX: suppress */
48 openpic_t *openpic; /* XXX: suppress */
49 PCIDevice *devices[256];
52 target_phys_addr_t pci_mem_base;
53 static int pci_irq_index;
54 static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
55 static PCIBus *first_bus;
57 static PCIBus *pci_register_bus(void)
60 bus = qemu_mallocz(sizeof(PCIBus));
65 void generic_pci_save(QEMUFile* f, void *opaque)
67 PCIDevice* s=(PCIDevice*)opaque;
69 qemu_put_buffer(f, s->config, 256);
72 int generic_pci_load(QEMUFile* f, void *opaque, int version_id)
74 PCIDevice* s=(PCIDevice*)opaque;
79 qemu_get_buffer(f, s->config, 256);
83 /* -1 for devfn means auto assign */
84 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
85 int instance_size, int devfn,
86 PCIConfigReadFunc *config_read,
87 PCIConfigWriteFunc *config_write)
91 if (pci_irq_index >= PCI_DEVICES_MAX)
95 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
96 if (!bus->devices[devfn])
102 pci_dev = qemu_mallocz(instance_size);
106 pci_dev->devfn = devfn;
107 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
110 config_read = pci_default_read_config;
112 config_write = pci_default_write_config;
113 pci_dev->config_read = config_read;
114 pci_dev->config_write = config_write;
115 pci_dev->irq_index = pci_irq_index++;
116 bus->devices[devfn] = pci_dev;
120 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
121 uint32_t size, int type,
122 PCIMapIORegionFunc *map_func)
126 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
128 r = &pci_dev->io_regions[region_num];
132 r->map_func = map_func;
135 static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
141 static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
144 return s->config_reg;
147 static void pci_update_mappings(PCIDevice *d)
151 uint32_t last_addr, new_addr, config_ofs;
153 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
154 for(i = 0; i < PCI_NUM_REGIONS; i++) {
155 r = &d->io_regions[i];
156 if (i == PCI_ROM_SLOT) {
159 config_ofs = 0x10 + i * 4;
162 if (r->type & PCI_ADDRESS_SPACE_IO) {
163 if (cmd & PCI_COMMAND_IO) {
164 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
166 new_addr = new_addr & ~(r->size - 1);
167 last_addr = new_addr + r->size - 1;
168 /* NOTE: we have only 64K ioports on PC */
169 if (last_addr <= new_addr || new_addr == 0 ||
170 last_addr >= 0x10000) {
177 if (cmd & PCI_COMMAND_MEMORY) {
178 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
180 /* the ROM slot has a specific enable bit */
181 if (i == PCI_ROM_SLOT && !(new_addr & 1))
183 new_addr = new_addr & ~(r->size - 1);
184 last_addr = new_addr + r->size - 1;
185 /* NOTE: we do not support wrapping */
186 /* XXX: as we cannot support really dynamic
187 mappings, we handle specific values as invalid
189 if (last_addr <= new_addr || new_addr == 0 ||
198 /* now do the real mapping */
199 if (new_addr != r->addr) {
201 if (r->type & PCI_ADDRESS_SPACE_IO) {
203 /* NOTE: specific hack for IDE in PC case:
204 only one byte must be mapped. */
205 class = d->config[0x0a] | (d->config[0x0b] << 8);
206 if (class == 0x0101 && r->size == 4) {
207 isa_unassign_ioport(r->addr + 2, 1);
209 isa_unassign_ioport(r->addr, r->size);
212 cpu_register_physical_memory(r->addr + pci_mem_base,
219 r->map_func(d, i, r->addr, r->size, r->type);
226 uint32_t pci_default_read_config(PCIDevice *d,
227 uint32_t address, int len)
232 val = d->config[address];
235 val = le16_to_cpu(*(uint16_t *)(d->config + address));
239 val = le32_to_cpu(*(uint32_t *)(d->config + address));
245 void pci_default_write_config(PCIDevice *d,
246 uint32_t address, uint32_t val, int len)
251 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
252 (address >= 0x30 && address < 0x34))) {
256 if ( address >= 0x30 ) {
259 reg = (address - 0x10) >> 2;
261 r = &d->io_regions[reg];
264 /* compute the stored value */
265 if (reg == PCI_ROM_SLOT) {
266 /* keep ROM enable bit */
267 val &= (~(r->size - 1)) | 1;
269 val &= ~(r->size - 1);
272 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
273 pci_update_mappings(d);
277 /* not efficient, but simple */
279 for(i = 0; i < len; i++) {
280 /* default read/write accesses */
281 switch(d->config[0x0e]) {
294 case 0x10 ... 0x27: /* base */
295 case 0x30 ... 0x33: /* rom */
316 case 0x38 ... 0x3b: /* rom */
327 d->config[addr] = val;
334 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
335 /* if the command register is modified, we must modify the mappings */
336 pci_update_mappings(d);
340 static void pci_data_write(void *opaque, uint32_t addr,
341 uint32_t val, int len)
345 int config_addr, bus_num;
347 #if defined(DEBUG_PCI) && 0
348 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
349 s->config_reg, val, len);
351 if (!(s->config_reg & (1 << 31))) {
354 if ((s->config_reg & 0x3) != 0) {
357 bus_num = (s->config_reg >> 16) & 0xff;
360 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
363 config_addr = (s->config_reg & 0xfc) | (addr & 3);
364 #if defined(DEBUG_PCI)
365 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
366 pci_dev->name, config_addr, val, len);
368 pci_dev->config_write(pci_dev, config_addr, val, len);
371 static uint32_t pci_data_read(void *opaque, uint32_t addr,
376 int config_addr, bus_num;
379 if (!(s->config_reg & (1 << 31)))
381 if ((s->config_reg & 0x3) != 0)
383 bus_num = (s->config_reg >> 16) & 0xff;
386 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
403 config_addr = (s->config_reg & 0xfc) | (addr & 3);
404 val = pci_dev->config_read(pci_dev, config_addr, len);
405 #if defined(DEBUG_PCI)
406 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
407 pci_dev->name, config_addr, val, len);
410 #if defined(DEBUG_PCI) && 0
411 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
412 s->config_reg, val, len);
417 static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
419 pci_data_write(opaque, addr, val, 1);
422 static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
424 pci_data_write(opaque, addr, val, 2);
427 static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
429 pci_data_write(opaque, addr, val, 4);
432 static uint32_t pci_data_readb(void* opaque, uint32_t addr)
434 return pci_data_read(opaque, addr, 1);
437 static uint32_t pci_data_readw(void* opaque, uint32_t addr)
439 return pci_data_read(opaque, addr, 2);
442 static uint32_t pci_data_readl(void* opaque, uint32_t addr)
444 return pci_data_read(opaque, addr, 4);
447 /* i440FX PCI bridge */
449 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);
451 PCIBus *i440fx_init(void)
456 s = pci_register_bus();
457 s->set_irq = piix3_set_irq;
459 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
460 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
462 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
463 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
464 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
465 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
466 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
467 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
469 d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0,
472 d->config[0x00] = 0x86; // vendor_id
473 d->config[0x01] = 0x80;
474 d->config[0x02] = 0x37; // device_id
475 d->config[0x03] = 0x12;
476 d->config[0x08] = 0x02; // revision
477 d->config[0x0a] = 0x00; // class_sub = host2pci
478 d->config[0x0b] = 0x06; // class_base = PCI_bridge
479 d->config[0x0e] = 0x00; // header_type
483 /* PIIX3 PCI to ISA bridge */
485 typedef struct PIIX3State {
489 PIIX3State *piix3_state;
491 /* return the global irq number corresponding to a given device irq
492 pin. We could also use the bus number to have a more precise
494 static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
497 slot_addend = (pci_dev->devfn >> 3) - 1;
498 return (irq_num + slot_addend) & 3;
501 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)
503 int irq_index, shift, pic_irq, pic_level;
506 irq_num = pci_slot_get_pirq(pci_dev, irq_num);
507 irq_index = pci_dev->irq_index;
508 p = &pci_irq_levels[irq_num][irq_index >> 5];
509 shift = (irq_index & 0x1f);
510 *p = (*p & ~(1 << shift)) | (level << shift);
512 /* now we change the pic irq level according to the piix irq mappings */
513 pic_irq = piix3_state->dev.config[0x60 + irq_num];
515 /* the pic level is the logical OR of all the PCI irqs mapped
518 #if (PCI_IRQ_WORDS == 2)
519 pic_level = ((pci_irq_levels[irq_num][0] |
520 pci_irq_levels[irq_num][1]) != 0);
525 for(i = 0; i < PCI_IRQ_WORDS; i++) {
526 if (pci_irq_levels[irq_num][i]) {
533 pic_set_irq(pic_irq, pic_level);
537 static void piix3_reset(PIIX3State *d)
539 uint8_t *pci_conf = d->dev.config;
541 pci_conf[0x04] = 0x07; // master, memory and I/O
542 pci_conf[0x05] = 0x00;
543 pci_conf[0x06] = 0x00;
544 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
545 pci_conf[0x4c] = 0x4d;
546 pci_conf[0x4e] = 0x03;
547 pci_conf[0x4f] = 0x00;
548 pci_conf[0x60] = 0x80;
549 pci_conf[0x69] = 0x02;
550 pci_conf[0x70] = 0x80;
551 pci_conf[0x76] = 0x0c;
552 pci_conf[0x77] = 0x0c;
553 pci_conf[0x78] = 0x02;
554 pci_conf[0x79] = 0x00;
555 pci_conf[0x80] = 0x00;
556 pci_conf[0x82] = 0x00;
557 pci_conf[0xa0] = 0x08;
558 pci_conf[0xa0] = 0x08;
559 pci_conf[0xa2] = 0x00;
560 pci_conf[0xa3] = 0x00;
561 pci_conf[0xa4] = 0x00;
562 pci_conf[0xa5] = 0x00;
563 pci_conf[0xa6] = 0x00;
564 pci_conf[0xa7] = 0x00;
565 pci_conf[0xa8] = 0x0f;
566 pci_conf[0xaa] = 0x00;
567 pci_conf[0xab] = 0x00;
568 pci_conf[0xac] = 0x00;
569 pci_conf[0xae] = 0x00;
572 void piix3_init(PCIBus *bus)
577 d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
579 register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
582 pci_conf = d->dev.config;
584 pci_conf[0x00] = 0x86; // Intel
585 pci_conf[0x01] = 0x80;
586 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
587 pci_conf[0x03] = 0x70;
588 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
589 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
590 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
597 static inline void set_config(PCIBus *s, target_phys_addr_t addr)
601 for(i = 0; i < 11; i++) {
602 if ((addr & (1 << (11 + i))) != 0)
605 devfn = ((addr >> 8) & 7) | (i << 3);
606 s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
609 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
613 pci_data_write(s, addr, val, 1);
616 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
620 #ifdef TARGET_WORDS_BIGENDIAN
623 pci_data_write(s, addr, val, 2);
626 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
630 #ifdef TARGET_WORDS_BIGENDIAN
633 pci_data_write(s, addr, val, 4);
636 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
641 val = pci_data_read(s, addr, 1);
645 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
650 val = pci_data_read(s, addr, 2);
651 #ifdef TARGET_WORDS_BIGENDIAN
657 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
662 val = pci_data_read(s, addr, 4);
663 #ifdef TARGET_WORDS_BIGENDIAN
669 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
675 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
681 static void prep_set_irq(PCIDevice *d, int irq_num, int level)
683 /* XXX: we do not simulate the hardware - we rely on the BIOS to
684 set correctly for irq line field */
685 pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
688 PCIBus *pci_prep_init(void)
694 s = pci_register_bus();
695 s->set_irq = prep_set_irq;
697 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
698 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
700 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
701 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
702 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
703 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
704 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
705 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
707 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
709 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
711 d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
714 /* XXX: put correct IDs */
715 d->config[0x00] = 0x11; // vendor_id
716 d->config[0x01] = 0x10;
717 d->config[0x02] = 0x26; // device_id
718 d->config[0x03] = 0x00;
719 d->config[0x08] = 0x02; // revision
720 d->config[0x0a] = 0x04; // class_sub = pci2pci
721 d->config[0x0b] = 0x06; // class_base = PCI_bridge
722 d->config[0x0e] = 0x01; // header_type
730 /* Grackle PCI host */
731 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
735 #ifdef TARGET_WORDS_BIGENDIAN
741 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
747 #ifdef TARGET_WORDS_BIGENDIAN
753 static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
754 &pci_grackle_config_writel,
755 &pci_grackle_config_writel,
756 &pci_grackle_config_writel,
759 static CPUReadMemoryFunc *pci_grackle_config_read[] = {
760 &pci_grackle_config_readl,
761 &pci_grackle_config_readl,
762 &pci_grackle_config_readl,
765 static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,
769 pci_data_write(s, addr, val, 1);
772 static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,
776 #ifdef TARGET_WORDS_BIGENDIAN
779 pci_data_write(s, addr, val, 2);
782 static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,
786 #ifdef TARGET_WORDS_BIGENDIAN
789 pci_data_write(s, addr, val, 4);
792 static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)
796 val = pci_data_read(s, addr, 1);
800 static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)
804 val = pci_data_read(s, addr, 2);
805 #ifdef TARGET_WORDS_BIGENDIAN
811 static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)
816 val = pci_data_read(s, addr, 4);
817 #ifdef TARGET_WORDS_BIGENDIAN
823 static CPUWriteMemoryFunc *pci_grackle_write[] = {
829 static CPUReadMemoryFunc *pci_grackle_read[] = {
836 /* Uninorth PCI host (for all Mac99 and newer machines */
837 static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
843 #ifdef TARGET_WORDS_BIGENDIAN
847 for (i = 11; i < 32; i++) {
848 if ((val & (1 << i)) != 0)
852 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
854 s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
858 static uint32_t pci_unin_main_config_readl (void *opaque,
859 target_phys_addr_t addr)
865 devfn = (s->config_reg >> 8) & 0xFF;
866 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
867 #ifdef TARGET_WORDS_BIGENDIAN
874 static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
875 &pci_unin_main_config_writel,
876 &pci_unin_main_config_writel,
877 &pci_unin_main_config_writel,
880 static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
881 &pci_unin_main_config_readl,
882 &pci_unin_main_config_readl,
883 &pci_unin_main_config_readl,
886 static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr,
890 pci_data_write(s, addr & 7, val, 1);
893 static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr,
897 #ifdef TARGET_WORDS_BIGENDIAN
900 pci_data_write(s, addr & 7, val, 2);
903 static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr,
907 #ifdef TARGET_WORDS_BIGENDIAN
910 pci_data_write(s, addr & 7, val, 4);
913 static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr)
918 val = pci_data_read(s, addr & 7, 1);
923 static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr)
928 val = pci_data_read(s, addr & 7, 2);
929 #ifdef TARGET_WORDS_BIGENDIAN
936 static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr)
941 val = pci_data_read(s, addr, 4);
942 #ifdef TARGET_WORDS_BIGENDIAN
949 static CPUWriteMemoryFunc *pci_unin_main_write[] = {
950 &pci_unin_main_writeb,
951 &pci_unin_main_writew,
952 &pci_unin_main_writel,
955 static CPUReadMemoryFunc *pci_unin_main_read[] = {
956 &pci_unin_main_readb,
957 &pci_unin_main_readw,
958 &pci_unin_main_readl,
963 static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
968 #ifdef TARGET_WORDS_BIGENDIAN
971 s->config_reg = 0x80000000 | (val & ~0x00000001);
974 static uint32_t pci_unin_config_readl (void *opaque,
975 target_phys_addr_t addr)
980 val = (s->config_reg | 0x00000001) & ~0x80000000;
981 #ifdef TARGET_WORDS_BIGENDIAN
988 static CPUWriteMemoryFunc *pci_unin_config_write[] = {
989 &pci_unin_config_writel,
990 &pci_unin_config_writel,
991 &pci_unin_config_writel,
994 static CPUReadMemoryFunc *pci_unin_config_read[] = {
995 &pci_unin_config_readl,
996 &pci_unin_config_readl,
997 &pci_unin_config_readl,
1000 static void pci_unin_writeb (void *opaque, target_phys_addr_t addr,
1004 pci_data_write(s, addr & 3, val, 1);
1007 static void pci_unin_writew (void *opaque, target_phys_addr_t addr,
1011 #ifdef TARGET_WORDS_BIGENDIAN
1014 pci_data_write(s, addr & 3, val, 2);
1017 static void pci_unin_writel (void *opaque, target_phys_addr_t addr,
1021 #ifdef TARGET_WORDS_BIGENDIAN
1024 pci_data_write(s, addr & 3, val, 4);
1027 static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr)
1032 val = pci_data_read(s, addr & 3, 1);
1037 static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr)
1042 val = pci_data_read(s, addr & 3, 2);
1043 #ifdef TARGET_WORDS_BIGENDIAN
1050 static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr)
1055 val = pci_data_read(s, addr & 3, 4);
1056 #ifdef TARGET_WORDS_BIGENDIAN
1063 static CPUWriteMemoryFunc *pci_unin_write[] = {
1069 static CPUReadMemoryFunc *pci_unin_read[] = {
1076 static void pmac_set_irq(PCIDevice *d, int irq_num, int level)
1079 /* XXX: we do not simulate the hardware - we rely on the BIOS to
1080 set correctly for irq line field */
1081 openpic = d->bus->openpic;
1084 openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level);
1088 void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
1090 bus->openpic = openpic;
1093 PCIBus *pci_pmac_init(void)
1097 int pci_mem_config, pci_mem_data;
1099 /* Use values found on a real PowerMac */
1100 /* Uninorth main bus */
1101 s = pci_register_bus();
1102 s->set_irq = pmac_set_irq;
1104 pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
1105 pci_unin_main_config_write, s);
1106 pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
1107 pci_unin_main_write, s);
1108 cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
1109 cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
1110 s->devfn_min = 11 << 3;
1111 d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice),
1112 11 << 3, NULL, NULL);
1113 d->config[0x00] = 0x6b; // vendor_id : Apple
1114 d->config[0x01] = 0x10;
1115 d->config[0x02] = 0x1F; // device_id
1116 d->config[0x03] = 0x00;
1117 d->config[0x08] = 0x00; // revision
1118 d->config[0x0A] = 0x00; // class_sub = pci host
1119 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1120 d->config[0x0C] = 0x08; // cache_line_size
1121 d->config[0x0D] = 0x10; // latency_timer
1122 d->config[0x0E] = 0x00; // header_type
1123 d->config[0x34] = 0x00; // capabilities_pointer
1125 #if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
1126 /* pci-to-pci bridge */
1127 d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
1129 d->config[0x00] = 0x11; // vendor_id : TI
1130 d->config[0x01] = 0x10;
1131 d->config[0x02] = 0x26; // device_id
1132 d->config[0x03] = 0x00;
1133 d->config[0x08] = 0x05; // revision
1134 d->config[0x0A] = 0x04; // class_sub = pci2pci
1135 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1136 d->config[0x0C] = 0x08; // cache_line_size
1137 d->config[0x0D] = 0x20; // latency_timer
1138 d->config[0x0E] = 0x01; // header_type
1140 d->config[0x18] = 0x01; // primary_bus
1141 d->config[0x19] = 0x02; // secondary_bus
1142 d->config[0x1A] = 0x02; // subordinate_bus
1143 d->config[0x1B] = 0x20; // secondary_latency_timer
1144 d->config[0x1C] = 0x11; // io_base
1145 d->config[0x1D] = 0x01; // io_limit
1146 d->config[0x20] = 0x00; // memory_base
1147 d->config[0x21] = 0x80;
1148 d->config[0x22] = 0x00; // memory_limit
1149 d->config[0x23] = 0x80;
1150 d->config[0x24] = 0x01; // prefetchable_memory_base
1151 d->config[0x25] = 0x80;
1152 d->config[0x26] = 0xF1; // prefectchable_memory_limit
1153 d->config[0x27] = 0x7F;
1154 // d->config[0x34] = 0xdc // capabilities_pointer
1156 #if 0 // XXX: not needed for now
1157 /* Uninorth AGP bus */
1159 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1160 pci_unin_config_write, s);
1161 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1163 cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
1164 cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
1166 d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
1168 d->config[0x00] = 0x6b; // vendor_id : Apple
1169 d->config[0x01] = 0x10;
1170 d->config[0x02] = 0x20; // device_id
1171 d->config[0x03] = 0x00;
1172 d->config[0x08] = 0x00; // revision
1173 d->config[0x0A] = 0x00; // class_sub = pci host
1174 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1175 d->config[0x0C] = 0x08; // cache_line_size
1176 d->config[0x0D] = 0x10; // latency_timer
1177 d->config[0x0E] = 0x00; // header_type
1178 // d->config[0x34] = 0x80; // capabilities_pointer
1181 #if 0 // XXX: not needed for now
1182 /* Uninorth internal bus */
1184 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1185 pci_unin_config_write, s);
1186 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1188 cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
1189 cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
1191 d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
1192 3, 11 << 3, NULL, NULL);
1193 d->config[0x00] = 0x6b; // vendor_id : Apple
1194 d->config[0x01] = 0x10;
1195 d->config[0x02] = 0x1E; // device_id
1196 d->config[0x03] = 0x00;
1197 d->config[0x08] = 0x00; // revision
1198 d->config[0x0A] = 0x00; // class_sub = pci host
1199 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1200 d->config[0x0C] = 0x08; // cache_line_size
1201 d->config[0x0D] = 0x10; // latency_timer
1202 d->config[0x0E] = 0x00; // header_type
1203 d->config[0x34] = 0x00; // capabilities_pointer
1207 /* same values as PearPC - check this */
1208 d->config[0x00] = 0x11; // vendor_id
1209 d->config[0x01] = 0x10;
1210 d->config[0x02] = 0x26; // device_id
1211 d->config[0x03] = 0x00;
1212 d->config[0x08] = 0x02; // revision
1213 d->config[0x0a] = 0x04; // class_sub = pci2pci
1214 d->config[0x0b] = 0x06; // class_base = PCI_bridge
1215 d->config[0x0e] = 0x01; // header_type
1217 d->config[0x18] = 0x0; // primary_bus
1218 d->config[0x19] = 0x1; // secondary_bus
1219 d->config[0x1a] = 0x1; // subordinate_bus
1220 d->config[0x1c] = 0x10; // io_base
1221 d->config[0x1d] = 0x20; // io_limit
1223 d->config[0x20] = 0x80; // memory_base
1224 d->config[0x21] = 0x80;
1225 d->config[0x22] = 0x90; // memory_limit
1226 d->config[0x23] = 0x80;
1228 d->config[0x24] = 0x00; // prefetchable_memory_base
1229 d->config[0x25] = 0x84;
1230 d->config[0x26] = 0x00; // prefetchable_memory_limit
1231 d->config[0x27] = 0x85;
1236 /***********************************************************/
1237 /* generic PCI irq support */
1239 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1240 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
1242 PCIBus *bus = pci_dev->bus;
1243 bus->set_irq(pci_dev, irq_num, level);
1246 /***********************************************************/
1247 /* monitor info on PCI */
1249 static void pci_info_device(PCIDevice *d)
1254 term_printf(" Bus %2d, device %3d, function %d:\n",
1255 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
1256 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1260 term_printf("IDE controller");
1263 term_printf("Ethernet controller");
1266 term_printf("VGA controller");
1269 term_printf("Class %04x", class);
1272 term_printf(": PCI device %04x:%04x\n",
1273 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1274 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
1276 if (d->config[PCI_INTERRUPT_PIN] != 0) {
1277 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
1279 for(i = 0;i < PCI_NUM_REGIONS; i++) {
1280 r = &d->io_regions[i];
1282 term_printf(" BAR%d: ", i);
1283 if (r->type & PCI_ADDRESS_SPACE_IO) {
1284 term_printf("I/O at 0x%04x [0x%04x].\n",
1285 r->addr, r->addr + r->size - 1);
1287 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
1288 r->addr, r->addr + r->size - 1);
1296 PCIBus *bus = first_bus;
1301 for(devfn = 0; devfn < 256; devfn++) {
1302 d = bus->devices[devfn];
1309 /***********************************************************/
1310 /* XXX: the following should be moved to the PC BIOS */
1312 static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
1314 return cpu_inb(cpu_single_env, addr);
1317 static void isa_outb(uint32_t val, uint32_t addr)
1319 cpu_outb(cpu_single_env, addr, val);
1322 static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
1324 return cpu_inw(cpu_single_env, addr);
1327 static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
1329 cpu_outw(cpu_single_env, addr, val);
1332 static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
1334 return cpu_inl(cpu_single_env, addr);
1337 static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
1339 cpu_outl(cpu_single_env, addr, val);
1342 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
1345 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1346 (d->devfn << 8) | addr;
1347 pci_data_write(s, 0, val, 4);
1350 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
1353 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1354 (d->devfn << 8) | (addr & ~3);
1355 pci_data_write(s, addr & 3, val, 2);
1358 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
1361 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1362 (d->devfn << 8) | (addr & ~3);
1363 pci_data_write(s, addr & 3, val, 1);
1366 static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
1369 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1370 (d->devfn << 8) | addr;
1371 return pci_data_read(s, 0, 4);
1374 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
1377 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1378 (d->devfn << 8) | (addr & ~3);
1379 return pci_data_read(s, addr & 3, 2);
1382 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
1385 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1386 (d->devfn << 8) | (addr & ~3);
1387 return pci_data_read(s, addr & 3, 1);
1390 static uint32_t pci_bios_io_addr;
1391 static uint32_t pci_bios_mem_addr;
1392 /* host irqs corresponding to PCI irqs A-D */
1393 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
1395 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
1401 if ( region_num == PCI_ROM_SLOT ) {
1404 ofs = 0x10 + region_num * 4;
1407 pci_config_writel(d, ofs, addr);
1408 r = &d->io_regions[region_num];
1410 /* enable memory mappings */
1411 cmd = pci_config_readw(d, PCI_COMMAND);
1412 if ( region_num == PCI_ROM_SLOT )
1414 else if (r->type & PCI_ADDRESS_SPACE_IO)
1418 pci_config_writew(d, PCI_COMMAND, cmd);
1421 static void pci_bios_init_device(PCIDevice *d)
1426 int i, pin, pic_irq, vendor_id, device_id;
1428 class = pci_config_readw(d, PCI_CLASS_DEVICE);
1429 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1430 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1433 if (vendor_id == 0x8086 && device_id == 0x7010) {
1435 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
1436 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
1439 /* IDE: we map it as in ISA mode */
1440 pci_set_io_region_addr(d, 0, 0x1f0);
1441 pci_set_io_region_addr(d, 1, 0x3f4);
1442 pci_set_io_region_addr(d, 2, 0x170);
1443 pci_set_io_region_addr(d, 3, 0x374);
1447 if (vendor_id != 0x1234)
1449 /* VGA: map frame buffer to default Bochs VBE address */
1450 pci_set_io_region_addr(d, 0, 0xE0000000);
1454 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1455 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1456 if (vendor_id == 0x1014) {
1458 if (device_id == 0x0046 || device_id == 0xFFFF) {
1460 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
1465 if (vendor_id == 0x0106b &&
1466 (device_id == 0x0017 || device_id == 0x0022)) {
1468 pci_set_io_region_addr(d, 0, 0x80800000);
1473 /* default memory mappings */
1474 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1475 r = &d->io_regions[i];
1477 if (r->type & PCI_ADDRESS_SPACE_IO)
1478 paddr = &pci_bios_io_addr;
1480 paddr = &pci_bios_mem_addr;
1481 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
1482 pci_set_io_region_addr(d, i, *paddr);
1489 /* map the interrupt */
1490 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1492 pin = pci_slot_get_pirq(d, pin - 1);
1493 pic_irq = pci_irqs[pin];
1494 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1499 * This function initializes the PCI devices as a normal PCI BIOS
1500 * would do. It is provided just in case the BIOS has no support for
1503 void pci_bios_init(void)
1510 pci_bios_io_addr = 0xc000;
1511 pci_bios_mem_addr = 0xf0000000;
1513 /* activate IRQ mappings */
1516 for(i = 0; i < 4; i++) {
1518 /* set to trigger level */
1519 elcr[irq >> 3] |= (1 << (irq & 7));
1520 /* activate irq remapping in PIIX */
1521 pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1523 isa_outb(elcr[0], 0x4d0);
1524 isa_outb(elcr[1], 0x4d1);
1528 for(devfn = 0; devfn < 256; devfn++) {
1529 d = bus->devices[devfn];
1531 pci_bios_init_device(d);