4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define DATA_TYPE uint64_t
27 #define DATA_TYPE uint32_t
31 #define DATA_TYPE uint16_t
32 #define DATA_STYPE int16_t
36 #define DATA_TYPE uint8_t
37 #define DATA_STYPE int8_t
39 #error unsupported data size
42 #if ACCESS_TYPE < (NB_MMU_MODES)
44 #define CPU_MMU_INDEX ACCESS_TYPE
45 #define MMUSUFFIX _mmu
47 #elif ACCESS_TYPE == (NB_MMU_MODES)
49 #define CPU_MMU_INDEX (cpu_mmu_index(env))
50 #define MMUSUFFIX _mmu
52 #elif ACCESS_TYPE == (NB_MMU_MODES + 1)
54 #define CPU_MMU_INDEX (cpu_mmu_index(env))
55 #define MMUSUFFIX _cmmu
58 #error invalid ACCESS_TYPE
62 #define RES_TYPE uint64_t
67 #if ACCESS_TYPE == (NB_MMU_MODES + 1)
68 #define ADDR_READ addr_code
70 #define ADDR_READ addr_read
73 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
75 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
77 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
78 (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
80 #define CPU_TLB_ENTRY_BITS 4
82 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
86 asm volatile ("movl %1, %%edx\n"
91 "leal %5(%%edx, %%ebp), %%edx\n"
92 "cmpl (%%edx), %%eax\n"
101 "addl 12(%%edx), %%eax\n"
103 "movzbl (%%eax), %0\n"
105 "movzwl (%%eax), %0\n"
109 #error unsupported size
114 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
115 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
116 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
117 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
119 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
120 : "%eax", "%ecx", "%edx", "memory", "cc");
125 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
129 asm volatile ("movl %1, %%edx\n"
134 "leal %5(%%edx, %%ebp), %%edx\n"
135 "cmpl (%%edx), %%eax\n"
146 #error unsupported size
150 "addl 12(%%edx), %%eax\n"
152 "movsbl (%%eax), %0\n"
154 "movswl (%%eax), %0\n"
156 #error unsupported size
161 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
162 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
163 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
164 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
166 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
167 : "%eax", "%ecx", "%edx", "memory", "cc");
172 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
174 asm volatile ("movl %0, %%edx\n"
179 "leal %5(%%edx, %%ebp), %%edx\n"
180 "cmpl (%%edx), %%eax\n"
184 "movzbl %b1, %%edx\n"
186 "movzwl %w1, %%edx\n"
190 #error unsupported size
197 "addl 8(%%edx), %%eax\n"
199 "movb %b1, (%%eax)\n"
201 "movw %w1, (%%eax)\n"
205 #error unsupported size
215 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
216 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
217 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
218 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
220 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
221 : "%eax", "%ecx", "%edx", "memory", "cc");
226 /* generic load/store macros */
228 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
233 unsigned long physaddr;
237 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
238 mmu_idx = CPU_MMU_INDEX;
239 if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
240 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
241 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
243 physaddr = addr + env->tlb_table[mmu_idx][index].addend;
244 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
250 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
254 unsigned long physaddr;
258 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
259 mmu_idx = CPU_MMU_INDEX;
260 if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
261 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
262 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
264 physaddr = addr + env->tlb_table[mmu_idx][index].addend;
265 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
271 #if ACCESS_TYPE != (NB_MMU_MODES + 1)
273 /* generic store macro */
275 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
279 unsigned long physaddr;
283 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
284 mmu_idx = CPU_MMU_INDEX;
285 if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_write !=
286 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
287 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
289 physaddr = addr + env->tlb_table[mmu_idx][index].addend;
290 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
294 #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
298 #if ACCESS_TYPE != (NB_MMU_MODES + 1)
301 static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
307 u.i = glue(ldq, MEMSUFFIX)(ptr);
311 static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
318 glue(stq, MEMSUFFIX)(ptr, u.i);
320 #endif /* DATA_SIZE == 8 */
323 static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
329 u.i = glue(ldl, MEMSUFFIX)(ptr);
333 static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
340 glue(stl, MEMSUFFIX)(ptr, u.i);
342 #endif /* DATA_SIZE == 4 */
344 #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */