2 * Alpha emulation cpu definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #if !defined (__CPU_ALPHA_H__)
22 #define __CPU_ALPHA_H__
26 #define TARGET_LONG_BITS 64
32 #include "softfloat.h"
34 #define TARGET_HAS_ICE 1
36 #define ELF_MACHINE EM_ALPHA
38 #define ICACHE_LINE_SIZE 32
39 #define DCACHE_LINE_SIZE 32
41 #define TARGET_PAGE_BITS 12
45 /* Alpha major type */
51 ALPHA_EV5 = 5, /* 21164 */
52 ALPHA_EV45 = 6, /* 21064A */
53 ALPHA_EV56 = 7, /* 21164A */
64 ALPHA_LCA_1 = 1, /* 21066 */
65 ALPHA_LCA_2 = 2, /* 20166 */
66 ALPHA_LCA_3 = 3, /* 21068 */
67 ALPHA_LCA_4 = 4, /* 21068 */
68 ALPHA_LCA_5 = 5, /* 21066A */
69 ALPHA_LCA_6 = 6, /* 21068A */
74 ALPHA_EV5_1 = 1, /* Rev BA, CA */
75 ALPHA_EV5_2 = 2, /* Rev DA, EA */
76 ALPHA_EV5_3 = 3, /* Pass 3 */
77 ALPHA_EV5_4 = 4, /* Pass 3.2 */
78 ALPHA_EV5_5 = 5, /* Pass 4 */
83 ALPHA_EV45_1 = 1, /* Pass 1 */
84 ALPHA_EV45_2 = 2, /* Pass 1.1 */
85 ALPHA_EV45_3 = 3, /* Pass 2 */
90 ALPHA_EV56_1 = 1, /* Pass 1 */
91 ALPHA_EV56_2 = 2, /* Pass 2 */
95 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
96 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
97 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
98 IMPLVER_21364 = 3, /* EV7 & EV79 */
102 AMASK_BWX = 0x00000001,
103 AMASK_FIX = 0x00000002,
104 AMASK_CIX = 0x00000004,
105 AMASK_MVI = 0x00000100,
106 AMASK_TRAP = 0x00000200,
107 AMASK_PREFETCH = 0x00001000,
111 VAX_ROUND_NORMAL = 0,
116 IEEE_ROUND_NORMAL = 0,
123 /* IEEE floating-point operations encoding */
135 FP_ROUND_CHOPPED = 0x0,
136 FP_ROUND_MINUS = 0x1,
137 FP_ROUND_NORMAL = 0x2,
138 FP_ROUND_DYNAMIC = 0x3,
141 /* Internal processor registers */
142 /* XXX: TOFIX: most of those registers are implementation dependant */
163 IPR_HW_INT_CLR = 0x0E,
169 IPR_IC_FLUSH_ASM = 0x12,
179 IPR_DTB_ALTMODE = 0xA6,
226 typedef struct CPUAlphaState CPUAlphaState;
228 typedef struct pal_handler_t pal_handler_t;
229 struct pal_handler_t {
231 void (*reset)(CPUAlphaState *env);
232 /* Uncorrectable hardware error */
233 void (*machine_check)(CPUAlphaState *env);
234 /* Arithmetic exception */
235 void (*arithmetic)(CPUAlphaState *env);
236 /* Interrupt / correctable hardware error */
237 void (*interrupt)(CPUAlphaState *env);
239 void (*dfault)(CPUAlphaState *env);
241 void (*dtb_miss_pal)(CPUAlphaState *env);
242 /* DTB miss native */
243 void (*dtb_miss_native)(CPUAlphaState *env);
244 /* Unaligned access */
245 void (*unalign)(CPUAlphaState *env);
247 void (*itb_miss)(CPUAlphaState *env);
248 /* Instruction stream access violation */
249 void (*itb_acv)(CPUAlphaState *env);
250 /* Reserved or privileged opcode */
251 void (*opcdec)(CPUAlphaState *env);
252 /* Floating point exception */
253 void (*fen)(CPUAlphaState *env);
254 /* Call pal instruction */
255 void (*call_pal)(CPUAlphaState *env, uint32_t palcode);
258 #define NB_MMU_MODES 4
260 struct CPUAlphaState {
263 float_status fp_status;
268 uint64_t ipr[IPR_LAST];
271 int saved_mode; /* Used for HW_LD / HW_ST */
273 #if TARGET_LONG_BITS > HOST_LONG_BITS
274 /* temporary fixed-point registers
275 * used to emulate 64 bits target on 32 bits hosts
277 target_ulong t0, t1, t2;
280 double ft0, ft1, ft2;
282 /* Those resources are used only in Qemu core */
285 int user_mode_only; /* user mode only simulation */
289 int interrupt_request;
294 pal_handler_t *pal_handler;
297 #define CPUState CPUAlphaState
298 #define cpu_init cpu_alpha_init
299 #define cpu_exec cpu_alpha_exec
300 #define cpu_gen_code cpu_alpha_gen_code
301 #define cpu_signal_handler cpu_alpha_signal_handler
303 /* MMU modes definitions */
304 #define MMU_MODE0_SUFFIX _kernel
305 #define MMU_MODE1_SUFFIX _executive
306 #define MMU_MODE2_SUFFIX _supervisor
307 #define MMU_MODE3_SUFFIX _user
308 #define MMU_USER_IDX 3
309 static inline int cpu_mmu_index (CPUState *env)
311 return (env->ps >> 3) & 3;
314 #if defined(CONFIG_USER_ONLY)
315 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
319 /* FIXME: Zero syscall return value. */
326 FEATURE_ASN = 0x00000001,
327 FEATURE_SPS = 0x00000002,
328 FEATURE_VIRBND = 0x00000004,
329 FEATURE_TBCHK = 0x00000008,
336 EXCP_HW_INTERRUPT = 0x00E0,
337 EXCP_DFAULT = 0x01E0,
338 EXCP_DTB_MISS_PAL = 0x09E0,
339 EXCP_ITB_MISS = 0x03E0,
340 EXCP_ITB_ACV = 0x07E0,
341 EXCP_DTB_MISS_NATIVE = 0x08E0,
342 EXCP_UNALIGN = 0x11E0,
343 EXCP_OPCDEC = 0x13E0,
345 EXCP_CALL_PAL = 0x2000,
346 EXCP_CALL_PALP = 0x3000,
347 EXCP_CALL_PALE = 0x4000,
348 /* Pseudo exception for console */
349 EXCP_CONSOLE_DISPATCH = 0x4001,
350 EXCP_CONSOLE_FIXUP = 0x4002,
353 /* Arithmetic exception */
359 PALCODE_CALL = 0x00000000,
360 PALCODE_LD = 0x01000000,
361 PALCODE_ST = 0x02000000,
362 PALCODE_MFPR = 0x03000000,
363 PALCODE_MTPR = 0x04000000,
364 PALCODE_REI = 0x05000000,
365 PALCODE_INIT = 0xF0000000,
405 CPUAlphaState * cpu_alpha_init (const char *cpu_model);
406 int cpu_alpha_exec(CPUAlphaState *s);
407 /* you can call this signal handler from your SIGBUS and SIGSEGV
408 signal handlers to inform the virtual CPU of exceptions. non zero
409 is returned if the signal was handled by the virtual CPU. */
410 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
412 int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
413 int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
414 void cpu_loop_exit (void);
415 void pal_init (CPUState *env);
416 void call_pal (CPUState *env, int palcode);
418 #define CPU_PC_FROM_TB(env, tb) env->pc = tb->pc
420 #endif /* !defined (__CPU_ALPHA_H__) */