2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
30 #include "qemu-common.h"
35 static void add_flagname_to_bitmaps(char *flagname, uint32_t *features,
36 uint32_t *ext_features,
37 uint32_t *ext2_features,
38 uint32_t *ext3_features)
41 /* feature flags taken from "Intel Processor Identification and the CPUID
42 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
43 * about feature names, the Linux name is used. */
44 static const char *feature_name[] = {
45 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
46 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
47 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, NULL, "ds" /* Intel dts */, "acpi", "mmx",
48 "fxsr", "sse", "sse2", "ss", "ht" /* Intel htt */, "tm", "ia64", "pbe",
50 static const char *ext_feature_name[] = {
51 "pni" /* Intel,AMD sse3 */, NULL, NULL, "monitor", "ds_cpl", "vmx", NULL /* Linux smx */, "est",
52 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
53 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
54 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
56 static const char *ext2_feature_name[] = {
57 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
58 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", "mtrr", "pge", "mca", "cmov",
59 "pat", "pse36", NULL, NULL /* Linux mp */, "nx" /* Intel xd */, NULL, "mmxext", "mmx",
60 "fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp", NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow",
62 static const char *ext3_feature_name[] = {
63 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
64 "3dnowprefetch", "osvw", NULL /* Linux ibs */, NULL, "skinit", "wdt", NULL, NULL,
65 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
66 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
69 for ( i = 0 ; i < 32 ; i++ )
70 if (feature_name[i] && !strcmp (flagname, feature_name[i])) {
74 for ( i = 0 ; i < 32 ; i++ )
75 if (ext_feature_name[i] && !strcmp (flagname, ext_feature_name[i])) {
76 *ext_features |= 1 << i;
79 for ( i = 0 ; i < 32 ; i++ )
80 if (ext2_feature_name[i] && !strcmp (flagname, ext2_feature_name[i])) {
81 *ext2_features |= 1 << i;
84 for ( i = 0 ; i < 32 ; i++ )
85 if (ext3_feature_name[i] && !strcmp (flagname, ext3_feature_name[i])) {
86 *ext3_features |= 1 << i;
89 fprintf(stderr, "CPU feature %s not found\n", flagname);
92 typedef struct x86_def_t {
95 uint32_t vendor1, vendor2, vendor3;
99 uint32_t features, ext_features, ext2_features, ext3_features;
104 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
105 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
106 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX)
107 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
108 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
109 CPUID_PSE36 | CPUID_FXSR)
110 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
111 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
112 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
113 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
114 CPUID_PAE | CPUID_SEP | CPUID_APIC)
115 static x86_def_t x86_defs[] = {
120 .vendor1 = CPUID_VENDOR_AMD_1,
121 .vendor2 = CPUID_VENDOR_AMD_2,
122 .vendor3 = CPUID_VENDOR_AMD_3,
126 .features = PPRO_FEATURES |
127 /* these features are needed for Win64 and aren't fully implemented */
128 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
129 /* this feature is needed for Solaris and isn't fully implemented */
131 .ext_features = CPUID_EXT_SSE3,
132 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
133 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
134 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
135 .ext3_features = CPUID_EXT3_SVM,
136 .xlevel = 0x8000000A,
137 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
142 .vendor1 = CPUID_VENDOR_AMD_1,
143 .vendor2 = CPUID_VENDOR_AMD_2,
144 .vendor3 = CPUID_VENDOR_AMD_3,
148 /* Missing: CPUID_VME, CPUID_HT */
149 .features = PPRO_FEATURES |
150 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
152 /* Missing: CPUID_EXT_CX16, CPUID_EXT_POPCNT */
153 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
154 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
155 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
156 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
157 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
159 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
160 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
161 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
162 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
163 .ext3_features = CPUID_EXT3_SVM,
164 .xlevel = 0x8000001A,
165 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
173 /* The original CPU also implements these features:
174 CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
175 CPUID_TM, CPUID_PBE */
176 .features = PPRO_FEATURES |
177 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
179 /* The original CPU also implements these ext features:
180 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
181 CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
182 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3,
183 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
184 /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
185 .xlevel = 0x80000008,
186 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
195 .features = PPRO_FEATURES,
196 .ext_features = CPUID_EXT_SSE3,
198 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
206 /* The original CPU also implements these features:
207 CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
208 CPUID_TM, CPUID_PBE */
209 .features = PPRO_FEATURES | CPUID_VME |
210 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA,
211 /* The original CPU also implements these ext features:
212 CPUID_EXT_VMX, CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_XTPR,
214 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
215 .ext2_features = CPUID_EXT2_NX,
216 .xlevel = 0x80000008,
217 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
225 .features = I486_FEATURES,
234 .features = PENTIUM_FEATURES,
243 .features = PENTIUM2_FEATURES,
252 .features = PENTIUM3_FEATURES,
258 .vendor1 = 0x68747541, /* "Auth" */
259 .vendor2 = 0x69746e65, /* "enti" */
260 .vendor3 = 0x444d4163, /* "cAMD" */
264 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
265 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
266 .xlevel = 0x80000008,
267 /* XXX: put another string ? */
268 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
272 /* original is on level 10 */
277 .features = PPRO_FEATURES |
278 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME,
279 /* Missing: CPUID_DTS | CPUID_ACPI | CPUID_SS |
280 * CPUID_HT | CPUID_TM | CPUID_PBE */
281 /* Some CPUs got no CPUID_SEP */
282 .ext_features = CPUID_EXT_MONITOR |
283 CPUID_EXT_SSE3 /* PNI */ | CPUID_EXT_SSSE3,
284 /* Missing: CPUID_EXT_DSCPL | CPUID_EXT_EST |
285 * CPUID_EXT_TM2 | CPUID_EXT_XTPR */
286 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_NX,
287 /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
288 .xlevel = 0x8000000A,
289 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
293 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
298 char *s = strdup(cpu_model);
299 char *featurestr, *name = strtok(s, ",");
300 uint32_t plus_features = 0, plus_ext_features = 0, plus_ext2_features = 0, plus_ext3_features = 0;
301 uint32_t minus_features = 0, minus_ext_features = 0, minus_ext2_features = 0, minus_ext3_features = 0;
302 int family = -1, model = -1, stepping = -1;
305 for (i = 0; i < ARRAY_SIZE(x86_defs); i++) {
306 if (strcmp(name, x86_defs[i].name) == 0) {
313 memcpy(x86_cpu_def, def, sizeof(*def));
315 featurestr = strtok(NULL, ",");
319 if (featurestr[0] == '+') {
320 add_flagname_to_bitmaps(featurestr + 1, &plus_features, &plus_ext_features, &plus_ext2_features, &plus_ext3_features);
321 } else if (featurestr[0] == '-') {
322 add_flagname_to_bitmaps(featurestr + 1, &minus_features, &minus_ext_features, &minus_ext2_features, &minus_ext3_features);
323 } else if ((val = strchr(featurestr, '='))) {
325 if (!strcmp(featurestr, "family")) {
327 family = strtol(val, &err, 10);
328 if (!*val || *err || family < 0) {
329 fprintf(stderr, "bad numerical value %s\n", val);
332 x86_cpu_def->family = family;
333 } else if (!strcmp(featurestr, "model")) {
335 model = strtol(val, &err, 10);
336 if (!*val || *err || model < 0 || model > 0xff) {
337 fprintf(stderr, "bad numerical value %s\n", val);
340 x86_cpu_def->model = model;
341 } else if (!strcmp(featurestr, "stepping")) {
343 stepping = strtol(val, &err, 10);
344 if (!*val || *err || stepping < 0 || stepping > 0xf) {
345 fprintf(stderr, "bad numerical value %s\n", val);
348 x86_cpu_def->stepping = stepping;
349 } else if (!strcmp(featurestr, "vendor")) {
350 if (strlen(val) != 12) {
351 fprintf(stderr, "vendor string must be 12 chars long\n");
354 x86_cpu_def->vendor1 = 0;
355 x86_cpu_def->vendor2 = 0;
356 x86_cpu_def->vendor3 = 0;
357 for(i = 0; i < 4; i++) {
358 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
359 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
360 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
362 } else if (!strcmp(featurestr, "model_id")) {
363 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
366 fprintf(stderr, "unrecognized feature %s\n", featurestr);
370 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
373 featurestr = strtok(NULL, ",");
375 x86_cpu_def->features |= plus_features;
376 x86_cpu_def->ext_features |= plus_ext_features;
377 x86_cpu_def->ext2_features |= plus_ext2_features;
378 x86_cpu_def->ext3_features |= plus_ext3_features;
379 x86_cpu_def->features &= ~minus_features;
380 x86_cpu_def->ext_features &= ~minus_ext_features;
381 x86_cpu_def->ext2_features &= ~minus_ext2_features;
382 x86_cpu_def->ext3_features &= ~minus_ext3_features;
391 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
395 for (i = 0; i < ARRAY_SIZE(x86_defs); i++)
396 (*cpu_fprintf)(f, "x86 %16s\n", x86_defs[i].name);
399 static int cpu_x86_register (CPUX86State *env, const char *cpu_model)
401 x86_def_t def1, *def = &def1;
403 if (cpu_x86_find_by_name(def, cpu_model) < 0)
406 env->cpuid_vendor1 = def->vendor1;
407 env->cpuid_vendor2 = def->vendor2;
408 env->cpuid_vendor3 = def->vendor3;
410 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
411 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
412 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
414 env->cpuid_level = def->level;
415 if (def->family > 0x0f)
416 env->cpuid_version = 0xf00 | ((def->family - 0x0f) << 20);
418 env->cpuid_version = def->family << 8;
419 env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16);
420 env->cpuid_version |= def->stepping;
421 env->cpuid_features = def->features;
422 env->pat = 0x0007040600070406ULL;
423 env->cpuid_ext_features = def->ext_features;
424 env->cpuid_ext2_features = def->ext2_features;
425 env->cpuid_xlevel = def->xlevel;
426 env->cpuid_ext3_features = def->ext3_features;
428 const char *model_id = def->model_id;
432 len = strlen(model_id);
433 for(i = 0; i < 48; i++) {
437 c = (uint8_t)model_id[i];
438 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
444 /* NOTE: must be called outside the CPU execute loop */
445 void cpu_reset(CPUX86State *env)
449 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
450 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
451 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
454 memset(env, 0, offsetof(CPUX86State, breakpoints));
458 env->old_exception = -1;
460 /* init to reset state */
462 #ifdef CONFIG_SOFTMMU
463 env->hflags |= HF_SOFTMMU_MASK;
465 env->hflags2 |= HF2_GIF_MASK;
467 cpu_x86_update_cr0(env, 0x60000010);
468 env->a20_mask = ~0x0;
469 env->smbase = 0x30000;
471 env->idt.limit = 0xffff;
472 env->gdt.limit = 0xffff;
473 env->ldt.limit = 0xffff;
474 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
475 env->tr.limit = 0xffff;
476 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
478 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
479 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
480 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
481 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
482 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
483 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
484 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
485 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
486 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
487 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
488 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
489 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
492 env->regs[R_EDX] = env->cpuid_version;
497 for(i = 0;i < 8; i++)
503 memset(env->dr, 0, sizeof(env->dr));
504 env->dr[6] = DR6_FIXED_1;
505 env->dr[7] = DR7_FIXED_1;
506 cpu_breakpoint_remove_all(env, BP_CPU);
507 cpu_watchpoint_remove_all(env, BP_CPU);
510 void cpu_x86_close(CPUX86State *env)
515 /***********************************************************/
518 static const char *cc_op_str[] = {
573 void cpu_dump_state(CPUState *env, FILE *f,
574 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
579 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
582 kvm_arch_get_registers(env);
584 eflags = env->eflags;
586 if (env->hflags & HF_CS64_MASK) {
588 "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
589 "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
590 "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
591 "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
592 "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
610 eflags & DF_MASK ? 'D' : '-',
611 eflags & CC_O ? 'O' : '-',
612 eflags & CC_S ? 'S' : '-',
613 eflags & CC_Z ? 'Z' : '-',
614 eflags & CC_A ? 'A' : '-',
615 eflags & CC_P ? 'P' : '-',
616 eflags & CC_C ? 'C' : '-',
617 env->hflags & HF_CPL_MASK,
618 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
619 (int)(env->a20_mask >> 20) & 1,
620 (env->hflags >> HF_SMM_SHIFT) & 1,
625 cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
626 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
627 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
628 (uint32_t)env->regs[R_EAX],
629 (uint32_t)env->regs[R_EBX],
630 (uint32_t)env->regs[R_ECX],
631 (uint32_t)env->regs[R_EDX],
632 (uint32_t)env->regs[R_ESI],
633 (uint32_t)env->regs[R_EDI],
634 (uint32_t)env->regs[R_EBP],
635 (uint32_t)env->regs[R_ESP],
636 (uint32_t)env->eip, eflags,
637 eflags & DF_MASK ? 'D' : '-',
638 eflags & CC_O ? 'O' : '-',
639 eflags & CC_S ? 'S' : '-',
640 eflags & CC_Z ? 'Z' : '-',
641 eflags & CC_A ? 'A' : '-',
642 eflags & CC_P ? 'P' : '-',
643 eflags & CC_C ? 'C' : '-',
644 env->hflags & HF_CPL_MASK,
645 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
646 (int)(env->a20_mask >> 20) & 1,
647 (env->hflags >> HF_SMM_SHIFT) & 1,
652 if (env->hflags & HF_LMA_MASK) {
653 for(i = 0; i < 6; i++) {
654 SegmentCache *sc = &env->segs[i];
655 cpu_fprintf(f, "%s =%04x %016" PRIx64 " %08x %08x\n",
662 cpu_fprintf(f, "LDT=%04x %016" PRIx64 " %08x %08x\n",
667 cpu_fprintf(f, "TR =%04x %016" PRIx64 " %08x %08x\n",
672 cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
673 env->gdt.base, env->gdt.limit);
674 cpu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
675 env->idt.base, env->idt.limit);
676 cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
677 (uint32_t)env->cr[0],
680 (uint32_t)env->cr[4]);
681 for(i = 0; i < 4; i++)
682 cpu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
683 cpu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
684 env->dr[6], env->dr[7]);
688 for(i = 0; i < 6; i++) {
689 SegmentCache *sc = &env->segs[i];
690 cpu_fprintf(f, "%s =%04x %08x %08x %08x\n",
697 cpu_fprintf(f, "LDT=%04x %08x %08x %08x\n",
699 (uint32_t)env->ldt.base,
702 cpu_fprintf(f, "TR =%04x %08x %08x %08x\n",
704 (uint32_t)env->tr.base,
707 cpu_fprintf(f, "GDT= %08x %08x\n",
708 (uint32_t)env->gdt.base, env->gdt.limit);
709 cpu_fprintf(f, "IDT= %08x %08x\n",
710 (uint32_t)env->idt.base, env->idt.limit);
711 cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
712 (uint32_t)env->cr[0],
713 (uint32_t)env->cr[2],
714 (uint32_t)env->cr[3],
715 (uint32_t)env->cr[4]);
716 for(i = 0; i < 4; i++)
717 cpu_fprintf(f, "DR%d=%08x ", i, env->dr[i]);
718 cpu_fprintf(f, "\nDR6=%08x DR7=%08x\n", env->dr[6], env->dr[7]);
720 if (flags & X86_DUMP_CCOP) {
721 if ((unsigned)env->cc_op < CC_OP_NB)
722 snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
724 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
726 if (env->hflags & HF_CS64_MASK) {
727 cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
728 env->cc_src, env->cc_dst,
733 cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
734 (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
738 if (flags & X86_DUMP_FPU) {
741 for(i = 0; i < 8; i++) {
742 fptag |= ((!env->fptags[i]) << i);
744 cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
746 (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
751 #if defined(USE_X86LDOUBLE)
759 tmp.d = env->fpregs[i].d;
760 cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
761 i, tmp.l.lower, tmp.l.upper);
763 cpu_fprintf(f, "FPR%d=%016" PRIx64,
764 i, env->fpregs[i].mmx.q);
767 cpu_fprintf(f, "\n");
771 if (env->hflags & HF_CS64_MASK)
776 cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
778 env->xmm_regs[i].XMM_L(3),
779 env->xmm_regs[i].XMM_L(2),
780 env->xmm_regs[i].XMM_L(1),
781 env->xmm_regs[i].XMM_L(0));
783 cpu_fprintf(f, "\n");
790 /***********************************************************/
792 /* XXX: add PGE support */
794 void cpu_x86_set_a20(CPUX86State *env, int a20_state)
796 a20_state = (a20_state != 0);
797 if (a20_state != ((env->a20_mask >> 20) & 1)) {
798 #if defined(DEBUG_MMU)
799 printf("A20 update: a20=%d\n", a20_state);
801 /* if the cpu is currently executing code, we must unlink it and
802 all the potentially executing TB */
803 cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
805 /* when a20 is changed, all the MMU mappings are invalid, so
806 we must flush everything */
808 env->a20_mask = (~0x100000) | (a20_state << 20);
812 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
816 #if defined(DEBUG_MMU)
817 printf("CR0 update: CR0=0x%08x\n", new_cr0);
819 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
820 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
825 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
826 (env->efer & MSR_EFER_LME)) {
827 /* enter in long mode */
828 /* XXX: generate an exception */
829 if (!(env->cr[4] & CR4_PAE_MASK))
831 env->efer |= MSR_EFER_LMA;
832 env->hflags |= HF_LMA_MASK;
833 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
834 (env->efer & MSR_EFER_LMA)) {
836 env->efer &= ~MSR_EFER_LMA;
837 env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
838 env->eip &= 0xffffffff;
841 env->cr[0] = new_cr0 | CR0_ET_MASK;
843 /* update PE flag in hidden flags */
844 pe_state = (env->cr[0] & CR0_PE_MASK);
845 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
846 /* ensure that ADDSEG is always set in real mode */
847 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
848 /* update FPU flags */
849 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
850 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
853 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
855 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
857 env->cr[3] = new_cr3;
858 if (env->cr[0] & CR0_PG_MASK) {
859 #if defined(DEBUG_MMU)
860 printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
866 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
868 #if defined(DEBUG_MMU)
869 printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
871 if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
872 (env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
876 if (!(env->cpuid_features & CPUID_SSE))
877 new_cr4 &= ~CR4_OSFXSR_MASK;
878 if (new_cr4 & CR4_OSFXSR_MASK)
879 env->hflags |= HF_OSFXSR_MASK;
881 env->hflags &= ~HF_OSFXSR_MASK;
883 env->cr[4] = new_cr4;
886 #if defined(CONFIG_USER_ONLY)
888 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
889 int is_write, int mmu_idx, int is_softmmu)
891 /* user mode only emulation */
894 env->error_code = (is_write << PG_ERROR_W_BIT);
895 env->error_code |= PG_ERROR_U_MASK;
896 env->exception_index = EXCP0E_PAGE;
900 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
907 /* XXX: This value should match the one returned by CPUID
909 #if defined(USE_KQEMU)
910 #define PHYS_ADDR_MASK 0xfffff000LL
912 # if defined(TARGET_X86_64)
913 # define PHYS_ADDR_MASK 0xfffffff000LL
915 # define PHYS_ADDR_MASK 0xffffff000LL
920 -1 = cannot handle fault
921 0 = nothing more to do
922 1 = generate PF fault
923 2 = soft MMU activation required for this block
925 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
926 int is_write1, int mmu_idx, int is_softmmu)
929 target_ulong pde_addr, pte_addr;
930 int error_code, is_dirty, prot, page_size, ret, is_write, is_user;
931 target_phys_addr_t paddr;
932 uint32_t page_offset;
933 target_ulong vaddr, virt_addr;
935 is_user = mmu_idx == MMU_USER_IDX;
936 #if defined(DEBUG_MMU)
937 printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
938 addr, is_write1, is_user, env->eip);
940 is_write = is_write1 & 1;
942 if (!(env->cr[0] & CR0_PG_MASK)) {
944 virt_addr = addr & TARGET_PAGE_MASK;
945 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
950 if (env->cr[4] & CR4_PAE_MASK) {
952 target_ulong pdpe_addr;
955 if (env->hflags & HF_LMA_MASK) {
956 uint64_t pml4e_addr, pml4e;
959 /* test virtual address sign extension */
960 sext = (int64_t)addr >> 47;
961 if (sext != 0 && sext != -1) {
963 env->exception_index = EXCP0D_GPF;
967 pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
969 pml4e = ldq_phys(pml4e_addr);
970 if (!(pml4e & PG_PRESENT_MASK)) {
974 if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
975 error_code = PG_ERROR_RSVD_MASK;
978 if (!(pml4e & PG_ACCESSED_MASK)) {
979 pml4e |= PG_ACCESSED_MASK;
980 stl_phys_notdirty(pml4e_addr, pml4e);
982 ptep = pml4e ^ PG_NX_MASK;
983 pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
985 pdpe = ldq_phys(pdpe_addr);
986 if (!(pdpe & PG_PRESENT_MASK)) {
990 if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
991 error_code = PG_ERROR_RSVD_MASK;
994 ptep &= pdpe ^ PG_NX_MASK;
995 if (!(pdpe & PG_ACCESSED_MASK)) {
996 pdpe |= PG_ACCESSED_MASK;
997 stl_phys_notdirty(pdpe_addr, pdpe);
1002 /* XXX: load them when cr3 is loaded ? */
1003 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
1005 pdpe = ldq_phys(pdpe_addr);
1006 if (!(pdpe & PG_PRESENT_MASK)) {
1010 ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
1013 pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
1015 pde = ldq_phys(pde_addr);
1016 if (!(pde & PG_PRESENT_MASK)) {
1020 if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
1021 error_code = PG_ERROR_RSVD_MASK;
1024 ptep &= pde ^ PG_NX_MASK;
1025 if (pde & PG_PSE_MASK) {
1027 page_size = 2048 * 1024;
1029 if ((ptep & PG_NX_MASK) && is_write1 == 2)
1030 goto do_fault_protect;
1032 if (!(ptep & PG_USER_MASK))
1033 goto do_fault_protect;
1034 if (is_write && !(ptep & PG_RW_MASK))
1035 goto do_fault_protect;
1037 if ((env->cr[0] & CR0_WP_MASK) &&
1038 is_write && !(ptep & PG_RW_MASK))
1039 goto do_fault_protect;
1041 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
1042 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
1043 pde |= PG_ACCESSED_MASK;
1045 pde |= PG_DIRTY_MASK;
1046 stl_phys_notdirty(pde_addr, pde);
1048 /* align to page_size */
1049 pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
1050 virt_addr = addr & ~(page_size - 1);
1053 if (!(pde & PG_ACCESSED_MASK)) {
1054 pde |= PG_ACCESSED_MASK;
1055 stl_phys_notdirty(pde_addr, pde);
1057 pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
1059 pte = ldq_phys(pte_addr);
1060 if (!(pte & PG_PRESENT_MASK)) {
1064 if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
1065 error_code = PG_ERROR_RSVD_MASK;
1068 /* combine pde and pte nx, user and rw protections */
1069 ptep &= pte ^ PG_NX_MASK;
1071 if ((ptep & PG_NX_MASK) && is_write1 == 2)
1072 goto do_fault_protect;
1074 if (!(ptep & PG_USER_MASK))
1075 goto do_fault_protect;
1076 if (is_write && !(ptep & PG_RW_MASK))
1077 goto do_fault_protect;
1079 if ((env->cr[0] & CR0_WP_MASK) &&
1080 is_write && !(ptep & PG_RW_MASK))
1081 goto do_fault_protect;
1083 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
1084 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
1085 pte |= PG_ACCESSED_MASK;
1087 pte |= PG_DIRTY_MASK;
1088 stl_phys_notdirty(pte_addr, pte);
1091 virt_addr = addr & ~0xfff;
1092 pte = pte & (PHYS_ADDR_MASK | 0xfff);
1097 /* page directory entry */
1098 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
1100 pde = ldl_phys(pde_addr);
1101 if (!(pde & PG_PRESENT_MASK)) {
1105 /* if PSE bit is set, then we use a 4MB page */
1106 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
1107 page_size = 4096 * 1024;
1109 if (!(pde & PG_USER_MASK))
1110 goto do_fault_protect;
1111 if (is_write && !(pde & PG_RW_MASK))
1112 goto do_fault_protect;
1114 if ((env->cr[0] & CR0_WP_MASK) &&
1115 is_write && !(pde & PG_RW_MASK))
1116 goto do_fault_protect;
1118 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
1119 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
1120 pde |= PG_ACCESSED_MASK;
1122 pde |= PG_DIRTY_MASK;
1123 stl_phys_notdirty(pde_addr, pde);
1126 pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
1128 virt_addr = addr & ~(page_size - 1);
1130 if (!(pde & PG_ACCESSED_MASK)) {
1131 pde |= PG_ACCESSED_MASK;
1132 stl_phys_notdirty(pde_addr, pde);
1135 /* page directory entry */
1136 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
1138 pte = ldl_phys(pte_addr);
1139 if (!(pte & PG_PRESENT_MASK)) {
1143 /* combine pde and pte user and rw protections */
1146 if (!(ptep & PG_USER_MASK))
1147 goto do_fault_protect;
1148 if (is_write && !(ptep & PG_RW_MASK))
1149 goto do_fault_protect;
1151 if ((env->cr[0] & CR0_WP_MASK) &&
1152 is_write && !(ptep & PG_RW_MASK))
1153 goto do_fault_protect;
1155 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
1156 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
1157 pte |= PG_ACCESSED_MASK;
1159 pte |= PG_DIRTY_MASK;
1160 stl_phys_notdirty(pte_addr, pte);
1163 virt_addr = addr & ~0xfff;
1166 /* the page can be put in the TLB */
1168 if (!(ptep & PG_NX_MASK))
1170 if (pte & PG_DIRTY_MASK) {
1171 /* only set write access if already dirty... otherwise wait
1174 if (ptep & PG_RW_MASK)
1177 if (!(env->cr[0] & CR0_WP_MASK) ||
1178 (ptep & PG_RW_MASK))
1183 pte = pte & env->a20_mask;
1185 /* Even if 4MB pages, we map only one 4KB page in the cache to
1186 avoid filling it too fast */
1187 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1188 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
1189 vaddr = virt_addr + page_offset;
1191 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
1194 error_code = PG_ERROR_P_MASK;
1196 error_code |= (is_write << PG_ERROR_W_BIT);
1198 error_code |= PG_ERROR_U_MASK;
1199 if (is_write1 == 2 &&
1200 (env->efer & MSR_EFER_NXE) &&
1201 (env->cr[4] & CR4_PAE_MASK))
1202 error_code |= PG_ERROR_I_D_MASK;
1203 if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
1204 /* cr2 is not modified in case of exceptions */
1205 stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
1210 env->error_code = error_code;
1211 env->exception_index = EXCP0E_PAGE;
1215 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1217 target_ulong pde_addr, pte_addr;
1219 target_phys_addr_t paddr;
1220 uint32_t page_offset;
1223 if (env->cr[4] & CR4_PAE_MASK) {
1224 target_ulong pdpe_addr;
1227 #ifdef TARGET_X86_64
1228 if (env->hflags & HF_LMA_MASK) {
1229 uint64_t pml4e_addr, pml4e;
1232 /* test virtual address sign extension */
1233 sext = (int64_t)addr >> 47;
1234 if (sext != 0 && sext != -1)
1237 pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
1239 pml4e = ldq_phys(pml4e_addr);
1240 if (!(pml4e & PG_PRESENT_MASK))
1243 pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
1245 pdpe = ldq_phys(pdpe_addr);
1246 if (!(pdpe & PG_PRESENT_MASK))
1251 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
1253 pdpe = ldq_phys(pdpe_addr);
1254 if (!(pdpe & PG_PRESENT_MASK))
1258 pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) &
1260 pde = ldq_phys(pde_addr);
1261 if (!(pde & PG_PRESENT_MASK)) {
1264 if (pde & PG_PSE_MASK) {
1266 page_size = 2048 * 1024;
1267 pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
1270 pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) &
1273 pte = ldq_phys(pte_addr);
1275 if (!(pte & PG_PRESENT_MASK))
1280 if (!(env->cr[0] & CR0_PG_MASK)) {
1284 /* page directory entry */
1285 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
1286 pde = ldl_phys(pde_addr);
1287 if (!(pde & PG_PRESENT_MASK))
1289 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
1290 pte = pde & ~0x003ff000; /* align to 4MB */
1291 page_size = 4096 * 1024;
1293 /* page directory entry */
1294 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
1295 pte = ldl_phys(pte_addr);
1296 if (!(pte & PG_PRESENT_MASK))
1301 pte = pte & env->a20_mask;
1304 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1305 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
1309 void hw_breakpoint_insert(CPUState *env, int index)
1313 switch (hw_breakpoint_type(env->dr[7], index)) {
1315 if (hw_breakpoint_enabled(env->dr[7], index))
1316 err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU,
1317 &env->cpu_breakpoint[index]);
1320 type = BP_CPU | BP_MEM_WRITE;
1323 /* No support for I/O watchpoints yet */
1326 type = BP_CPU | BP_MEM_ACCESS;
1328 err = cpu_watchpoint_insert(env, env->dr[index],
1329 hw_breakpoint_len(env->dr[7], index),
1330 type, &env->cpu_watchpoint[index]);
1334 env->cpu_breakpoint[index] = NULL;
1337 void hw_breakpoint_remove(CPUState *env, int index)
1339 if (!env->cpu_breakpoint[index])
1341 switch (hw_breakpoint_type(env->dr[7], index)) {
1343 if (hw_breakpoint_enabled(env->dr[7], index))
1344 cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]);
1348 cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]);
1351 /* No support for I/O watchpoints yet */
1356 int check_hw_breakpoints(CPUState *env, int force_dr6_update)
1360 int hit_enabled = 0;
1362 dr6 = env->dr[6] & ~0xf;
1363 for (reg = 0; reg < 4; reg++) {
1364 type = hw_breakpoint_type(env->dr[7], reg);
1365 if ((type == 0 && env->dr[reg] == env->eip) ||
1366 ((type & 1) && env->cpu_watchpoint[reg] &&
1367 (env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT))) {
1369 if (hw_breakpoint_enabled(env->dr[7], reg))
1373 if (hit_enabled || force_dr6_update)
1378 static CPUDebugExcpHandler *prev_debug_excp_handler;
1380 void raise_exception(int exception_index);
1382 static void breakpoint_handler(CPUState *env)
1386 if (env->watchpoint_hit) {
1387 if (env->watchpoint_hit->flags & BP_CPU) {
1388 env->watchpoint_hit = NULL;
1389 if (check_hw_breakpoints(env, 0))
1390 raise_exception(EXCP01_DB);
1392 cpu_resume_from_signal(env, NULL);
1395 TAILQ_FOREACH(bp, &env->breakpoints, entry)
1396 if (bp->pc == env->eip) {
1397 if (bp->flags & BP_CPU) {
1398 check_hw_breakpoints(env, 1);
1399 raise_exception(EXCP01_DB);
1404 if (prev_debug_excp_handler)
1405 prev_debug_excp_handler(env);
1407 #endif /* !CONFIG_USER_ONLY */
1409 static void host_cpuid(uint32_t function, uint32_t count,
1410 uint32_t *eax, uint32_t *ebx,
1411 uint32_t *ecx, uint32_t *edx)
1413 #if defined(CONFIG_KVM)
1417 asm volatile("cpuid"
1418 : "=a"(vec[0]), "=b"(vec[1]),
1419 "=c"(vec[2]), "=d"(vec[3])
1420 : "0"(function), "c"(count) : "cc");
1422 asm volatile("pusha \n\t"
1424 "mov %%eax, 0(%2) \n\t"
1425 "mov %%ebx, 4(%2) \n\t"
1426 "mov %%ecx, 8(%2) \n\t"
1427 "mov %%edx, 12(%2) \n\t"
1429 : : "a"(function), "c"(count), "S"(vec)
1444 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1445 uint32_t *eax, uint32_t *ebx,
1446 uint32_t *ecx, uint32_t *edx)
1448 /* test if maximum index reached */
1449 if (index & 0x80000000) {
1450 if (index > env->cpuid_xlevel)
1451 index = env->cpuid_level;
1453 if (index > env->cpuid_level)
1454 index = env->cpuid_level;
1459 *eax = env->cpuid_level;
1460 *ebx = env->cpuid_vendor1;
1461 *edx = env->cpuid_vendor2;
1462 *ecx = env->cpuid_vendor3;
1464 /* sysenter isn't supported on compatibility mode on AMD. and syscall
1465 * isn't supported in compatibility mode on Intel. so advertise the
1466 * actuall cpu, and say goodbye to migration between different vendors
1467 * is you use compatibility mode. */
1469 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1472 *eax = env->cpuid_version;
1473 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1474 *ecx = env->cpuid_ext_features;
1475 *edx = env->cpuid_features;
1477 /* "Hypervisor present" bit required for Microsoft SVVP */
1482 /* cache info: needed for Pentium Pro compatibility */
1489 /* cache info: needed for Core compatibility */
1491 case 0: /* L1 dcache info */
1497 case 1: /* L1 icache info */
1503 case 2: /* L2 cache info */
1509 default: /* end of info */
1518 /* mwait info: needed for Core compatibility */
1519 *eax = 0; /* Smallest monitor-line size in bytes */
1520 *ebx = 0; /* Largest monitor-line size in bytes */
1521 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1525 /* Thermal and Power Leaf */
1532 /* Direct Cache Access Information Leaf */
1533 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1539 /* Architectural Performance Monitoring Leaf */
1546 *eax = env->cpuid_xlevel;
1547 *ebx = env->cpuid_vendor1;
1548 *edx = env->cpuid_vendor2;
1549 *ecx = env->cpuid_vendor3;
1552 *eax = env->cpuid_features;
1554 *ecx = env->cpuid_ext3_features;
1555 *edx = env->cpuid_ext2_features;
1557 if (kvm_enabled()) {
1558 uint32_t h_eax, h_edx;
1560 host_cpuid(index, 0, &h_eax, NULL, NULL, &h_edx);
1562 /* disable CPU features that the host does not support */
1565 if ((h_edx & 0x20000000) == 0 /* || !lm_capable_kernel */)
1566 *edx &= ~0x20000000;
1568 if ((h_edx & 0x00000800) == 0)
1569 *edx &= ~0x00000800;
1571 if ((h_edx & 0x00100000) == 0)
1572 *edx &= ~0x00100000;
1574 /* disable CPU features that KVM cannot support */
1579 *edx &= ~0xc0000000;
1585 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1586 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1587 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1588 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1591 /* cache info (L1 cache) */
1598 /* cache info (L2 cache) */
1605 /* virtual & phys address size in low 2 bytes. */
1606 /* XXX: This value must match the one used in the MMU code. */
1607 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1608 /* 64 bit processor */
1609 #if defined(USE_KQEMU)
1610 *eax = 0x00003020; /* 48 bits virtual, 32 bits physical */
1612 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1613 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1616 #if defined(USE_KQEMU)
1617 *eax = 0x00000020; /* 32 bits physical */
1619 if (env->cpuid_features & CPUID_PSE36)
1620 *eax = 0x00000024; /* 36 bits physical */
1622 *eax = 0x00000020; /* 32 bits physical */
1630 *eax = 0x00000001; /* SVM Revision */
1631 *ebx = 0x00000010; /* nr of ASIDs */
1633 *edx = 0; /* optional features */
1636 /* reserved values: zero */
1645 CPUX86State *cpu_x86_init(const char *cpu_model)
1650 env = qemu_mallocz(sizeof(CPUX86State));
1652 env->cpu_model_str = cpu_model;
1654 /* init various static tables */
1657 optimize_flags_init();
1658 #ifndef CONFIG_USER_ONLY
1659 prev_debug_excp_handler =
1660 cpu_set_debug_excp_handler(breakpoint_handler);
1663 if (cpu_x86_register(env, cpu_model) < 0) {