4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
19 #include <linux/kvm.h>
21 #include "qemu-common.h"
29 #define dprintf(fmt, ...) \
30 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
32 #define dprintf(fmt, ...) \
36 int kvm_arch_init_vcpu(CPUState *env)
39 struct kvm_cpuid2 cpuid;
40 struct kvm_cpuid_entry2 entries[100];
41 } __attribute__((packed)) cpuid_data;
42 uint32_t limit, i, j, cpuid_i;
43 uint32_t eax, ebx, ecx, edx;
47 cpu_x86_cpuid(env, 0, 0, &eax, &ebx, &ecx, &edx);
50 for (i = 0; i <= limit; i++) {
51 struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
55 /* Keep reading function 2 till all the input is received */
58 cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
62 c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
63 c->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
69 for (j = 1; j < times; ++j) {
70 cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
72 c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
84 cpu_x86_cpuid(env, i, j, &eax, &ebx, &ecx, &edx);
86 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
92 c = &cpuid_data.entries[++cpuid_i];
94 if (i == 4 && eax == 0)
96 if (i == 0xb && !(ecx & 0xff00))
98 if (i == 0xd && eax == 0)
103 cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
112 cpu_x86_cpuid(env, 0x80000000, 0, &eax, &ebx, &ecx, &edx);
115 for (i = 0x80000000; i <= limit; i++) {
116 struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
118 cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
126 cpuid_data.cpuid.nent = cpuid_i;
128 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
131 static int kvm_has_msr_star(CPUState *env)
133 static int has_msr_star;
137 if (has_msr_star == 0) {
138 struct kvm_msr_list msr_list, *kvm_msr_list;
142 /* Obtain MSR list from KVM. These are the MSRs that we must
145 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
149 kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
150 msr_list.nmsrs * sizeof(msr_list.indices[0]));
152 kvm_msr_list->nmsrs = msr_list.nmsrs;
153 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
157 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
158 if (kvm_msr_list->indices[i] == MSR_STAR) {
168 if (has_msr_star == 1)
173 int kvm_arch_init(KVMState *s, int smp_cpus)
177 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
178 * directly. In order to use vm86 mode, a TSS is needed. Since this
179 * must be part of guest physical memory, we need to allocate it. Older
180 * versions of KVM just assumed that it would be at the end of physical
181 * memory but that doesn't work with more than 4GB of memory. We simply
182 * refuse to work with those older versions of KVM. */
183 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
185 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
189 /* this address is 3 pages before the bios, and the bios should present
190 * as unavaible memory. FIXME, need to ensure the e820 map deals with
193 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
196 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
198 lhs->selector = rhs->selector;
199 lhs->base = rhs->base;
200 lhs->limit = rhs->limit;
212 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
214 unsigned flags = rhs->flags;
215 lhs->selector = rhs->selector;
216 lhs->base = rhs->base;
217 lhs->limit = rhs->limit;
218 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
219 lhs->present = (flags & DESC_P_MASK) != 0;
220 lhs->dpl = rhs->selector & 3;
221 lhs->db = (flags >> DESC_B_SHIFT) & 1;
222 lhs->s = (flags & DESC_S_MASK) != 0;
223 lhs->l = (flags >> DESC_L_SHIFT) & 1;
224 lhs->g = (flags & DESC_G_MASK) != 0;
225 lhs->avl = (flags & DESC_AVL_MASK) != 0;
229 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
231 lhs->selector = rhs->selector;
232 lhs->base = rhs->base;
233 lhs->limit = rhs->limit;
235 (rhs->type << DESC_TYPE_SHIFT)
236 | (rhs->present * DESC_P_MASK)
237 | (rhs->dpl << DESC_DPL_SHIFT)
238 | (rhs->db << DESC_B_SHIFT)
239 | (rhs->s * DESC_S_MASK)
240 | (rhs->l << DESC_L_SHIFT)
241 | (rhs->g * DESC_G_MASK)
242 | (rhs->avl * DESC_AVL_MASK);
245 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
248 *kvm_reg = *qemu_reg;
250 *qemu_reg = *kvm_reg;
253 static int kvm_getput_regs(CPUState *env, int set)
255 struct kvm_regs regs;
259 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
264 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
265 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
266 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
267 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
268 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
269 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
270 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
271 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
273 kvm_getput_reg(®s.r8, &env->regs[8], set);
274 kvm_getput_reg(®s.r9, &env->regs[9], set);
275 kvm_getput_reg(®s.r10, &env->regs[10], set);
276 kvm_getput_reg(®s.r11, &env->regs[11], set);
277 kvm_getput_reg(®s.r12, &env->regs[12], set);
278 kvm_getput_reg(®s.r13, &env->regs[13], set);
279 kvm_getput_reg(®s.r14, &env->regs[14], set);
280 kvm_getput_reg(®s.r15, &env->regs[15], set);
283 kvm_getput_reg(®s.rflags, &env->eflags, set);
284 kvm_getput_reg(®s.rip, &env->eip, set);
287 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s);
292 static int kvm_put_fpu(CPUState *env)
297 memset(&fpu, 0, sizeof fpu);
298 fpu.fsw = env->fpus & ~(7 << 11);
299 fpu.fsw |= (env->fpstt & 7) << 11;
301 for (i = 0; i < 8; ++i)
302 fpu.ftwx |= (!env->fptags[i]) << i;
303 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
304 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
305 fpu.mxcsr = env->mxcsr;
307 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
310 static int kvm_put_sregs(CPUState *env)
312 struct kvm_sregs sregs;
314 memcpy(sregs.interrupt_bitmap,
315 env->interrupt_bitmap,
316 sizeof(sregs.interrupt_bitmap));
318 if ((env->eflags & VM_MASK)) {
319 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
320 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
321 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
322 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
323 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
324 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
326 set_seg(&sregs.cs, &env->segs[R_CS]);
327 set_seg(&sregs.ds, &env->segs[R_DS]);
328 set_seg(&sregs.es, &env->segs[R_ES]);
329 set_seg(&sregs.fs, &env->segs[R_FS]);
330 set_seg(&sregs.gs, &env->segs[R_GS]);
331 set_seg(&sregs.ss, &env->segs[R_SS]);
333 if (env->cr[0] & CR0_PE_MASK) {
334 /* force ss cpl to cs cpl */
335 sregs.ss.selector = (sregs.ss.selector & ~3) |
336 (sregs.cs.selector & 3);
337 sregs.ss.dpl = sregs.ss.selector & 3;
341 set_seg(&sregs.tr, &env->tr);
342 set_seg(&sregs.ldt, &env->ldt);
344 sregs.idt.limit = env->idt.limit;
345 sregs.idt.base = env->idt.base;
346 sregs.gdt.limit = env->gdt.limit;
347 sregs.gdt.base = env->gdt.base;
349 sregs.cr0 = env->cr[0];
350 sregs.cr2 = env->cr[2];
351 sregs.cr3 = env->cr[3];
352 sregs.cr4 = env->cr[4];
354 sregs.cr8 = cpu_get_apic_tpr(env);
355 sregs.apic_base = cpu_get_apic_base(env);
357 sregs.efer = env->efer;
359 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
362 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
363 uint32_t index, uint64_t value)
365 entry->index = index;
369 static int kvm_put_msrs(CPUState *env)
372 struct kvm_msrs info;
373 struct kvm_msr_entry entries[100];
375 struct kvm_msr_entry *msrs = msr_data.entries;
378 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
379 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
380 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
381 if (kvm_has_msr_star(env))
382 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
383 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
385 /* FIXME if lm capable */
386 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
387 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
388 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
389 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
391 msr_data.info.nmsrs = n;
393 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
398 static int kvm_get_fpu(CPUState *env)
403 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
407 env->fpstt = (fpu.fsw >> 11) & 7;
410 for (i = 0; i < 8; ++i)
411 env->fptags[i] = !((fpu.ftwx >> i) & 1);
412 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
413 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
414 env->mxcsr = fpu.mxcsr;
419 static int kvm_get_sregs(CPUState *env)
421 struct kvm_sregs sregs;
425 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
429 memcpy(env->interrupt_bitmap,
430 sregs.interrupt_bitmap,
431 sizeof(sregs.interrupt_bitmap));
433 get_seg(&env->segs[R_CS], &sregs.cs);
434 get_seg(&env->segs[R_DS], &sregs.ds);
435 get_seg(&env->segs[R_ES], &sregs.es);
436 get_seg(&env->segs[R_FS], &sregs.fs);
437 get_seg(&env->segs[R_GS], &sregs.gs);
438 get_seg(&env->segs[R_SS], &sregs.ss);
440 get_seg(&env->tr, &sregs.tr);
441 get_seg(&env->ldt, &sregs.ldt);
443 env->idt.limit = sregs.idt.limit;
444 env->idt.base = sregs.idt.base;
445 env->gdt.limit = sregs.gdt.limit;
446 env->gdt.base = sregs.gdt.base;
448 env->cr[0] = sregs.cr0;
449 env->cr[2] = sregs.cr2;
450 env->cr[3] = sregs.cr3;
451 env->cr[4] = sregs.cr4;
453 cpu_set_apic_base(env, sregs.apic_base);
455 env->efer = sregs.efer;
456 //cpu_set_apic_tpr(env, sregs.cr8);
458 #define HFLAG_COPY_MASK ~( \
459 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
460 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
461 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
462 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
466 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
467 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
468 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
469 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
470 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
471 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
472 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
474 if (env->efer & MSR_EFER_LMA) {
475 hflags |= HF_LMA_MASK;
478 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
479 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
481 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
482 (DESC_B_SHIFT - HF_CS32_SHIFT);
483 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
484 (DESC_B_SHIFT - HF_SS32_SHIFT);
485 if (!(env->cr[0] & CR0_PE_MASK) ||
486 (env->eflags & VM_MASK) ||
487 !(hflags & HF_CS32_MASK)) {
488 hflags |= HF_ADDSEG_MASK;
490 hflags |= ((env->segs[R_DS].base |
491 env->segs[R_ES].base |
492 env->segs[R_SS].base) != 0) <<
496 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
501 static int kvm_get_msrs(CPUState *env)
504 struct kvm_msrs info;
505 struct kvm_msr_entry entries[100];
507 struct kvm_msr_entry *msrs = msr_data.entries;
511 msrs[n++].index = MSR_IA32_SYSENTER_CS;
512 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
513 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
514 if (kvm_has_msr_star(env))
515 msrs[n++].index = MSR_STAR;
516 msrs[n++].index = MSR_IA32_TSC;
518 /* FIXME lm_capable_kernel */
519 msrs[n++].index = MSR_CSTAR;
520 msrs[n++].index = MSR_KERNELGSBASE;
521 msrs[n++].index = MSR_FMASK;
522 msrs[n++].index = MSR_LSTAR;
524 msr_data.info.nmsrs = n;
525 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
529 for (i = 0; i < ret; i++) {
530 switch (msrs[i].index) {
531 case MSR_IA32_SYSENTER_CS:
532 env->sysenter_cs = msrs[i].data;
534 case MSR_IA32_SYSENTER_ESP:
535 env->sysenter_esp = msrs[i].data;
537 case MSR_IA32_SYSENTER_EIP:
538 env->sysenter_eip = msrs[i].data;
541 env->star = msrs[i].data;
545 env->cstar = msrs[i].data;
547 case MSR_KERNELGSBASE:
548 env->kernelgsbase = msrs[i].data;
551 env->fmask = msrs[i].data;
554 env->lstar = msrs[i].data;
558 env->tsc = msrs[i].data;
566 int kvm_arch_put_registers(CPUState *env)
570 ret = kvm_getput_regs(env, 1);
574 ret = kvm_put_fpu(env);
578 ret = kvm_put_sregs(env);
582 ret = kvm_put_msrs(env);
589 int kvm_arch_get_registers(CPUState *env)
593 ret = kvm_getput_regs(env, 0);
597 ret = kvm_get_fpu(env);
601 ret = kvm_get_sregs(env);
605 ret = kvm_get_msrs(env);
612 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
614 /* Try to inject an interrupt if the guest can accept it */
615 if (run->ready_for_interrupt_injection &&
616 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
617 (env->eflags & IF_MASK)) {
620 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
621 irq = cpu_get_pic_interrupt(env);
623 struct kvm_interrupt intr;
626 dprintf("injected interrupt %d\n", irq);
627 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
631 /* If we have an interrupt but the guest is not ready to receive an
632 * interrupt, request an interrupt window exit. This will
633 * cause a return to userspace as soon as the guest is ready to
634 * receive interrupts. */
635 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
636 run->request_interrupt_window = 1;
638 run->request_interrupt_window = 0;
640 dprintf("setting tpr\n");
641 run->cr8 = cpu_get_apic_tpr(env);
646 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
649 env->eflags |= IF_MASK;
651 env->eflags &= ~IF_MASK;
653 cpu_set_apic_tpr(env, run->cr8);
654 cpu_set_apic_base(env, run->apic_base);
659 static int kvm_handle_halt(CPUState *env)
661 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
662 (env->eflags & IF_MASK)) &&
663 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
665 env->exception_index = EXCP_HLT;
672 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
676 switch (run->exit_reason) {
678 dprintf("handle_hlt\n");
679 ret = kvm_handle_halt(env);