4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
37 #define PREFIX_REPZ 0x01
38 #define PREFIX_REPNZ 0x02
39 #define PREFIX_LOCK 0x04
40 #define PREFIX_DATA 0x08
41 #define PREFIX_ADR 0x10
44 #define X86_64_ONLY(x) x
45 #define X86_64_DEF(...) __VA_ARGS__
46 #define CODE64(s) ((s)->code64)
47 #define REX_X(s) ((s)->rex_x)
48 #define REX_B(s) ((s)->rex_b)
49 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
51 #define BUGGY_64(x) NULL
54 #define X86_64_ONLY(x) NULL
55 #define X86_64_DEF(...)
61 //#define MACRO_TEST 1
63 /* global register indexes */
64 static TCGv_ptr cpu_env;
65 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
66 static TCGv_i32 cpu_cc_op;
68 static TCGv cpu_T[2], cpu_T3;
69 /* local register indexes (only used inside old micro ops) */
70 static TCGv cpu_tmp0, cpu_tmp4;
71 static TCGv_ptr cpu_ptr0, cpu_ptr1;
72 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
73 static TCGv_i64 cpu_tmp1_i64;
74 static TCGv cpu_tmp5, cpu_tmp6;
76 #include "gen-icount.h"
79 static int x86_64_hregs;
82 typedef struct DisasContext {
83 /* current insn context */
84 int override; /* -1 if no override */
87 target_ulong pc; /* pc = eip + cs_base */
88 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
89 static state change (stop translation) */
90 /* current block context */
91 target_ulong cs_base; /* base of CS segment */
92 int pe; /* protected mode */
93 int code32; /* 32 bit code segment */
95 int lma; /* long mode active */
96 int code64; /* 64 bit code segment */
99 int ss32; /* 32 bit stack segment */
100 int cc_op; /* current CC operation */
101 int addseg; /* non zero if either DS/ES/SS have a non zero base */
102 int f_st; /* currently unused */
103 int vm86; /* vm86 mode */
106 int tf; /* TF cpu flag */
107 int singlestep_enabled; /* "hardware" single step enabled */
108 int jmp_opt; /* use direct block chaining for direct jumps */
109 int mem_index; /* select memory access functions */
110 uint64_t flags; /* all execution flags */
111 struct TranslationBlock *tb;
112 int popl_esp_hack; /* for correct popl with esp base handling */
113 int rip_offset; /* only used in x86_64, but left for simplicity */
115 int cpuid_ext_features;
116 int cpuid_ext2_features;
117 int cpuid_ext3_features;
120 static void gen_eob(DisasContext *s);
121 static void gen_jmp(DisasContext *s, target_ulong eip);
122 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
124 /* i386 arith/logic operations */
144 OP_SHL1, /* undocumented */
168 /* I386 int registers */
169 OR_EAX, /* MUST be even numbered */
178 OR_TMP0 = 16, /* temporary operand register */
180 OR_A0, /* temporary register used when doing address evaluation */
183 static inline void gen_op_movl_T0_0(void)
185 tcg_gen_movi_tl(cpu_T[0], 0);
188 static inline void gen_op_movl_T0_im(int32_t val)
190 tcg_gen_movi_tl(cpu_T[0], val);
193 static inline void gen_op_movl_T0_imu(uint32_t val)
195 tcg_gen_movi_tl(cpu_T[0], val);
198 static inline void gen_op_movl_T1_im(int32_t val)
200 tcg_gen_movi_tl(cpu_T[1], val);
203 static inline void gen_op_movl_T1_imu(uint32_t val)
205 tcg_gen_movi_tl(cpu_T[1], val);
208 static inline void gen_op_movl_A0_im(uint32_t val)
210 tcg_gen_movi_tl(cpu_A0, val);
214 static inline void gen_op_movq_A0_im(int64_t val)
216 tcg_gen_movi_tl(cpu_A0, val);
220 static inline void gen_movtl_T0_im(target_ulong val)
222 tcg_gen_movi_tl(cpu_T[0], val);
225 static inline void gen_movtl_T1_im(target_ulong val)
227 tcg_gen_movi_tl(cpu_T[1], val);
230 static inline void gen_op_andl_T0_ffff(void)
232 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
235 static inline void gen_op_andl_T0_im(uint32_t val)
237 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
240 static inline void gen_op_movl_T0_T1(void)
242 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
245 static inline void gen_op_andl_A0_ffff(void)
247 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
252 #define NB_OP_SIZES 4
254 #else /* !TARGET_X86_64 */
256 #define NB_OP_SIZES 3
258 #endif /* !TARGET_X86_64 */
260 #if defined(WORDS_BIGENDIAN)
261 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
262 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
263 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
264 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
265 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
267 #define REG_B_OFFSET 0
268 #define REG_H_OFFSET 1
269 #define REG_W_OFFSET 0
270 #define REG_L_OFFSET 0
271 #define REG_LH_OFFSET 4
274 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
278 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
290 /* high part of register set to zero */
291 tcg_gen_movi_tl(cpu_tmp0, 0);
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
307 static inline void gen_op_mov_reg_T0(int ot, int reg)
309 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
312 static inline void gen_op_mov_reg_T1(int ot, int reg)
314 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
317 static inline void gen_op_mov_reg_A0(int size, int reg)
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
326 /* high part of register set to zero */
327 tcg_gen_movi_tl(cpu_tmp0, 0);
328 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
332 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
337 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
343 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
347 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
350 tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
355 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
360 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
362 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
365 static inline void gen_op_movl_A0_reg(int reg)
367 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
370 static inline void gen_op_addl_A0_im(int32_t val)
372 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
374 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
379 static inline void gen_op_addq_A0_im(int64_t val)
381 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
385 static void gen_add_A0_im(DisasContext *s, int val)
389 gen_op_addq_A0_im(val);
392 gen_op_addl_A0_im(val);
395 static inline void gen_op_addl_T0_T1(void)
397 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
400 static inline void gen_op_jmp_T0(void)
402 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
405 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
409 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
410 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
411 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
414 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
415 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
417 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
419 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
423 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
424 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
425 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
431 static inline void gen_op_add_reg_T0(int size, int reg)
435 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
436 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
437 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
440 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
441 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
443 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
445 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
449 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
450 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
451 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
457 static inline void gen_op_set_cc_op(int32_t val)
459 tcg_gen_movi_i32(cpu_cc_op, val);
462 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
466 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
467 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
469 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
473 static inline void gen_op_movl_A0_seg(int reg)
475 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
478 static inline void gen_op_addl_A0_seg(int reg)
480 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
481 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
483 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
488 static inline void gen_op_movq_A0_seg(int reg)
490 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
493 static inline void gen_op_addq_A0_seg(int reg)
495 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
496 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
499 static inline void gen_op_movq_A0_reg(int reg)
501 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
504 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
506 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
508 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
509 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
513 static inline void gen_op_lds_T0_A0(int idx)
515 int mem_index = (idx >> 2) - 1;
518 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
521 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
525 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
530 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
532 int mem_index = (idx >> 2) - 1;
535 tcg_gen_qemu_ld8u(t0, a0, mem_index);
538 tcg_gen_qemu_ld16u(t0, a0, mem_index);
541 tcg_gen_qemu_ld32u(t0, a0, mem_index);
545 /* Should never happen on 32-bit targets. */
547 tcg_gen_qemu_ld64(t0, a0, mem_index);
553 /* XXX: always use ldu or lds */
554 static inline void gen_op_ld_T0_A0(int idx)
556 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
559 static inline void gen_op_ldu_T0_A0(int idx)
561 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
564 static inline void gen_op_ld_T1_A0(int idx)
566 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
569 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
571 int mem_index = (idx >> 2) - 1;
574 tcg_gen_qemu_st8(t0, a0, mem_index);
577 tcg_gen_qemu_st16(t0, a0, mem_index);
580 tcg_gen_qemu_st32(t0, a0, mem_index);
584 /* Should never happen on 32-bit targets. */
586 tcg_gen_qemu_st64(t0, a0, mem_index);
592 static inline void gen_op_st_T0_A0(int idx)
594 gen_op_st_v(idx, cpu_T[0], cpu_A0);
597 static inline void gen_op_st_T1_A0(int idx)
599 gen_op_st_v(idx, cpu_T[1], cpu_A0);
602 static inline void gen_jmp_im(target_ulong pc)
604 tcg_gen_movi_tl(cpu_tmp0, pc);
605 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
608 static inline void gen_string_movl_A0_ESI(DisasContext *s)
612 override = s->override;
616 gen_op_movq_A0_seg(override);
617 gen_op_addq_A0_reg_sN(0, R_ESI);
619 gen_op_movq_A0_reg(R_ESI);
625 if (s->addseg && override < 0)
628 gen_op_movl_A0_seg(override);
629 gen_op_addl_A0_reg_sN(0, R_ESI);
631 gen_op_movl_A0_reg(R_ESI);
634 /* 16 address, always override */
637 gen_op_movl_A0_reg(R_ESI);
638 gen_op_andl_A0_ffff();
639 gen_op_addl_A0_seg(override);
643 static inline void gen_string_movl_A0_EDI(DisasContext *s)
647 gen_op_movq_A0_reg(R_EDI);
652 gen_op_movl_A0_seg(R_ES);
653 gen_op_addl_A0_reg_sN(0, R_EDI);
655 gen_op_movl_A0_reg(R_EDI);
658 gen_op_movl_A0_reg(R_EDI);
659 gen_op_andl_A0_ffff();
660 gen_op_addl_A0_seg(R_ES);
664 static inline void gen_op_movl_T0_Dshift(int ot)
666 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
667 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
670 static void gen_extu(int ot, TCGv reg)
674 tcg_gen_ext8u_tl(reg, reg);
677 tcg_gen_ext16u_tl(reg, reg);
680 tcg_gen_ext32u_tl(reg, reg);
687 static void gen_exts(int ot, TCGv reg)
691 tcg_gen_ext8s_tl(reg, reg);
694 tcg_gen_ext16s_tl(reg, reg);
697 tcg_gen_ext32s_tl(reg, reg);
704 static inline void gen_op_jnz_ecx(int size, int label1)
706 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
707 gen_extu(size + 1, cpu_tmp0);
708 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
711 static inline void gen_op_jz_ecx(int size, int label1)
713 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
714 gen_extu(size + 1, cpu_tmp0);
715 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
718 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
721 case 0: gen_helper_inb(v, n); break;
722 case 1: gen_helper_inw(v, n); break;
723 case 2: gen_helper_inl(v, n); break;
728 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
731 case 0: gen_helper_outb(v, n); break;
732 case 1: gen_helper_outw(v, n); break;
733 case 2: gen_helper_outl(v, n); break;
738 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
742 target_ulong next_eip;
745 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
746 if (s->cc_op != CC_OP_DYNAMIC)
747 gen_op_set_cc_op(s->cc_op);
750 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
752 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
753 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
754 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
757 if(s->flags & HF_SVMI_MASK) {
759 if (s->cc_op != CC_OP_DYNAMIC)
760 gen_op_set_cc_op(s->cc_op);
764 svm_flags |= (1 << (4 + ot));
765 next_eip = s->pc - s->cs_base;
766 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
767 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
768 tcg_const_i32(next_eip - cur_eip));
772 static inline void gen_movs(DisasContext *s, int ot)
774 gen_string_movl_A0_ESI(s);
775 gen_op_ld_T0_A0(ot + s->mem_index);
776 gen_string_movl_A0_EDI(s);
777 gen_op_st_T0_A0(ot + s->mem_index);
778 gen_op_movl_T0_Dshift(ot);
779 gen_op_add_reg_T0(s->aflag, R_ESI);
780 gen_op_add_reg_T0(s->aflag, R_EDI);
783 static inline void gen_update_cc_op(DisasContext *s)
785 if (s->cc_op != CC_OP_DYNAMIC) {
786 gen_op_set_cc_op(s->cc_op);
787 s->cc_op = CC_OP_DYNAMIC;
791 static void gen_op_update1_cc(void)
793 tcg_gen_discard_tl(cpu_cc_src);
794 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
797 static void gen_op_update2_cc(void)
799 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
800 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
803 static inline void gen_op_cmpl_T0_T1_cc(void)
805 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
806 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
809 static inline void gen_op_testl_T0_T1_cc(void)
811 tcg_gen_discard_tl(cpu_cc_src);
812 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
815 static void gen_op_update_neg_cc(void)
817 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
818 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
821 /* compute eflags.C to reg */
822 static void gen_compute_eflags_c(TCGv reg)
824 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
825 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
828 /* compute all eflags to cc_src */
829 static void gen_compute_eflags(TCGv reg)
831 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
832 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
835 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
837 if (s->cc_op != CC_OP_DYNAMIC)
838 gen_op_set_cc_op(s->cc_op);
841 gen_compute_eflags(cpu_T[0]);
842 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
843 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
846 gen_compute_eflags_c(cpu_T[0]);
849 gen_compute_eflags(cpu_T[0]);
850 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
851 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
854 gen_compute_eflags(cpu_tmp0);
855 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
856 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
857 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
860 gen_compute_eflags(cpu_T[0]);
861 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
862 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865 gen_compute_eflags(cpu_T[0]);
866 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
867 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
870 gen_compute_eflags(cpu_tmp0);
871 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
872 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
873 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
874 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
878 gen_compute_eflags(cpu_tmp0);
879 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
880 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
881 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
882 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
883 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
884 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
889 /* return true if setcc_slow is not needed (WARNING: must be kept in
890 sync with gen_jcc1) */
891 static int is_fast_jcc_case(DisasContext *s, int b)
894 jcc_op = (b >> 1) & 7;
896 /* we optimize the cmp/jcc case */
901 if (jcc_op == JCC_O || jcc_op == JCC_P)
905 /* some jumps are easy to compute */
930 if (jcc_op != JCC_Z && jcc_op != JCC_S)
940 /* generate a conditional jump to label 'l1' according to jump opcode
941 value 'b'. In the fast case, T0 is guaranted not to be used. */
942 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
944 int inv, jcc_op, size, cond;
948 jcc_op = (b >> 1) & 7;
951 /* we optimize the cmp/jcc case */
957 size = cc_op - CC_OP_SUBB;
963 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
967 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
972 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
980 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
986 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
987 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
991 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
992 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
997 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
998 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1003 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1010 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1013 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1015 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1019 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1020 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1024 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1025 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1027 #ifdef TARGET_X86_64
1030 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1031 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1038 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1042 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1045 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1047 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1051 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1052 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1056 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1057 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1059 #ifdef TARGET_X86_64
1062 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1063 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1070 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1078 /* some jumps are easy to compute */
1120 size = (cc_op - CC_OP_ADDB) & 3;
1123 size = (cc_op - CC_OP_ADDB) & 3;
1131 gen_setcc_slow_T0(s, jcc_op);
1132 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1138 /* XXX: does not work with gdbstub "ice" single step - not a
1140 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1144 l1 = gen_new_label();
1145 l2 = gen_new_label();
1146 gen_op_jnz_ecx(s->aflag, l1);
1148 gen_jmp_tb(s, next_eip, 1);
1153 static inline void gen_stos(DisasContext *s, int ot)
1155 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1156 gen_string_movl_A0_EDI(s);
1157 gen_op_st_T0_A0(ot + s->mem_index);
1158 gen_op_movl_T0_Dshift(ot);
1159 gen_op_add_reg_T0(s->aflag, R_EDI);
1162 static inline void gen_lods(DisasContext *s, int ot)
1164 gen_string_movl_A0_ESI(s);
1165 gen_op_ld_T0_A0(ot + s->mem_index);
1166 gen_op_mov_reg_T0(ot, R_EAX);
1167 gen_op_movl_T0_Dshift(ot);
1168 gen_op_add_reg_T0(s->aflag, R_ESI);
1171 static inline void gen_scas(DisasContext *s, int ot)
1173 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1174 gen_string_movl_A0_EDI(s);
1175 gen_op_ld_T1_A0(ot + s->mem_index);
1176 gen_op_cmpl_T0_T1_cc();
1177 gen_op_movl_T0_Dshift(ot);
1178 gen_op_add_reg_T0(s->aflag, R_EDI);
1181 static inline void gen_cmps(DisasContext *s, int ot)
1183 gen_string_movl_A0_ESI(s);
1184 gen_op_ld_T0_A0(ot + s->mem_index);
1185 gen_string_movl_A0_EDI(s);
1186 gen_op_ld_T1_A0(ot + s->mem_index);
1187 gen_op_cmpl_T0_T1_cc();
1188 gen_op_movl_T0_Dshift(ot);
1189 gen_op_add_reg_T0(s->aflag, R_ESI);
1190 gen_op_add_reg_T0(s->aflag, R_EDI);
1193 static inline void gen_ins(DisasContext *s, int ot)
1197 gen_string_movl_A0_EDI(s);
1198 /* Note: we must do this dummy write first to be restartable in
1199 case of page fault. */
1201 gen_op_st_T0_A0(ot + s->mem_index);
1202 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1203 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1204 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1205 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1206 gen_op_st_T0_A0(ot + s->mem_index);
1207 gen_op_movl_T0_Dshift(ot);
1208 gen_op_add_reg_T0(s->aflag, R_EDI);
1213 static inline void gen_outs(DisasContext *s, int ot)
1217 gen_string_movl_A0_ESI(s);
1218 gen_op_ld_T0_A0(ot + s->mem_index);
1220 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1221 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1222 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1223 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1224 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1226 gen_op_movl_T0_Dshift(ot);
1227 gen_op_add_reg_T0(s->aflag, R_ESI);
1232 /* same method as Valgrind : we generate jumps to current or next
1234 #define GEN_REPZ(op) \
1235 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1236 target_ulong cur_eip, target_ulong next_eip) \
1239 gen_update_cc_op(s); \
1240 l2 = gen_jz_ecx_string(s, next_eip); \
1241 gen_ ## op(s, ot); \
1242 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1243 /* a loop would cause two single step exceptions if ECX = 1 \
1244 before rep string_insn */ \
1246 gen_op_jz_ecx(s->aflag, l2); \
1247 gen_jmp(s, cur_eip); \
1250 #define GEN_REPZ2(op) \
1251 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1252 target_ulong cur_eip, \
1253 target_ulong next_eip, \
1257 gen_update_cc_op(s); \
1258 l2 = gen_jz_ecx_string(s, next_eip); \
1259 gen_ ## op(s, ot); \
1260 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1261 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1262 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1264 gen_op_jz_ecx(s->aflag, l2); \
1265 gen_jmp(s, cur_eip); \
1276 static void gen_helper_fp_arith_ST0_FT0(int op)
1279 case 0: gen_helper_fadd_ST0_FT0(); break;
1280 case 1: gen_helper_fmul_ST0_FT0(); break;
1281 case 2: gen_helper_fcom_ST0_FT0(); break;
1282 case 3: gen_helper_fcom_ST0_FT0(); break;
1283 case 4: gen_helper_fsub_ST0_FT0(); break;
1284 case 5: gen_helper_fsubr_ST0_FT0(); break;
1285 case 6: gen_helper_fdiv_ST0_FT0(); break;
1286 case 7: gen_helper_fdivr_ST0_FT0(); break;
1290 /* NOTE the exception in "r" op ordering */
1291 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1293 TCGv_i32 tmp = tcg_const_i32(opreg);
1295 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1296 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1297 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1298 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1299 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1300 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1304 /* if d == OR_TMP0, it means memory operand (address in A0) */
1305 static void gen_op(DisasContext *s1, int op, int ot, int d)
1308 gen_op_mov_TN_reg(ot, 0, d);
1310 gen_op_ld_T0_A0(ot + s1->mem_index);
1314 if (s1->cc_op != CC_OP_DYNAMIC)
1315 gen_op_set_cc_op(s1->cc_op);
1316 gen_compute_eflags_c(cpu_tmp4);
1317 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1318 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1320 gen_op_mov_reg_T0(ot, d);
1322 gen_op_st_T0_A0(ot + s1->mem_index);
1323 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1324 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1325 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1326 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1327 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1328 s1->cc_op = CC_OP_DYNAMIC;
1331 if (s1->cc_op != CC_OP_DYNAMIC)
1332 gen_op_set_cc_op(s1->cc_op);
1333 gen_compute_eflags_c(cpu_tmp4);
1334 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1335 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1337 gen_op_mov_reg_T0(ot, d);
1339 gen_op_st_T0_A0(ot + s1->mem_index);
1340 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1341 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1342 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1343 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1344 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1345 s1->cc_op = CC_OP_DYNAMIC;
1348 gen_op_addl_T0_T1();
1350 gen_op_mov_reg_T0(ot, d);
1352 gen_op_st_T0_A0(ot + s1->mem_index);
1353 gen_op_update2_cc();
1354 s1->cc_op = CC_OP_ADDB + ot;
1357 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1359 gen_op_mov_reg_T0(ot, d);
1361 gen_op_st_T0_A0(ot + s1->mem_index);
1362 gen_op_update2_cc();
1363 s1->cc_op = CC_OP_SUBB + ot;
1367 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1369 gen_op_mov_reg_T0(ot, d);
1371 gen_op_st_T0_A0(ot + s1->mem_index);
1372 gen_op_update1_cc();
1373 s1->cc_op = CC_OP_LOGICB + ot;
1376 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1378 gen_op_mov_reg_T0(ot, d);
1380 gen_op_st_T0_A0(ot + s1->mem_index);
1381 gen_op_update1_cc();
1382 s1->cc_op = CC_OP_LOGICB + ot;
1385 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1387 gen_op_mov_reg_T0(ot, d);
1389 gen_op_st_T0_A0(ot + s1->mem_index);
1390 gen_op_update1_cc();
1391 s1->cc_op = CC_OP_LOGICB + ot;
1394 gen_op_cmpl_T0_T1_cc();
1395 s1->cc_op = CC_OP_SUBB + ot;
1400 /* if d == OR_TMP0, it means memory operand (address in A0) */
1401 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1404 gen_op_mov_TN_reg(ot, 0, d);
1406 gen_op_ld_T0_A0(ot + s1->mem_index);
1407 if (s1->cc_op != CC_OP_DYNAMIC)
1408 gen_op_set_cc_op(s1->cc_op);
1410 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1411 s1->cc_op = CC_OP_INCB + ot;
1413 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1414 s1->cc_op = CC_OP_DECB + ot;
1417 gen_op_mov_reg_T0(ot, d);
1419 gen_op_st_T0_A0(ot + s1->mem_index);
1420 gen_compute_eflags_c(cpu_cc_src);
1421 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1424 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1425 int is_right, int is_arith)
1438 gen_op_ld_T0_A0(ot + s->mem_index);
1440 gen_op_mov_TN_reg(ot, 0, op1);
1442 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1444 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1448 gen_exts(ot, cpu_T[0]);
1449 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1450 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1452 gen_extu(ot, cpu_T[0]);
1453 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1454 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1457 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1458 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1463 gen_op_st_T0_A0(ot + s->mem_index);
1465 gen_op_mov_reg_T0(ot, op1);
1467 /* update eflags if non zero shift */
1468 if (s->cc_op != CC_OP_DYNAMIC)
1469 gen_op_set_cc_op(s->cc_op);
1471 /* XXX: inefficient */
1472 t0 = tcg_temp_local_new();
1473 t1 = tcg_temp_local_new();
1475 tcg_gen_mov_tl(t0, cpu_T[0]);
1476 tcg_gen_mov_tl(t1, cpu_T3);
1478 shift_label = gen_new_label();
1479 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1481 tcg_gen_mov_tl(cpu_cc_src, t1);
1482 tcg_gen_mov_tl(cpu_cc_dst, t0);
1484 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1486 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1488 gen_set_label(shift_label);
1489 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1495 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1496 int is_right, int is_arith)
1507 gen_op_ld_T0_A0(ot + s->mem_index);
1509 gen_op_mov_TN_reg(ot, 0, op1);
1515 gen_exts(ot, cpu_T[0]);
1516 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1517 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1519 gen_extu(ot, cpu_T[0]);
1520 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1521 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1524 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1525 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1531 gen_op_st_T0_A0(ot + s->mem_index);
1533 gen_op_mov_reg_T0(ot, op1);
1535 /* update eflags if non zero shift */
1537 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1538 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1540 s->cc_op = CC_OP_SARB + ot;
1542 s->cc_op = CC_OP_SHLB + ot;
1546 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1549 tcg_gen_shli_tl(ret, arg1, arg2);
1551 tcg_gen_shri_tl(ret, arg1, -arg2);
1554 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1558 int label1, label2, data_bits;
1559 TCGv t0, t1, t2, a0;
1561 /* XXX: inefficient, but we must use local temps */
1562 t0 = tcg_temp_local_new();
1563 t1 = tcg_temp_local_new();
1564 t2 = tcg_temp_local_new();
1565 a0 = tcg_temp_local_new();
1573 if (op1 == OR_TMP0) {
1574 tcg_gen_mov_tl(a0, cpu_A0);
1575 gen_op_ld_v(ot + s->mem_index, t0, a0);
1577 gen_op_mov_v_reg(ot, t0, op1);
1580 tcg_gen_mov_tl(t1, cpu_T[1]);
1582 tcg_gen_andi_tl(t1, t1, mask);
1584 /* Must test zero case to avoid using undefined behaviour in TCG
1586 label1 = gen_new_label();
1587 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1590 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1592 tcg_gen_mov_tl(cpu_tmp0, t1);
1595 tcg_gen_mov_tl(t2, t0);
1597 data_bits = 8 << ot;
1598 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1599 fix TCG definition) */
1601 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1602 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1603 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1605 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1606 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1607 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1609 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1611 gen_set_label(label1);
1613 if (op1 == OR_TMP0) {
1614 gen_op_st_v(ot + s->mem_index, t0, a0);
1616 gen_op_mov_reg_v(ot, op1, t0);
1620 if (s->cc_op != CC_OP_DYNAMIC)
1621 gen_op_set_cc_op(s->cc_op);
1623 label2 = gen_new_label();
1624 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1626 gen_compute_eflags(cpu_cc_src);
1627 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1628 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1629 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1630 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1631 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1633 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1635 tcg_gen_andi_tl(t0, t0, CC_C);
1636 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1638 tcg_gen_discard_tl(cpu_cc_dst);
1639 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1641 gen_set_label(label2);
1642 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1650 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1657 /* XXX: inefficient, but we must use local temps */
1658 t0 = tcg_temp_local_new();
1659 t1 = tcg_temp_local_new();
1660 a0 = tcg_temp_local_new();
1668 if (op1 == OR_TMP0) {
1669 tcg_gen_mov_tl(a0, cpu_A0);
1670 gen_op_ld_v(ot + s->mem_index, t0, a0);
1672 gen_op_mov_v_reg(ot, t0, op1);
1676 tcg_gen_mov_tl(t1, t0);
1679 data_bits = 8 << ot;
1681 int shift = op2 & ((1 << (3 + ot)) - 1);
1683 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1684 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1687 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1688 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1690 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1694 if (op1 == OR_TMP0) {
1695 gen_op_st_v(ot + s->mem_index, t0, a0);
1697 gen_op_mov_reg_v(ot, op1, t0);
1702 if (s->cc_op != CC_OP_DYNAMIC)
1703 gen_op_set_cc_op(s->cc_op);
1705 gen_compute_eflags(cpu_cc_src);
1706 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1707 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1708 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1709 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1710 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1712 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1714 tcg_gen_andi_tl(t0, t0, CC_C);
1715 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1717 tcg_gen_discard_tl(cpu_cc_dst);
1718 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1719 s->cc_op = CC_OP_EFLAGS;
1727 /* XXX: add faster immediate = 1 case */
1728 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1733 if (s->cc_op != CC_OP_DYNAMIC)
1734 gen_op_set_cc_op(s->cc_op);
1738 gen_op_ld_T0_A0(ot + s->mem_index);
1740 gen_op_mov_TN_reg(ot, 0, op1);
1744 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1745 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1746 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1747 #ifdef TARGET_X86_64
1748 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1753 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1754 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1755 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1756 #ifdef TARGET_X86_64
1757 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1763 gen_op_st_T0_A0(ot + s->mem_index);
1765 gen_op_mov_reg_T0(ot, op1);
1768 label1 = gen_new_label();
1769 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1771 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1772 tcg_gen_discard_tl(cpu_cc_dst);
1773 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1775 gen_set_label(label1);
1776 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1779 /* XXX: add faster immediate case */
1780 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1783 int label1, label2, data_bits;
1785 TCGv t0, t1, t2, a0;
1787 t0 = tcg_temp_local_new();
1788 t1 = tcg_temp_local_new();
1789 t2 = tcg_temp_local_new();
1790 a0 = tcg_temp_local_new();
1798 if (op1 == OR_TMP0) {
1799 tcg_gen_mov_tl(a0, cpu_A0);
1800 gen_op_ld_v(ot + s->mem_index, t0, a0);
1802 gen_op_mov_v_reg(ot, t0, op1);
1805 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1807 tcg_gen_mov_tl(t1, cpu_T[1]);
1808 tcg_gen_mov_tl(t2, cpu_T3);
1810 /* Must test zero case to avoid using undefined behaviour in TCG
1812 label1 = gen_new_label();
1813 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1815 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1816 if (ot == OT_WORD) {
1817 /* Note: we implement the Intel behaviour for shift count > 16 */
1819 tcg_gen_andi_tl(t0, t0, 0xffff);
1820 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1821 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1822 tcg_gen_ext32u_tl(t0, t0);
1824 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1826 /* only needed if count > 16, but a test would complicate */
1827 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1828 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1830 tcg_gen_shr_tl(t0, t0, t2);
1832 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1834 /* XXX: not optimal */
1835 tcg_gen_andi_tl(t0, t0, 0xffff);
1836 tcg_gen_shli_tl(t1, t1, 16);
1837 tcg_gen_or_tl(t1, t1, t0);
1838 tcg_gen_ext32u_tl(t1, t1);
1840 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1841 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1842 tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0);
1843 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1845 tcg_gen_shl_tl(t0, t0, t2);
1846 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1847 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1848 tcg_gen_or_tl(t0, t0, t1);
1851 data_bits = 8 << ot;
1854 tcg_gen_ext32u_tl(t0, t0);
1856 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1858 tcg_gen_shr_tl(t0, t0, t2);
1859 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1860 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1861 tcg_gen_or_tl(t0, t0, t1);
1865 tcg_gen_ext32u_tl(t1, t1);
1867 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1869 tcg_gen_shl_tl(t0, t0, t2);
1870 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1871 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1872 tcg_gen_or_tl(t0, t0, t1);
1875 tcg_gen_mov_tl(t1, cpu_tmp4);
1877 gen_set_label(label1);
1879 if (op1 == OR_TMP0) {
1880 gen_op_st_v(ot + s->mem_index, t0, a0);
1882 gen_op_mov_reg_v(ot, op1, t0);
1886 if (s->cc_op != CC_OP_DYNAMIC)
1887 gen_op_set_cc_op(s->cc_op);
1889 label2 = gen_new_label();
1890 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1892 tcg_gen_mov_tl(cpu_cc_src, t1);
1893 tcg_gen_mov_tl(cpu_cc_dst, t0);
1895 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1897 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1899 gen_set_label(label2);
1900 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1908 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1911 gen_op_mov_TN_reg(ot, 1, s);
1914 gen_rot_rm_T1(s1, ot, d, 0);
1917 gen_rot_rm_T1(s1, ot, d, 1);
1921 gen_shift_rm_T1(s1, ot, d, 0, 0);
1924 gen_shift_rm_T1(s1, ot, d, 1, 0);
1927 gen_shift_rm_T1(s1, ot, d, 1, 1);
1930 gen_rotc_rm_T1(s1, ot, d, 0);
1933 gen_rotc_rm_T1(s1, ot, d, 1);
1938 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1942 gen_rot_rm_im(s1, ot, d, c, 0);
1945 gen_rot_rm_im(s1, ot, d, c, 1);
1949 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1952 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1955 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1958 /* currently not optimized */
1959 gen_op_movl_T1_im(c);
1960 gen_shift(s1, op, ot, d, OR_TMP1);
1965 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1973 int mod, rm, code, override, must_add_seg;
1975 override = s->override;
1976 must_add_seg = s->addseg;
1979 mod = (modrm >> 6) & 3;
1991 code = ldub_code(s->pc++);
1992 scale = (code >> 6) & 3;
1993 index = ((code >> 3) & 7) | REX_X(s);
2000 if ((base & 7) == 5) {
2002 disp = (int32_t)ldl_code(s->pc);
2004 if (CODE64(s) && !havesib) {
2005 disp += s->pc + s->rip_offset;
2012 disp = (int8_t)ldub_code(s->pc++);
2016 disp = ldl_code(s->pc);
2022 /* for correct popl handling with esp */
2023 if (base == 4 && s->popl_esp_hack)
2024 disp += s->popl_esp_hack;
2025 #ifdef TARGET_X86_64
2026 if (s->aflag == 2) {
2027 gen_op_movq_A0_reg(base);
2029 gen_op_addq_A0_im(disp);
2034 gen_op_movl_A0_reg(base);
2036 gen_op_addl_A0_im(disp);
2039 #ifdef TARGET_X86_64
2040 if (s->aflag == 2) {
2041 gen_op_movq_A0_im(disp);
2045 gen_op_movl_A0_im(disp);
2048 /* XXX: index == 4 is always invalid */
2049 if (havesib && (index != 4 || scale != 0)) {
2050 #ifdef TARGET_X86_64
2051 if (s->aflag == 2) {
2052 gen_op_addq_A0_reg_sN(scale, index);
2056 gen_op_addl_A0_reg_sN(scale, index);
2061 if (base == R_EBP || base == R_ESP)
2066 #ifdef TARGET_X86_64
2067 if (s->aflag == 2) {
2068 gen_op_addq_A0_seg(override);
2072 gen_op_addl_A0_seg(override);
2079 disp = lduw_code(s->pc);
2081 gen_op_movl_A0_im(disp);
2082 rm = 0; /* avoid SS override */
2089 disp = (int8_t)ldub_code(s->pc++);
2093 disp = lduw_code(s->pc);
2099 gen_op_movl_A0_reg(R_EBX);
2100 gen_op_addl_A0_reg_sN(0, R_ESI);
2103 gen_op_movl_A0_reg(R_EBX);
2104 gen_op_addl_A0_reg_sN(0, R_EDI);
2107 gen_op_movl_A0_reg(R_EBP);
2108 gen_op_addl_A0_reg_sN(0, R_ESI);
2111 gen_op_movl_A0_reg(R_EBP);
2112 gen_op_addl_A0_reg_sN(0, R_EDI);
2115 gen_op_movl_A0_reg(R_ESI);
2118 gen_op_movl_A0_reg(R_EDI);
2121 gen_op_movl_A0_reg(R_EBP);
2125 gen_op_movl_A0_reg(R_EBX);
2129 gen_op_addl_A0_im(disp);
2130 gen_op_andl_A0_ffff();
2134 if (rm == 2 || rm == 3 || rm == 6)
2139 gen_op_addl_A0_seg(override);
2149 static void gen_nop_modrm(DisasContext *s, int modrm)
2151 int mod, rm, base, code;
2153 mod = (modrm >> 6) & 3;
2163 code = ldub_code(s->pc++);
2199 /* used for LEA and MOV AX, mem */
2200 static void gen_add_A0_ds_seg(DisasContext *s)
2202 int override, must_add_seg;
2203 must_add_seg = s->addseg;
2205 if (s->override >= 0) {
2206 override = s->override;
2212 #ifdef TARGET_X86_64
2214 gen_op_addq_A0_seg(override);
2218 gen_op_addl_A0_seg(override);
2223 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2225 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2227 int mod, rm, opreg, disp;
2229 mod = (modrm >> 6) & 3;
2230 rm = (modrm & 7) | REX_B(s);
2234 gen_op_mov_TN_reg(ot, 0, reg);
2235 gen_op_mov_reg_T0(ot, rm);
2237 gen_op_mov_TN_reg(ot, 0, rm);
2239 gen_op_mov_reg_T0(ot, reg);
2242 gen_lea_modrm(s, modrm, &opreg, &disp);
2245 gen_op_mov_TN_reg(ot, 0, reg);
2246 gen_op_st_T0_A0(ot + s->mem_index);
2248 gen_op_ld_T0_A0(ot + s->mem_index);
2250 gen_op_mov_reg_T0(ot, reg);
2255 static inline uint32_t insn_get(DisasContext *s, int ot)
2261 ret = ldub_code(s->pc);
2265 ret = lduw_code(s->pc);
2270 ret = ldl_code(s->pc);
2277 static inline int insn_const_size(unsigned int ot)
2285 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2287 TranslationBlock *tb;
2290 pc = s->cs_base + eip;
2292 /* NOTE: we handle the case where the TB spans two pages here */
2293 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2294 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2295 /* jump to same page: we can use a direct jump */
2296 tcg_gen_goto_tb(tb_num);
2298 tcg_gen_exit_tb((long)tb + tb_num);
2300 /* jump to another page: currently not optimized */
2306 static inline void gen_jcc(DisasContext *s, int b,
2307 target_ulong val, target_ulong next_eip)
2312 if (s->cc_op != CC_OP_DYNAMIC) {
2313 gen_op_set_cc_op(s->cc_op);
2314 s->cc_op = CC_OP_DYNAMIC;
2317 l1 = gen_new_label();
2318 gen_jcc1(s, cc_op, b, l1);
2320 gen_goto_tb(s, 0, next_eip);
2323 gen_goto_tb(s, 1, val);
2327 l1 = gen_new_label();
2328 l2 = gen_new_label();
2329 gen_jcc1(s, cc_op, b, l1);
2331 gen_jmp_im(next_eip);
2341 static void gen_setcc(DisasContext *s, int b)
2343 int inv, jcc_op, l1;
2346 if (is_fast_jcc_case(s, b)) {
2347 /* nominal case: we use a jump */
2348 /* XXX: make it faster by adding new instructions in TCG */
2349 t0 = tcg_temp_local_new();
2350 tcg_gen_movi_tl(t0, 0);
2351 l1 = gen_new_label();
2352 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2353 tcg_gen_movi_tl(t0, 1);
2355 tcg_gen_mov_tl(cpu_T[0], t0);
2358 /* slow case: it is more efficient not to generate a jump,
2359 although it is questionnable whether this optimization is
2362 jcc_op = (b >> 1) & 7;
2363 gen_setcc_slow_T0(s, jcc_op);
2365 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2370 static inline void gen_op_movl_T0_seg(int seg_reg)
2372 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2373 offsetof(CPUX86State,segs[seg_reg].selector));
2376 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2378 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2379 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2380 offsetof(CPUX86State,segs[seg_reg].selector));
2381 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2382 tcg_gen_st_tl(cpu_T[0], cpu_env,
2383 offsetof(CPUX86State,segs[seg_reg].base));
2386 /* move T0 to seg_reg and compute if the CPU state may change. Never
2387 call this function with seg_reg == R_CS */
2388 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2390 if (s->pe && !s->vm86) {
2391 /* XXX: optimize by finding processor state dynamically */
2392 if (s->cc_op != CC_OP_DYNAMIC)
2393 gen_op_set_cc_op(s->cc_op);
2394 gen_jmp_im(cur_eip);
2395 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2396 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2397 /* abort translation because the addseg value may change or
2398 because ss32 may change. For R_SS, translation must always
2399 stop as a special handling must be done to disable hardware
2400 interrupts for the next instruction */
2401 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2404 gen_op_movl_seg_T0_vm(seg_reg);
2405 if (seg_reg == R_SS)
2410 static inline int svm_is_rep(int prefixes)
2412 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2416 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2417 uint32_t type, uint64_t param)
2419 /* no SVM activated; fast case */
2420 if (likely(!(s->flags & HF_SVMI_MASK)))
2422 if (s->cc_op != CC_OP_DYNAMIC)
2423 gen_op_set_cc_op(s->cc_op);
2424 gen_jmp_im(pc_start - s->cs_base);
2425 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2426 tcg_const_i64(param));
2430 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2432 gen_svm_check_intercept_param(s, pc_start, type, 0);
2435 static inline void gen_stack_update(DisasContext *s, int addend)
2437 #ifdef TARGET_X86_64
2439 gen_op_add_reg_im(2, R_ESP, addend);
2443 gen_op_add_reg_im(1, R_ESP, addend);
2445 gen_op_add_reg_im(0, R_ESP, addend);
2449 /* generate a push. It depends on ss32, addseg and dflag */
2450 static void gen_push_T0(DisasContext *s)
2452 #ifdef TARGET_X86_64
2454 gen_op_movq_A0_reg(R_ESP);
2456 gen_op_addq_A0_im(-8);
2457 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2459 gen_op_addq_A0_im(-2);
2460 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2462 gen_op_mov_reg_A0(2, R_ESP);
2466 gen_op_movl_A0_reg(R_ESP);
2468 gen_op_addl_A0_im(-2);
2470 gen_op_addl_A0_im(-4);
2473 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2474 gen_op_addl_A0_seg(R_SS);
2477 gen_op_andl_A0_ffff();
2478 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2479 gen_op_addl_A0_seg(R_SS);
2481 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2482 if (s->ss32 && !s->addseg)
2483 gen_op_mov_reg_A0(1, R_ESP);
2485 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2489 /* generate a push. It depends on ss32, addseg and dflag */
2490 /* slower version for T1, only used for call Ev */
2491 static void gen_push_T1(DisasContext *s)
2493 #ifdef TARGET_X86_64
2495 gen_op_movq_A0_reg(R_ESP);
2497 gen_op_addq_A0_im(-8);
2498 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2500 gen_op_addq_A0_im(-2);
2501 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2503 gen_op_mov_reg_A0(2, R_ESP);
2507 gen_op_movl_A0_reg(R_ESP);
2509 gen_op_addl_A0_im(-2);
2511 gen_op_addl_A0_im(-4);
2514 gen_op_addl_A0_seg(R_SS);
2517 gen_op_andl_A0_ffff();
2518 gen_op_addl_A0_seg(R_SS);
2520 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2522 if (s->ss32 && !s->addseg)
2523 gen_op_mov_reg_A0(1, R_ESP);
2525 gen_stack_update(s, (-2) << s->dflag);
2529 /* two step pop is necessary for precise exceptions */
2530 static void gen_pop_T0(DisasContext *s)
2532 #ifdef TARGET_X86_64
2534 gen_op_movq_A0_reg(R_ESP);
2535 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2539 gen_op_movl_A0_reg(R_ESP);
2542 gen_op_addl_A0_seg(R_SS);
2544 gen_op_andl_A0_ffff();
2545 gen_op_addl_A0_seg(R_SS);
2547 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2551 static void gen_pop_update(DisasContext *s)
2553 #ifdef TARGET_X86_64
2554 if (CODE64(s) && s->dflag) {
2555 gen_stack_update(s, 8);
2559 gen_stack_update(s, 2 << s->dflag);
2563 static void gen_stack_A0(DisasContext *s)
2565 gen_op_movl_A0_reg(R_ESP);
2567 gen_op_andl_A0_ffff();
2568 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2570 gen_op_addl_A0_seg(R_SS);
2573 /* NOTE: wrap around in 16 bit not fully handled */
2574 static void gen_pusha(DisasContext *s)
2577 gen_op_movl_A0_reg(R_ESP);
2578 gen_op_addl_A0_im(-16 << s->dflag);
2580 gen_op_andl_A0_ffff();
2581 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2583 gen_op_addl_A0_seg(R_SS);
2584 for(i = 0;i < 8; i++) {
2585 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2586 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2587 gen_op_addl_A0_im(2 << s->dflag);
2589 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2592 /* NOTE: wrap around in 16 bit not fully handled */
2593 static void gen_popa(DisasContext *s)
2596 gen_op_movl_A0_reg(R_ESP);
2598 gen_op_andl_A0_ffff();
2599 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2600 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2602 gen_op_addl_A0_seg(R_SS);
2603 for(i = 0;i < 8; i++) {
2604 /* ESP is not reloaded */
2606 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2607 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2609 gen_op_addl_A0_im(2 << s->dflag);
2611 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2614 static void gen_enter(DisasContext *s, int esp_addend, int level)
2619 #ifdef TARGET_X86_64
2621 ot = s->dflag ? OT_QUAD : OT_WORD;
2624 gen_op_movl_A0_reg(R_ESP);
2625 gen_op_addq_A0_im(-opsize);
2626 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2629 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2630 gen_op_st_T0_A0(ot + s->mem_index);
2632 /* XXX: must save state */
2633 gen_helper_enter64_level(tcg_const_i32(level),
2634 tcg_const_i32((ot == OT_QUAD)),
2637 gen_op_mov_reg_T1(ot, R_EBP);
2638 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2639 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2643 ot = s->dflag + OT_WORD;
2644 opsize = 2 << s->dflag;
2646 gen_op_movl_A0_reg(R_ESP);
2647 gen_op_addl_A0_im(-opsize);
2649 gen_op_andl_A0_ffff();
2650 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2652 gen_op_addl_A0_seg(R_SS);
2654 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2655 gen_op_st_T0_A0(ot + s->mem_index);
2657 /* XXX: must save state */
2658 gen_helper_enter_level(tcg_const_i32(level),
2659 tcg_const_i32(s->dflag),
2662 gen_op_mov_reg_T1(ot, R_EBP);
2663 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2664 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2668 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2670 if (s->cc_op != CC_OP_DYNAMIC)
2671 gen_op_set_cc_op(s->cc_op);
2672 gen_jmp_im(cur_eip);
2673 gen_helper_raise_exception(tcg_const_i32(trapno));
2677 /* an interrupt is different from an exception because of the
2679 static void gen_interrupt(DisasContext *s, int intno,
2680 target_ulong cur_eip, target_ulong next_eip)
2682 if (s->cc_op != CC_OP_DYNAMIC)
2683 gen_op_set_cc_op(s->cc_op);
2684 gen_jmp_im(cur_eip);
2685 gen_helper_raise_interrupt(tcg_const_i32(intno),
2686 tcg_const_i32(next_eip - cur_eip));
2690 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2692 if (s->cc_op != CC_OP_DYNAMIC)
2693 gen_op_set_cc_op(s->cc_op);
2694 gen_jmp_im(cur_eip);
2699 /* generate a generic end of block. Trace exception is also generated
2701 static void gen_eob(DisasContext *s)
2703 if (s->cc_op != CC_OP_DYNAMIC)
2704 gen_op_set_cc_op(s->cc_op);
2705 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2706 gen_helper_reset_inhibit_irq();
2708 if (s->singlestep_enabled) {
2711 gen_helper_single_step();
2718 /* generate a jump to eip. No segment change must happen before as a
2719 direct call to the next block may occur */
2720 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2723 if (s->cc_op != CC_OP_DYNAMIC) {
2724 gen_op_set_cc_op(s->cc_op);
2725 s->cc_op = CC_OP_DYNAMIC;
2727 gen_goto_tb(s, tb_num, eip);
2735 static void gen_jmp(DisasContext *s, target_ulong eip)
2737 gen_jmp_tb(s, eip, 0);
2740 static inline void gen_ldq_env_A0(int idx, int offset)
2742 int mem_index = (idx >> 2) - 1;
2743 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2744 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2747 static inline void gen_stq_env_A0(int idx, int offset)
2749 int mem_index = (idx >> 2) - 1;
2750 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2751 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2754 static inline void gen_ldo_env_A0(int idx, int offset)
2756 int mem_index = (idx >> 2) - 1;
2757 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2758 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2759 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2760 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2761 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2764 static inline void gen_sto_env_A0(int idx, int offset)
2766 int mem_index = (idx >> 2) - 1;
2767 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2768 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2769 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2770 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2771 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2774 static inline void gen_op_movo(int d_offset, int s_offset)
2776 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2777 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2778 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2779 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2782 static inline void gen_op_movq(int d_offset, int s_offset)
2784 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2785 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2788 static inline void gen_op_movl(int d_offset, int s_offset)
2790 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2791 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2794 static inline void gen_op_movq_env_0(int d_offset)
2796 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2797 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2800 #define SSE_SPECIAL ((void *)1)
2801 #define SSE_DUMMY ((void *)2)
2803 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2804 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2805 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2807 static void *sse_op_table1[256][4] = {
2808 /* 3DNow! extensions */
2809 [0x0e] = { SSE_DUMMY }, /* femms */
2810 [0x0f] = { SSE_DUMMY }, /* pf... */
2811 /* pure SSE operations */
2812 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2813 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2814 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2815 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2816 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2817 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2818 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2819 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2821 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2822 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2823 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2824 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2825 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2826 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2827 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2828 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2829 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2830 [0x51] = SSE_FOP(sqrt),
2831 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2832 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2833 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2834 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2835 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2836 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2837 [0x58] = SSE_FOP(add),
2838 [0x59] = SSE_FOP(mul),
2839 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2840 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2841 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2842 [0x5c] = SSE_FOP(sub),
2843 [0x5d] = SSE_FOP(min),
2844 [0x5e] = SSE_FOP(div),
2845 [0x5f] = SSE_FOP(max),
2847 [0xc2] = SSE_FOP(cmpeq),
2848 [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
2850 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2851 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2853 /* MMX ops and their SSE extensions */
2854 [0x60] = MMX_OP2(punpcklbw),
2855 [0x61] = MMX_OP2(punpcklwd),
2856 [0x62] = MMX_OP2(punpckldq),
2857 [0x63] = MMX_OP2(packsswb),
2858 [0x64] = MMX_OP2(pcmpgtb),
2859 [0x65] = MMX_OP2(pcmpgtw),
2860 [0x66] = MMX_OP2(pcmpgtl),
2861 [0x67] = MMX_OP2(packuswb),
2862 [0x68] = MMX_OP2(punpckhbw),
2863 [0x69] = MMX_OP2(punpckhwd),
2864 [0x6a] = MMX_OP2(punpckhdq),
2865 [0x6b] = MMX_OP2(packssdw),
2866 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2867 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2868 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2869 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2870 [0x70] = { gen_helper_pshufw_mmx,
2871 gen_helper_pshufd_xmm,
2872 gen_helper_pshufhw_xmm,
2873 gen_helper_pshuflw_xmm },
2874 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2875 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2876 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2877 [0x74] = MMX_OP2(pcmpeqb),
2878 [0x75] = MMX_OP2(pcmpeqw),
2879 [0x76] = MMX_OP2(pcmpeql),
2880 [0x77] = { SSE_DUMMY }, /* emms */
2881 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2882 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2883 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2884 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2885 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2886 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2887 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2888 [0xd1] = MMX_OP2(psrlw),
2889 [0xd2] = MMX_OP2(psrld),
2890 [0xd3] = MMX_OP2(psrlq),
2891 [0xd4] = MMX_OP2(paddq),
2892 [0xd5] = MMX_OP2(pmullw),
2893 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2894 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2895 [0xd8] = MMX_OP2(psubusb),
2896 [0xd9] = MMX_OP2(psubusw),
2897 [0xda] = MMX_OP2(pminub),
2898 [0xdb] = MMX_OP2(pand),
2899 [0xdc] = MMX_OP2(paddusb),
2900 [0xdd] = MMX_OP2(paddusw),
2901 [0xde] = MMX_OP2(pmaxub),
2902 [0xdf] = MMX_OP2(pandn),
2903 [0xe0] = MMX_OP2(pavgb),
2904 [0xe1] = MMX_OP2(psraw),
2905 [0xe2] = MMX_OP2(psrad),
2906 [0xe3] = MMX_OP2(pavgw),
2907 [0xe4] = MMX_OP2(pmulhuw),
2908 [0xe5] = MMX_OP2(pmulhw),
2909 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2910 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2911 [0xe8] = MMX_OP2(psubsb),
2912 [0xe9] = MMX_OP2(psubsw),
2913 [0xea] = MMX_OP2(pminsw),
2914 [0xeb] = MMX_OP2(por),
2915 [0xec] = MMX_OP2(paddsb),
2916 [0xed] = MMX_OP2(paddsw),
2917 [0xee] = MMX_OP2(pmaxsw),
2918 [0xef] = MMX_OP2(pxor),
2919 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2920 [0xf1] = MMX_OP2(psllw),
2921 [0xf2] = MMX_OP2(pslld),
2922 [0xf3] = MMX_OP2(psllq),
2923 [0xf4] = MMX_OP2(pmuludq),
2924 [0xf5] = MMX_OP2(pmaddwd),
2925 [0xf6] = MMX_OP2(psadbw),
2926 [0xf7] = MMX_OP2(maskmov),
2927 [0xf8] = MMX_OP2(psubb),
2928 [0xf9] = MMX_OP2(psubw),
2929 [0xfa] = MMX_OP2(psubl),
2930 [0xfb] = MMX_OP2(psubq),
2931 [0xfc] = MMX_OP2(paddb),
2932 [0xfd] = MMX_OP2(paddw),
2933 [0xfe] = MMX_OP2(paddl),
2936 static void *sse_op_table2[3 * 8][2] = {
2937 [0 + 2] = MMX_OP2(psrlw),
2938 [0 + 4] = MMX_OP2(psraw),
2939 [0 + 6] = MMX_OP2(psllw),
2940 [8 + 2] = MMX_OP2(psrld),
2941 [8 + 4] = MMX_OP2(psrad),
2942 [8 + 6] = MMX_OP2(pslld),
2943 [16 + 2] = MMX_OP2(psrlq),
2944 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2945 [16 + 6] = MMX_OP2(psllq),
2946 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2949 static void *sse_op_table3[4 * 3] = {
2950 gen_helper_cvtsi2ss,
2951 gen_helper_cvtsi2sd,
2952 X86_64_ONLY(gen_helper_cvtsq2ss),
2953 X86_64_ONLY(gen_helper_cvtsq2sd),
2955 gen_helper_cvttss2si,
2956 gen_helper_cvttsd2si,
2957 X86_64_ONLY(gen_helper_cvttss2sq),
2958 X86_64_ONLY(gen_helper_cvttsd2sq),
2960 gen_helper_cvtss2si,
2961 gen_helper_cvtsd2si,
2962 X86_64_ONLY(gen_helper_cvtss2sq),
2963 X86_64_ONLY(gen_helper_cvtsd2sq),
2966 static void *sse_op_table4[8][4] = {
2977 static void *sse_op_table5[256] = {
2978 [0x0c] = gen_helper_pi2fw,
2979 [0x0d] = gen_helper_pi2fd,
2980 [0x1c] = gen_helper_pf2iw,
2981 [0x1d] = gen_helper_pf2id,
2982 [0x8a] = gen_helper_pfnacc,
2983 [0x8e] = gen_helper_pfpnacc,
2984 [0x90] = gen_helper_pfcmpge,
2985 [0x94] = gen_helper_pfmin,
2986 [0x96] = gen_helper_pfrcp,
2987 [0x97] = gen_helper_pfrsqrt,
2988 [0x9a] = gen_helper_pfsub,
2989 [0x9e] = gen_helper_pfadd,
2990 [0xa0] = gen_helper_pfcmpgt,
2991 [0xa4] = gen_helper_pfmax,
2992 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
2993 [0xa7] = gen_helper_movq, /* pfrsqit1 */
2994 [0xaa] = gen_helper_pfsubr,
2995 [0xae] = gen_helper_pfacc,
2996 [0xb0] = gen_helper_pfcmpeq,
2997 [0xb4] = gen_helper_pfmul,
2998 [0xb6] = gen_helper_movq, /* pfrcpit2 */
2999 [0xb7] = gen_helper_pmulhrw_mmx,
3000 [0xbb] = gen_helper_pswapd,
3001 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3004 struct sse_op_helper_s {
3005 void *op[2]; uint32_t ext_mask;
3007 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3008 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3009 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3010 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3011 static struct sse_op_helper_s sse_op_table6[256] = {
3012 [0x00] = SSSE3_OP(pshufb),
3013 [0x01] = SSSE3_OP(phaddw),
3014 [0x02] = SSSE3_OP(phaddd),
3015 [0x03] = SSSE3_OP(phaddsw),
3016 [0x04] = SSSE3_OP(pmaddubsw),
3017 [0x05] = SSSE3_OP(phsubw),
3018 [0x06] = SSSE3_OP(phsubd),
3019 [0x07] = SSSE3_OP(phsubsw),
3020 [0x08] = SSSE3_OP(psignb),
3021 [0x09] = SSSE3_OP(psignw),
3022 [0x0a] = SSSE3_OP(psignd),
3023 [0x0b] = SSSE3_OP(pmulhrsw),
3024 [0x10] = SSE41_OP(pblendvb),
3025 [0x14] = SSE41_OP(blendvps),
3026 [0x15] = SSE41_OP(blendvpd),
3027 [0x17] = SSE41_OP(ptest),
3028 [0x1c] = SSSE3_OP(pabsb),
3029 [0x1d] = SSSE3_OP(pabsw),
3030 [0x1e] = SSSE3_OP(pabsd),
3031 [0x20] = SSE41_OP(pmovsxbw),
3032 [0x21] = SSE41_OP(pmovsxbd),
3033 [0x22] = SSE41_OP(pmovsxbq),
3034 [0x23] = SSE41_OP(pmovsxwd),
3035 [0x24] = SSE41_OP(pmovsxwq),
3036 [0x25] = SSE41_OP(pmovsxdq),
3037 [0x28] = SSE41_OP(pmuldq),
3038 [0x29] = SSE41_OP(pcmpeqq),
3039 [0x2a] = SSE41_SPECIAL, /* movntqda */
3040 [0x2b] = SSE41_OP(packusdw),
3041 [0x30] = SSE41_OP(pmovzxbw),
3042 [0x31] = SSE41_OP(pmovzxbd),
3043 [0x32] = SSE41_OP(pmovzxbq),
3044 [0x33] = SSE41_OP(pmovzxwd),
3045 [0x34] = SSE41_OP(pmovzxwq),
3046 [0x35] = SSE41_OP(pmovzxdq),
3047 [0x37] = SSE42_OP(pcmpgtq),
3048 [0x38] = SSE41_OP(pminsb),
3049 [0x39] = SSE41_OP(pminsd),
3050 [0x3a] = SSE41_OP(pminuw),
3051 [0x3b] = SSE41_OP(pminud),
3052 [0x3c] = SSE41_OP(pmaxsb),
3053 [0x3d] = SSE41_OP(pmaxsd),
3054 [0x3e] = SSE41_OP(pmaxuw),
3055 [0x3f] = SSE41_OP(pmaxud),
3056 [0x40] = SSE41_OP(pmulld),
3057 [0x41] = SSE41_OP(phminposuw),
3060 static struct sse_op_helper_s sse_op_table7[256] = {
3061 [0x08] = SSE41_OP(roundps),
3062 [0x09] = SSE41_OP(roundpd),
3063 [0x0a] = SSE41_OP(roundss),
3064 [0x0b] = SSE41_OP(roundsd),
3065 [0x0c] = SSE41_OP(blendps),
3066 [0x0d] = SSE41_OP(blendpd),
3067 [0x0e] = SSE41_OP(pblendw),
3068 [0x0f] = SSSE3_OP(palignr),
3069 [0x14] = SSE41_SPECIAL, /* pextrb */
3070 [0x15] = SSE41_SPECIAL, /* pextrw */
3071 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3072 [0x17] = SSE41_SPECIAL, /* extractps */
3073 [0x20] = SSE41_SPECIAL, /* pinsrb */
3074 [0x21] = SSE41_SPECIAL, /* insertps */
3075 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3076 [0x40] = SSE41_OP(dpps),
3077 [0x41] = SSE41_OP(dppd),
3078 [0x42] = SSE41_OP(mpsadbw),
3079 [0x60] = SSE42_OP(pcmpestrm),
3080 [0x61] = SSE42_OP(pcmpestri),
3081 [0x62] = SSE42_OP(pcmpistrm),
3082 [0x63] = SSE42_OP(pcmpistri),
3085 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3087 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3088 int modrm, mod, rm, reg, reg_addr, offset_addr;
3092 if (s->prefix & PREFIX_DATA)
3094 else if (s->prefix & PREFIX_REPZ)
3096 else if (s->prefix & PREFIX_REPNZ)
3100 sse_op2 = sse_op_table1[b][b1];
3103 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3113 /* simple MMX/SSE operation */
3114 if (s->flags & HF_TS_MASK) {
3115 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3118 if (s->flags & HF_EM_MASK) {
3120 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3123 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3124 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3127 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3138 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3139 the static cpu state) */
3141 gen_helper_enter_mmx();
3144 modrm = ldub_code(s->pc++);
3145 reg = ((modrm >> 3) & 7);
3148 mod = (modrm >> 6) & 3;
3149 if (sse_op2 == SSE_SPECIAL) {
3152 case 0x0e7: /* movntq */
3155 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3156 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3158 case 0x1e7: /* movntdq */
3159 case 0x02b: /* movntps */
3160 case 0x12b: /* movntps */
3161 case 0x3f0: /* lddqu */
3164 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3165 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3167 case 0x6e: /* movd mm, ea */
3168 #ifdef TARGET_X86_64
3169 if (s->dflag == 2) {
3170 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3171 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3175 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3176 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3177 offsetof(CPUX86State,fpregs[reg].mmx));
3178 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3179 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3182 case 0x16e: /* movd xmm, ea */
3183 #ifdef TARGET_X86_64
3184 if (s->dflag == 2) {
3185 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3186 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3187 offsetof(CPUX86State,xmm_regs[reg]));
3188 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3192 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3193 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3194 offsetof(CPUX86State,xmm_regs[reg]));
3195 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3196 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3199 case 0x6f: /* movq mm, ea */
3201 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3202 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3205 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3206 offsetof(CPUX86State,fpregs[rm].mmx));
3207 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3208 offsetof(CPUX86State,fpregs[reg].mmx));
3211 case 0x010: /* movups */
3212 case 0x110: /* movupd */
3213 case 0x028: /* movaps */
3214 case 0x128: /* movapd */
3215 case 0x16f: /* movdqa xmm, ea */
3216 case 0x26f: /* movdqu xmm, ea */
3218 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3219 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3221 rm = (modrm & 7) | REX_B(s);
3222 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3223 offsetof(CPUX86State,xmm_regs[rm]));
3226 case 0x210: /* movss xmm, ea */
3228 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3229 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3230 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3232 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3233 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3234 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3236 rm = (modrm & 7) | REX_B(s);
3237 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3238 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3241 case 0x310: /* movsd xmm, ea */
3243 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3244 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3246 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3247 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3249 rm = (modrm & 7) | REX_B(s);
3250 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3251 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3254 case 0x012: /* movlps */
3255 case 0x112: /* movlpd */
3257 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3258 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3261 rm = (modrm & 7) | REX_B(s);
3262 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3263 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3266 case 0x212: /* movsldup */
3268 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3269 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3271 rm = (modrm & 7) | REX_B(s);
3272 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3273 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3274 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3275 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3277 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3278 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3279 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3280 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3282 case 0x312: /* movddup */
3284 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3285 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3287 rm = (modrm & 7) | REX_B(s);
3288 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3289 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3291 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3292 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3294 case 0x016: /* movhps */
3295 case 0x116: /* movhpd */
3297 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3298 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3301 rm = (modrm & 7) | REX_B(s);
3302 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3303 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3306 case 0x216: /* movshdup */
3308 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3309 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3311 rm = (modrm & 7) | REX_B(s);
3312 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3313 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3314 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3315 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3317 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3318 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3319 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3320 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3322 case 0x7e: /* movd ea, mm */
3323 #ifdef TARGET_X86_64
3324 if (s->dflag == 2) {
3325 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3326 offsetof(CPUX86State,fpregs[reg].mmx));
3327 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3331 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3332 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3333 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3336 case 0x17e: /* movd ea, xmm */
3337 #ifdef TARGET_X86_64
3338 if (s->dflag == 2) {
3339 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3340 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3341 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3345 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3346 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3347 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3350 case 0x27e: /* movq xmm, ea */
3352 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3353 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3355 rm = (modrm & 7) | REX_B(s);
3356 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3357 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3359 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3361 case 0x7f: /* movq ea, mm */
3363 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3364 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3367 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3368 offsetof(CPUX86State,fpregs[reg].mmx));
3371 case 0x011: /* movups */
3372 case 0x111: /* movupd */
3373 case 0x029: /* movaps */
3374 case 0x129: /* movapd */
3375 case 0x17f: /* movdqa ea, xmm */
3376 case 0x27f: /* movdqu ea, xmm */
3378 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3379 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3381 rm = (modrm & 7) | REX_B(s);
3382 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3383 offsetof(CPUX86State,xmm_regs[reg]));
3386 case 0x211: /* movss ea, xmm */
3388 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3389 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3390 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3392 rm = (modrm & 7) | REX_B(s);
3393 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3394 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3397 case 0x311: /* movsd ea, xmm */
3399 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3400 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3402 rm = (modrm & 7) | REX_B(s);
3403 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3404 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3407 case 0x013: /* movlps */
3408 case 0x113: /* movlpd */
3410 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3411 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3416 case 0x017: /* movhps */
3417 case 0x117: /* movhpd */
3419 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3420 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3425 case 0x71: /* shift mm, im */
3428 case 0x171: /* shift xmm, im */
3431 val = ldub_code(s->pc++);
3433 gen_op_movl_T0_im(val);
3434 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3436 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3437 op1_offset = offsetof(CPUX86State,xmm_t0);
3439 gen_op_movl_T0_im(val);
3440 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3442 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3443 op1_offset = offsetof(CPUX86State,mmx_t0);
3445 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3449 rm = (modrm & 7) | REX_B(s);
3450 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3453 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3455 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3456 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3457 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3459 case 0x050: /* movmskps */
3460 rm = (modrm & 7) | REX_B(s);
3461 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3462 offsetof(CPUX86State,xmm_regs[rm]));
3463 gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3464 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3465 gen_op_mov_reg_T0(OT_LONG, reg);
3467 case 0x150: /* movmskpd */
3468 rm = (modrm & 7) | REX_B(s);
3469 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3470 offsetof(CPUX86State,xmm_regs[rm]));
3471 gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3472 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3473 gen_op_mov_reg_T0(OT_LONG, reg);
3475 case 0x02a: /* cvtpi2ps */
3476 case 0x12a: /* cvtpi2pd */
3477 gen_helper_enter_mmx();
3479 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3480 op2_offset = offsetof(CPUX86State,mmx_t0);
3481 gen_ldq_env_A0(s->mem_index, op2_offset);
3484 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3486 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3487 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3488 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3491 gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
3495 gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
3499 case 0x22a: /* cvtsi2ss */
3500 case 0x32a: /* cvtsi2sd */
3501 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3502 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3503 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3504 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3505 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3506 if (ot == OT_LONG) {
3507 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3508 ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
3510 ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]);
3513 case 0x02c: /* cvttps2pi */
3514 case 0x12c: /* cvttpd2pi */
3515 case 0x02d: /* cvtps2pi */
3516 case 0x12d: /* cvtpd2pi */
3517 gen_helper_enter_mmx();
3519 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3520 op2_offset = offsetof(CPUX86State,xmm_t0);
3521 gen_ldo_env_A0(s->mem_index, op2_offset);
3523 rm = (modrm & 7) | REX_B(s);
3524 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3526 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3527 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3528 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3531 gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
3534 gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
3537 gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
3540 gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
3544 case 0x22c: /* cvttss2si */
3545 case 0x32c: /* cvttsd2si */
3546 case 0x22d: /* cvtss2si */
3547 case 0x32d: /* cvtsd2si */
3548 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3550 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3552 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3554 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3555 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3557 op2_offset = offsetof(CPUX86State,xmm_t0);
3559 rm = (modrm & 7) | REX_B(s);
3560 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3562 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3564 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3565 if (ot == OT_LONG) {
3566 ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
3567 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3569 ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0);
3571 gen_op_mov_reg_T0(ot, reg);
3573 case 0xc4: /* pinsrw */
3576 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3577 val = ldub_code(s->pc++);
3580 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3581 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3584 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3585 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3588 case 0xc5: /* pextrw */
3592 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3593 val = ldub_code(s->pc++);
3596 rm = (modrm & 7) | REX_B(s);
3597 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3598 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3602 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3603 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3605 reg = ((modrm >> 3) & 7) | rex_r;
3606 gen_op_mov_reg_T0(ot, reg);
3608 case 0x1d6: /* movq ea, xmm */
3610 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3611 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3613 rm = (modrm & 7) | REX_B(s);
3614 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3615 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3616 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3619 case 0x2d6: /* movq2dq */
3620 gen_helper_enter_mmx();
3622 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3623 offsetof(CPUX86State,fpregs[rm].mmx));
3624 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3626 case 0x3d6: /* movdq2q */
3627 gen_helper_enter_mmx();
3628 rm = (modrm & 7) | REX_B(s);
3629 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3630 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3632 case 0xd7: /* pmovmskb */
3637 rm = (modrm & 7) | REX_B(s);
3638 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3639 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
3642 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3643 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3645 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3646 reg = ((modrm >> 3) & 7) | rex_r;
3647 gen_op_mov_reg_T0(OT_LONG, reg);
3650 if (s->prefix & PREFIX_REPNZ)
3654 modrm = ldub_code(s->pc++);
3656 reg = ((modrm >> 3) & 7) | rex_r;
3657 mod = (modrm >> 6) & 3;
3659 sse_op2 = sse_op_table6[b].op[b1];
3662 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3666 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3668 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3670 op2_offset = offsetof(CPUX86State,xmm_t0);
3671 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3673 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3674 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3675 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3676 gen_ldq_env_A0(s->mem_index, op2_offset +
3677 offsetof(XMMReg, XMM_Q(0)));
3679 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3680 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3681 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3682 (s->mem_index >> 2) - 1);
3683 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3684 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3685 offsetof(XMMReg, XMM_L(0)));
3687 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3688 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3689 (s->mem_index >> 2) - 1);
3690 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3691 offsetof(XMMReg, XMM_W(0)));
3693 case 0x2a: /* movntqda */
3694 gen_ldo_env_A0(s->mem_index, op1_offset);
3697 gen_ldo_env_A0(s->mem_index, op2_offset);
3701 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3703 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3705 op2_offset = offsetof(CPUX86State,mmx_t0);
3706 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3707 gen_ldq_env_A0(s->mem_index, op2_offset);
3710 if (sse_op2 == SSE_SPECIAL)
3713 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3714 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3715 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3718 s->cc_op = CC_OP_EFLAGS;
3720 case 0x338: /* crc32 */
3723 modrm = ldub_code(s->pc++);
3724 reg = ((modrm >> 3) & 7) | rex_r;
3726 if (b != 0xf0 && b != 0xf1)
3728 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3733 else if (b == 0xf1 && s->dflag != 2)
3734 if (s->prefix & PREFIX_DATA)
3741 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3742 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3743 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3744 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3745 cpu_T[0], tcg_const_i32(8 << ot));
3747 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3748 gen_op_mov_reg_T0(ot, reg);
3753 modrm = ldub_code(s->pc++);
3755 reg = ((modrm >> 3) & 7) | rex_r;
3756 mod = (modrm >> 6) & 3;
3758 sse_op2 = sse_op_table7[b].op[b1];
3761 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3764 if (sse_op2 == SSE_SPECIAL) {
3765 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3766 rm = (modrm & 7) | REX_B(s);
3768 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3769 reg = ((modrm >> 3) & 7) | rex_r;
3770 val = ldub_code(s->pc++);
3772 case 0x14: /* pextrb */
3773 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3774 xmm_regs[reg].XMM_B(val & 15)));
3776 gen_op_mov_reg_T0(ot, rm);
3778 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3779 (s->mem_index >> 2) - 1);
3781 case 0x15: /* pextrw */
3782 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3783 xmm_regs[reg].XMM_W(val & 7)));
3785 gen_op_mov_reg_T0(ot, rm);
3787 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3788 (s->mem_index >> 2) - 1);
3791 if (ot == OT_LONG) { /* pextrd */
3792 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3793 offsetof(CPUX86State,
3794 xmm_regs[reg].XMM_L(val & 3)));
3795 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3797 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3799 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3800 (s->mem_index >> 2) - 1);
3801 } else { /* pextrq */
3802 #ifdef TARGET_X86_64
3803 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3804 offsetof(CPUX86State,
3805 xmm_regs[reg].XMM_Q(val & 1)));
3807 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3809 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3810 (s->mem_index >> 2) - 1);
3816 case 0x17: /* extractps */
3817 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3818 xmm_regs[reg].XMM_L(val & 3)));
3820 gen_op_mov_reg_T0(ot, rm);
3822 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3823 (s->mem_index >> 2) - 1);
3825 case 0x20: /* pinsrb */
3827 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3829 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3830 (s->mem_index >> 2) - 1);
3831 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3832 xmm_regs[reg].XMM_B(val & 15)));
3834 case 0x21: /* insertps */
3836 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3837 offsetof(CPUX86State,xmm_regs[rm]
3838 .XMM_L((val >> 6) & 3)));
3840 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3841 (s->mem_index >> 2) - 1);
3842 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3844 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3845 offsetof(CPUX86State,xmm_regs[reg]
3846 .XMM_L((val >> 4) & 3)));
3848 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3849 cpu_env, offsetof(CPUX86State,
3850 xmm_regs[reg].XMM_L(0)));
3852 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3853 cpu_env, offsetof(CPUX86State,
3854 xmm_regs[reg].XMM_L(1)));
3856 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3857 cpu_env, offsetof(CPUX86State,
3858 xmm_regs[reg].XMM_L(2)));
3860 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3861 cpu_env, offsetof(CPUX86State,
3862 xmm_regs[reg].XMM_L(3)));
3865 if (ot == OT_LONG) { /* pinsrd */
3867 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3869 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3870 (s->mem_index >> 2) - 1);
3871 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3872 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3873 offsetof(CPUX86State,
3874 xmm_regs[reg].XMM_L(val & 3)));
3875 } else { /* pinsrq */
3876 #ifdef TARGET_X86_64
3878 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3880 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3881 (s->mem_index >> 2) - 1);
3882 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3883 offsetof(CPUX86State,
3884 xmm_regs[reg].XMM_Q(val & 1)));
3895 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3897 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3899 op2_offset = offsetof(CPUX86State,xmm_t0);
3900 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3901 gen_ldo_env_A0(s->mem_index, op2_offset);
3904 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3906 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3908 op2_offset = offsetof(CPUX86State,mmx_t0);
3909 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3910 gen_ldq_env_A0(s->mem_index, op2_offset);
3913 val = ldub_code(s->pc++);
3915 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3916 s->cc_op = CC_OP_EFLAGS;
3919 /* The helper must use entire 64-bit gp registers */
3923 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3924 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3925 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3931 /* generic MMX or SSE operation */
3933 case 0x70: /* pshufx insn */
3934 case 0xc6: /* pshufx insn */
3935 case 0xc2: /* compare insns */
3942 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3944 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3945 op2_offset = offsetof(CPUX86State,xmm_t0);
3946 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3948 /* specific case for SSE single instructions */
3951 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3952 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3955 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3958 gen_ldo_env_A0(s->mem_index, op2_offset);
3961 rm = (modrm & 7) | REX_B(s);
3962 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3965 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3967 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3968 op2_offset = offsetof(CPUX86State,mmx_t0);
3969 gen_ldq_env_A0(s->mem_index, op2_offset);
3972 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3976 case 0x0f: /* 3DNow! data insns */
3977 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3979 val = ldub_code(s->pc++);
3980 sse_op2 = sse_op_table5[val];
3983 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3984 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3985 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3987 case 0x70: /* pshufx insn */
3988 case 0xc6: /* pshufx insn */
3989 val = ldub_code(s->pc++);
3990 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3991 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3992 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3996 val = ldub_code(s->pc++);
3999 sse_op2 = sse_op_table4[val][b1];
4000 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4001 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4002 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4005 /* maskmov : we must prepare A0 */
4008 #ifdef TARGET_X86_64
4009 if (s->aflag == 2) {
4010 gen_op_movq_A0_reg(R_EDI);
4014 gen_op_movl_A0_reg(R_EDI);
4016 gen_op_andl_A0_ffff();
4018 gen_add_A0_ds_seg(s);
4020 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4021 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4022 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
4025 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4026 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4027 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4030 if (b == 0x2e || b == 0x2f) {
4031 s->cc_op = CC_OP_EFLAGS;
4036 /* convert one instruction. s->is_jmp is set if the translation must
4037 be stopped. Return the next pc value */
4038 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4040 int b, prefixes, aflag, dflag;
4042 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4043 target_ulong next_eip, tval;
4046 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4047 tcg_gen_debug_insn_start(pc_start);
4055 #ifdef TARGET_X86_64
4060 s->rip_offset = 0; /* for relative ip address */
4062 b = ldub_code(s->pc);
4064 /* check prefixes */
4065 #ifdef TARGET_X86_64
4069 prefixes |= PREFIX_REPZ;
4072 prefixes |= PREFIX_REPNZ;
4075 prefixes |= PREFIX_LOCK;
4096 prefixes |= PREFIX_DATA;
4099 prefixes |= PREFIX_ADR;
4103 rex_w = (b >> 3) & 1;
4104 rex_r = (b & 0x4) << 1;
4105 s->rex_x = (b & 0x2) << 2;
4106 REX_B(s) = (b & 0x1) << 3;
4107 x86_64_hregs = 1; /* select uniform byte register addressing */
4111 /* 0x66 is ignored if rex.w is set */
4114 if (prefixes & PREFIX_DATA)
4117 if (!(prefixes & PREFIX_ADR))
4124 prefixes |= PREFIX_REPZ;
4127 prefixes |= PREFIX_REPNZ;
4130 prefixes |= PREFIX_LOCK;
4151 prefixes |= PREFIX_DATA;
4154 prefixes |= PREFIX_ADR;
4157 if (prefixes & PREFIX_DATA)
4159 if (prefixes & PREFIX_ADR)
4163 s->prefix = prefixes;
4167 /* lock generation */
4168 if (prefixes & PREFIX_LOCK)
4171 /* now check op code */
4175 /**************************/
4176 /* extended op code */
4177 b = ldub_code(s->pc++) | 0x100;
4180 /**************************/
4198 ot = dflag + OT_WORD;
4201 case 0: /* OP Ev, Gv */
4202 modrm = ldub_code(s->pc++);
4203 reg = ((modrm >> 3) & 7) | rex_r;
4204 mod = (modrm >> 6) & 3;
4205 rm = (modrm & 7) | REX_B(s);
4207 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4209 } else if (op == OP_XORL && rm == reg) {
4211 /* xor reg, reg optimisation */
4213 s->cc_op = CC_OP_LOGICB + ot;
4214 gen_op_mov_reg_T0(ot, reg);
4215 gen_op_update1_cc();
4220 gen_op_mov_TN_reg(ot, 1, reg);
4221 gen_op(s, op, ot, opreg);
4223 case 1: /* OP Gv, Ev */
4224 modrm = ldub_code(s->pc++);
4225 mod = (modrm >> 6) & 3;
4226 reg = ((modrm >> 3) & 7) | rex_r;
4227 rm = (modrm & 7) | REX_B(s);
4229 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4230 gen_op_ld_T1_A0(ot + s->mem_index);
4231 } else if (op == OP_XORL && rm == reg) {
4234 gen_op_mov_TN_reg(ot, 1, rm);
4236 gen_op(s, op, ot, reg);
4238 case 2: /* OP A, Iv */
4239 val = insn_get(s, ot);
4240 gen_op_movl_T1_im(val);
4241 gen_op(s, op, ot, OR_EAX);
4250 case 0x80: /* GRP1 */
4259 ot = dflag + OT_WORD;
4261 modrm = ldub_code(s->pc++);
4262 mod = (modrm >> 6) & 3;
4263 rm = (modrm & 7) | REX_B(s);
4264 op = (modrm >> 3) & 7;
4270 s->rip_offset = insn_const_size(ot);
4271 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4282 val = insn_get(s, ot);
4285 val = (int8_t)insn_get(s, OT_BYTE);
4288 gen_op_movl_T1_im(val);
4289 gen_op(s, op, ot, opreg);
4293 /**************************/
4294 /* inc, dec, and other misc arith */
4295 case 0x40 ... 0x47: /* inc Gv */
4296 ot = dflag ? OT_LONG : OT_WORD;
4297 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4299 case 0x48 ... 0x4f: /* dec Gv */
4300 ot = dflag ? OT_LONG : OT_WORD;
4301 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4303 case 0xf6: /* GRP3 */
4308 ot = dflag + OT_WORD;
4310 modrm = ldub_code(s->pc++);
4311 mod = (modrm >> 6) & 3;
4312 rm = (modrm & 7) | REX_B(s);
4313 op = (modrm >> 3) & 7;
4316 s->rip_offset = insn_const_size(ot);
4317 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4318 gen_op_ld_T0_A0(ot + s->mem_index);
4320 gen_op_mov_TN_reg(ot, 0, rm);
4325 val = insn_get(s, ot);
4326 gen_op_movl_T1_im(val);
4327 gen_op_testl_T0_T1_cc();
4328 s->cc_op = CC_OP_LOGICB + ot;
4331 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4333 gen_op_st_T0_A0(ot + s->mem_index);
4335 gen_op_mov_reg_T0(ot, rm);
4339 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4341 gen_op_st_T0_A0(ot + s->mem_index);
4343 gen_op_mov_reg_T0(ot, rm);
4345 gen_op_update_neg_cc();
4346 s->cc_op = CC_OP_SUBB + ot;
4351 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4352 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4353 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4354 /* XXX: use 32 bit mul which could be faster */
4355 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4356 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4357 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4358 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4359 s->cc_op = CC_OP_MULB;
4362 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4363 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4364 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4365 /* XXX: use 32 bit mul which could be faster */
4366 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4367 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4368 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4369 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4370 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4371 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4372 s->cc_op = CC_OP_MULW;
4376 #ifdef TARGET_X86_64
4377 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4378 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4379 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4380 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4381 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4382 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4383 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4384 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4385 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4389 t0 = tcg_temp_new_i64();
4390 t1 = tcg_temp_new_i64();
4391 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4392 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4393 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4394 tcg_gen_mul_i64(t0, t0, t1);
4395 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4396 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4397 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4398 tcg_gen_shri_i64(t0, t0, 32);
4399 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4400 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4401 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4404 s->cc_op = CC_OP_MULL;
4406 #ifdef TARGET_X86_64
4408 gen_helper_mulq_EAX_T0(cpu_T[0]);
4409 s->cc_op = CC_OP_MULQ;
4417 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4418 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4419 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4420 /* XXX: use 32 bit mul which could be faster */
4421 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4422 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4423 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4424 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4425 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4426 s->cc_op = CC_OP_MULB;
4429 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4430 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4431 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4432 /* XXX: use 32 bit mul which could be faster */
4433 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4434 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4435 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4436 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4437 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4438 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4439 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4440 s->cc_op = CC_OP_MULW;
4444 #ifdef TARGET_X86_64
4445 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4446 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4447 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4448 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4449 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4450 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4451 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4452 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4453 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4454 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4458 t0 = tcg_temp_new_i64();
4459 t1 = tcg_temp_new_i64();
4460 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4461 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4462 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4463 tcg_gen_mul_i64(t0, t0, t1);
4464 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4465 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4466 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4467 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4468 tcg_gen_shri_i64(t0, t0, 32);
4469 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4470 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4471 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4474 s->cc_op = CC_OP_MULL;
4476 #ifdef TARGET_X86_64
4478 gen_helper_imulq_EAX_T0(cpu_T[0]);
4479 s->cc_op = CC_OP_MULQ;
4487 gen_jmp_im(pc_start - s->cs_base);
4488 gen_helper_divb_AL(cpu_T[0]);
4491 gen_jmp_im(pc_start - s->cs_base);
4492 gen_helper_divw_AX(cpu_T[0]);
4496 gen_jmp_im(pc_start - s->cs_base);
4497 gen_helper_divl_EAX(cpu_T[0]);
4499 #ifdef TARGET_X86_64
4501 gen_jmp_im(pc_start - s->cs_base);
4502 gen_helper_divq_EAX(cpu_T[0]);
4510 gen_jmp_im(pc_start - s->cs_base);
4511 gen_helper_idivb_AL(cpu_T[0]);
4514 gen_jmp_im(pc_start - s->cs_base);
4515 gen_helper_idivw_AX(cpu_T[0]);
4519 gen_jmp_im(pc_start - s->cs_base);
4520 gen_helper_idivl_EAX(cpu_T[0]);
4522 #ifdef TARGET_X86_64
4524 gen_jmp_im(pc_start - s->cs_base);
4525 gen_helper_idivq_EAX(cpu_T[0]);
4535 case 0xfe: /* GRP4 */
4536 case 0xff: /* GRP5 */
4540 ot = dflag + OT_WORD;
4542 modrm = ldub_code(s->pc++);
4543 mod = (modrm >> 6) & 3;
4544 rm = (modrm & 7) | REX_B(s);
4545 op = (modrm >> 3) & 7;
4546 if (op >= 2 && b == 0xfe) {
4550 if (op == 2 || op == 4) {
4551 /* operand size for jumps is 64 bit */
4553 } else if (op == 3 || op == 5) {
4554 /* for call calls, the operand is 16 or 32 bit, even
4556 ot = dflag ? OT_LONG : OT_WORD;
4557 } else if (op == 6) {
4558 /* default push size is 64 bit */
4559 ot = dflag ? OT_QUAD : OT_WORD;
4563 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4564 if (op >= 2 && op != 3 && op != 5)
4565 gen_op_ld_T0_A0(ot + s->mem_index);
4567 gen_op_mov_TN_reg(ot, 0, rm);
4571 case 0: /* inc Ev */
4576 gen_inc(s, ot, opreg, 1);
4578 case 1: /* dec Ev */
4583 gen_inc(s, ot, opreg, -1);
4585 case 2: /* call Ev */
4586 /* XXX: optimize if memory (no 'and' is necessary) */
4588 gen_op_andl_T0_ffff();
4589 next_eip = s->pc - s->cs_base;
4590 gen_movtl_T1_im(next_eip);
4595 case 3: /* lcall Ev */
4596 gen_op_ld_T1_A0(ot + s->mem_index);
4597 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4598 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4600 if (s->pe && !s->vm86) {
4601 if (s->cc_op != CC_OP_DYNAMIC)
4602 gen_op_set_cc_op(s->cc_op);
4603 gen_jmp_im(pc_start - s->cs_base);
4604 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4605 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4606 tcg_const_i32(dflag),
4607 tcg_const_i32(s->pc - pc_start));
4609 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4610 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4611 tcg_const_i32(dflag),
4612 tcg_const_i32(s->pc - s->cs_base));
4616 case 4: /* jmp Ev */
4618 gen_op_andl_T0_ffff();
4622 case 5: /* ljmp Ev */
4623 gen_op_ld_T1_A0(ot + s->mem_index);
4624 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4625 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4627 if (s->pe && !s->vm86) {
4628 if (s->cc_op != CC_OP_DYNAMIC)
4629 gen_op_set_cc_op(s->cc_op);
4630 gen_jmp_im(pc_start - s->cs_base);
4631 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4632 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4633 tcg_const_i32(s->pc - pc_start));
4635 gen_op_movl_seg_T0_vm(R_CS);
4636 gen_op_movl_T0_T1();
4641 case 6: /* push Ev */
4649 case 0x84: /* test Ev, Gv */
4654 ot = dflag + OT_WORD;
4656 modrm = ldub_code(s->pc++);
4657 mod = (modrm >> 6) & 3;
4658 rm = (modrm & 7) | REX_B(s);
4659 reg = ((modrm >> 3) & 7) | rex_r;
4661 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4662 gen_op_mov_TN_reg(ot, 1, reg);
4663 gen_op_testl_T0_T1_cc();
4664 s->cc_op = CC_OP_LOGICB + ot;
4667 case 0xa8: /* test eAX, Iv */
4672 ot = dflag + OT_WORD;
4673 val = insn_get(s, ot);
4675 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4676 gen_op_movl_T1_im(val);
4677 gen_op_testl_T0_T1_cc();
4678 s->cc_op = CC_OP_LOGICB + ot;
4681 case 0x98: /* CWDE/CBW */
4682 #ifdef TARGET_X86_64
4684 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4685 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4686 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4690 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4691 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4692 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4694 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4695 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4696 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4699 case 0x99: /* CDQ/CWD */
4700 #ifdef TARGET_X86_64
4702 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4703 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4704 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4708 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4709 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4710 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4711 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4713 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4714 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4715 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4716 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4719 case 0x1af: /* imul Gv, Ev */
4720 case 0x69: /* imul Gv, Ev, I */
4722 ot = dflag + OT_WORD;
4723 modrm = ldub_code(s->pc++);
4724 reg = ((modrm >> 3) & 7) | rex_r;
4726 s->rip_offset = insn_const_size(ot);
4729 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4731 val = insn_get(s, ot);
4732 gen_op_movl_T1_im(val);
4733 } else if (b == 0x6b) {
4734 val = (int8_t)insn_get(s, OT_BYTE);
4735 gen_op_movl_T1_im(val);
4737 gen_op_mov_TN_reg(ot, 1, reg);
4740 #ifdef TARGET_X86_64
4741 if (ot == OT_QUAD) {
4742 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4745 if (ot == OT_LONG) {
4746 #ifdef TARGET_X86_64
4747 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4748 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4749 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4750 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4751 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4752 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4756 t0 = tcg_temp_new_i64();
4757 t1 = tcg_temp_new_i64();
4758 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4759 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4760 tcg_gen_mul_i64(t0, t0, t1);
4761 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4762 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4763 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4764 tcg_gen_shri_i64(t0, t0, 32);
4765 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4766 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4770 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4771 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4772 /* XXX: use 32 bit mul which could be faster */
4773 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4774 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4775 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4776 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4778 gen_op_mov_reg_T0(ot, reg);
4779 s->cc_op = CC_OP_MULB + ot;
4782 case 0x1c1: /* xadd Ev, Gv */
4786 ot = dflag + OT_WORD;
4787 modrm = ldub_code(s->pc++);
4788 reg = ((modrm >> 3) & 7) | rex_r;
4789 mod = (modrm >> 6) & 3;
4791 rm = (modrm & 7) | REX_B(s);
4792 gen_op_mov_TN_reg(ot, 0, reg);
4793 gen_op_mov_TN_reg(ot, 1, rm);
4794 gen_op_addl_T0_T1();
4795 gen_op_mov_reg_T1(ot, reg);
4796 gen_op_mov_reg_T0(ot, rm);
4798 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4799 gen_op_mov_TN_reg(ot, 0, reg);
4800 gen_op_ld_T1_A0(ot + s->mem_index);
4801 gen_op_addl_T0_T1();
4802 gen_op_st_T0_A0(ot + s->mem_index);
4803 gen_op_mov_reg_T1(ot, reg);
4805 gen_op_update2_cc();
4806 s->cc_op = CC_OP_ADDB + ot;
4809 case 0x1b1: /* cmpxchg Ev, Gv */
4812 TCGv t0, t1, t2, a0;
4817 ot = dflag + OT_WORD;
4818 modrm = ldub_code(s->pc++);
4819 reg = ((modrm >> 3) & 7) | rex_r;
4820 mod = (modrm >> 6) & 3;
4821 t0 = tcg_temp_local_new();
4822 t1 = tcg_temp_local_new();
4823 t2 = tcg_temp_local_new();
4824 a0 = tcg_temp_local_new();
4825 gen_op_mov_v_reg(ot, t1, reg);
4827 rm = (modrm & 7) | REX_B(s);
4828 gen_op_mov_v_reg(ot, t0, rm);
4830 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4831 tcg_gen_mov_tl(a0, cpu_A0);
4832 gen_op_ld_v(ot + s->mem_index, t0, a0);
4833 rm = 0; /* avoid warning */
4835 label1 = gen_new_label();
4836 tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX]));
4837 tcg_gen_sub_tl(t2, t2, t0);
4839 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4841 label2 = gen_new_label();
4842 gen_op_mov_reg_v(ot, R_EAX, t0);
4844 gen_set_label(label1);
4845 gen_op_mov_reg_v(ot, rm, t1);
4846 gen_set_label(label2);
4848 tcg_gen_mov_tl(t1, t0);
4849 gen_op_mov_reg_v(ot, R_EAX, t0);
4850 gen_set_label(label1);
4852 gen_op_st_v(ot + s->mem_index, t1, a0);
4854 tcg_gen_mov_tl(cpu_cc_src, t0);
4855 tcg_gen_mov_tl(cpu_cc_dst, t2);
4856 s->cc_op = CC_OP_SUBB + ot;
4863 case 0x1c7: /* cmpxchg8b */
4864 modrm = ldub_code(s->pc++);
4865 mod = (modrm >> 6) & 3;
4866 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4868 #ifdef TARGET_X86_64
4870 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4872 gen_jmp_im(pc_start - s->cs_base);
4873 if (s->cc_op != CC_OP_DYNAMIC)
4874 gen_op_set_cc_op(s->cc_op);
4875 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4876 gen_helper_cmpxchg16b(cpu_A0);
4880 if (!(s->cpuid_features & CPUID_CX8))
4882 gen_jmp_im(pc_start - s->cs_base);
4883 if (s->cc_op != CC_OP_DYNAMIC)
4884 gen_op_set_cc_op(s->cc_op);
4885 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4886 gen_helper_cmpxchg8b(cpu_A0);
4888 s->cc_op = CC_OP_EFLAGS;
4891 /**************************/
4893 case 0x50 ... 0x57: /* push */
4894 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4897 case 0x58 ... 0x5f: /* pop */
4899 ot = dflag ? OT_QUAD : OT_WORD;
4901 ot = dflag + OT_WORD;
4904 /* NOTE: order is important for pop %sp */
4906 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4908 case 0x60: /* pusha */
4913 case 0x61: /* popa */
4918 case 0x68: /* push Iv */
4921 ot = dflag ? OT_QUAD : OT_WORD;
4923 ot = dflag + OT_WORD;
4926 val = insn_get(s, ot);
4928 val = (int8_t)insn_get(s, OT_BYTE);
4929 gen_op_movl_T0_im(val);
4932 case 0x8f: /* pop Ev */
4934 ot = dflag ? OT_QUAD : OT_WORD;
4936 ot = dflag + OT_WORD;
4938 modrm = ldub_code(s->pc++);
4939 mod = (modrm >> 6) & 3;
4942 /* NOTE: order is important for pop %sp */
4944 rm = (modrm & 7) | REX_B(s);
4945 gen_op_mov_reg_T0(ot, rm);
4947 /* NOTE: order is important too for MMU exceptions */
4948 s->popl_esp_hack = 1 << ot;
4949 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4950 s->popl_esp_hack = 0;
4954 case 0xc8: /* enter */
4957 val = lduw_code(s->pc);
4959 level = ldub_code(s->pc++);
4960 gen_enter(s, val, level);
4963 case 0xc9: /* leave */
4964 /* XXX: exception not precise (ESP is updated before potential exception) */
4966 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4967 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
4968 } else if (s->ss32) {
4969 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4970 gen_op_mov_reg_T0(OT_LONG, R_ESP);
4972 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4973 gen_op_mov_reg_T0(OT_WORD, R_ESP);
4977 ot = dflag ? OT_QUAD : OT_WORD;
4979 ot = dflag + OT_WORD;
4981 gen_op_mov_reg_T0(ot, R_EBP);
4984 case 0x06: /* push es */
4985 case 0x0e: /* push cs */
4986 case 0x16: /* push ss */
4987 case 0x1e: /* push ds */
4990 gen_op_movl_T0_seg(b >> 3);
4993 case 0x1a0: /* push fs */
4994 case 0x1a8: /* push gs */
4995 gen_op_movl_T0_seg((b >> 3) & 7);
4998 case 0x07: /* pop es */
4999 case 0x17: /* pop ss */
5000 case 0x1f: /* pop ds */
5005 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5008 /* if reg == SS, inhibit interrupts/trace. */
5009 /* If several instructions disable interrupts, only the
5011 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5012 gen_helper_set_inhibit_irq();
5016 gen_jmp_im(s->pc - s->cs_base);
5020 case 0x1a1: /* pop fs */
5021 case 0x1a9: /* pop gs */
5023 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5026 gen_jmp_im(s->pc - s->cs_base);
5031 /**************************/
5034 case 0x89: /* mov Gv, Ev */
5038 ot = dflag + OT_WORD;
5039 modrm = ldub_code(s->pc++);
5040 reg = ((modrm >> 3) & 7) | rex_r;
5042 /* generate a generic store */
5043 gen_ldst_modrm(s, modrm, ot, reg, 1);
5046 case 0xc7: /* mov Ev, Iv */
5050 ot = dflag + OT_WORD;
5051 modrm = ldub_code(s->pc++);
5052 mod = (modrm >> 6) & 3;
5054 s->rip_offset = insn_const_size(ot);
5055 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5057 val = insn_get(s, ot);
5058 gen_op_movl_T0_im(val);
5060 gen_op_st_T0_A0(ot + s->mem_index);
5062 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5065 case 0x8b: /* mov Ev, Gv */
5069 ot = OT_WORD + dflag;
5070 modrm = ldub_code(s->pc++);
5071 reg = ((modrm >> 3) & 7) | rex_r;
5073 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5074 gen_op_mov_reg_T0(ot, reg);
5076 case 0x8e: /* mov seg, Gv */
5077 modrm = ldub_code(s->pc++);
5078 reg = (modrm >> 3) & 7;
5079 if (reg >= 6 || reg == R_CS)
5081 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5082 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5084 /* if reg == SS, inhibit interrupts/trace */
5085 /* If several instructions disable interrupts, only the
5087 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5088 gen_helper_set_inhibit_irq();
5092 gen_jmp_im(s->pc - s->cs_base);
5096 case 0x8c: /* mov Gv, seg */
5097 modrm = ldub_code(s->pc++);
5098 reg = (modrm >> 3) & 7;
5099 mod = (modrm >> 6) & 3;
5102 gen_op_movl_T0_seg(reg);
5104 ot = OT_WORD + dflag;
5107 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5110 case 0x1b6: /* movzbS Gv, Eb */
5111 case 0x1b7: /* movzwS Gv, Eb */
5112 case 0x1be: /* movsbS Gv, Eb */
5113 case 0x1bf: /* movswS Gv, Eb */
5116 /* d_ot is the size of destination */
5117 d_ot = dflag + OT_WORD;
5118 /* ot is the size of source */
5119 ot = (b & 1) + OT_BYTE;
5120 modrm = ldub_code(s->pc++);
5121 reg = ((modrm >> 3) & 7) | rex_r;
5122 mod = (modrm >> 6) & 3;
5123 rm = (modrm & 7) | REX_B(s);
5126 gen_op_mov_TN_reg(ot, 0, rm);
5127 switch(ot | (b & 8)) {
5129 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5132 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5135 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5139 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5142 gen_op_mov_reg_T0(d_ot, reg);
5144 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5146 gen_op_lds_T0_A0(ot + s->mem_index);
5148 gen_op_ldu_T0_A0(ot + s->mem_index);
5150 gen_op_mov_reg_T0(d_ot, reg);
5155 case 0x8d: /* lea */
5156 ot = dflag + OT_WORD;
5157 modrm = ldub_code(s->pc++);
5158 mod = (modrm >> 6) & 3;
5161 reg = ((modrm >> 3) & 7) | rex_r;
5162 /* we must ensure that no segment is added */
5166 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5168 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5171 case 0xa0: /* mov EAX, Ov */
5173 case 0xa2: /* mov Ov, EAX */
5176 target_ulong offset_addr;
5181 ot = dflag + OT_WORD;
5182 #ifdef TARGET_X86_64
5183 if (s->aflag == 2) {
5184 offset_addr = ldq_code(s->pc);
5186 gen_op_movq_A0_im(offset_addr);
5191 offset_addr = insn_get(s, OT_LONG);
5193 offset_addr = insn_get(s, OT_WORD);
5195 gen_op_movl_A0_im(offset_addr);
5197 gen_add_A0_ds_seg(s);
5199 gen_op_ld_T0_A0(ot + s->mem_index);
5200 gen_op_mov_reg_T0(ot, R_EAX);
5202 gen_op_mov_TN_reg(ot, 0, R_EAX);
5203 gen_op_st_T0_A0(ot + s->mem_index);
5207 case 0xd7: /* xlat */
5208 #ifdef TARGET_X86_64
5209 if (s->aflag == 2) {
5210 gen_op_movq_A0_reg(R_EBX);
5211 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5212 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5213 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5217 gen_op_movl_A0_reg(R_EBX);
5218 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5219 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5220 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5222 gen_op_andl_A0_ffff();
5224 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5226 gen_add_A0_ds_seg(s);
5227 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5228 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5230 case 0xb0 ... 0xb7: /* mov R, Ib */
5231 val = insn_get(s, OT_BYTE);
5232 gen_op_movl_T0_im(val);
5233 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5235 case 0xb8 ... 0xbf: /* mov R, Iv */
5236 #ifdef TARGET_X86_64
5240 tmp = ldq_code(s->pc);
5242 reg = (b & 7) | REX_B(s);
5243 gen_movtl_T0_im(tmp);
5244 gen_op_mov_reg_T0(OT_QUAD, reg);
5248 ot = dflag ? OT_LONG : OT_WORD;
5249 val = insn_get(s, ot);
5250 reg = (b & 7) | REX_B(s);
5251 gen_op_movl_T0_im(val);
5252 gen_op_mov_reg_T0(ot, reg);
5256 case 0x91 ... 0x97: /* xchg R, EAX */
5257 ot = dflag + OT_WORD;
5258 reg = (b & 7) | REX_B(s);
5262 case 0x87: /* xchg Ev, Gv */
5266 ot = dflag + OT_WORD;
5267 modrm = ldub_code(s->pc++);
5268 reg = ((modrm >> 3) & 7) | rex_r;
5269 mod = (modrm >> 6) & 3;
5271 rm = (modrm & 7) | REX_B(s);
5273 gen_op_mov_TN_reg(ot, 0, reg);
5274 gen_op_mov_TN_reg(ot, 1, rm);
5275 gen_op_mov_reg_T0(ot, rm);
5276 gen_op_mov_reg_T1(ot, reg);
5278 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5279 gen_op_mov_TN_reg(ot, 0, reg);
5280 /* for xchg, lock is implicit */
5281 if (!(prefixes & PREFIX_LOCK))
5283 gen_op_ld_T1_A0(ot + s->mem_index);
5284 gen_op_st_T0_A0(ot + s->mem_index);
5285 if (!(prefixes & PREFIX_LOCK))
5286 gen_helper_unlock();
5287 gen_op_mov_reg_T1(ot, reg);
5290 case 0xc4: /* les Gv */
5295 case 0xc5: /* lds Gv */
5300 case 0x1b2: /* lss Gv */
5303 case 0x1b4: /* lfs Gv */
5306 case 0x1b5: /* lgs Gv */
5309 ot = dflag ? OT_LONG : OT_WORD;
5310 modrm = ldub_code(s->pc++);
5311 reg = ((modrm >> 3) & 7) | rex_r;
5312 mod = (modrm >> 6) & 3;
5315 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5316 gen_op_ld_T1_A0(ot + s->mem_index);
5317 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5318 /* load the segment first to handle exceptions properly */
5319 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5320 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5321 /* then put the data */
5322 gen_op_mov_reg_T1(ot, reg);
5324 gen_jmp_im(s->pc - s->cs_base);
5329 /************************/
5340 ot = dflag + OT_WORD;
5342 modrm = ldub_code(s->pc++);
5343 mod = (modrm >> 6) & 3;
5344 op = (modrm >> 3) & 7;
5350 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5353 opreg = (modrm & 7) | REX_B(s);
5358 gen_shift(s, op, ot, opreg, OR_ECX);
5361 shift = ldub_code(s->pc++);
5363 gen_shifti(s, op, ot, opreg, shift);
5378 case 0x1a4: /* shld imm */
5382 case 0x1a5: /* shld cl */
5386 case 0x1ac: /* shrd imm */
5390 case 0x1ad: /* shrd cl */
5394 ot = dflag + OT_WORD;
5395 modrm = ldub_code(s->pc++);
5396 mod = (modrm >> 6) & 3;
5397 rm = (modrm & 7) | REX_B(s);
5398 reg = ((modrm >> 3) & 7) | rex_r;
5400 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5405 gen_op_mov_TN_reg(ot, 1, reg);
5408 val = ldub_code(s->pc++);
5409 tcg_gen_movi_tl(cpu_T3, val);
5411 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
5413 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5416 /************************/
5419 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5420 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5421 /* XXX: what to do if illegal op ? */
5422 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5425 modrm = ldub_code(s->pc++);
5426 mod = (modrm >> 6) & 3;
5428 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5431 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5433 case 0x00 ... 0x07: /* fxxxs */
5434 case 0x10 ... 0x17: /* fixxxl */
5435 case 0x20 ... 0x27: /* fxxxl */
5436 case 0x30 ... 0x37: /* fixxx */
5443 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5444 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5445 gen_helper_flds_FT0(cpu_tmp2_i32);
5448 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5449 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5450 gen_helper_fildl_FT0(cpu_tmp2_i32);
5453 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5454 (s->mem_index >> 2) - 1);
5455 gen_helper_fldl_FT0(cpu_tmp1_i64);
5459 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5460 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5461 gen_helper_fildl_FT0(cpu_tmp2_i32);
5465 gen_helper_fp_arith_ST0_FT0(op1);
5467 /* fcomp needs pop */
5472 case 0x08: /* flds */
5473 case 0x0a: /* fsts */
5474 case 0x0b: /* fstps */
5475 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5476 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5477 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5482 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5483 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5484 gen_helper_flds_ST0(cpu_tmp2_i32);
5487 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5488 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5489 gen_helper_fildl_ST0(cpu_tmp2_i32);
5492 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5493 (s->mem_index >> 2) - 1);
5494 gen_helper_fldl_ST0(cpu_tmp1_i64);
5498 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5499 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5500 gen_helper_fildl_ST0(cpu_tmp2_i32);
5505 /* XXX: the corresponding CPUID bit must be tested ! */
5508 gen_helper_fisttl_ST0(cpu_tmp2_i32);
5509 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5510 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5513 gen_helper_fisttll_ST0(cpu_tmp1_i64);
5514 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5515 (s->mem_index >> 2) - 1);
5519 gen_helper_fistt_ST0(cpu_tmp2_i32);
5520 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5521 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5529 gen_helper_fsts_ST0(cpu_tmp2_i32);
5530 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5531 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5534 gen_helper_fistl_ST0(cpu_tmp2_i32);
5535 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5536 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5539 gen_helper_fstl_ST0(cpu_tmp1_i64);
5540 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5541 (s->mem_index >> 2) - 1);
5545 gen_helper_fist_ST0(cpu_tmp2_i32);
5546 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5547 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5555 case 0x0c: /* fldenv mem */
5556 if (s->cc_op != CC_OP_DYNAMIC)
5557 gen_op_set_cc_op(s->cc_op);
5558 gen_jmp_im(pc_start - s->cs_base);
5560 cpu_A0, tcg_const_i32(s->dflag));
5562 case 0x0d: /* fldcw mem */
5563 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5564 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5565 gen_helper_fldcw(cpu_tmp2_i32);
5567 case 0x0e: /* fnstenv mem */
5568 if (s->cc_op != CC_OP_DYNAMIC)
5569 gen_op_set_cc_op(s->cc_op);
5570 gen_jmp_im(pc_start - s->cs_base);
5571 gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
5573 case 0x0f: /* fnstcw mem */
5574 gen_helper_fnstcw(cpu_tmp2_i32);
5575 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5576 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5578 case 0x1d: /* fldt mem */
5579 if (s->cc_op != CC_OP_DYNAMIC)
5580 gen_op_set_cc_op(s->cc_op);
5581 gen_jmp_im(pc_start - s->cs_base);
5582 gen_helper_fldt_ST0(cpu_A0);
5584 case 0x1f: /* fstpt mem */
5585 if (s->cc_op != CC_OP_DYNAMIC)
5586 gen_op_set_cc_op(s->cc_op);
5587 gen_jmp_im(pc_start - s->cs_base);
5588 gen_helper_fstt_ST0(cpu_A0);
5591 case 0x2c: /* frstor mem */
5592 if (s->cc_op != CC_OP_DYNAMIC)
5593 gen_op_set_cc_op(s->cc_op);
5594 gen_jmp_im(pc_start - s->cs_base);
5595 gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
5597 case 0x2e: /* fnsave mem */
5598 if (s->cc_op != CC_OP_DYNAMIC)
5599 gen_op_set_cc_op(s->cc_op);
5600 gen_jmp_im(pc_start - s->cs_base);
5601 gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
5603 case 0x2f: /* fnstsw mem */
5604 gen_helper_fnstsw(cpu_tmp2_i32);
5605 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5606 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5608 case 0x3c: /* fbld */
5609 if (s->cc_op != CC_OP_DYNAMIC)
5610 gen_op_set_cc_op(s->cc_op);
5611 gen_jmp_im(pc_start - s->cs_base);
5612 gen_helper_fbld_ST0(cpu_A0);
5614 case 0x3e: /* fbstp */
5615 if (s->cc_op != CC_OP_DYNAMIC)
5616 gen_op_set_cc_op(s->cc_op);
5617 gen_jmp_im(pc_start - s->cs_base);
5618 gen_helper_fbst_ST0(cpu_A0);
5621 case 0x3d: /* fildll */
5622 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5623 (s->mem_index >> 2) - 1);
5624 gen_helper_fildll_ST0(cpu_tmp1_i64);
5626 case 0x3f: /* fistpll */
5627 gen_helper_fistll_ST0(cpu_tmp1_i64);
5628 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5629 (s->mem_index >> 2) - 1);
5636 /* register float ops */
5640 case 0x08: /* fld sti */
5642 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
5644 case 0x09: /* fxchg sti */
5645 case 0x29: /* fxchg4 sti, undocumented op */
5646 case 0x39: /* fxchg7 sti, undocumented op */
5647 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
5649 case 0x0a: /* grp d9/2 */
5652 /* check exceptions (FreeBSD FPU probe) */
5653 if (s->cc_op != CC_OP_DYNAMIC)
5654 gen_op_set_cc_op(s->cc_op);
5655 gen_jmp_im(pc_start - s->cs_base);
5662 case 0x0c: /* grp d9/4 */
5665 gen_helper_fchs_ST0();
5668 gen_helper_fabs_ST0();
5671 gen_helper_fldz_FT0();
5672 gen_helper_fcom_ST0_FT0();
5675 gen_helper_fxam_ST0();
5681 case 0x0d: /* grp d9/5 */
5686 gen_helper_fld1_ST0();
5690 gen_helper_fldl2t_ST0();
5694 gen_helper_fldl2e_ST0();
5698 gen_helper_fldpi_ST0();
5702 gen_helper_fldlg2_ST0();
5706 gen_helper_fldln2_ST0();
5710 gen_helper_fldz_ST0();
5717 case 0x0e: /* grp d9/6 */
5728 case 3: /* fpatan */
5729 gen_helper_fpatan();
5731 case 4: /* fxtract */
5732 gen_helper_fxtract();
5734 case 5: /* fprem1 */
5735 gen_helper_fprem1();
5737 case 6: /* fdecstp */
5738 gen_helper_fdecstp();
5741 case 7: /* fincstp */
5742 gen_helper_fincstp();
5746 case 0x0f: /* grp d9/7 */
5751 case 1: /* fyl2xp1 */
5752 gen_helper_fyl2xp1();
5757 case 3: /* fsincos */
5758 gen_helper_fsincos();
5760 case 5: /* fscale */
5761 gen_helper_fscale();
5763 case 4: /* frndint */
5764 gen_helper_frndint();
5775 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5776 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5777 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5783 gen_helper_fp_arith_STN_ST0(op1, opreg);
5787 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5788 gen_helper_fp_arith_ST0_FT0(op1);
5792 case 0x02: /* fcom */
5793 case 0x22: /* fcom2, undocumented op */
5794 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5795 gen_helper_fcom_ST0_FT0();
5797 case 0x03: /* fcomp */
5798 case 0x23: /* fcomp3, undocumented op */
5799 case 0x32: /* fcomp5, undocumented op */
5800 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5801 gen_helper_fcom_ST0_FT0();
5804 case 0x15: /* da/5 */
5806 case 1: /* fucompp */
5807 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5808 gen_helper_fucom_ST0_FT0();
5818 case 0: /* feni (287 only, just do nop here) */
5820 case 1: /* fdisi (287 only, just do nop here) */
5825 case 3: /* fninit */
5826 gen_helper_fninit();
5828 case 4: /* fsetpm (287 only, just do nop here) */
5834 case 0x1d: /* fucomi */
5835 if (s->cc_op != CC_OP_DYNAMIC)
5836 gen_op_set_cc_op(s->cc_op);
5837 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5838 gen_helper_fucomi_ST0_FT0();
5839 s->cc_op = CC_OP_EFLAGS;
5841 case 0x1e: /* fcomi */
5842 if (s->cc_op != CC_OP_DYNAMIC)
5843 gen_op_set_cc_op(s->cc_op);
5844 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5845 gen_helper_fcomi_ST0_FT0();
5846 s->cc_op = CC_OP_EFLAGS;
5848 case 0x28: /* ffree sti */
5849 gen_helper_ffree_STN(tcg_const_i32(opreg));
5851 case 0x2a: /* fst sti */
5852 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5854 case 0x2b: /* fstp sti */
5855 case 0x0b: /* fstp1 sti, undocumented op */
5856 case 0x3a: /* fstp8 sti, undocumented op */
5857 case 0x3b: /* fstp9 sti, undocumented op */
5858 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5861 case 0x2c: /* fucom st(i) */
5862 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5863 gen_helper_fucom_ST0_FT0();
5865 case 0x2d: /* fucomp st(i) */
5866 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5867 gen_helper_fucom_ST0_FT0();
5870 case 0x33: /* de/3 */
5872 case 1: /* fcompp */
5873 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5874 gen_helper_fcom_ST0_FT0();
5882 case 0x38: /* ffreep sti, undocumented op */
5883 gen_helper_ffree_STN(tcg_const_i32(opreg));
5886 case 0x3c: /* df/4 */
5889 gen_helper_fnstsw(cpu_tmp2_i32);
5890 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5891 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5897 case 0x3d: /* fucomip */
5898 if (s->cc_op != CC_OP_DYNAMIC)
5899 gen_op_set_cc_op(s->cc_op);
5900 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5901 gen_helper_fucomi_ST0_FT0();
5903 s->cc_op = CC_OP_EFLAGS;
5905 case 0x3e: /* fcomip */
5906 if (s->cc_op != CC_OP_DYNAMIC)
5907 gen_op_set_cc_op(s->cc_op);
5908 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5909 gen_helper_fcomi_ST0_FT0();
5911 s->cc_op = CC_OP_EFLAGS;
5913 case 0x10 ... 0x13: /* fcmovxx */
5917 static const uint8_t fcmov_cc[8] = {
5923 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5924 l1 = gen_new_label();
5925 gen_jcc1(s, s->cc_op, op1, l1);
5926 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
5935 /************************/
5938 case 0xa4: /* movsS */
5943 ot = dflag + OT_WORD;
5945 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5946 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5952 case 0xaa: /* stosS */
5957 ot = dflag + OT_WORD;
5959 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5960 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5965 case 0xac: /* lodsS */
5970 ot = dflag + OT_WORD;
5971 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5972 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5977 case 0xae: /* scasS */
5982 ot = dflag + OT_WORD;
5983 if (prefixes & PREFIX_REPNZ) {
5984 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5985 } else if (prefixes & PREFIX_REPZ) {
5986 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5989 s->cc_op = CC_OP_SUBB + ot;
5993 case 0xa6: /* cmpsS */
5998 ot = dflag + OT_WORD;
5999 if (prefixes & PREFIX_REPNZ) {
6000 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6001 } else if (prefixes & PREFIX_REPZ) {
6002 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6005 s->cc_op = CC_OP_SUBB + ot;
6008 case 0x6c: /* insS */
6013 ot = dflag ? OT_LONG : OT_WORD;
6014 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6015 gen_op_andl_T0_ffff();
6016 gen_check_io(s, ot, pc_start - s->cs_base,
6017 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6018 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6019 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6023 gen_jmp(s, s->pc - s->cs_base);
6027 case 0x6e: /* outsS */
6032 ot = dflag ? OT_LONG : OT_WORD;
6033 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6034 gen_op_andl_T0_ffff();
6035 gen_check_io(s, ot, pc_start - s->cs_base,
6036 svm_is_rep(prefixes) | 4);
6037 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6038 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6042 gen_jmp(s, s->pc - s->cs_base);
6047 /************************/
6055 ot = dflag ? OT_LONG : OT_WORD;
6056 val = ldub_code(s->pc++);
6057 gen_op_movl_T0_im(val);
6058 gen_check_io(s, ot, pc_start - s->cs_base,
6059 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6062 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6063 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6064 gen_op_mov_reg_T1(ot, R_EAX);
6067 gen_jmp(s, s->pc - s->cs_base);
6075 ot = dflag ? OT_LONG : OT_WORD;
6076 val = ldub_code(s->pc++);
6077 gen_op_movl_T0_im(val);
6078 gen_check_io(s, ot, pc_start - s->cs_base,
6079 svm_is_rep(prefixes));
6080 gen_op_mov_TN_reg(ot, 1, R_EAX);
6084 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6085 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6086 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6087 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6090 gen_jmp(s, s->pc - s->cs_base);
6098 ot = dflag ? OT_LONG : OT_WORD;
6099 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6100 gen_op_andl_T0_ffff();
6101 gen_check_io(s, ot, pc_start - s->cs_base,
6102 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6105 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6106 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6107 gen_op_mov_reg_T1(ot, R_EAX);
6110 gen_jmp(s, s->pc - s->cs_base);
6118 ot = dflag ? OT_LONG : OT_WORD;
6119 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6120 gen_op_andl_T0_ffff();
6121 gen_check_io(s, ot, pc_start - s->cs_base,
6122 svm_is_rep(prefixes));
6123 gen_op_mov_TN_reg(ot, 1, R_EAX);
6127 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6128 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6129 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6130 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6133 gen_jmp(s, s->pc - s->cs_base);
6137 /************************/
6139 case 0xc2: /* ret im */
6140 val = ldsw_code(s->pc);
6143 if (CODE64(s) && s->dflag)
6145 gen_stack_update(s, val + (2 << s->dflag));
6147 gen_op_andl_T0_ffff();
6151 case 0xc3: /* ret */
6155 gen_op_andl_T0_ffff();
6159 case 0xca: /* lret im */
6160 val = ldsw_code(s->pc);
6163 if (s->pe && !s->vm86) {
6164 if (s->cc_op != CC_OP_DYNAMIC)
6165 gen_op_set_cc_op(s->cc_op);
6166 gen_jmp_im(pc_start - s->cs_base);
6167 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6168 tcg_const_i32(val));
6172 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6174 gen_op_andl_T0_ffff();
6175 /* NOTE: keeping EIP updated is not a problem in case of
6179 gen_op_addl_A0_im(2 << s->dflag);
6180 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6181 gen_op_movl_seg_T0_vm(R_CS);
6182 /* add stack offset */
6183 gen_stack_update(s, val + (4 << s->dflag));
6187 case 0xcb: /* lret */
6190 case 0xcf: /* iret */
6191 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6194 gen_helper_iret_real(tcg_const_i32(s->dflag));
6195 s->cc_op = CC_OP_EFLAGS;
6196 } else if (s->vm86) {
6198 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6200 gen_helper_iret_real(tcg_const_i32(s->dflag));
6201 s->cc_op = CC_OP_EFLAGS;
6204 if (s->cc_op != CC_OP_DYNAMIC)
6205 gen_op_set_cc_op(s->cc_op);
6206 gen_jmp_im(pc_start - s->cs_base);
6207 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6208 tcg_const_i32(s->pc - s->cs_base));
6209 s->cc_op = CC_OP_EFLAGS;
6213 case 0xe8: /* call im */
6216 tval = (int32_t)insn_get(s, OT_LONG);
6218 tval = (int16_t)insn_get(s, OT_WORD);
6219 next_eip = s->pc - s->cs_base;
6223 gen_movtl_T0_im(next_eip);
6228 case 0x9a: /* lcall im */
6230 unsigned int selector, offset;
6234 ot = dflag ? OT_LONG : OT_WORD;
6235 offset = insn_get(s, ot);
6236 selector = insn_get(s, OT_WORD);
6238 gen_op_movl_T0_im(selector);
6239 gen_op_movl_T1_imu(offset);
6242 case 0xe9: /* jmp im */
6244 tval = (int32_t)insn_get(s, OT_LONG);
6246 tval = (int16_t)insn_get(s, OT_WORD);
6247 tval += s->pc - s->cs_base;
6254 case 0xea: /* ljmp im */
6256 unsigned int selector, offset;
6260 ot = dflag ? OT_LONG : OT_WORD;
6261 offset = insn_get(s, ot);
6262 selector = insn_get(s, OT_WORD);
6264 gen_op_movl_T0_im(selector);
6265 gen_op_movl_T1_imu(offset);
6268 case 0xeb: /* jmp Jb */
6269 tval = (int8_t)insn_get(s, OT_BYTE);
6270 tval += s->pc - s->cs_base;
6275 case 0x70 ... 0x7f: /* jcc Jb */
6276 tval = (int8_t)insn_get(s, OT_BYTE);
6278 case 0x180 ... 0x18f: /* jcc Jv */
6280 tval = (int32_t)insn_get(s, OT_LONG);
6282 tval = (int16_t)insn_get(s, OT_WORD);
6285 next_eip = s->pc - s->cs_base;
6289 gen_jcc(s, b, tval, next_eip);
6292 case 0x190 ... 0x19f: /* setcc Gv */
6293 modrm = ldub_code(s->pc++);
6295 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6297 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6302 ot = dflag + OT_WORD;
6303 modrm = ldub_code(s->pc++);
6304 reg = ((modrm >> 3) & 7) | rex_r;
6305 mod = (modrm >> 6) & 3;
6306 t0 = tcg_temp_local_new();
6308 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6309 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6311 rm = (modrm & 7) | REX_B(s);
6312 gen_op_mov_v_reg(ot, t0, rm);
6314 #ifdef TARGET_X86_64
6315 if (ot == OT_LONG) {
6316 /* XXX: specific Intel behaviour ? */
6317 l1 = gen_new_label();
6318 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6319 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
6321 tcg_gen_movi_tl(cpu_tmp0, 0);
6322 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
6326 l1 = gen_new_label();
6327 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6328 gen_op_mov_reg_v(ot, reg, t0);
6335 /************************/
6337 case 0x9c: /* pushf */
6338 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6339 if (s->vm86 && s->iopl != 3) {
6340 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6342 if (s->cc_op != CC_OP_DYNAMIC)
6343 gen_op_set_cc_op(s->cc_op);
6344 gen_helper_read_eflags(cpu_T[0]);
6348 case 0x9d: /* popf */
6349 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6350 if (s->vm86 && s->iopl != 3) {
6351 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6356 gen_helper_write_eflags(cpu_T[0],
6357 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6359 gen_helper_write_eflags(cpu_T[0],
6360 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6363 if (s->cpl <= s->iopl) {
6365 gen_helper_write_eflags(cpu_T[0],
6366 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6368 gen_helper_write_eflags(cpu_T[0],
6369 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6373 gen_helper_write_eflags(cpu_T[0],
6374 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6376 gen_helper_write_eflags(cpu_T[0],
6377 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6382 s->cc_op = CC_OP_EFLAGS;
6383 /* abort translation because TF flag may change */
6384 gen_jmp_im(s->pc - s->cs_base);
6388 case 0x9e: /* sahf */
6389 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6391 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6392 if (s->cc_op != CC_OP_DYNAMIC)
6393 gen_op_set_cc_op(s->cc_op);
6394 gen_compute_eflags(cpu_cc_src);
6395 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6396 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6397 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6398 s->cc_op = CC_OP_EFLAGS;
6400 case 0x9f: /* lahf */
6401 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6403 if (s->cc_op != CC_OP_DYNAMIC)
6404 gen_op_set_cc_op(s->cc_op);
6405 gen_compute_eflags(cpu_T[0]);
6406 /* Note: gen_compute_eflags() only gives the condition codes */
6407 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6408 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6410 case 0xf5: /* cmc */
6411 if (s->cc_op != CC_OP_DYNAMIC)
6412 gen_op_set_cc_op(s->cc_op);
6413 gen_compute_eflags(cpu_cc_src);
6414 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6415 s->cc_op = CC_OP_EFLAGS;
6417 case 0xf8: /* clc */
6418 if (s->cc_op != CC_OP_DYNAMIC)
6419 gen_op_set_cc_op(s->cc_op);
6420 gen_compute_eflags(cpu_cc_src);
6421 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6422 s->cc_op = CC_OP_EFLAGS;
6424 case 0xf9: /* stc */
6425 if (s->cc_op != CC_OP_DYNAMIC)
6426 gen_op_set_cc_op(s->cc_op);
6427 gen_compute_eflags(cpu_cc_src);
6428 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6429 s->cc_op = CC_OP_EFLAGS;
6431 case 0xfc: /* cld */
6432 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6433 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6435 case 0xfd: /* std */
6436 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6437 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6440 /************************/
6441 /* bit operations */
6442 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6443 ot = dflag + OT_WORD;
6444 modrm = ldub_code(s->pc++);
6445 op = (modrm >> 3) & 7;
6446 mod = (modrm >> 6) & 3;
6447 rm = (modrm & 7) | REX_B(s);
6450 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6451 gen_op_ld_T0_A0(ot + s->mem_index);
6453 gen_op_mov_TN_reg(ot, 0, rm);
6456 val = ldub_code(s->pc++);
6457 gen_op_movl_T1_im(val);
6462 case 0x1a3: /* bt Gv, Ev */
6465 case 0x1ab: /* bts */
6468 case 0x1b3: /* btr */
6471 case 0x1bb: /* btc */
6474 ot = dflag + OT_WORD;
6475 modrm = ldub_code(s->pc++);
6476 reg = ((modrm >> 3) & 7) | rex_r;
6477 mod = (modrm >> 6) & 3;
6478 rm = (modrm & 7) | REX_B(s);
6479 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6481 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6482 /* specific case: we need to add a displacement */
6483 gen_exts(ot, cpu_T[1]);
6484 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6485 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6486 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6487 gen_op_ld_T0_A0(ot + s->mem_index);
6489 gen_op_mov_TN_reg(ot, 0, rm);
6492 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6495 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6496 tcg_gen_movi_tl(cpu_cc_dst, 0);
6499 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6500 tcg_gen_movi_tl(cpu_tmp0, 1);
6501 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6502 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6505 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6506 tcg_gen_movi_tl(cpu_tmp0, 1);
6507 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6508 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6509 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6513 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6514 tcg_gen_movi_tl(cpu_tmp0, 1);
6515 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6516 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6519 s->cc_op = CC_OP_SARB + ot;
6522 gen_op_st_T0_A0(ot + s->mem_index);
6524 gen_op_mov_reg_T0(ot, rm);
6525 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6526 tcg_gen_movi_tl(cpu_cc_dst, 0);
6529 case 0x1bc: /* bsf */
6530 case 0x1bd: /* bsr */
6535 ot = dflag + OT_WORD;
6536 modrm = ldub_code(s->pc++);
6537 reg = ((modrm >> 3) & 7) | rex_r;
6538 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6539 gen_extu(ot, cpu_T[0]);
6540 label1 = gen_new_label();
6541 tcg_gen_movi_tl(cpu_cc_dst, 0);
6542 t0 = tcg_temp_local_new();
6543 tcg_gen_mov_tl(t0, cpu_T[0]);
6544 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6546 gen_helper_bsr(cpu_T[0], t0);
6548 gen_helper_bsf(cpu_T[0], t0);
6550 gen_op_mov_reg_T0(ot, reg);
6551 tcg_gen_movi_tl(cpu_cc_dst, 1);
6552 gen_set_label(label1);
6553 tcg_gen_discard_tl(cpu_cc_src);
6554 s->cc_op = CC_OP_LOGICB + ot;
6558 /************************/
6560 case 0x27: /* daa */
6563 if (s->cc_op != CC_OP_DYNAMIC)
6564 gen_op_set_cc_op(s->cc_op);
6566 s->cc_op = CC_OP_EFLAGS;
6568 case 0x2f: /* das */
6571 if (s->cc_op != CC_OP_DYNAMIC)
6572 gen_op_set_cc_op(s->cc_op);
6574 s->cc_op = CC_OP_EFLAGS;
6576 case 0x37: /* aaa */
6579 if (s->cc_op != CC_OP_DYNAMIC)
6580 gen_op_set_cc_op(s->cc_op);
6582 s->cc_op = CC_OP_EFLAGS;
6584 case 0x3f: /* aas */
6587 if (s->cc_op != CC_OP_DYNAMIC)
6588 gen_op_set_cc_op(s->cc_op);
6590 s->cc_op = CC_OP_EFLAGS;
6592 case 0xd4: /* aam */
6595 val = ldub_code(s->pc++);
6597 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6599 gen_helper_aam(tcg_const_i32(val));
6600 s->cc_op = CC_OP_LOGICB;
6603 case 0xd5: /* aad */
6606 val = ldub_code(s->pc++);
6607 gen_helper_aad(tcg_const_i32(val));
6608 s->cc_op = CC_OP_LOGICB;
6610 /************************/
6612 case 0x90: /* nop */
6613 /* XXX: xchg + rex handling */
6614 /* XXX: correct lock test for all insn */
6615 if (prefixes & PREFIX_LOCK)
6617 if (prefixes & PREFIX_REPZ) {
6618 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6621 case 0x9b: /* fwait */
6622 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6623 (HF_MP_MASK | HF_TS_MASK)) {
6624 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6626 if (s->cc_op != CC_OP_DYNAMIC)
6627 gen_op_set_cc_op(s->cc_op);
6628 gen_jmp_im(pc_start - s->cs_base);
6632 case 0xcc: /* int3 */
6633 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6635 case 0xcd: /* int N */
6636 val = ldub_code(s->pc++);
6637 if (s->vm86 && s->iopl != 3) {
6638 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6640 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6643 case 0xce: /* into */
6646 if (s->cc_op != CC_OP_DYNAMIC)
6647 gen_op_set_cc_op(s->cc_op);
6648 gen_jmp_im(pc_start - s->cs_base);
6649 gen_helper_into(tcg_const_i32(s->pc - pc_start));
6652 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6653 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6655 gen_debug(s, pc_start - s->cs_base);
6658 tb_flush(cpu_single_env);
6659 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6663 case 0xfa: /* cli */
6665 if (s->cpl <= s->iopl) {
6668 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6674 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6678 case 0xfb: /* sti */
6680 if (s->cpl <= s->iopl) {
6683 /* interruptions are enabled only the first insn after sti */
6684 /* If several instructions disable interrupts, only the
6686 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6687 gen_helper_set_inhibit_irq();
6688 /* give a chance to handle pending irqs */
6689 gen_jmp_im(s->pc - s->cs_base);
6692 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6698 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6702 case 0x62: /* bound */
6705 ot = dflag ? OT_LONG : OT_WORD;
6706 modrm = ldub_code(s->pc++);
6707 reg = (modrm >> 3) & 7;
6708 mod = (modrm >> 6) & 3;
6711 gen_op_mov_TN_reg(ot, 0, reg);
6712 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6713 gen_jmp_im(pc_start - s->cs_base);
6714 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6716 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
6718 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
6720 case 0x1c8 ... 0x1cf: /* bswap reg */
6721 reg = (b & 7) | REX_B(s);
6722 #ifdef TARGET_X86_64
6724 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6725 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6726 gen_op_mov_reg_T0(OT_QUAD, reg);
6730 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6731 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6732 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6733 gen_op_mov_reg_T0(OT_LONG, reg);
6736 case 0xd6: /* salc */
6739 if (s->cc_op != CC_OP_DYNAMIC)
6740 gen_op_set_cc_op(s->cc_op);
6741 gen_compute_eflags_c(cpu_T[0]);
6742 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6743 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6745 case 0xe0: /* loopnz */
6746 case 0xe1: /* loopz */
6747 case 0xe2: /* loop */
6748 case 0xe3: /* jecxz */
6752 tval = (int8_t)insn_get(s, OT_BYTE);
6753 next_eip = s->pc - s->cs_base;
6758 l1 = gen_new_label();
6759 l2 = gen_new_label();
6760 l3 = gen_new_label();
6763 case 0: /* loopnz */
6765 if (s->cc_op != CC_OP_DYNAMIC)
6766 gen_op_set_cc_op(s->cc_op);
6767 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6768 gen_op_jz_ecx(s->aflag, l3);
6769 gen_compute_eflags(cpu_tmp0);
6770 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6772 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6774 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6778 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6779 gen_op_jnz_ecx(s->aflag, l1);
6783 gen_op_jz_ecx(s->aflag, l1);
6788 gen_jmp_im(next_eip);
6797 case 0x130: /* wrmsr */
6798 case 0x132: /* rdmsr */
6800 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6802 if (s->cc_op != CC_OP_DYNAMIC)
6803 gen_op_set_cc_op(s->cc_op);
6804 gen_jmp_im(pc_start - s->cs_base);
6812 case 0x131: /* rdtsc */
6813 if (s->cc_op != CC_OP_DYNAMIC)
6814 gen_op_set_cc_op(s->cc_op);
6815 gen_jmp_im(pc_start - s->cs_base);
6821 gen_jmp(s, s->pc - s->cs_base);
6824 case 0x133: /* rdpmc */
6825 if (s->cc_op != CC_OP_DYNAMIC)
6826 gen_op_set_cc_op(s->cc_op);
6827 gen_jmp_im(pc_start - s->cs_base);
6830 case 0x134: /* sysenter */
6831 /* For Intel SYSENTER is valid on 64-bit */
6832 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6835 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6837 if (s->cc_op != CC_OP_DYNAMIC) {
6838 gen_op_set_cc_op(s->cc_op);
6839 s->cc_op = CC_OP_DYNAMIC;
6841 gen_jmp_im(pc_start - s->cs_base);
6842 gen_helper_sysenter();
6846 case 0x135: /* sysexit */
6847 /* For Intel SYSEXIT is valid on 64-bit */
6848 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6851 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6853 if (s->cc_op != CC_OP_DYNAMIC) {
6854 gen_op_set_cc_op(s->cc_op);
6855 s->cc_op = CC_OP_DYNAMIC;
6857 gen_jmp_im(pc_start - s->cs_base);
6858 gen_helper_sysexit(tcg_const_i32(dflag));
6862 #ifdef TARGET_X86_64
6863 case 0x105: /* syscall */
6864 /* XXX: is it usable in real mode ? */
6865 if (s->cc_op != CC_OP_DYNAMIC) {
6866 gen_op_set_cc_op(s->cc_op);
6867 s->cc_op = CC_OP_DYNAMIC;
6869 gen_jmp_im(pc_start - s->cs_base);
6870 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
6873 case 0x107: /* sysret */
6875 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6877 if (s->cc_op != CC_OP_DYNAMIC) {
6878 gen_op_set_cc_op(s->cc_op);
6879 s->cc_op = CC_OP_DYNAMIC;
6881 gen_jmp_im(pc_start - s->cs_base);
6882 gen_helper_sysret(tcg_const_i32(s->dflag));
6883 /* condition codes are modified only in long mode */
6885 s->cc_op = CC_OP_EFLAGS;
6890 case 0x1a2: /* cpuid */
6891 if (s->cc_op != CC_OP_DYNAMIC)
6892 gen_op_set_cc_op(s->cc_op);
6893 gen_jmp_im(pc_start - s->cs_base);
6896 case 0xf4: /* hlt */
6898 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6900 if (s->cc_op != CC_OP_DYNAMIC)
6901 gen_op_set_cc_op(s->cc_op);
6902 gen_jmp_im(pc_start - s->cs_base);
6903 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
6908 modrm = ldub_code(s->pc++);
6909 mod = (modrm >> 6) & 3;
6910 op = (modrm >> 3) & 7;
6913 if (!s->pe || s->vm86)
6915 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6916 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6920 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6923 if (!s->pe || s->vm86)
6926 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6928 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
6929 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6930 gen_jmp_im(pc_start - s->cs_base);
6931 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6932 gen_helper_lldt(cpu_tmp2_i32);
6936 if (!s->pe || s->vm86)
6938 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
6939 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6943 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6946 if (!s->pe || s->vm86)
6949 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6951 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
6952 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6953 gen_jmp_im(pc_start - s->cs_base);
6954 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6955 gen_helper_ltr(cpu_tmp2_i32);
6960 if (!s->pe || s->vm86)
6962 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6963 if (s->cc_op != CC_OP_DYNAMIC)
6964 gen_op_set_cc_op(s->cc_op);
6966 gen_helper_verr(cpu_T[0]);
6968 gen_helper_verw(cpu_T[0]);
6969 s->cc_op = CC_OP_EFLAGS;
6976 modrm = ldub_code(s->pc++);
6977 mod = (modrm >> 6) & 3;
6978 op = (modrm >> 3) & 7;
6984 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
6985 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6986 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6987 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6988 gen_add_A0_im(s, 2);
6989 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
6991 gen_op_andl_T0_im(0xffffff);
6992 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6997 case 0: /* monitor */
6998 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7001 if (s->cc_op != CC_OP_DYNAMIC)
7002 gen_op_set_cc_op(s->cc_op);
7003 gen_jmp_im(pc_start - s->cs_base);
7004 #ifdef TARGET_X86_64
7005 if (s->aflag == 2) {
7006 gen_op_movq_A0_reg(R_EAX);
7010 gen_op_movl_A0_reg(R_EAX);
7012 gen_op_andl_A0_ffff();
7014 gen_add_A0_ds_seg(s);
7015 gen_helper_monitor(cpu_A0);
7018 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7021 if (s->cc_op != CC_OP_DYNAMIC) {
7022 gen_op_set_cc_op(s->cc_op);
7023 s->cc_op = CC_OP_DYNAMIC;
7025 gen_jmp_im(pc_start - s->cs_base);
7026 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
7033 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7034 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7035 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7036 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7037 gen_add_A0_im(s, 2);
7038 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7040 gen_op_andl_T0_im(0xffffff);
7041 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7047 if (s->cc_op != CC_OP_DYNAMIC)
7048 gen_op_set_cc_op(s->cc_op);
7049 gen_jmp_im(pc_start - s->cs_base);
7052 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7055 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7058 gen_helper_vmrun(tcg_const_i32(s->aflag),
7059 tcg_const_i32(s->pc - pc_start));
7064 case 1: /* VMMCALL */
7065 if (!(s->flags & HF_SVME_MASK))
7067 gen_helper_vmmcall();
7069 case 2: /* VMLOAD */
7070 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7073 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7076 gen_helper_vmload(tcg_const_i32(s->aflag));
7079 case 3: /* VMSAVE */
7080 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7083 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7086 gen_helper_vmsave(tcg_const_i32(s->aflag));
7090 if ((!(s->flags & HF_SVME_MASK) &&
7091 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7095 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7102 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7105 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7111 case 6: /* SKINIT */
7112 if ((!(s->flags & HF_SVME_MASK) &&
7113 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7116 gen_helper_skinit();
7118 case 7: /* INVLPGA */
7119 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7122 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7125 gen_helper_invlpga(tcg_const_i32(s->aflag));
7131 } else if (s->cpl != 0) {
7132 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7134 gen_svm_check_intercept(s, pc_start,
7135 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7136 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7137 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7138 gen_add_A0_im(s, 2);
7139 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7141 gen_op_andl_T0_im(0xffffff);
7143 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7144 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7146 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7147 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7152 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7153 #if defined TARGET_X86_64 && defined WORDS_BIGENDIAN
7154 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7156 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7158 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7162 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7164 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7165 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7166 gen_helper_lmsw(cpu_T[0]);
7167 gen_jmp_im(s->pc - s->cs_base);
7171 case 7: /* invlpg */
7173 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7176 #ifdef TARGET_X86_64
7177 if (CODE64(s) && rm == 0) {
7179 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7180 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
7181 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7182 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
7189 if (s->cc_op != CC_OP_DYNAMIC)
7190 gen_op_set_cc_op(s->cc_op);
7191 gen_jmp_im(pc_start - s->cs_base);
7192 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7193 gen_helper_invlpg(cpu_A0);
7194 gen_jmp_im(s->pc - s->cs_base);
7203 case 0x108: /* invd */
7204 case 0x109: /* wbinvd */
7206 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7208 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7212 case 0x63: /* arpl or movslS (x86_64) */
7213 #ifdef TARGET_X86_64
7216 /* d_ot is the size of destination */
7217 d_ot = dflag + OT_WORD;
7219 modrm = ldub_code(s->pc++);
7220 reg = ((modrm >> 3) & 7) | rex_r;
7221 mod = (modrm >> 6) & 3;
7222 rm = (modrm & 7) | REX_B(s);
7225 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7227 if (d_ot == OT_QUAD)
7228 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7229 gen_op_mov_reg_T0(d_ot, reg);
7231 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7232 if (d_ot == OT_QUAD) {
7233 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7235 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7237 gen_op_mov_reg_T0(d_ot, reg);
7245 if (!s->pe || s->vm86)
7247 t0 = tcg_temp_local_new();
7248 t1 = tcg_temp_local_new();
7249 t2 = tcg_temp_local_new();
7251 modrm = ldub_code(s->pc++);
7252 reg = (modrm >> 3) & 7;
7253 mod = (modrm >> 6) & 3;
7256 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7257 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7259 gen_op_mov_v_reg(ot, t0, rm);
7261 gen_op_mov_v_reg(ot, t1, reg);
7262 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7263 tcg_gen_andi_tl(t1, t1, 3);
7264 tcg_gen_movi_tl(t2, 0);
7265 label1 = gen_new_label();
7266 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7267 tcg_gen_andi_tl(t0, t0, ~3);
7268 tcg_gen_or_tl(t0, t0, t1);
7269 tcg_gen_movi_tl(t2, CC_Z);
7270 gen_set_label(label1);
7272 gen_op_st_v(ot + s->mem_index, t0, cpu_A0);
7274 gen_op_mov_reg_v(ot, rm, t0);
7276 if (s->cc_op != CC_OP_DYNAMIC)
7277 gen_op_set_cc_op(s->cc_op);
7278 gen_compute_eflags(cpu_cc_src);
7279 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7280 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7281 s->cc_op = CC_OP_EFLAGS;
7287 case 0x102: /* lar */
7288 case 0x103: /* lsl */
7292 if (!s->pe || s->vm86)
7294 ot = dflag ? OT_LONG : OT_WORD;
7295 modrm = ldub_code(s->pc++);
7296 reg = ((modrm >> 3) & 7) | rex_r;
7297 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7298 t0 = tcg_temp_local_new();
7299 if (s->cc_op != CC_OP_DYNAMIC)
7300 gen_op_set_cc_op(s->cc_op);
7302 gen_helper_lar(t0, cpu_T[0]);
7304 gen_helper_lsl(t0, cpu_T[0]);
7305 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7306 label1 = gen_new_label();
7307 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7308 gen_op_mov_reg_v(ot, reg, t0);
7309 gen_set_label(label1);
7310 s->cc_op = CC_OP_EFLAGS;
7315 modrm = ldub_code(s->pc++);
7316 mod = (modrm >> 6) & 3;
7317 op = (modrm >> 3) & 7;
7319 case 0: /* prefetchnta */
7320 case 1: /* prefetchnt0 */
7321 case 2: /* prefetchnt0 */
7322 case 3: /* prefetchnt0 */
7325 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7326 /* nothing more to do */
7328 default: /* nop (multi byte) */
7329 gen_nop_modrm(s, modrm);
7333 case 0x119 ... 0x11f: /* nop (multi byte) */
7334 modrm = ldub_code(s->pc++);
7335 gen_nop_modrm(s, modrm);
7337 case 0x120: /* mov reg, crN */
7338 case 0x122: /* mov crN, reg */
7340 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7342 modrm = ldub_code(s->pc++);
7343 if ((modrm & 0xc0) != 0xc0)
7345 rm = (modrm & 7) | REX_B(s);
7346 reg = ((modrm >> 3) & 7) | rex_r;
7357 if (s->cc_op != CC_OP_DYNAMIC)
7358 gen_op_set_cc_op(s->cc_op);
7359 gen_jmp_im(pc_start - s->cs_base);
7361 gen_op_mov_TN_reg(ot, 0, rm);
7362 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7363 gen_jmp_im(s->pc - s->cs_base);
7366 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7367 gen_op_mov_reg_T0(ot, rm);
7375 case 0x121: /* mov reg, drN */
7376 case 0x123: /* mov drN, reg */
7378 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7380 modrm = ldub_code(s->pc++);
7381 if ((modrm & 0xc0) != 0xc0)
7383 rm = (modrm & 7) | REX_B(s);
7384 reg = ((modrm >> 3) & 7) | rex_r;
7389 /* XXX: do it dynamically with CR4.DE bit */
7390 if (reg == 4 || reg == 5 || reg >= 8)
7393 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7394 gen_op_mov_TN_reg(ot, 0, rm);
7395 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7396 gen_jmp_im(s->pc - s->cs_base);
7399 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7400 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7401 gen_op_mov_reg_T0(ot, rm);
7405 case 0x106: /* clts */
7407 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7409 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7411 /* abort block because static cpu state changed */
7412 gen_jmp_im(s->pc - s->cs_base);
7416 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7417 case 0x1c3: /* MOVNTI reg, mem */
7418 if (!(s->cpuid_features & CPUID_SSE2))
7420 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7421 modrm = ldub_code(s->pc++);
7422 mod = (modrm >> 6) & 3;
7425 reg = ((modrm >> 3) & 7) | rex_r;
7426 /* generate a generic store */
7427 gen_ldst_modrm(s, modrm, ot, reg, 1);
7430 modrm = ldub_code(s->pc++);
7431 mod = (modrm >> 6) & 3;
7432 op = (modrm >> 3) & 7;
7434 case 0: /* fxsave */
7435 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7436 (s->flags & HF_EM_MASK))
7438 if (s->flags & HF_TS_MASK) {
7439 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7442 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7443 if (s->cc_op != CC_OP_DYNAMIC)
7444 gen_op_set_cc_op(s->cc_op);
7445 gen_jmp_im(pc_start - s->cs_base);
7446 gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
7448 case 1: /* fxrstor */
7449 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7450 (s->flags & HF_EM_MASK))
7452 if (s->flags & HF_TS_MASK) {
7453 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7456 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7457 if (s->cc_op != CC_OP_DYNAMIC)
7458 gen_op_set_cc_op(s->cc_op);
7459 gen_jmp_im(pc_start - s->cs_base);
7460 gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
7462 case 2: /* ldmxcsr */
7463 case 3: /* stmxcsr */
7464 if (s->flags & HF_TS_MASK) {
7465 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7468 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7471 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7473 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7474 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7476 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7477 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7480 case 5: /* lfence */
7481 case 6: /* mfence */
7482 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7485 case 7: /* sfence / clflush */
7486 if ((modrm & 0xc7) == 0xc0) {
7488 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7489 if (!(s->cpuid_features & CPUID_SSE))
7493 if (!(s->cpuid_features & CPUID_CLFLUSH))
7495 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7502 case 0x10d: /* 3DNow! prefetch(w) */
7503 modrm = ldub_code(s->pc++);
7504 mod = (modrm >> 6) & 3;
7507 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7508 /* ignore for now */
7510 case 0x1aa: /* rsm */
7511 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7512 if (!(s->flags & HF_SMM_MASK))
7514 if (s->cc_op != CC_OP_DYNAMIC) {
7515 gen_op_set_cc_op(s->cc_op);
7516 s->cc_op = CC_OP_DYNAMIC;
7518 gen_jmp_im(s->pc - s->cs_base);
7522 case 0x1b8: /* SSE4.2 popcnt */
7523 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7526 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7529 modrm = ldub_code(s->pc++);
7530 reg = ((modrm >> 3) & 7);
7532 if (s->prefix & PREFIX_DATA)
7534 else if (s->dflag != 2)
7539 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7540 gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7541 gen_op_mov_reg_T0(ot, reg);
7543 s->cc_op = CC_OP_EFLAGS;
7545 case 0x10e ... 0x10f:
7546 /* 3DNow! instructions, ignore prefixes */
7547 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7548 case 0x110 ... 0x117:
7549 case 0x128 ... 0x12f:
7550 case 0x138 ... 0x13a:
7551 case 0x150 ... 0x177:
7552 case 0x17c ... 0x17f:
7554 case 0x1c4 ... 0x1c6:
7555 case 0x1d0 ... 0x1fe:
7556 gen_sse(s, b, pc_start, rex_r);
7561 /* lock generation */
7562 if (s->prefix & PREFIX_LOCK)
7563 gen_helper_unlock();
7566 if (s->prefix & PREFIX_LOCK)
7567 gen_helper_unlock();
7568 /* XXX: ensure that no lock was generated */
7569 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7573 void optimize_flags_init(void)
7575 #if TCG_TARGET_REG_BITS == 32
7576 assert(sizeof(CCTable) == (1 << 3));
7578 assert(sizeof(CCTable) == (1 << 4));
7580 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7581 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7582 offsetof(CPUState, cc_op), "cc_op");
7583 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
7585 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
7587 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
7590 /* register helpers */
7591 #define GEN_HELPER 2
7595 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7596 basic block 'tb'. If search_pc is TRUE, also generate PC
7597 information for each intermediate instruction. */
7598 static inline void gen_intermediate_code_internal(CPUState *env,
7599 TranslationBlock *tb,
7602 DisasContext dc1, *dc = &dc1;
7603 target_ulong pc_ptr;
7604 uint16_t *gen_opc_end;
7608 target_ulong pc_start;
7609 target_ulong cs_base;
7613 /* generate intermediate code */
7615 cs_base = tb->cs_base;
7617 cflags = tb->cflags;
7619 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7620 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7621 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7622 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7624 dc->vm86 = (flags >> VM_SHIFT) & 1;
7625 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7626 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7627 dc->tf = (flags >> TF_SHIFT) & 1;
7628 dc->singlestep_enabled = env->singlestep_enabled;
7629 dc->cc_op = CC_OP_DYNAMIC;
7630 dc->cs_base = cs_base;
7632 dc->popl_esp_hack = 0;
7633 /* select memory access functions */
7635 if (flags & HF_SOFTMMU_MASK) {
7637 dc->mem_index = 2 * 4;
7639 dc->mem_index = 1 * 4;
7641 dc->cpuid_features = env->cpuid_features;
7642 dc->cpuid_ext_features = env->cpuid_ext_features;
7643 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7644 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7645 #ifdef TARGET_X86_64
7646 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7647 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7650 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7651 (flags & HF_INHIBIT_IRQ_MASK)
7652 #ifndef CONFIG_SOFTMMU
7653 || (flags & HF_SOFTMMU_MASK)
7657 /* check addseg logic */
7658 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7659 printf("ERROR addseg\n");
7662 cpu_T[0] = tcg_temp_new();
7663 cpu_T[1] = tcg_temp_new();
7664 cpu_A0 = tcg_temp_new();
7665 cpu_T3 = tcg_temp_new();
7667 cpu_tmp0 = tcg_temp_new();
7668 cpu_tmp1_i64 = tcg_temp_new_i64();
7669 cpu_tmp2_i32 = tcg_temp_new_i32();
7670 cpu_tmp3_i32 = tcg_temp_new_i32();
7671 cpu_tmp4 = tcg_temp_new();
7672 cpu_tmp5 = tcg_temp_new();
7673 cpu_tmp6 = tcg_temp_new();
7674 cpu_ptr0 = tcg_temp_new_ptr();
7675 cpu_ptr1 = tcg_temp_new_ptr();
7677 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7679 dc->is_jmp = DISAS_NEXT;
7683 max_insns = tb->cflags & CF_COUNT_MASK;
7685 max_insns = CF_COUNT_MASK;
7689 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7690 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7691 if (bp->pc == pc_ptr) {
7692 gen_debug(dc, pc_ptr - dc->cs_base);
7698 j = gen_opc_ptr - gen_opc_buf;
7702 gen_opc_instr_start[lj++] = 0;
7704 gen_opc_pc[lj] = pc_ptr;
7705 gen_opc_cc_op[lj] = dc->cc_op;
7706 gen_opc_instr_start[lj] = 1;
7707 gen_opc_icount[lj] = num_insns;
7709 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7712 pc_ptr = disas_insn(dc, pc_ptr);
7714 /* stop translation if indicated */
7717 /* if single step mode, we generate only one instruction and
7718 generate an exception */
7719 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7720 the flag and abort the translation to give the irqs a
7721 change to be happen */
7722 if (dc->tf || dc->singlestep_enabled ||
7723 (flags & HF_INHIBIT_IRQ_MASK)) {
7724 gen_jmp_im(pc_ptr - dc->cs_base);
7728 /* if too long translation, stop generation too */
7729 if (gen_opc_ptr >= gen_opc_end ||
7730 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7731 num_insns >= max_insns) {
7732 gen_jmp_im(pc_ptr - dc->cs_base);
7737 gen_jmp_im(pc_ptr - dc->cs_base);
7742 if (tb->cflags & CF_LAST_IO)
7744 gen_icount_end(tb, num_insns);
7745 *gen_opc_ptr = INDEX_op_end;
7746 /* we don't forget to fill the last values */
7748 j = gen_opc_ptr - gen_opc_buf;
7751 gen_opc_instr_start[lj++] = 0;
7755 log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP);
7756 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
7758 qemu_log("----------------\n");
7759 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7760 #ifdef TARGET_X86_64
7765 disas_flags = !dc->code32;
7766 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7772 tb->size = pc_ptr - pc_start;
7773 tb->icount = num_insns;
7777 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7779 gen_intermediate_code_internal(env, tb, 0);
7782 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7784 gen_intermediate_code_internal(env, tb, 1);
7787 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7788 unsigned long searched_pc, int pc_pos, void *puc)
7792 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
7794 qemu_log("RESTORE:\n");
7795 for(i = 0;i <= pc_pos; i++) {
7796 if (gen_opc_instr_start[i]) {
7797 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7800 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7801 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7802 (uint32_t)tb->cs_base);
7805 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7806 cc_op = gen_opc_cc_op[pc_pos];
7807 if (cc_op != CC_OP_DYNAMIC)