4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
29 #include "hw/sh_intc.h"
31 #if defined(CONFIG_USER_ONLY)
33 void do_interrupt (CPUState *env)
35 env->exception_index = -1;
38 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
39 int mmu_idx, int is_softmmu)
42 env->exception_index = 0;
45 env->exception_index = 0x0a0;
48 env->exception_index = 0x0c0;
51 env->exception_index = 0x0a0;
57 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
62 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
64 /* For user mode, only U0 area is cachable. */
65 return !(addr & 0x80000000);
68 #else /* !CONFIG_USER_ONLY */
71 #define MMU_ITLB_MISS (-1)
72 #define MMU_ITLB_MULTIPLE (-2)
73 #define MMU_ITLB_VIOLATION (-3)
74 #define MMU_DTLB_MISS_READ (-4)
75 #define MMU_DTLB_MISS_WRITE (-5)
76 #define MMU_DTLB_INITIAL_WRITE (-6)
77 #define MMU_DTLB_VIOLATION_READ (-7)
78 #define MMU_DTLB_VIOLATION_WRITE (-8)
79 #define MMU_DTLB_MULTIPLE (-9)
80 #define MMU_DTLB_MISS (-10)
81 #define MMU_IADDR_ERROR (-11)
82 #define MMU_DADDR_ERROR_READ (-12)
83 #define MMU_DADDR_ERROR_WRITE (-13)
85 void do_interrupt(CPUState * env)
87 int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
88 int do_exp, irq_vector = env->exception_index;
90 /* prioritize exceptions over interrupts */
92 do_exp = env->exception_index != -1;
93 do_irq = do_irq && (env->exception_index == -1);
95 if (env->sr & SR_BL) {
96 if (do_exp && env->exception_index != 0x1e0) {
97 env->exception_index = 0x000; /* masked exception -> reset */
99 if (do_irq && !env->intr_at_halt) {
102 env->intr_at_halt = 0;
106 irq_vector = sh_intc_get_pending_vector(env->intc_handle,
107 (env->sr >> 4) & 0xf);
108 if (irq_vector == -1) {
113 if (qemu_loglevel_mask(CPU_LOG_INT)) {
115 switch (env->exception_index) {
117 expname = "addr_error";
120 expname = "tlb_miss";
123 expname = "tlb_violation";
126 expname = "illegal_instruction";
129 expname = "slot_illegal_instruction";
132 expname = "fpu_disable";
135 expname = "slot_fpu";
138 expname = "data_write";
141 expname = "dtlb_miss_write";
144 expname = "dtlb_violation_write";
147 expname = "fpu_exception";
150 expname = "initial_page_write";
156 expname = do_irq ? "interrupt" : "???";
159 qemu_log("exception 0x%03x [%s] raised\n",
160 irq_vector, expname);
161 log_cpu_state(env, 0);
166 env->sgr = env->gregs[15];
167 env->sr |= SR_BL | SR_MD | SR_RB;
169 if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
170 /* Branch instruction should be executed again before delay slot. */
172 /* Clear flags for exception/interrupt routine. */
173 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
175 if (env->flags & DELAY_SLOT_CLEARME)
179 env->expevt = env->exception_index;
180 switch (env->exception_index) {
185 env->sr |= 0xf << 4; /* IMASK */
186 env->pc = 0xa0000000;
190 env->pc = env->vbr + 0x400;
193 env->spc += 2; /* special case for TRAPA */
196 env->pc = env->vbr + 0x100;
203 env->intevt = irq_vector;
204 env->pc = env->vbr + 0x600;
209 static void update_itlb_use(CPUState * env, int itlbnb)
211 uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
230 env->mmucr &= (and_mask << 24) | 0x00ffffff;
231 env->mmucr |= (or_mask << 24);
234 static int itlb_replacement(CPUState * env)
236 if ((env->mmucr & 0xe0000000) == 0xe0000000)
238 if ((env->mmucr & 0x98000000) == 0x18000000)
240 if ((env->mmucr & 0x54000000) == 0x04000000)
242 if ((env->mmucr & 0x2c000000) == 0x00000000)
247 /* Find the corresponding entry in the right TLB
248 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
250 static int find_tlb_entry(CPUState * env, target_ulong address,
251 tlb_t * entries, uint8_t nbtlb, int use_asid)
253 int match = MMU_DTLB_MISS;
258 asid = env->pteh & 0xff;
260 for (i = 0; i < nbtlb; i++) {
262 continue; /* Invalid entry */
263 if (!entries[i].sh && use_asid && entries[i].asid != asid)
264 continue; /* Bad ASID */
266 switch (entries[i].sz) {
268 size = 1024; /* 1kB */
271 size = 4 * 1024; /* 4kB */
274 size = 64 * 1024; /* 64kB */
277 size = 1024 * 1024; /* 1MB */
283 start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
284 end = start + entries[i].size - 1;
285 if (address >= start && address <= end) { /* Match */
286 if (match != MMU_DTLB_MISS)
287 return MMU_DTLB_MULTIPLE; /* Multiple match */
294 static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
295 const tlb_t * needle)
298 for (i = 0; i < nbtlb; i++)
299 if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
304 static void increment_urc(CPUState * env)
309 urb = ((env->mmucr) >> 18) & 0x3f;
310 urc = ((env->mmucr) >> 10) & 0x3f;
312 if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
314 env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
317 /* Find itlb entry - update itlb from utlb if necessary and asked for
318 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
319 Update the itlb from utlb if update is not 0
321 static int find_itlb_entry(CPUState * env, target_ulong address,
322 int use_asid, int update)
326 e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
327 if (e == MMU_DTLB_MULTIPLE)
328 e = MMU_ITLB_MULTIPLE;
329 else if (e == MMU_DTLB_MISS && update) {
330 e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
333 n = itlb_replacement(env);
334 ientry = &env->itlb[n];
336 if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
337 tlb_flush_page(env, ientry->vpn << 10);
339 *ientry = env->utlb[e];
341 } else if (e == MMU_DTLB_MISS)
343 } else if (e == MMU_DTLB_MISS)
346 update_itlb_use(env, e);
351 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
352 static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
354 /* per utlb access */
358 return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
361 /* Match address against MMU
362 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
363 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
364 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
365 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
366 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
368 static int get_mmu_address(CPUState * env, target_ulong * physical,
369 int *prot, target_ulong address,
370 int rw, int access_type)
373 tlb_t *matching = NULL;
375 use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
378 n = find_itlb_entry(env, address, use_asid, 1);
380 matching = &env->itlb[n];
381 if ((env->sr & SR_MD) & !(matching->pr & 2))
382 n = MMU_ITLB_VIOLATION;
387 n = find_utlb_entry(env, address, use_asid);
389 matching = &env->utlb[n];
390 switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
393 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
394 MMU_DTLB_VIOLATION_READ;
400 n = MMU_DTLB_VIOLATION_WRITE;
407 *prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
410 } else if (n == MMU_DTLB_MISS) {
411 n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
416 *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
417 (address & (matching->size - 1));
418 if ((rw == 1) & !matching->d)
419 n = MMU_DTLB_INITIAL_WRITE;
426 static int get_physical_address(CPUState * env, target_ulong * physical,
427 int *prot, target_ulong address,
428 int rw, int access_type)
430 /* P1, P2 and P4 areas do not use translation */
431 if ((address >= 0x80000000 && address < 0xc0000000) ||
432 address >= 0xe0000000) {
433 if (!(env->sr & SR_MD)
434 && (address < 0xe0000000 || address > 0xe4000000)) {
435 /* Unauthorized access in user mode (only store queues are available) */
436 fprintf(stderr, "Unauthorized access\n");
438 return MMU_DADDR_ERROR_READ;
440 return MMU_DADDR_ERROR_WRITE;
442 return MMU_IADDR_ERROR;
444 if (address >= 0x80000000 && address < 0xc0000000) {
445 /* Mask upper 3 bits for P1 and P2 areas */
446 *physical = address & 0x1fffffff;
450 *prot = PAGE_READ | PAGE_WRITE;
454 /* If MMU is disabled, return the corresponding physical page */
455 if (!env->mmucr & MMUCR_AT) {
456 *physical = address & 0x1FFFFFFF;
457 *prot = PAGE_READ | PAGE_WRITE;
461 /* We need to resort to the MMU */
462 return get_mmu_address(env, physical, prot, address, rw, access_type);
465 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
466 int mmu_idx, int is_softmmu)
468 target_ulong physical, page_offset, page_size;
469 int prot, ret, access_type;
471 access_type = ACCESS_INT;
473 get_physical_address(env, &physical, &prot, address, rw,
480 case MMU_DTLB_MISS_READ:
481 env->exception_index = 0x040;
483 case MMU_DTLB_MULTIPLE:
484 case MMU_ITLB_MULTIPLE:
485 env->exception_index = 0x140;
487 case MMU_ITLB_VIOLATION:
488 env->exception_index = 0x0a0;
490 case MMU_DTLB_MISS_WRITE:
491 env->exception_index = 0x060;
493 case MMU_DTLB_INITIAL_WRITE:
494 env->exception_index = 0x080;
496 case MMU_DTLB_VIOLATION_READ:
497 env->exception_index = 0x0a0;
499 case MMU_DTLB_VIOLATION_WRITE:
500 env->exception_index = 0x0c0;
502 case MMU_IADDR_ERROR:
503 case MMU_DADDR_ERROR_READ:
504 env->exception_index = 0x0c0;
506 case MMU_DADDR_ERROR_WRITE:
507 env->exception_index = 0x100;
515 page_size = TARGET_PAGE_SIZE;
517 (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
518 address = (address & TARGET_PAGE_MASK) + page_offset;
519 physical = (physical & TARGET_PAGE_MASK) + page_offset;
521 return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
524 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
526 target_ulong physical;
529 get_physical_address(env, &physical, &prot, addr, 0, 0);
533 void cpu_load_tlb(CPUSH4State * env)
535 int n = cpu_mmucr_urc(env->mmucr);
536 tlb_t * entry = &env->utlb[n];
539 /* Overwriting valid entry in utlb. */
540 target_ulong address = entry->vpn << 10;
541 if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
542 tlb_flush_page(env, address);
546 /* Take values into cpu status from registers. */
547 entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
548 entry->vpn = cpu_pteh_vpn(env->pteh);
549 entry->v = (uint8_t)cpu_ptel_v(env->ptel);
550 entry->ppn = cpu_ptel_ppn(env->ptel);
551 entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
554 entry->size = 1024; /* 1K */
557 entry->size = 1024 * 4; /* 4K */
560 entry->size = 1024 * 64; /* 64K */
563 entry->size = 1024 * 1024; /* 1M */
569 entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
570 entry->c = (uint8_t)cpu_ptel_c(env->ptel);
571 entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
572 entry->d = (uint8_t)cpu_ptel_d(env->ptel);
573 entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
574 entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
575 entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
578 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
581 int associate = addr & 0x0000080;
582 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
583 uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
584 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
585 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
586 int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
590 tlb_t * utlb_match_entry = NULL;
591 int needs_tlb_flush = 0;
594 for (i = 0; i < UTLB_SIZE; i++) {
595 tlb_t * entry = &s->utlb[i];
599 if (entry->vpn == vpn
600 && (!use_asid || entry->asid == asid || entry->sh)) {
601 if (utlb_match_entry) {
602 /* Multiple TLB Exception */
603 s->exception_index = 0x140;
611 utlb_match_entry = entry;
613 increment_urc(s); /* per utlb access */
617 for (i = 0; i < ITLB_SIZE; i++) {
618 tlb_t * entry = &s->itlb[i];
619 if (entry->vpn == vpn
620 && (!use_asid || entry->asid == asid || entry->sh)) {
623 if (utlb_match_entry)
624 *entry = *utlb_match_entry;
632 tlb_flush_page(s, vpn << 10);
635 int index = (addr & 0x00003f00) >> 8;
636 tlb_t * entry = &s->utlb[index];
638 /* Overwriting valid entry in utlb. */
639 target_ulong address = entry->vpn << 10;
640 if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
641 tlb_flush_page(s, address);
652 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
655 int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
658 if (env->sr & SR_MD) {
659 /* For previledged mode, P2 and P4 area is not cachable. */
660 if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
663 /* For user mode, only U0 area is cachable. */
664 if (0x80000000 <= addr)
669 * TODO : Evaluate CCR and check if the cache is on or off.
670 * Now CCR is not in CPUSH4State, but in SH7750State.
671 * When you move the ccr inot CPUSH4State, the code will be
675 /* check if operand cache is enabled or not. */
680 /* if MMU is off, no check for TLB. */
681 if (env->mmucr & MMUCR_AT)
685 n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
687 return env->itlb[n].c;
689 n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
691 return env->utlb[n].c;