git.maemo.org Git - qemu/blob - target-sh4/translate.c

   1 /*
   2  *  SH4 translation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <assert.h>
  26
  27 #define DEBUG_DISAS
  28 #define SH4_DEBUG_DISAS
  29 //#define SH4_SINGLE_STEP
  30
  31 #include "cpu.h"
  32 #include "exec-all.h"
  33 #include "disas.h"
  34 #include "tcg-op.h"
  35 #include "qemu-common.h"
  36
  37 #include "helper.h"
  38 #define GEN_HELPER 1
  39 #include "helper.h"
  40
  41 typedef struct DisasContext {
  42     struct TranslationBlock *tb;
  43     target_ulong pc;
  44     uint32_t sr;
  45     uint32_t fpscr;
  46     uint16_t opcode;
  47     uint32_t flags;
  48     int bstate;
  49     int memidx;
  50     uint32_t delayed_pc;
  51     int singlestep_enabled;
  52     uint32_t features;
  53 } DisasContext;
  54
  55 #if defined(CONFIG_USER_ONLY)
  56 #define IS_USER(ctx) 1
  57 #else
  58 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
  59 #endif
  60
  61 enum {
  62     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  63                       * exception condition
  64                       */
  65     BS_STOP     = 1, /* We want to stop translation for any reason */
  66     BS_BRANCH   = 2, /* We reached a branch condition     */
  67     BS_EXCP     = 3, /* We reached an exception condition */
  68 };
  69
  70 /* global register indexes */
  71 static TCGv_ptr cpu_env;
  72 static TCGv cpu_gregs[24];
  73 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
  74 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
  75 static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
  76 static TCGv cpu_fregs[32];
  77
  78 /* internal register indexes */
  79 static TCGv cpu_flags, cpu_delayed_pc;
  80
  81 #include "gen-icount.h"
  82
  83 static void sh4_translate_init(void)
  84 {
  85     int i;
  86     static int done_init = 0;
  87     static const char * const gregnames[24] = {
  88         "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
  89         "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
  90         "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
  91         "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
  92         "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
  93     };
  94     static const char * const fregnames[32] = {
  95          "FPR0_BANK0",  "FPR1_BANK0",  "FPR2_BANK0",  "FPR3_BANK0",
  96          "FPR4_BANK0",  "FPR5_BANK0",  "FPR6_BANK0",  "FPR7_BANK0",
  97          "FPR8_BANK0",  "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
  98         "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
  99          "FPR0_BANK1",  "FPR1_BANK1",  "FPR2_BANK1",  "FPR3_BANK1",
 100          "FPR4_BANK1",  "FPR5_BANK1",  "FPR6_BANK1",  "FPR7_BANK1",
 101          "FPR8_BANK1",  "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
 102         "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
 103     };
 104
 105     if (done_init)
 106         return;
 107
 108     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 109
 110     for (i = 0; i < 24; i++)
 111         cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
 112                                               offsetof(CPUState, gregs[i]),
 113                                               gregnames[i]);
 114
 115     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
 116                                     offsetof(CPUState, pc), "PC");
 117     cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
 118                                     offsetof(CPUState, sr), "SR");
 119     cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
 120                                      offsetof(CPUState, ssr), "SSR");
 121     cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
 122                                      offsetof(CPUState, spc), "SPC");
 123     cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
 124                                      offsetof(CPUState, gbr), "GBR");
 125     cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
 126                                      offsetof(CPUState, vbr), "VBR");
 127     cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
 128                                      offsetof(CPUState, sgr), "SGR");
 129     cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
 130                                      offsetof(CPUState, dbr), "DBR");
 131     cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
 132                                       offsetof(CPUState, mach), "MACH");
 133     cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
 134                                       offsetof(CPUState, macl), "MACL");
 135     cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
 136                                     offsetof(CPUState, pr), "PR");
 137     cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
 138                                        offsetof(CPUState, fpscr), "FPSCR");
 139     cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
 140                                       offsetof(CPUState, fpul), "FPUL");
 141
 142     cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
 143                                        offsetof(CPUState, flags), "_flags_");
 144     cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
 145                                             offsetof(CPUState, delayed_pc),
 146                                             "_delayed_pc_");
 147
 148     for (i = 0; i < 32; i++)
 149         cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
 150                                               offsetof(CPUState, fregs[i]),
 151                                               fregnames[i]);
 152
 153     /* register helpers */
 154 #define GEN_HELPER 2
 155 #include "helper.h"
 156
 157     done_init = 1;
 158 }
 159
 160 void cpu_dump_state(CPUState * env, FILE * f,
 161                     int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
 162                     int flags)
 163 {
 164     int i;
 165     cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
 166                 env->pc, env->sr, env->pr, env->fpscr);
 167     cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
 168                 env->spc, env->ssr, env->gbr, env->vbr);
 169     cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
 170                 env->sgr, env->dbr, env->delayed_pc, env->fpul);
 171     for (i = 0; i < 24; i += 4) {
 172         cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
 173                     i, env->gregs[i], i + 1, env->gregs[i + 1],
 174                     i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
 175     }
 176     if (env->flags & DELAY_SLOT) {
 177         cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
 178                     env->delayed_pc);
 179     } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
 180         cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
 181                     env->delayed_pc);
 182     }
 183 }
 184
 185 static void cpu_sh4_reset(CPUSH4State * env)
 186 {
 187 #if defined(CONFIG_USER_ONLY)
 188     env->sr = 0;
 189 #else
 190     env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
 191 #endif
 192     env->vbr = 0;
 193     env->pc = 0xA0000000;
 194 #if defined(CONFIG_USER_ONLY)
 195     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
 196     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
 197 #else
 198     env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
 199     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 200 #endif
 201     env->mmucr = 0;
 202 }
 203
 204 typedef struct {
 205     const char *name;
 206     int id;
 207     uint32_t pvr;
 208     uint32_t prr;
 209     uint32_t cvr;
 210     uint32_t features;
 211 } sh4_def_t;
 212
 213 static sh4_def_t sh4_defs[] = {
 214     {
 215         .name = "SH7750R",
 216         .id = SH_CPU_SH7750R,
 217         .pvr = 0x00050000,
 218         .prr = 0x00000100,
 219         .cvr = 0x00110000,
 220     }, {
 221         .name = "SH7751R",
 222         .id = SH_CPU_SH7751R,
 223         .pvr = 0x04050005,
 224         .prr = 0x00000113,
 225         .cvr = 0x00110000,      /* Neutered caches, should be 0x20480000 */
 226     }, {
 227         .name = "SH7785",
 228         .id = SH_CPU_SH7785,
 229         .pvr = 0x10300700,
 230         .prr = 0x00000200,
 231         .cvr = 0x71440211,
 232         .features = SH_FEATURE_SH4A,
 233      },
 234 };
 235
 236 static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
 237 {
 238     int i;
 239
 240     if (strcasecmp(name, "any") == 0)
 241         return &sh4_defs[0];
 242
 243     for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
 244         if (strcasecmp(name, sh4_defs[i].name) == 0)
 245             return &sh4_defs[i];
 246
 247     return NULL;
 248 }
 249
 250 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 251 {
 252     int i;
 253
 254     for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
 255         (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
 256 }
 257
 258 static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)
 259 {
 260     env->pvr = def->pvr;
 261     env->prr = def->prr;
 262     env->cvr = def->cvr;
 263     env->id = def->id;
 264 }
 265
 266 CPUSH4State *cpu_sh4_init(const char *cpu_model)
 267 {
 268     CPUSH4State *env;
 269     const sh4_def_t *def;
 270
 271     def = cpu_sh4_find_by_name(cpu_model);
 272     if (!def)
 273         return NULL;
 274     env = qemu_mallocz(sizeof(CPUSH4State));
 275     if (!env)
 276         return NULL;
 277     env->features = def->features;
 278     cpu_exec_init(env);
 279     sh4_translate_init();
 280     env->cpu_model_str = cpu_model;
 281     cpu_sh4_reset(env);
 282     cpu_sh4_register(env, def);
 283     tlb_flush(env, 1);
 284     return env;
 285 }
 286
 287 static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
 288 {
 289     TranslationBlock *tb;
 290     tb = ctx->tb;
 291
 292     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 293         !ctx->singlestep_enabled) {
 294         /* Use a direct jump if in same page and singlestep not enabled */
 295         tcg_gen_goto_tb(n);
 296         tcg_gen_movi_i32(cpu_pc, dest);
 297         tcg_gen_exit_tb((long) tb + n);
 298     } else {
 299         tcg_gen_movi_i32(cpu_pc, dest);
 300         if (ctx->singlestep_enabled)
 301             gen_helper_debug();
 302         tcg_gen_exit_tb(0);
 303     }
 304 }
 305
 306 static void gen_jump(DisasContext * ctx)
 307 {
 308     if (ctx->delayed_pc == (uint32_t) - 1) {
 309         /* Target is not statically known, it comes necessarily from a
 310            delayed jump as immediate jump are conditinal jumps */
 311         tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
 312         if (ctx->singlestep_enabled)
 313             gen_helper_debug();
 314         tcg_gen_exit_tb(0);
 315     } else {
 316         gen_goto_tb(ctx, 0, ctx->delayed_pc);
 317     }
 318 }
 319
 320 static inline void gen_branch_slot(uint32_t delayed_pc, int t)
 321 {
 322     TCGv sr;
 323     int label = gen_new_label();
 324     tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
 325     sr = tcg_temp_new();
 326     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 327     tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
 328     tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 329     gen_set_label(label);
 330 }
 331
 332 /* Immediate conditional jump (bt or bf) */
 333 static void gen_conditional_jump(DisasContext * ctx,
 334                                  target_ulong ift, target_ulong ifnott)
 335 {
 336     int l1;
 337     TCGv sr;
 338
 339     l1 = gen_new_label();
 340     sr = tcg_temp_new();
 341     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 342     tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
 343     gen_goto_tb(ctx, 0, ifnott);
 344     gen_set_label(l1);
 345     gen_goto_tb(ctx, 1, ift);
 346 }
 347
 348 /* Delayed conditional jump (bt or bf) */
 349 static void gen_delayed_conditional_jump(DisasContext * ctx)
 350 {
 351     int l1;
 352     TCGv ds;
 353
 354     l1 = gen_new_label();
 355     ds = tcg_temp_new();
 356     tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
 357     tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
 358     gen_goto_tb(ctx, 1, ctx->pc + 2);
 359     gen_set_label(l1);
 360     tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
 361     gen_jump(ctx);
 362 }
 363
 364 static inline void gen_set_t(void)
 365 {
 366     tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 367 }
 368
 369 static inline void gen_clr_t(void)
 370 {
 371     tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 372 }
 373
 374 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
 375 {
 376     int label1 = gen_new_label();
 377     int label2 = gen_new_label();
 378     tcg_gen_brcond_i32(cond, t1, t0, label1);
 379     gen_clr_t();
 380     tcg_gen_br(label2);
 381     gen_set_label(label1);
 382     gen_set_t();
 383     gen_set_label(label2);
 384 }
 385
 386 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
 387 {
 388     int label1 = gen_new_label();
 389     int label2 = gen_new_label();
 390     tcg_gen_brcondi_i32(cond, t0, imm, label1);
 391     gen_clr_t();
 392     tcg_gen_br(label2);
 393     gen_set_label(label1);
 394     gen_set_t();
 395     gen_set_label(label2);
 396 }
 397
 398 static inline void gen_store_flags(uint32_t flags)
 399 {
 400     tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 401     tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
 402 }
 403
 404 static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
 405 {
 406     TCGv tmp = tcg_temp_new();
 407
 408     p0 &= 0x1f;
 409     p1 &= 0x1f;
 410
 411     tcg_gen_andi_i32(tmp, t1, (1 << p1));
 412     tcg_gen_andi_i32(t0, t0, ~(1 << p0));
 413     if (p0 < p1)
 414         tcg_gen_shri_i32(tmp, tmp, p1 - p0);
 415     else if (p0 > p1)
 416         tcg_gen_shli_i32(tmp, tmp, p0 - p1);
 417     tcg_gen_or_i32(t0, t0, tmp);
 418
 419     tcg_temp_free(tmp);
 420 }
 421
 422 static inline void gen_load_fpr64(TCGv_i64 t, int reg)
 423 {
 424     tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
 425 }
 426
 427 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
 428 {
 429     TCGv_i32 tmp = tcg_temp_new_i32();
 430     tcg_gen_trunc_i64_i32(tmp, t);
 431     tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
 432     tcg_gen_shri_i64(t, t, 32);
 433     tcg_gen_trunc_i64_i32(tmp, t);
 434     tcg_gen_mov_i32(cpu_fregs[reg], tmp);
 435     tcg_temp_free_i32(tmp);
 436 }
 437
 438 #define B3_0 (ctx->opcode & 0xf)
 439 #define B6_4 ((ctx->opcode >> 4) & 0x7)
 440 #define B7_4 ((ctx->opcode >> 4) & 0xf)
 441 #define B7_0 (ctx->opcode & 0xff)
 442 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
 443 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
 444   (ctx->opcode & 0xfff))
 445 #define B11_8 ((ctx->opcode >> 8) & 0xf)
 446 #define B15_12 ((ctx->opcode >> 12) & 0xf)
 447
 448 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
 449                 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 450
 451 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
 452                 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 453
 454 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
 455 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
 456 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
 457 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
 458
 459 #define CHECK_NOT_DELAY_SLOT \
 460   if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))     \
 461   {                                                           \
 462       tcg_gen_movi_i32(cpu_pc, ctx->pc-2);                    \
 463       gen_helper_raise_slot_illegal_instruction();            \
 464       ctx->bstate = BS_EXCP;                                  \
 465       return;                                                 \
 466   }
 467
 468 #define CHECK_PRIVILEGED                                      \
 469   if (IS_USER(ctx)) {                                         \
 470       tcg_gen_movi_i32(cpu_pc, ctx->pc);                      \
 471       gen_helper_raise_illegal_instruction();                 \
 472       ctx->bstate = BS_EXCP;                                  \
 473       return;                                                 \
 474   }
 475
 476 #define CHECK_FPU_ENABLED                                       \
 477   if (ctx->flags & SR_FD) {                                     \
 478       if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
 479           tcg_gen_movi_i32(cpu_pc, ctx->pc-2);                  \
 480           gen_helper_raise_slot_fpu_disable();                  \
 481       } else {                                                  \
 482           tcg_gen_movi_i32(cpu_pc, ctx->pc);                    \
 483           gen_helper_raise_fpu_disable();                       \
 484       }                                                         \
 485       ctx->bstate = BS_EXCP;                                    \
 486       return;                                                   \
 487   }
 488
 489 static void _decode_opc(DisasContext * ctx)
 490 {
 491 #if 0
 492     fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
 493 #endif
 494
 495     switch (ctx->opcode) {
 496     case 0x0019:                /* div0u */
 497         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
 498         return;
 499     case 0x000b:                /* rts */
 500         CHECK_NOT_DELAY_SLOT
 501         tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
 502         ctx->flags |= DELAY_SLOT;
 503         ctx->delayed_pc = (uint32_t) - 1;
 504         return;
 505     case 0x0028:                /* clrmac */
 506         tcg_gen_movi_i32(cpu_mach, 0);
 507         tcg_gen_movi_i32(cpu_macl, 0);
 508         return;
 509     case 0x0048:                /* clrs */
 510         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
 511         return;
 512     case 0x0008:                /* clrt */
 513         gen_clr_t();
 514         return;
 515     case 0x0038:                /* ldtlb */
 516         CHECK_PRIVILEGED
 517         gen_helper_ldtlb();
 518         return;
 519     case 0x002b:                /* rte */
 520         CHECK_PRIVILEGED
 521         CHECK_NOT_DELAY_SLOT
 522         tcg_gen_mov_i32(cpu_sr, cpu_ssr);
 523         tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
 524         ctx->flags |= DELAY_SLOT;
 525         ctx->delayed_pc = (uint32_t) - 1;
 526         return;
 527     case 0x0058:                /* sets */
 528         tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
 529         return;
 530     case 0x0018:                /* sett */
 531         gen_set_t();
 532         return;
 533     case 0xfbfd:                /* frchg */
 534         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
 535         ctx->bstate = BS_STOP;
 536         return;
 537     case 0xf3fd:                /* fschg */
 538         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
 539         ctx->bstate = BS_STOP;
 540         return;
 541     case 0x0009:                /* nop */
 542         return;
 543     case 0x001b:                /* sleep */
 544         CHECK_PRIVILEGED
 545         gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
 546         return;
 547     }
 548
 549     switch (ctx->opcode & 0xf000) {
 550     case 0x1000:                /* mov.l Rm,@(disp,Rn) */
 551         {
 552             TCGv addr = tcg_temp_new();
 553             tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
 554             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 555             tcg_temp_free(addr);
 556         }
 557         return;
 558     case 0x5000:                /* mov.l @(disp,Rm),Rn */
 559         {
 560             TCGv addr = tcg_temp_new();
 561             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
 562             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 563             tcg_temp_free(addr);
 564         }
 565         return;
 566     case 0xe000:                /* mov #imm,Rn */
 567         tcg_gen_movi_i32(REG(B11_8), B7_0s);
 568         return;
 569     case 0x9000:                /* mov.w @(disp,PC),Rn */
 570         {
 571             TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
 572             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 573             tcg_temp_free(addr);
 574         }
 575         return;
 576     case 0xd000:                /* mov.l @(disp,PC),Rn */
 577         {
 578             TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
 579             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 580             tcg_temp_free(addr);
 581         }
 582         return;
 583     case 0x7000:                /* add #imm,Rn */
 584         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
 585         return;
 586     case 0xa000:                /* bra disp */
 587         CHECK_NOT_DELAY_SLOT
 588         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 589         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 590         ctx->flags |= DELAY_SLOT;
 591         return;
 592     case 0xb000:                /* bsr disp */
 593         CHECK_NOT_DELAY_SLOT
 594         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
 595         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 596         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 597         ctx->flags |= DELAY_SLOT;
 598         return;
 599     }
 600
 601     switch (ctx->opcode & 0xf00f) {
 602     case 0x6003:                /* mov Rm,Rn */
 603         tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
 604         return;
 605     case 0x2000:                /* mov.b Rm,@Rn */
 606         tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
 607         return;
 608     case 0x2001:                /* mov.w Rm,@Rn */
 609         tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
 610         return;
 611     case 0x2002:                /* mov.l Rm,@Rn */
 612         tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
 613         return;
 614     case 0x6000:                /* mov.b @Rm,Rn */
 615         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 616         return;
 617     case 0x6001:                /* mov.w @Rm,Rn */
 618         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 619         return;
 620     case 0x6002:                /* mov.l @Rm,Rn */
 621         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 622         return;
 623     case 0x2004:                /* mov.b Rm,@-Rn */
 624         {
 625             TCGv addr = tcg_temp_new();
 626             tcg_gen_subi_i32(addr, REG(B11_8), 1);
 627             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);     /* might cause re-execution */
 628             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);        /* modify register status */
 629             tcg_temp_free(addr);
 630         }
 631         return;
 632     case 0x2005:                /* mov.w Rm,@-Rn */
 633         {
 634             TCGv addr = tcg_temp_new();
 635             tcg_gen_subi_i32(addr, REG(B11_8), 2);
 636             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 637             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
 638             tcg_temp_free(addr);
 639         }
 640         return;
 641     case 0x2006:                /* mov.l Rm,@-Rn */
 642         {
 643             TCGv addr = tcg_temp_new();
 644             tcg_gen_subi_i32(addr, REG(B11_8), 4);
 645             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 646             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
 647         }
 648         return;
 649     case 0x6004:                /* mov.b @Rm+,Rn */
 650         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 651         if ( B11_8 != B7_4 )
 652                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
 653         return;
 654     case 0x6005:                /* mov.w @Rm+,Rn */
 655         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 656         if ( B11_8 != B7_4 )
 657                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 658         return;
 659     case 0x6006:                /* mov.l @Rm+,Rn */
 660         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 661         if ( B11_8 != B7_4 )
 662                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 663         return;
 664     case 0x0004:                /* mov.b Rm,@(R0,Rn) */
 665         {
 666             TCGv addr = tcg_temp_new();
 667             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 668             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
 669             tcg_temp_free(addr);
 670         }
 671         return;
 672     case 0x0005:                /* mov.w Rm,@(R0,Rn) */
 673         {
 674             TCGv addr = tcg_temp_new();
 675             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 676             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 677             tcg_temp_free(addr);
 678         }
 679         return;
 680     case 0x0006:                /* mov.l Rm,@(R0,Rn) */
 681         {
 682             TCGv addr = tcg_temp_new();
 683             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 684             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 685             tcg_temp_free(addr);
 686         }
 687         return;
 688     case 0x000c:                /* mov.b @(R0,Rm),Rn */
 689         {
 690             TCGv addr = tcg_temp_new();
 691             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 692             tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
 693             tcg_temp_free(addr);
 694         }
 695         return;
 696     case 0x000d:                /* mov.w @(R0,Rm),Rn */
 697         {
 698             TCGv addr = tcg_temp_new();
 699             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 700             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 701             tcg_temp_free(addr);
 702         }
 703         return;
 704     case 0x000e:                /* mov.l @(R0,Rm),Rn */
 705         {
 706             TCGv addr = tcg_temp_new();
 707             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 708             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 709             tcg_temp_free(addr);
 710         }
 711         return;
 712     case 0x6008:                /* swap.b Rm,Rn */
 713         {
 714             TCGv highw, high, low;
 715             highw = tcg_temp_new();
 716             tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
 717             high = tcg_temp_new();
 718             tcg_gen_ext8u_i32(high, REG(B7_4));
 719             tcg_gen_shli_i32(high, high, 8);
 720             low = tcg_temp_new();
 721             tcg_gen_shri_i32(low, REG(B7_4), 8);
 722             tcg_gen_ext8u_i32(low, low);
 723             tcg_gen_or_i32(REG(B11_8), high, low);
 724             tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
 725             tcg_temp_free(low);
 726             tcg_temp_free(high);
 727         }
 728         return;
 729     case 0x6009:                /* swap.w Rm,Rn */
 730         {
 731             TCGv high, low;
 732             high = tcg_temp_new();
 733             tcg_gen_ext16u_i32(high, REG(B7_4));
 734             tcg_gen_shli_i32(high, high, 16);
 735             low = tcg_temp_new();
 736             tcg_gen_shri_i32(low, REG(B7_4), 16);
 737             tcg_gen_ext16u_i32(low, low);
 738             tcg_gen_or_i32(REG(B11_8), high, low);
 739             tcg_temp_free(low);
 740             tcg_temp_free(high);
 741         }
 742         return;
 743     case 0x200d:                /* xtrct Rm,Rn */
 744         {
 745             TCGv high, low;
 746             high = tcg_temp_new();
 747             tcg_gen_ext16u_i32(high, REG(B7_4));
 748             tcg_gen_shli_i32(high, high, 16);
 749             low = tcg_temp_new();
 750             tcg_gen_shri_i32(low, REG(B11_8), 16);
 751             tcg_gen_ext16u_i32(low, low);
 752             tcg_gen_or_i32(REG(B11_8), high, low);
 753             tcg_temp_free(low);
 754             tcg_temp_free(high);
 755         }
 756         return;
 757     case 0x300c:                /* add Rm,Rn */
 758         tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 759         return;
 760     case 0x300e:                /* addc Rm,Rn */
 761         gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
 762         return;
 763     case 0x300f:                /* addv Rm,Rn */
 764         gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
 765         return;
 766     case 0x2009:                /* and Rm,Rn */
 767         tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 768         return;
 769     case 0x3000:                /* cmp/eq Rm,Rn */
 770         gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
 771         return;
 772     case 0x3003:                /* cmp/ge Rm,Rn */
 773         gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
 774         return;
 775     case 0x3007:                /* cmp/gt Rm,Rn */
 776         gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
 777         return;
 778     case 0x3006:                /* cmp/hi Rm,Rn */
 779         gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
 780         return;
 781     case 0x3002:                /* cmp/hs Rm,Rn */
 782         gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
 783         return;
 784     case 0x200c:                /* cmp/str Rm,Rn */
 785         {
 786             int label1 = gen_new_label();
 787             int label2 = gen_new_label();
 788             TCGv cmp1 = tcg_temp_local_new();
 789             TCGv cmp2 = tcg_temp_local_new();
 790             tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
 791             tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
 792             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 793             tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
 794             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 795             tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
 796             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 797             tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
 798             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 799             tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 800             tcg_gen_br(label2);
 801             gen_set_label(label1);
 802             tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 803             gen_set_label(label2);
 804             tcg_temp_free(cmp2);
 805             tcg_temp_free(cmp1);
 806         }
 807         return;
 808     case 0x2007:                /* div0s Rm,Rn */
 809         {
 810             gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31);        /* SR_Q */
 811             gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31);         /* SR_M */
 812             TCGv val = tcg_temp_new();
 813             tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
 814             gen_copy_bit_i32(cpu_sr, 0, val, 31);               /* SR_T */
 815             tcg_temp_free(val);
 816         }
 817         return;
 818     case 0x3004:                /* div1 Rm,Rn */
 819         gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
 820         return;
 821     case 0x300d:                /* dmuls.l Rm,Rn */
 822         {
 823             TCGv_i64 tmp1 = tcg_temp_new_i64();
 824             TCGv_i64 tmp2 = tcg_temp_new_i64();
 825
 826             tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
 827             tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
 828             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 829             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 830             tcg_gen_shri_i64(tmp1, tmp1, 32);
 831             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 832
 833             tcg_temp_free_i64(tmp2);
 834             tcg_temp_free_i64(tmp1);
 835         }
 836         return;
 837     case 0x3005:                /* dmulu.l Rm,Rn */
 838         {
 839             TCGv_i64 tmp1 = tcg_temp_new_i64();
 840             TCGv_i64 tmp2 = tcg_temp_new_i64();
 841
 842             tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
 843             tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
 844             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 845             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 846             tcg_gen_shri_i64(tmp1, tmp1, 32);
 847             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 848
 849             tcg_temp_free_i64(tmp2);
 850             tcg_temp_free_i64(tmp1);
 851         }
 852         return;
 853     case 0x600e:                /* exts.b Rm,Rn */
 854         tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
 855         return;
 856     case 0x600f:                /* exts.w Rm,Rn */
 857         tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
 858         return;
 859     case 0x600c:                /* extu.b Rm,Rn */
 860         tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
 861         return;
 862     case 0x600d:                /* extu.w Rm,Rn */
 863         tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
 864         return;
 865     case 0x000f:                /* mac.l @Rm+,@Rn+ */
 866         {
 867             TCGv arg0, arg1;
 868             arg0 = tcg_temp_new();
 869             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 870             arg1 = tcg_temp_new();
 871             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 872             gen_helper_macl(arg0, arg1);
 873             tcg_temp_free(arg1);
 874             tcg_temp_free(arg0);
 875             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 876             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
 877         }
 878         return;
 879     case 0x400f:                /* mac.w @Rm+,@Rn+ */
 880         {
 881             TCGv arg0, arg1;
 882             arg0 = tcg_temp_new();
 883             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 884             arg1 = tcg_temp_new();
 885             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 886             gen_helper_macw(arg0, arg1);
 887             tcg_temp_free(arg1);
 888             tcg_temp_free(arg0);
 889             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
 890             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 891         }
 892         return;
 893     case 0x0007:                /* mul.l Rm,Rn */
 894         tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
 895         return;
 896     case 0x200f:                /* muls.w Rm,Rn */
 897         {
 898             TCGv arg0, arg1;
 899             arg0 = tcg_temp_new();
 900             tcg_gen_ext16s_i32(arg0, REG(B7_4));
 901             arg1 = tcg_temp_new();
 902             tcg_gen_ext16s_i32(arg1, REG(B11_8));
 903             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 904             tcg_temp_free(arg1);
 905             tcg_temp_free(arg0);
 906         }
 907         return;
 908     case 0x200e:                /* mulu.w Rm,Rn */
 909         {
 910             TCGv arg0, arg1;
 911             arg0 = tcg_temp_new();
 912             tcg_gen_ext16u_i32(arg0, REG(B7_4));
 913             arg1 = tcg_temp_new();
 914             tcg_gen_ext16u_i32(arg1, REG(B11_8));
 915             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 916             tcg_temp_free(arg1);
 917             tcg_temp_free(arg0);
 918         }
 919         return;
 920     case 0x600b:                /* neg Rm,Rn */
 921         tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
 922         return;
 923     case 0x600a:                /* negc Rm,Rn */
 924         gen_helper_negc(REG(B11_8), REG(B7_4));
 925         return;
 926     case 0x6007:                /* not Rm,Rn */
 927         tcg_gen_not_i32(REG(B11_8), REG(B7_4));
 928         return;
 929     case 0x200b:                /* or Rm,Rn */
 930         tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 931         return;
 932     case 0x400c:                /* shad Rm,Rn */
 933         {
 934             int label1 = gen_new_label();
 935             int label2 = gen_new_label();
 936             int label3 = gen_new_label();
 937             int label4 = gen_new_label();
 938             TCGv shift = tcg_temp_local_new();
 939             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 940             /* Rm positive, shift to the left */
 941             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 942             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 943             tcg_gen_br(label4);
 944             /* Rm negative, shift to the right */
 945             gen_set_label(label1);
 946             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 947             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 948             tcg_gen_not_i32(shift, REG(B7_4));
 949             tcg_gen_andi_i32(shift, shift, 0x1f);
 950             tcg_gen_addi_i32(shift, shift, 1);
 951             tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
 952             tcg_gen_br(label4);
 953             /* Rm = -32 */
 954             gen_set_label(label2);
 955             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
 956             tcg_gen_movi_i32(REG(B11_8), 0);
 957             tcg_gen_br(label4);
 958             gen_set_label(label3);
 959             tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
 960             gen_set_label(label4);
 961             tcg_temp_free(shift);
 962         }
 963         return;
 964     case 0x400d:                /* shld Rm,Rn */
 965         {
 966             int label1 = gen_new_label();
 967             int label2 = gen_new_label();
 968             int label3 = gen_new_label();
 969             TCGv shift = tcg_temp_local_new();
 970             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 971             /* Rm positive, shift to the left */
 972             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 973             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 974             tcg_gen_br(label3);
 975             /* Rm negative, shift to the right */
 976             gen_set_label(label1);
 977             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 978             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 979             tcg_gen_not_i32(shift, REG(B7_4));
 980             tcg_gen_andi_i32(shift, shift, 0x1f);
 981             tcg_gen_addi_i32(shift, shift, 1);
 982             tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
 983             tcg_gen_br(label3);
 984             /* Rm = -32 */
 985             gen_set_label(label2);
 986             tcg_gen_movi_i32(REG(B11_8), 0);
 987             gen_set_label(label3);
 988             tcg_temp_free(shift);
 989         }
 990         return;
 991     case 0x3008:                /* sub Rm,Rn */
 992         tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 993         return;
 994     case 0x300a:                /* subc Rm,Rn */
 995         gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
 996         return;
 997     case 0x300b:                /* subv Rm,Rn */
 998         gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
 999         return;
1000     case 0x2008:                /* tst Rm,Rn */
1001         {
1002             TCGv val = tcg_temp_new();
1003             tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
1004             gen_cmp_imm(TCG_COND_EQ, val, 0);
1005             tcg_temp_free(val);
1006         }
1007         return;
1008     case 0x200a:                /* xor Rm,Rn */
1009         tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
1010         return;
1011     case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
1012         CHECK_FPU_ENABLED
1013         if (ctx->fpscr & FPSCR_SZ) {
1014             TCGv_i64 fp = tcg_temp_new_i64();
1015             gen_load_fpr64(fp, XREG(B7_4));
1016             gen_store_fpr64(fp, XREG(B11_8));
1017             tcg_temp_free_i64(fp);
1018         } else {
1019             tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1020         }
1021         return;
1022     case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
1023         CHECK_FPU_ENABLED
1024         if (ctx->fpscr & FPSCR_SZ) {
1025             TCGv addr_hi = tcg_temp_new();
1026             int fr = XREG(B7_4);
1027             tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
1028             tcg_gen_qemu_st32(cpu_fregs[fr  ], REG(B11_8), ctx->memidx);
1029             tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi,    ctx->memidx);
1030             tcg_temp_free(addr_hi);
1031         } else {
1032             tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
1033         }
1034         return;
1035     case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1036         CHECK_FPU_ENABLED
1037         if (ctx->fpscr & FPSCR_SZ) {
1038             TCGv addr_hi = tcg_temp_new();
1039             int fr = XREG(B11_8);
1040             tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1041             tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);
1042             tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);
1043             tcg_temp_free(addr_hi);
1044         } else {
1045             tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1046         }
1047         return;
1048     case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1049         CHECK_FPU_ENABLED
1050         if (ctx->fpscr & FPSCR_SZ) {
1051             TCGv addr_hi = tcg_temp_new();
1052             int fr = XREG(B11_8);
1053             tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1054             tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);
1055             tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);
1056             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
1057             tcg_temp_free(addr_hi);
1058         } else {
1059             tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1060             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1061         }
1062         return;
1063     case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1064         CHECK_FPU_ENABLED
1065         if (ctx->fpscr & FPSCR_SZ) {
1066             TCGv addr = tcg_temp_new_i32();
1067             int fr = XREG(B7_4);
1068             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1069             tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
1070             tcg_gen_subi_i32(addr, REG(B11_8), 8);
1071             tcg_gen_qemu_st32(cpu_fregs[fr  ], addr, ctx->memidx);
1072             tcg_gen_mov_i32(REG(B11_8), addr);
1073             tcg_temp_free(addr);
1074         } else {
1075             TCGv addr;
1076             addr = tcg_temp_new_i32();
1077             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1078             tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1079             tcg_temp_free(addr);
1080             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1081         }
1082         return;
1083     case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1084         CHECK_FPU_ENABLED
1085         {
1086             TCGv addr = tcg_temp_new_i32();
1087             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
1088             if (ctx->fpscr & FPSCR_SZ) {
1089                 int fr = XREG(B11_8);
1090                 tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
1091                 tcg_gen_addi_i32(addr, addr, 4);
1092                 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1093             } else {
1094                 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
1095             }
1096             tcg_temp_free(addr);
1097         }
1098         return;
1099     case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1100         CHECK_FPU_ENABLED
1101         {
1102             TCGv addr = tcg_temp_new();
1103             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
1104             if (ctx->fpscr & FPSCR_SZ) {
1105                 int fr = XREG(B7_4);
1106                 tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
1107                 tcg_gen_addi_i32(addr, addr, 4);
1108                 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1109             } else {
1110                 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1111             }
1112             tcg_temp_free(addr);
1113         }
1114         return;
1115     case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1116     case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1117     case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1118     case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1119     case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1120     case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1121         {
1122             CHECK_FPU_ENABLED
1123             if (ctx->fpscr & FPSCR_PR) {
1124                 TCGv_i64 fp0, fp1;
1125
1126                 if (ctx->opcode & 0x0110)
1127                     break; /* illegal instruction */
1128                 fp0 = tcg_temp_new_i64();
1129                 fp1 = tcg_temp_new_i64();
1130                 gen_load_fpr64(fp0, DREG(B11_8));
1131                 gen_load_fpr64(fp1, DREG(B7_4));
1132                 switch (ctx->opcode & 0xf00f) {
1133                 case 0xf000:            /* fadd Rm,Rn */
1134                     gen_helper_fadd_DT(fp0, fp0, fp1);
1135                     break;
1136                 case 0xf001:            /* fsub Rm,Rn */
1137                     gen_helper_fsub_DT(fp0, fp0, fp1);
1138                     break;
1139                 case 0xf002:            /* fmul Rm,Rn */
1140                     gen_helper_fmul_DT(fp0, fp0, fp1);
1141                     break;
1142                 case 0xf003:            /* fdiv Rm,Rn */
1143                     gen_helper_fdiv_DT(fp0, fp0, fp1);
1144                     break;
1145                 case 0xf004:            /* fcmp/eq Rm,Rn */
1146                     gen_helper_fcmp_eq_DT(fp0, fp1);
1147                     return;
1148                 case 0xf005:            /* fcmp/gt Rm,Rn */
1149                     gen_helper_fcmp_gt_DT(fp0, fp1);
1150                     return;
1151                 }
1152                 gen_store_fpr64(fp0, DREG(B11_8));
1153                 tcg_temp_free_i64(fp0);
1154                 tcg_temp_free_i64(fp1);
1155             } else {
1156                 switch (ctx->opcode & 0xf00f) {
1157                 case 0xf000:            /* fadd Rm,Rn */
1158                     gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1159                     break;
1160                 case 0xf001:            /* fsub Rm,Rn */
1161                     gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1162                     break;
1163                 case 0xf002:            /* fmul Rm,Rn */
1164                     gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1165                     break;
1166                 case 0xf003:            /* fdiv Rm,Rn */
1167                     gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1168                     break;
1169                 case 0xf004:            /* fcmp/eq Rm,Rn */
1170                     gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1171                     return;
1172                 case 0xf005:            /* fcmp/gt Rm,Rn */
1173                     gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1174                     return;
1175                 }
1176             }
1177         }
1178         return;
1179     case 0xf00e: /* fmac FR0,RM,Rn */
1180         {
1181             CHECK_FPU_ENABLED
1182             if (ctx->fpscr & FPSCR_PR) {
1183                 break; /* illegal instruction */
1184             } else {
1185                 gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
1186                                    cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
1187                 return;
1188             }
1189         }
1190     }
1191
1192     switch (ctx->opcode & 0xff00) {
1193     case 0xc900:                /* and #imm,R0 */
1194         tcg_gen_andi_i32(REG(0), REG(0), B7_0);
1195         return;
1196     case 0xcd00:                /* and.b #imm,@(R0,GBR) */
1197         {
1198             TCGv addr, val;
1199             addr = tcg_temp_new();
1200             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1201             val = tcg_temp_new();
1202             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1203             tcg_gen_andi_i32(val, val, B7_0);
1204             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1205             tcg_temp_free(val);
1206             tcg_temp_free(addr);
1207         }
1208         return;
1209     case 0x8b00:                /* bf label */
1210         CHECK_NOT_DELAY_SLOT
1211             gen_conditional_jump(ctx, ctx->pc + 2,
1212                                  ctx->pc + 4 + B7_0s * 2);
1213         ctx->bstate = BS_BRANCH;
1214         return;
1215     case 0x8f00:                /* bf/s label */
1216         CHECK_NOT_DELAY_SLOT
1217         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
1218         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1219         return;
1220     case 0x8900:                /* bt label */
1221         CHECK_NOT_DELAY_SLOT
1222             gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
1223                                  ctx->pc + 2);
1224         ctx->bstate = BS_BRANCH;
1225         return;
1226     case 0x8d00:                /* bt/s label */
1227         CHECK_NOT_DELAY_SLOT
1228         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
1229         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1230         return;
1231     case 0x8800:                /* cmp/eq #imm,R0 */
1232         gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
1233         return;
1234     case 0xc400:                /* mov.b @(disp,GBR),R0 */
1235         {
1236             TCGv addr = tcg_temp_new();
1237             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1238             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1239             tcg_temp_free(addr);
1240         }
1241         return;
1242     case 0xc500:                /* mov.w @(disp,GBR),R0 */
1243         {
1244             TCGv addr = tcg_temp_new();
1245             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1246             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1247             tcg_temp_free(addr);
1248         }
1249         return;
1250     case 0xc600:                /* mov.l @(disp,GBR),R0 */
1251         {
1252             TCGv addr = tcg_temp_new();
1253             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1254             tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
1255             tcg_temp_free(addr);
1256         }
1257         return;
1258     case 0xc000:                /* mov.b R0,@(disp,GBR) */
1259         {
1260             TCGv addr = tcg_temp_new();
1261             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1262             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1263             tcg_temp_free(addr);
1264         }
1265         return;
1266     case 0xc100:                /* mov.w R0,@(disp,GBR) */
1267         {
1268             TCGv addr = tcg_temp_new();
1269             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1270             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1271             tcg_temp_free(addr);
1272         }
1273         return;
1274     case 0xc200:                /* mov.l R0,@(disp,GBR) */
1275         {
1276             TCGv addr = tcg_temp_new();
1277             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1278             tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
1279             tcg_temp_free(addr);
1280         }
1281         return;
1282     case 0x8000:                /* mov.b R0,@(disp,Rn) */
1283         {
1284             TCGv addr = tcg_temp_new();
1285             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1286             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1287             tcg_temp_free(addr);
1288         }
1289         return;
1290     case 0x8100:                /* mov.w R0,@(disp,Rn) */
1291         {
1292             TCGv addr = tcg_temp_new();
1293             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1294             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1295             tcg_temp_free(addr);
1296         }
1297         return;
1298     case 0x8400:                /* mov.b @(disp,Rn),R0 */
1299         {
1300             TCGv addr = tcg_temp_new();
1301             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1302             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1303             tcg_temp_free(addr);
1304         }
1305         return;
1306     case 0x8500:                /* mov.w @(disp,Rn),R0 */
1307         {
1308             TCGv addr = tcg_temp_new();
1309             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1310             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1311             tcg_temp_free(addr);
1312         }
1313         return;
1314     case 0xc700:                /* mova @(disp,PC),R0 */
1315         tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
1316         return;
1317     case 0xcb00:                /* or #imm,R0 */
1318         tcg_gen_ori_i32(REG(0), REG(0), B7_0);
1319         return;
1320     case 0xcf00:                /* or.b #imm,@(R0,GBR) */
1321         {
1322             TCGv addr, val;
1323             addr = tcg_temp_new();
1324             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1325             val = tcg_temp_new();
1326             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1327             tcg_gen_ori_i32(val, val, B7_0);
1328             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1329             tcg_temp_free(val);
1330             tcg_temp_free(addr);
1331         }
1332         return;
1333     case 0xc300:                /* trapa #imm */
1334         {
1335             TCGv imm;
1336             CHECK_NOT_DELAY_SLOT
1337             tcg_gen_movi_i32(cpu_pc, ctx->pc);
1338             imm = tcg_const_i32(B7_0);
1339             gen_helper_trapa(imm);
1340             tcg_temp_free(imm);
1341             ctx->bstate = BS_BRANCH;
1342         }
1343         return;
1344     case 0xc800:                /* tst #imm,R0 */
1345         {
1346             TCGv val = tcg_temp_new();
1347             tcg_gen_andi_i32(val, REG(0), B7_0);
1348             gen_cmp_imm(TCG_COND_EQ, val, 0);
1349             tcg_temp_free(val);
1350         }
1351         return;
1352     case 0xcc00:                /* tst.b #imm,@(R0,GBR) */
1353         {
1354             TCGv val = tcg_temp_new();
1355             tcg_gen_add_i32(val, REG(0), cpu_gbr);
1356             tcg_gen_qemu_ld8u(val, val, ctx->memidx);
1357             tcg_gen_andi_i32(val, val, B7_0);
1358             gen_cmp_imm(TCG_COND_EQ, val, 0);
1359             tcg_temp_free(val);
1360         }
1361         return;
1362     case 0xca00:                /* xor #imm,R0 */
1363         tcg_gen_xori_i32(REG(0), REG(0), B7_0);
1364         return;
1365     case 0xce00:                /* xor.b #imm,@(R0,GBR) */
1366         {
1367             TCGv addr, val;
1368             addr = tcg_temp_new();
1369             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1370             val = tcg_temp_new();
1371             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1372             tcg_gen_xori_i32(val, val, B7_0);
1373             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1374             tcg_temp_free(val);
1375             tcg_temp_free(addr);
1376         }
1377         return;
1378     }
1379
1380     switch (ctx->opcode & 0xf08f) {
1381     case 0x408e:                /* ldc Rm,Rn_BANK */
1382         CHECK_PRIVILEGED
1383         tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));
1384         return;
1385     case 0x4087:                /* ldc.l @Rm+,Rn_BANK */
1386         CHECK_PRIVILEGED
1387         tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
1388         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1389         return;
1390     case 0x0082:                /* stc Rm_BANK,Rn */
1391         CHECK_PRIVILEGED
1392         tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));
1393         return;
1394     case 0x4083:                /* stc.l Rm_BANK,@-Rn */
1395         CHECK_PRIVILEGED
1396         {
1397             TCGv addr = tcg_temp_new();
1398             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1399             tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
1400             tcg_temp_free(addr);
1401             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1402         }
1403         return;
1404     }
1405
1406     switch (ctx->opcode & 0xf0ff) {
1407     case 0x0023:                /* braf Rn */
1408         CHECK_NOT_DELAY_SLOT
1409         tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
1410         ctx->flags |= DELAY_SLOT;
1411         ctx->delayed_pc = (uint32_t) - 1;
1412         return;
1413     case 0x0003:                /* bsrf Rn */
1414         CHECK_NOT_DELAY_SLOT
1415         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1416         tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
1417         ctx->flags |= DELAY_SLOT;
1418         ctx->delayed_pc = (uint32_t) - 1;
1419         return;
1420     case 0x4015:                /* cmp/pl Rn */
1421         gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
1422         return;
1423     case 0x4011:                /* cmp/pz Rn */
1424         gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
1425         return;
1426     case 0x4010:                /* dt Rn */
1427         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
1428         gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
1429         return;
1430     case 0x402b:                /* jmp @Rn */
1431         CHECK_NOT_DELAY_SLOT
1432         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1433         ctx->flags |= DELAY_SLOT;
1434         ctx->delayed_pc = (uint32_t) - 1;
1435         return;
1436     case 0x400b:                /* jsr @Rn */
1437         CHECK_NOT_DELAY_SLOT
1438         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1439         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1440         ctx->flags |= DELAY_SLOT;
1441         ctx->delayed_pc = (uint32_t) - 1;
1442         return;
1443     case 0x400e:                /* ldc Rm,SR */
1444         CHECK_PRIVILEGED
1445         tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
1446         ctx->bstate = BS_STOP;
1447         return;
1448     case 0x4007:                /* ldc.l @Rm+,SR */
1449         CHECK_PRIVILEGED
1450         {
1451             TCGv val = tcg_temp_new();
1452             tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
1453             tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
1454             tcg_temp_free(val);
1455             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1456             ctx->bstate = BS_STOP;
1457         }
1458         return;
1459     case 0x0002:                /* stc SR,Rn */
1460         CHECK_PRIVILEGED
1461         tcg_gen_mov_i32(REG(B11_8), cpu_sr);
1462         return;
1463     case 0x4003:                /* stc SR,@-Rn */
1464         CHECK_PRIVILEGED
1465         {
1466             TCGv addr = tcg_temp_new();
1467             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1468             tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
1469             tcg_temp_free(addr);
1470             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1471         }
1472         return;
1473 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk)              \
1474   case ldnum:                                                   \
1475     prechk                                                      \
1476     tcg_gen_mov_i32 (cpu_##reg, REG(B11_8));                    \
1477     return;                                                     \
1478   case ldpnum:                                                  \
1479     prechk                                                      \
1480     tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx);    \
1481     tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);                \
1482     return;                                                     \
1483   case stnum:                                                   \
1484     prechk                                                      \
1485     tcg_gen_mov_i32 (REG(B11_8), cpu_##reg);                    \
1486     return;                                                     \
1487   case stpnum:                                                  \
1488     prechk                                                      \
1489     {                                                           \
1490         TCGv addr = tcg_temp_new();                     \
1491         tcg_gen_subi_i32(addr, REG(B11_8), 4);                  \
1492         tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx);       \
1493         tcg_temp_free(addr);                                    \
1494         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);            \
1495     }                                                           \
1496     return;
1497         LDST(gbr,  0x401e, 0x4017, 0x0012, 0x4013, {})
1498         LDST(vbr,  0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
1499         LDST(ssr,  0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
1500         LDST(spc,  0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
1501         LDST(dbr,  0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
1502         LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
1503         LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
1504         LDST(pr,   0x402a, 0x4026, 0x002a, 0x4022, {})
1505         LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
1506     case 0x406a:                /* lds Rm,FPSCR */
1507         CHECK_FPU_ENABLED
1508         gen_helper_ld_fpscr(REG(B11_8));
1509         ctx->bstate = BS_STOP;
1510         return;
1511     case 0x4066:                /* lds.l @Rm+,FPSCR */
1512         CHECK_FPU_ENABLED
1513         {
1514             TCGv addr = tcg_temp_new();
1515             tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
1516             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1517             gen_helper_ld_fpscr(addr);
1518             tcg_temp_free(addr);
1519             ctx->bstate = BS_STOP;
1520         }
1521         return;
1522     case 0x006a:                /* sts FPSCR,Rn */
1523         CHECK_FPU_ENABLED
1524         tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
1525         return;
1526     case 0x4062:                /* sts FPSCR,@-Rn */
1527         CHECK_FPU_ENABLED
1528         {
1529             TCGv addr, val;
1530             val = tcg_temp_new();
1531             tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
1532             addr = tcg_temp_new();
1533             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1534             tcg_gen_qemu_st32(val, addr, ctx->memidx);
1535             tcg_temp_free(addr);
1536             tcg_temp_free(val);
1537             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1538         }
1539         return;
1540     case 0x00c3:                /* movca.l R0,@Rm */
1541         tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1542         return;
1543     case 0x40a9:
1544         /* MOVUA.L @Rm,R0 (Rm) -> R0
1545            Load non-boundary-aligned data */
1546         tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1547         return;
1548     case 0x40e9:
1549         /* MOVUA.L @Rm+,R0   (Rm) -> R0, Rm + 4 -> Rm
1550            Load non-boundary-aligned data */
1551         tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1552         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1553         return;
1554     case 0x0029:                /* movt Rn */
1555         tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1556         return;
1557     case 0x0093:                /* ocbi @Rn */
1558         {
1559             TCGv dummy = tcg_temp_new();
1560             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1561             tcg_temp_free(dummy);
1562         }
1563         return;
1564     case 0x00a3:                /* ocbp @Rn */
1565         {
1566             TCGv dummy = tcg_temp_new();
1567             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1568             tcg_temp_free(dummy);
1569         }
1570         return;
1571     case 0x00b3:                /* ocbwb @Rn */
1572         {
1573             TCGv dummy = tcg_temp_new();
1574             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1575             tcg_temp_free(dummy);
1576         }
1577         return;
1578     case 0x0083:                /* pref @Rn */
1579         return;
1580     case 0x00d3:                /* prefi @Rn */
1581         if (ctx->features & SH_FEATURE_SH4A)
1582             return;
1583         else
1584             break;
1585     case 0x00e3:                /* icbi @Rn */
1586         if (ctx->features & SH_FEATURE_SH4A)
1587             return;
1588         else
1589             break;
1590     case 0x00ab:                /* synco */
1591         if (ctx->features & SH_FEATURE_SH4A)
1592             return;
1593         else
1594             break;
1595     case 0x4024:                /* rotcl Rn */
1596         {
1597             TCGv tmp = tcg_temp_new();
1598             tcg_gen_mov_i32(tmp, cpu_sr);
1599             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1600             tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1601             gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
1602             tcg_temp_free(tmp);
1603         }
1604         return;
1605     case 0x4025:                /* rotcr Rn */
1606         {
1607             TCGv tmp = tcg_temp_new();
1608             tcg_gen_mov_i32(tmp, cpu_sr);
1609             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1610             tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1611             gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
1612             tcg_temp_free(tmp);
1613         }
1614         return;
1615     case 0x4004:                /* rotl Rn */
1616         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1617         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1618         gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
1619         return;
1620     case 0x4005:                /* rotr Rn */
1621         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1622         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1623         gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
1624         return;
1625     case 0x4000:                /* shll Rn */
1626     case 0x4020:                /* shal Rn */
1627         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1628         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1629         return;
1630     case 0x4021:                /* shar Rn */
1631         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1632         tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
1633         return;
1634     case 0x4001:                /* shlr Rn */
1635         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1636         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1637         return;
1638     case 0x4008:                /* shll2 Rn */
1639         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
1640         return;
1641     case 0x4018:                /* shll8 Rn */
1642         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
1643         return;
1644     case 0x4028:                /* shll16 Rn */
1645         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
1646         return;
1647     case 0x4009:                /* shlr2 Rn */
1648         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
1649         return;
1650     case 0x4019:                /* shlr8 Rn */
1651         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
1652         return;
1653     case 0x4029:                /* shlr16 Rn */
1654         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
1655         return;
1656     case 0x401b:                /* tas.b @Rn */
1657         {
1658             TCGv addr, val;
1659             addr = tcg_temp_local_new();
1660             tcg_gen_mov_i32(addr, REG(B11_8));
1661             val = tcg_temp_local_new();
1662             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1663             gen_cmp_imm(TCG_COND_EQ, val, 0);
1664             tcg_gen_ori_i32(val, val, 0x80);
1665             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1666             tcg_temp_free(val);
1667             tcg_temp_free(addr);
1668         }
1669         return;
1670     case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1671         CHECK_FPU_ENABLED
1672         tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
1673         return;
1674     case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1675         CHECK_FPU_ENABLED
1676         tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1677         return;
1678     case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1679         CHECK_FPU_ENABLED
1680         if (ctx->fpscr & FPSCR_PR) {
1681             TCGv_i64 fp;
1682             if (ctx->opcode & 0x0100)
1683                 break; /* illegal instruction */
1684             fp = tcg_temp_new_i64();
1685             gen_helper_float_DT(fp, cpu_fpul);
1686             gen_store_fpr64(fp, DREG(B11_8));
1687             tcg_temp_free_i64(fp);
1688         }
1689         else {
1690             gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
1691         }
1692         return;
1693     case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1694         CHECK_FPU_ENABLED
1695         if (ctx->fpscr & FPSCR_PR) {
1696             TCGv_i64 fp;
1697             if (ctx->opcode & 0x0100)
1698                 break; /* illegal instruction */
1699             fp = tcg_temp_new_i64();
1700             gen_load_fpr64(fp, DREG(B11_8));
1701             gen_helper_ftrc_DT(cpu_fpul, fp);
1702             tcg_temp_free_i64(fp);
1703         }
1704         else {
1705             gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1706         }
1707         return;
1708     case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1709         CHECK_FPU_ENABLED
1710         {
1711             gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1712         }
1713         return;
1714     case 0xf05d: /* fabs FRn/DRn */
1715         CHECK_FPU_ENABLED
1716         if (ctx->fpscr & FPSCR_PR) {
1717             if (ctx->opcode & 0x0100)
1718                 break; /* illegal instruction */
1719             TCGv_i64 fp = tcg_temp_new_i64();
1720             gen_load_fpr64(fp, DREG(B11_8));
1721             gen_helper_fabs_DT(fp, fp);
1722             gen_store_fpr64(fp, DREG(B11_8));
1723             tcg_temp_free_i64(fp);
1724         } else {
1725             gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1726         }
1727         return;
1728     case 0xf06d: /* fsqrt FRn */
1729         CHECK_FPU_ENABLED
1730         if (ctx->fpscr & FPSCR_PR) {
1731             if (ctx->opcode & 0x0100)
1732                 break; /* illegal instruction */
1733             TCGv_i64 fp = tcg_temp_new_i64();
1734             gen_load_fpr64(fp, DREG(B11_8));
1735             gen_helper_fsqrt_DT(fp, fp);
1736             gen_store_fpr64(fp, DREG(B11_8));
1737             tcg_temp_free_i64(fp);
1738         } else {
1739             gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1740         }
1741         return;
1742     case 0xf07d: /* fsrra FRn */
1743         CHECK_FPU_ENABLED
1744         break;
1745     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1746         CHECK_FPU_ENABLED
1747         if (!(ctx->fpscr & FPSCR_PR)) {
1748             tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
1749         }
1750         return;
1751     case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1752         CHECK_FPU_ENABLED
1753         if (!(ctx->fpscr & FPSCR_PR)) {
1754             tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
1755         }
1756         return;
1757     case 0xf0ad: /* fcnvsd FPUL,DRn */
1758         CHECK_FPU_ENABLED
1759         {
1760             TCGv_i64 fp = tcg_temp_new_i64();
1761             gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
1762             gen_store_fpr64(fp, DREG(B11_8));
1763             tcg_temp_free_i64(fp);
1764         }
1765         return;
1766     case 0xf0bd: /* fcnvds DRn,FPUL */
1767         CHECK_FPU_ENABLED
1768         {
1769             TCGv_i64 fp = tcg_temp_new_i64();
1770             gen_load_fpr64(fp, DREG(B11_8));
1771             gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
1772             tcg_temp_free_i64(fp);
1773         }
1774         return;
1775     }
1776 #if 0
1777     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
1778             ctx->opcode, ctx->pc);
1779     fflush(stderr);
1780 #endif
1781     gen_helper_raise_illegal_instruction();
1782     ctx->bstate = BS_EXCP;
1783 }
1784
1785 static void decode_opc(DisasContext * ctx)
1786 {
1787     uint32_t old_flags = ctx->flags;
1788
1789     _decode_opc(ctx);
1790
1791     if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1792         if (ctx->flags & DELAY_SLOT_CLEARME) {
1793             gen_store_flags(0);
1794         } else {
1795             /* go out of the delay slot */
1796             uint32_t new_flags = ctx->flags;
1797             new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
1798             gen_store_flags(new_flags);
1799         }
1800         ctx->flags = 0;
1801         ctx->bstate = BS_BRANCH;
1802         if (old_flags & DELAY_SLOT_CONDITIONAL) {
1803             gen_delayed_conditional_jump(ctx);
1804         } else if (old_flags & DELAY_SLOT) {
1805             gen_jump(ctx);
1806         }
1807
1808     }
1809
1810     /* go into a delay slot */
1811     if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
1812         gen_store_flags(ctx->flags);
1813 }
1814
1815 static inline void
1816 gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1817                                int search_pc)
1818 {
1819     DisasContext ctx;
1820     target_ulong pc_start;
1821     static uint16_t *gen_opc_end;
1822     CPUBreakpoint *bp;
1823     int i, ii;
1824     int num_insns;
1825     int max_insns;
1826
1827     pc_start = tb->pc;
1828     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1829     ctx.pc = pc_start;
1830     ctx.flags = (uint32_t)tb->flags;
1831     ctx.bstate = BS_NONE;
1832     ctx.sr = env->sr;
1833     ctx.fpscr = env->fpscr;
1834     ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
1835     /* We don't know if the delayed pc came from a dynamic or static branch,
1836        so assume it is a dynamic branch.  */
1837     ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1838     ctx.tb = tb;
1839     ctx.singlestep_enabled = env->singlestep_enabled;
1840     ctx.features = env->features;
1841
1842 #ifdef DEBUG_DISAS
1843     qemu_log_mask(CPU_LOG_TB_CPU,
1844                  "------------------------------------------------\n");
1845     log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
1846 #endif
1847
1848     ii = -1;
1849     num_insns = 0;
1850     max_insns = tb->cflags & CF_COUNT_MASK;
1851     if (max_insns == 0)
1852         max_insns = CF_COUNT_MASK;
1853     gen_icount_start();
1854     while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1855         if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
1856             TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1857                 if (ctx.pc == bp->pc) {
1858                     /* We have hit a breakpoint - make sure PC is up-to-date */
1859                     tcg_gen_movi_i32(cpu_pc, ctx.pc);
1860                     gen_helper_debug();
1861                     ctx.bstate = BS_EXCP;
1862                     break;
1863                 }
1864             }
1865         }
1866         if (search_pc) {
1867             i = gen_opc_ptr - gen_opc_buf;
1868             if (ii < i) {
1869                 ii++;
1870                 while (ii < i)
1871                     gen_opc_instr_start[ii++] = 0;
1872             }
1873             gen_opc_pc[ii] = ctx.pc;
1874             gen_opc_hflags[ii] = ctx.flags;
1875             gen_opc_instr_start[ii] = 1;
1876             gen_opc_icount[ii] = num_insns;
1877         }
1878         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1879             gen_io_start();
1880 #if 0
1881         fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
1882         fflush(stderr);
1883 #endif
1884         ctx.opcode = lduw_code(ctx.pc);
1885         decode_opc(&ctx);
1886         num_insns++;
1887         ctx.pc += 2;
1888         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1889             break;
1890         if (env->singlestep_enabled)
1891             break;
1892         if (num_insns >= max_insns)
1893             break;
1894 #ifdef SH4_SINGLE_STEP
1895         break;
1896 #endif
1897     }
1898     if (tb->cflags & CF_LAST_IO)
1899         gen_io_end();
1900     if (env->singlestep_enabled) {
1901         tcg_gen_movi_i32(cpu_pc, ctx.pc);
1902         gen_helper_debug();
1903     } else {
1904         switch (ctx.bstate) {
1905         case BS_STOP:
1906             /* gen_op_interrupt_restart(); */
1907             /* fall through */
1908         case BS_NONE:
1909             if (ctx.flags) {
1910                 gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
1911             }
1912             gen_goto_tb(&ctx, 0, ctx.pc);
1913             break;
1914         case BS_EXCP:
1915             /* gen_op_interrupt_restart(); */
1916             tcg_gen_exit_tb(0);
1917             break;
1918         case BS_BRANCH:
1919         default:
1920             break;
1921         }
1922     }
1923
1924     gen_icount_end(tb, num_insns);
1925     *gen_opc_ptr = INDEX_op_end;
1926     if (search_pc) {
1927         i = gen_opc_ptr - gen_opc_buf;
1928         ii++;
1929         while (ii <= i)
1930             gen_opc_instr_start[ii++] = 0;
1931     } else {
1932         tb->size = ctx.pc - pc_start;
1933         tb->icount = num_insns;
1934     }
1935
1936 #ifdef DEBUG_DISAS
1937 #ifdef SH4_DEBUG_DISAS
1938     qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
1939 #endif
1940     if (loglevel & CPU_LOG_TB_IN_ASM) {
1941         qemu_log("IN:\n");      /* , lookup_symbol(pc_start)); */
1942         log_target_disas(pc_start, ctx.pc - pc_start, 0);
1943         qemu_log("\n");
1944     }
1945 #endif
1946 }
1947
1948 void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
1949 {
1950     gen_intermediate_code_internal(env, tb, 0);
1951 }
1952
1953 void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
1954 {
1955     gen_intermediate_code_internal(env, tb, 1);
1956 }
1957
1958 void gen_pc_load(CPUState *env, TranslationBlock *tb,
1959                 unsigned long searched_pc, int pc_pos, void *puc)
1960 {
1961     env->pc = gen_opc_pc[pc_pos];
1962     env->flags = gen_opc_hflags[pc_pos];
1963 }